Searched refs:__BIT (Results 1 – 25 of 412) sorted by relevance
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95 #define CR3_NO_TLB_FLUSH __BIT(63)143 #define XCR0_X87 __BIT(0) /* x87 FPU/MMX state */144 #define XCR0_SSE __BIT(1) /* SSE state */145 #define XCR0_YMM_Hi128 __BIT(2) /* AVX-256 (ymmn registers) */146 #define XCR0_BNDREGS __BIT(3) /* Memory protection ext bounds */147 #define XCR0_BNDCSR __BIT(4) /* Memory protection ext state */148 #define XCR0_Opmask __BIT(5) /* AVX-512 Opmask */149 #define XCR0_ZMM_Hi256 __BIT(6) /* AVX-512 upper 256 bits low regs */150 #define XCR0_Hi16_ZMM __BIT(7) /* AVX-512 512 bits upper registers */151 #define XCR0_PT __BIT(8) /* Processor Trace state */[all …]
161 #define SYSCTL_CFG0_INIC_EE_SDRAM __BIT(29)162 #define SYSCTL_CFG0_INIC_8MB_SDRAM __BIT(28)164 #define SYSCTL_CFG0_BYPASS_PLL __BIT(21)165 #define SYSCTL_CFG0_BE __BIT(20)166 #define SYSCTL_CFG0_CPU_CLK_SEL __BIT(18)170 #define SYSCTL_CFG0_SDRAM_CLK_DRV __BIT(0)172 #define SYSCTL_CFG0_BE __BIT(19)184 #define SYSCTL_CFG0_DRAM_FROM_EE __BIT(8)185 #define SYSCTL_CFG0_DBG_JTAG_MODE __BIT(7)186 #define SYSCTL_CFG0_XTAL_FREQ_SEL __BIT(6)[all …]
49 #define AWIN_GMAC_MAC_CONF_DISABLEJABBER __BIT(22) /* jabber disable */50 #define AWIN_GMAC_MAC_CONF_FRAMEBURST __BIT(21) /* allow TX frameburst when52 #define AWIN_GMAC_MAC_CONF_MIISEL __BIT(15) /* select MII phy */53 #define AWIN_GMAC_MAC_CONF_FES100 __BIT(14) /* 100 mbit mode */54 #define AWIN_GMAC_MAC_CONF_DISABLERXOWN __BIT(13) /* do not receive our own57 #define AWIN_GMAC_MAC_CONF_FULLDPLX __BIT(11) /* select full duplex */58 #define AWIN_GMAC_MAC_CONF_ACS __BIT(7) /* auto pad/CRC stripping */59 #define AWIN_GMAC_MAC_CONF_TXENABLE __BIT(3) /* enable TX dma engine */60 #define AWIN_GMAC_MAC_CONF_RXENABLE __BIT(2) /* enable RX dma engine */62 #define AWIN_GMAC_MAC_FFILT_RA __BIT(31) /* receive all mode */[all …]
136 #define ATW_PAR_MWIE __BIT(24) /* memory write and invalidate139 #define ATW_PAR_MRLE __BIT(23) /* memory read line enable */140 #define ATW_PAR_MRME __BIT(21) /* memory read multiple162 #define ATW_PAR_BLE __BIT(7) /* big/little endian selection */164 #define ATW_PAR_BAR __BIT(1) /* bus arbitration */165 #define ATW_PAR_SWR __BIT(0) /* software reset */167 #define ATW_FRCTL_PWRMGMT __BIT(31) /* power management */169 #define ATW_FRCTL_ORDER __BIT(28) /* order bit */170 #define ATW_FRCTL_MAXPSP __BIT(27) /* maximum power saving */171 #define ATW_C_FRCTL_PRSP __BIT(26) /* 1: driver sends probe[all …]
72 #define DWC_MMC_GCTRL_USE_INTERNAL_DMAC __BIT(25)73 #define DWC_MMC_GCTRL_SEND_AUTO_STOP_CCSD __BIT(10)74 #define DWC_MMC_GCTRL_DMAEN __BIT(5)75 #define DWC_MMC_GCTRL_INTEN __BIT(4)76 #define DWC_MMC_GCTRL_DMARESET __BIT(2)77 #define DWC_MMC_GCTRL_FIFORESET __BIT(1)78 #define DWC_MMC_GCTRL_SOFTRESET __BIT(0)83 #define DWC_MMC_CLKENA_LOWPOWERON __BIT(16)84 #define DWC_MMC_CLKENA_CARDCLKON __BIT(0)90 #define DWC_MMC_CMD_START __BIT(31)[all …]
59 #define RTW_BRSR_BPLCP __BIT(8)/* 1: use short PLCP header for CTS/ACK packet,69 #define RTW_BRSR_MBR8181_1MBPS __BIT(0)70 #define RTW_BRSR_MBR8181_2MBPS __BIT(1)71 #define RTW_BRSR_MBR8181_5MBPS __BIT(2)72 #define RTW_BRSR_MBR8181_11MBPS __BIT(3)86 #define RTW_CR_RST __BIT(4)/* Reset: host sets to 1 to disable90 #define RTW_CR_RE __BIT(3)/* Receiver Enable: host enables receiver95 #define RTW_CR_TE __BIT(2)/* Transmitter Enable: host enables transmitter100 #define RTW_CR_MULRW __BIT(0)/* PCI Multiple Read/Write enable: 1 enables,107 #define RTW_INTR_TXFOVW __BIT(15) /* Tx FIFO underflow */[all …]
53 #define SGE_FLAG_TRM __BIT(31)54 #define SGE_FLAG_LNK __BIT(30)55 #define SGE_FLAG_DRD __BIT(29)56 #define SGE_FLAG_XCF __BIT(28)68 #define PRB_CF_PROTOCOL_OVERRIDE __BIT(0)69 #define PRB_CF_RETRANSMIT __BIT(1)70 #define PRB_CF_EXTERNAL_COMMAND __BIT(2)71 #define PRB_CF_RECEIVE __BIT(3)72 #define PRB_CF_PACKET_READ __BIT(4)73 #define PRB_CF_PACKET_WRITE __BIT(5)[all …]
48 #define HW_POWER_CTRL_RSRVD3 __BIT(31)49 #define HW_POWER_CTRL_CLKGATE __BIT(30)51 #define HW_POWER_CTRL_PSWITCH_MID_TRAN __BIT(27)53 #define HW_POWER_CTRL_DCDC4P2_BO_IRQ __BIT(24)54 #define HW_POWER_CTRL_ENIRQ_DCDC4P2_BO __BIT(23)55 #define HW_POWER_CTRL_VDD5V_DROOP_IRQ __BIT(22)56 #define HW_POWER_CTRL_ENIRQ_VDD5V_DROOP __BIT(21)57 #define HW_POWER_CTRL_PSWITCH_IRQ __BIT(20)58 #define HW_POWER_CTRL_PSWITCH_IRQ_SRC __BIT(19)59 #define HW_POWER_CTRL_POLARITY_PSWITCH __BIT(18)[all …]
39 # define ENET_EIR_BABR __BIT(30)40 # define ENET_EIR_BABT __BIT(29)41 # define ENET_EIR_GRA __BIT(28)42 # define ENET_EIR_TXF __BIT(27)43 # define ENET_EIR_TXB __BIT(26)44 # define ENET_EIR_RXF __BIT(25)45 # define ENET_EIR_RXB __BIT(24)46 # define ENET_EIR_MII __BIT(23)47 # define ENET_EIR_EBERR __BIT(22)48 # define ENET_EIR_LC __BIT(21)[all …]
51 #define HW_UARTDBGDR_OE __BIT(11)52 #define HW_UARTDBGDR_BE __BIT(10)53 #define HW_UARTDBGDR_PE __BIT(9)54 #define HW_UARTDBGDR_FE __BIT(8)64 #define HW_UARTDBGRSR_ECR_OE __BIT(3)65 #define HW_UARTDBGRSR_ECR_BE __BIT(2)66 #define HW_UARTDBGRSR_ECR_PE __BIT(1)67 #define HW_UARTDBGRSR_ECR_FE __BIT(0)76 #define HW_UARTDBGFR_RI __BIT(8)77 #define HW_UARTDBGFR_TXFE __BIT(7)[all …]
54 #define HW_CLKCTRL_PLLCTRL0_RSRVD3 __BIT(19)55 #define HW_CLKCTRL_PLLCTRL0_EN_USB_CLKS __BIT(18)56 #define HW_CLKCTRL_PLLCTRL0_RSRVD2 __BIT(17)57 #define HW_CLKCTRL_PLLCTRL0_POWER __BIT(16)65 #define HW_CLKCTRL_PLLCTRL1_LOCK __BIT(31)66 #define HW_CLKCTRL_PLLCTRL1_FORCE_LOCK __BIT(30)79 #define HW_CLKCTRL_CPU_BUSY_REF_XTAL __BIT(29)80 #define HW_CLKCTRL_CPU_BUSY_REF_CPU __BIT(28)81 #define HW_CLKCTRL_CPU_RSVD5 __BIT(27)82 #define HW_CLKCTRL_CPU_DIV_XTAL_FRAC_EN __BIT(26)[all …]
51 #define HW_SSP_CTRL0_SFTRST __BIT(31)52 #define HW_SSP_CTRL0_CLKGATE __BIT(30)53 #define HW_SSP_CTRL0_RUN __BIT(29)54 #define HW_SSP_CTRL0_SDIO_IRQ_CHECK __BIT(28)55 #define HW_SSP_CTRL0_LOCK_CS __BIT(27)56 #define HW_SSP_CTRL0_IGNORE_CRC __BIT(26)57 #define HW_SSP_CTRL0_READ __BIT(25)58 #define HW_SSP_CTRL0_DATA_XFER __BIT(24)60 #define HW_SSP_CTRL0_WAIT_FOR_IRQ __BIT(21)61 #define HW_SSP_CTRL0_WAIT_FOR_CMD __BIT(20)[all …]
54 #define HW_AUDIOIN_CTRL_SFTRST __BIT(31)55 #define HW_AUDIOIN_CTRL_CLKGATE __BIT(30)59 #define HW_AUDIOIN_CTRL_LR_SWAP __BIT(10)60 #define HW_AUDIOIN_CTRL_EDGE_SYNC __BIT(9)61 #define HW_AUDIOIN_CTRL_INVERT_1BIT __BIT(8)62 #define HW_AUDIOIN_CTRL_OFFSET_ENABLE __BIT(7)63 #define HW_AUDIOIN_CTRL_HPF_ENABLE __BIT(6)64 #define HW_AUDIOIN_CTRL_WORD_LENGTH __BIT(5)65 #define HW_AUDIOIN_CTRL_LOOPBACK __BIT(4)66 #define HW_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ __BIT(3)[all …]
68 #define IMX_URXD_PRERR __BIT(10) /* ro */69 #define IMX_URXD_BRK __BIT(11) /* ro */70 #define IMX_URXD_FRMERR __BIT(12) /* ro */71 #define IMX_URXD_OVRRUN __BIT(13) /* ro */72 #define IMX_URXD_ERR __BIT(14) /* ro */73 #define IMX_URXD_CHARDY __BIT(15) /* ro */84 #define IMX_UCR1_UARTEN __BIT(0) /* rw */85 #define IMX_UCR1_DOZE __BIT(1) /* rw */86 #define IMX_UCR1_ATDMAEN __BIT(2) /* rw */87 #define IMX_UCR1_TXDMAEN __BIT(3) /* rw */[all …]
48 #define HW_APBH_CTRL0_SFTRST __BIT(31)49 #define HW_APBH_CTRL0_CLKGATE __BIT(30)50 #define HW_APBH_CTRL0_AHB_BURST8_EN __BIT(29)51 #define HW_APBH_CTRL0_APB_BURST4_EN __BIT(28)66 #define HW_APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN __BIT(23)67 #define HW_APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN __BIT(22)68 #define HW_APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN __BIT(21)69 #define HW_APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN __BIT(20)70 #define HW_APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN __BIT(19)71 #define HW_APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN __BIT(18)[all …]
49 #define HW_USBPHY_PWD_RXPWDRX __BIT(20)50 #define HW_USBPHY_PWD_RXPWDDIFF __BIT(19)51 #define HW_USBPHY_PWD_RXPWD1PT1 __BIT(18)52 #define HW_USBPHY_PWD_RXPWDENV __BIT(17)54 #define HW_USBPHY_PWD_TXPWDV2I __BIT(12)55 #define HW_USBPHY_PWD_TXPWDIBIAS __BIT(11)56 #define HW_USBPHY_PWD_TXPWDFS __BIT(10)69 #define HW_USBPHY_TX_USBPHY_TX_SYNC_INVERT __BIT(25)70 #define HW_USBPHY_TX_USBPHY_TX_SYNC_MUX __BIT(24)72 #define HW_USBPHY_TX_TXENCAL45DP __BIT(21)[all …]
104 #define WRX_ST_DD __BIT(0) /* descriptor done */105 #define WRX_ST_EOP __BIT(1) /* end of packet */106 #define WRX_ST_IXSM __BIT(2) /* ignore checksum indication */107 #define WRX_ST_VP __BIT(3) /* VLAN packet */108 #define WRX_ST_BPDU __BIT(4) /* ??? */109 #define WRX_ST_TCPCS __BIT(5) /* TCP checksum performed */110 #define WRX_ST_IPCS __BIT(6) /* IP checksum performed */111 #define WRX_ST_PIF __BIT(7) /* passed in-exact filter */114 #define WRX_ER_CE __BIT(0) /* CRC error */115 #define WRX_ER_SE __BIT(1) /* symbol error */[all …]
73 #define PCI_CONF_TYPE0_IDSEL(d) __BIT((d) + 11)110 #define PCI_STATUS_IMMD_READNESS __BIT(0+16)655 #define AGP_MODE_SBA __BIT(9)656 #define AGP_MODE_AGP __BIT(8)657 #define AGP_MODE_HTRANS __BIT(6)658 #define AGP_MODE_4G __BIT(5)659 #define AGP_MODE_FW __BIT(4)660 #define AGP_MODE_MODE_3 __BIT(3)713 #define PCI_MSI_CTL_EXTMDATA_EN __SHIFTIN(__BIT(10), PCI_MSI_CTL_MASK)714 #define PCI_MSI_CTL_EXTMDATA_CAP __SHIFTIN(__BIT(9), PCI_MSI_CTL_MASK)[all …]
57 #define VLPCI_DIP_SW_PCLK_CCLK __BIT(7)58 #define VLPCI_DIP_SW_SYNC_CLK __BIT(6)59 #define VLPCI_DIP_SW_IRQ14_15_PIN __BIT(5)60 #define VLPCI_DIP_SW_BLAST_PIN __BIT(4)70 #define VLPCI_BUF_CTL_CPU2PCI_WR_BUF __BIT(7)71 #define VLPCI_BUF_CTL_PCI2CPU_WR_BUF __BIT(6)72 #define VLPCI_BUF_CTL_CPU2PCI_PREF_BUF __BIT(5)73 #define VLPCI_BUF_CTL_PCI2CPU_PREF_BUF __BIT(4)74 #define VLPCI_BUF_CTL_PCI_DYN_ACC_DEC __BIT(3)75 #define VLPCI_BUF_CTL_BST_B4_LST_BRDY __BIT(2)[all …]
174 #define CAPABILITY_JTAG_PRESENT __BIT(22)179 #define CAPABILITY_BIG_ENDIAN __BIT(2)183 #define CORECTL_UART_CLK_EN __BIT(3)184 #define CORECTL_GPIO_ASYNC_INT_EN __BIT(2)185 #define CORECTL_UART_CLK_OVERRIDE __BIT(0)188 #define INTSTATUS_WDRESET __BIT(31) // WO2C189 #define INTSTATUS_UARTINT __BIT(6) // RO190 #define INTSTATUS_GPIOINT __BIT(0) // RO193 #define INTMASK_UARTINT __BIT(6) // 1 = enabled194 #define INTMASK_GPIOINT __BIT(0) // 1 = enabled[all …]
117 #define WBSIO_GPIO0_WDT1 __BIT(0)118 #define WBSIO_GPIO0_ENABLE __BIT(1)121 #define WBSIO_GPIO_BASEADDR __BIT(3) /* Base address mode */122 #define WBSIO_GPIO1_ENABLE __BIT(1)123 #define WBSIO_GPIO2_ENABLE __BIT(2)124 #define WBSIO_GPIO3_ENABLE __BIT(3)125 #define WBSIO_GPIO4_ENABLE __BIT(4)126 #define WBSIO_GPIO5_ENABLE __BIT(5)127 #define WBSIO_GPIO6_ENABLE __BIT(6)128 #define WBSIO_GPIO7_ENABLE __BIT(7)[all …]
86 #define GTMPSC_MRRE_DSC __BIT(31) /* "Don't Stop Clock" */110 #define GTMPSC_MMCR_LO_TTX __BIT(3) /* Transparent TX */111 #define GTMPSC_MMCR_LO_TRX __BIT(4) /* Transparent RX */112 #define GTMPSC_MMCR_LO_RESa __BIT(5)113 #define GTMPSC_MMCR_LO_ET __BIT(6) /* Enable TX */114 #define GTMPSC_MMCR_LO_ER __BIT(7) /* Enable RX */120 #define GTMPSC_MMCR_LO_NLM __BIT(10) /* Null Modem */121 #define GTMPSC_MMCR_LO_RESb __BIT(11)122 #define GTMPSC_MMCR_LO_TSYN __BIT(12) /* Transmitter sync to Rcvr. */123 #define GTMPSC_MMCR_LO_RESc __BIT(13)[all …]
56 #define INT0_TXDERR1 __BIT(31) /* GMAC1 AHB bus err while TX */57 #define INT0_TXPERR1 __BIT(30) /* GMAC1 TX descriptor error */58 #define INT0_TXDERR0 __BIT(29) /* GMAC0 AHB bus err while TX */59 #define INT0_TXPERR0 __BIT(28) /* GMAC0 TX descriptor error */60 #define INT0_RXDERR1 __BIT(27) /* GMAC1 AHB bus err while RX */61 #define INT0_RXPERR1 __BIT(26) /* GMAC1 RX descriptor error */62 #define INT0_RXDERR0 __BIT(25) /* GMAC0 AHB bus err while RX */63 #define INT0_RXPERR0 __BIT(24) /* GMAC0 RX descriptor error */64 #define INT0_SWTXQ15_FIN __BIT(23) /* GMAC1 SW TX queue 5 finish */65 #define INT0_SWTXQ14_FIN __BIT(22) /* GMAC1 SW TX queue 4 finish */[all …]
90 #define AR9344_CPU_PLL_CONFIG_UPDATING __BIT(31)91 #define AR9344_CPU_PLL_CONFIG_PLLPWD __BIT(30)98 #define AR7100_CPU_PLL_SW_UPDATE __BIT(31)99 #define AR7100_PLL_LOCKED __BIT(30)107 #define AR7100_CPU_PLL_PLL_BYPASS __BIT(1)108 #define AR7100_PLL_PLL_POWER_DOWN __BIT(0)110 #define AR9344_DDR_PLL_CONFIG_UPDATING __BIT(31)111 #define AR9344_DDR_PLL_CONFIG_PLLPWD __BIT(30)118 #define AR9344_CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL __BIT(24)119 #define AR9344_CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASRT __BIT(23)[all …]
116 #define CTR_EL0_DIC __BIT(29) // Instruction cache requirement117 #define CTR_EL0_IDC __BIT(28) // Data Cache clean requirement130 #define DCZID_DZP __BIT(4) // Data Zero Prohibited in AARCH64REG_READ_INLINE()136 #define FPCR_AHP __BIT(26) // Alternative Half Precision in AARCH64REG_READ_INLINE()137 #define FPCR_DN __BIT(25) // Default Nan Control in AARCH64REG_READ_INLINE()138 #define FPCR_FZ __BIT(24) // Flush-To-Zero in AARCH64REG_READ_INLINE()145 #define FPCR_FZ16 __BIT(19) // Flush-To-Zero for FP16 in AARCH64REG_READ_INLINE()147 #define FPCR_IDE __BIT(15) // Input Denormal Exception enable in AARCH64REG_READ_INLINE()148 #define FPCR_IXE __BIT(12) // IneXact Exception enable in AARCH64REG_READ_INLINE()149 #define FPCR_UFE __BIT(11) // UnderFlow Exception enable in AARCH64REG_READ_INLINE()[all …]