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/netbsd/src/external/gpl3/gcc/dist/gcc/config/mips/
Dloongson2ef.md27 ;; Automaton for integer instructions.
44 ;; Reservations for ALU1 (ALU2) instructions.
52 ;; Reservation for ALU1/2 instructions.
62 ;; Automaton for floating-point instructions.
79 ;; Reservations for FALU1 (FALU2) instructions.
87 ;; Reservation for FALU1/2 instructions.
97 ;; The following 4 instructions each subscribe one of
99 ;; These instructions are used in mips.cc: sched_ls2_dfa_post_advance_cycle.
154 ;; Reservation for integer instructions.
161 ;; Reservation for branch instructions.
[all …]
Dmips.opt59 Use PMC-style 'mad' instructions.
63 Use integer madd/msub instructions.
71 -mbranch-cost=COST Set the cost of branches to roughly COST instructions.
75 Use Branch Likely instructions, overriding the architecture default.
87 -mcode-readable=SETTING Specify when instructions are allowed to access code.
108 Use trap instructions to check for integer divide by zero.
112 Allow the use of MDMX instructions.
116 Allow hardware floating-point instructions to cover both 32-bit and 64-bit operations.
120 Use MIPS-DSP instructions.
124 Use MIPS-DSP REV 2 instructions.
[all …]
D4130.md21 ;; The processor issues each 8-byte aligned pair of instructions together,
23 ;; want two instructions to issue in parallel, we need to make sure that the
32 ;; can change the addresses of many instructions.
37 ;; through the function looking for pairs of instructions that could
49 ;; (a) dependent instructions are separated by a non-dependent
52 ;; (b) instructions that use the multiplication unit are separated
53 ;; by non-multiplication instructions; and
55 ;; (c) memory access instructions are separated by non-memory
56 ;; instructions.
58 ;; The idea is to keep conflicting instructions apart wherever possible
/netbsd/src/external/gpl3/gdb/dist/sim/ppc/
Digen.c351 insn_table *instructions = NULL; in main() local
497 instructions = load_insn_table(optarg, decode_rules, filters, includes, in main()
500 insn_table_expand_insns(instructions); in main()
525 ASSERT(instructions != NULL); in main()
529 gen_semantics_h(instructions, file, code); in main()
531 gen_semantics_c(instructions, cache_rules, file, code); in main()
535 gen_idecode_h(file, instructions, cache_rules); in main()
537 gen_idecode_c(file, instructions, cache_rules); in main()
541 gen_model_h(instructions, file); in main()
543 gen_model_c(instructions, file); in main()
[all …]
DRUN174 The frequency of all instructions is tabulated. In
181 In addition to counting basic instructions also model
199 CPU #1 executed 41,994 AND instructions.
200 CPU #1 executed 519,785 AND Immediate instructions.
201 CPU #1 executed 680,058 Add instructions.
202 CPU #1 executed 41,994 Add Extended instructions.
203 CPU #1 executed 921,916 Add Immediate instructions.
204 CPU #1 executed 221,199 Add Immediate Carrying instructions.
205 CPU #1 executed 943,823 Add Immediate Shifted instructions.
206 CPU #1 executed 471,909 Add to Zero Extended instructions.
[all …]
/netbsd/src/external/gpl3/gcc/dist/gcc/config/sparc/
Dm8.md22 ;; - Store instructions are implemented by micro-ops, one of which
27 ;; implementation assumes that all the instructions executing in a
31 ;; slot 0 and slot 1 instructions. This is not currently reflected
39 ;; instructions per-cycle, and up to 4 instructions are committed each
62 ;; Some instructions stall the pipeline and avoid any other
73 ;; Most of the instructions executing in the integer units have a
89 ;; The integer multiplication instructions have a latency of 10 cycles
92 ;; Likewise for array*, edge* and pdistn instructions.
105 ;; The integer division instructions `sdiv' and `udivx' have a latency
113 ;; Both integer and floating-point load instructions have a latency of
[all …]
Dniagara7.md24 ;; up to 2 instructions are committed each cycle. Each slot serves
39 ;; Some instructions stall the pipeline and avoid any other
50 ;; Most of the instructions executing in the integer unit have a
65 ;; The integer multiplication instructions have a latency of 12 cycles
68 ;; Likewise for array*, edge* and pdistn instructions.
75 ;; The integer division instructions have a latency of 35 cycles and
83 ;; Both integer and floating-point load instructions have a latency of
102 ;; Both integer and floating-point store instructions have a latency
110 ;; Control-transfer instructions execute in the Branch Unit in the
118 ;; Many instructions executing in the Floating-point and Graphics unit
[all …]
/netbsd/src/external/gpl3/binutils/dist/gas/doc/
Dc-xtensa.texi46 @code{L32R} instructions in the text section. Literals are grouped into
48 @code{ENTRY} instructions. These options only affect literals referenced
49 via PC-relative @code{L32R} instructions; literals for absolute mode
50 @code{L32R} instructions are handled separately.
65 @code{L32R} instructions at the end. These options only affect
66 literals referenced via PC-relative @code{L32R} instructions; literals
67 for absolute mode @code{L32R} instructions are handled separately.
75 Indicate to the assembler whether @code{L32R} instructions use absolute
87 that the assembler will always align instructions like @code{LOOP} that
93 Enable or disable transformation of call instructions to allow calls
[all …]
Dc-mips.texi29 * MIPS autoextend:: Directives for extending MIPS 16 bit instructions
35 generation of MIPS ASE instructions
119 set, 64-bit instructions generate a trap. Also, some 32-bit OSes only
156 Enable the use of MIPS16e2 instructions in MIPS16 mode. This is equivalent
170 provides a number of new instructions which target smartcard and
178 This tells the assembler to accept MIPS-3D instructions.
184 This tells the assembler to accept MDMX instructions.
190 This tells the assembler to accept DSP Release 1 instructions.
197 This tells the assembler to accept DSP Release 2 instructions.
204 This tells the assembler to accept DSP Release 3 instructions.
[all …]
Dc-csky.texi61 Enable/disable transformation of the short branch instructions
72 instructions to the linker.
86 Enable/disable transformation of @code{jbsr} instructions to @code{bsr}.
99 Enable/disable transformation of @code{jsri} instructions to @code{bsr}.
106 Enable/disable transformation of @code{lrw} instructions into a
113 Enable/disable extended @code{lrw} instructions.
141 Enable/disable interrupt stack instructions. This option is enabled by
146 The following options explicitly enable certain optional instructions.
153 Enable hard float instructions.
157 Enable multiprocessor instructions.
[all …]
Dc-i386.texi76 By default, x86 GAS replaces multiple nop instructions used for
77 alignment within code sections with multi-byte nop instructions such
289 conjunction with the @option{-march} option, only instructions
299 This option specifies that the assembler should encode SSE instructions
313 These options control if the assembler should check SSE instructions.
315 instructions, which is the default. @option{-msse-check=@var{warning}}
325 instructions. @option{-mavxscalar=@var{128}} will encode scalar
326 AVX instructions with 128bit vector length, which is the default.
327 @option{-mavxscalar=@var{256}} will encode scalar AVX instructions
338 VEX instructions. @option{-mvexwig=@var{0}} will encode WIG VEX
[all …]
Dc-ppc.texi30 core instruction set, but including a few additional instructions at
32 instructions each variant supports, please see the chip's architecture
64 Generate code for PowerPC 440. BookE and some 405 instructions.
106 Enable LSP instructions. (Disables SPE and SPE2.)
109 Generate code for Motorola SPE instructions. (Disables LSP.)
112 Generate code for Freescale SPE2 instructions. (Disables LSP.)
127 Generate code for processors with AltiVec instructions.
130 Generate code for Freescale PowerPC VLE instructions.
133 Generate code for processors with Vector-Scalar (VSX) instructions.
136 Generate code for processors with Hardware Transactional Memory instructions.
[all …]
Dc-d10v.texi31 The D10V can often execute two sub-instructions in parallel. When this option
33 instructions can be executed in parallel.
36 order of instructions. Normally this generates a warning. When this option
37 is used, no warning will be generated when instructions are swapped.
40 @code{@value{AS}} packs adjacent short instructions into a single packed
79 Objdump and GDB will always append @samp{.s} or @samp{.l} to instructions which
84 @cindex D10V sub-instructions
85 @cindex sub-instructions, D10V
86 The D10V assembler takes as input a series of instructions, either one-per-line,
88 instructions will be short-form or sub-instructions. These sub-instructions can be packed
[all …]
/netbsd/src/external/gpl3/gcc/dist/gcc/config/arm/
Dcortex-a8.md53 ;; prevent any other instructions from being issued upon that first cycle.)
55 ;; ALU pipe, multi-cycle instructions always issue in pipeline 0.
80 ;; The model given here assumes that all instructions are unconditional.
82 ;; Data processing instructions, but not move instructions.
109 ;; Move instructions.
118 ;; Exceptions to the default latencies for data processing instructions.
138 ;; Multiplication instructions. These are categorized according to their
141 ;; (but some of these are multi-cycle instructions which explains the
164 ;; smlald and smlsld are multiply-accumulate instructions but do not
174 ;; such instructions can issue back-to-back.
[all …]
Darm1026ejs.md30 ;; instructions is "true", i.e., that all of the instructions are
59 ;; ALU instructions require three cycles to execute, and use the ALU
101 ;; Multiplication instructions loop in the execute stage until the
105 ;; The result of the "smul" and "smulw" instructions is not available
112 ;; The "smlaxy" and "smlawx" instructions require two iterations through
120 ;; The "smlalxy", "mul", and "mla" instructions require two iterations
128 ;; The "muls" and "mlas" instructions loop in the execute stage for
136 ;; Long multiply instructions that produce two registers of
139 ;; word. That fact is not modeled; instead, the instructions are
143 ;; The "umull", "umlal", "smull", and "smlal" instructions all take
[all …]
Dcortex-a5.md29 ;; instructions, so do not model them. We only need to model the
30 ;; first execute stage because instructions always advance one stage
31 ;; per cycle in order. Only branch instructions may dual-issue, so a
36 ;; The branch pipeline. Branches can dual-issue with other instructions
37 ;; (except when those instructions take multiple cycles to issue).
47 ;; of the add pipeline by fmac instructions, etc.
56 ;; ALU instructions.
100 ;; Load/store instructions.
155 ;; Direct branches are the only instructions we can dual-issue (also IT and
197 ;; block other instructions attempting to use it simultaneously. We try to
[all …]
/netbsd/src/external/gpl3/gcc/dist/gcc/config/arc/
Darc.opt34 Disable ARCompact specific pass to generate conditional execution instructions.
132 Enable DIV-REM instructions for ARCv2.
136 Enable code density instructions for ARCv2.
154 Generate instructions supported by barrel shifter.
166 Generate mul64 and mulu64 instructions.
170 Do not generate mpy instructions for ARC700.
174 Generate extended arithmetic instructions, only valid for ARC700.
186 Do no generate BRcc instructions in arc_reorg.
198 FPX: Generate Single Precision FPX (compact) instructions.
202 FPX: Generate Single Precision FPX (compact) instructions.
[all …]
Dbuiltins.def124 /* Va, Vb, Ic instructions. */
129 /* Va, Vb, u6 instructions. */
138 /* Va, Vb, u8 (simm) instructions. */
144 /* Va, rlimm, u8 (simm) instructions. */
149 /* Va, Vb instructions. */
162 /* SIMD special DIb, rlimm, rlimm instructions. */
166 /* SIMD special DIb, limm, rlimm instructions. */
170 /* rlimm instructions. */
176 /* Va, [Ib,u8] instructions. */
188 /* Va, [Ib, u8] instructions. */
[all …]
/netbsd/src/external/gpl3/gcc/dist/gcc/config/i386/
Dx86-tune.def95 set by instructions affecting just some flags (in particular shifts).
152 by push/pop instructions.
177 /* X86_TUNE_PUSH_MEMORY: Enable generation of "push mem" instructions.
179 and push instructions. */
208 instructions long. */
220 than 4 branch instructions in the 16 byte window. */
239 /* X86_TUNE_READ_MODIFY: Enable use of read-modify instructions such
243 /* X86_TUNE_USE_INCDEC: Enable use of inc/dec instructions.
316 /* X86_TUNE_USE_CLTD: Controls use of CLTD and CTQO instructions. */
321 /* X86_TUNE_USE_BT: Enable use of BT (bit test) instructions. */
[all …]
Dppro.md50 ;; Since the P6 CPUs execute instructions out-of-order, the most important
56 ;; - Find a less crude way to model complex instructions, in
69 ;; Simple instructions of the register-register form have only one uop.
70 ;; Load instructions are also only one uop. Store instructions decode to
71 ;; two uops, and simple read-modify instructions also take two uops.
72 ;; Simple instructions of the register-memory form have two to three uops.
73 ;; Simple read-modify-write instructions have four uops. The rules for
83 ;; in each cycle, to decode as many instructions per cycle as possible.
94 ;; Most instructions can be decoded on any of the three decoders.
120 ;; Only the irregular instructions have to be modeled here. A load
[all …]
/netbsd/src/external/gpl3/gcc/dist/gcc/config/lm32/
Dlm32.opt24 Enable multiply instructions.
28 Enable divide and modulus instructions.
32 Enable barrel shift instructions.
36 Enable sign extend instructions.
40 Enable user-defined instructions.
/netbsd/src/external/gpl3/gcc/dist/gcc/config/rs6000/
Drs6000.opt51 ;; Schedule instructions for group formation.
95 ;; What type of reciprocal estimation instructions to generate
125 Use PowerPC General Purpose group optional instructions.
129 Use PowerPC Graphics group optional instructions.
141 Use PowerPC V2.02 floating point rounding instructions.
156 Use AltiVec instructions.
160 Use decimal floating point instructions.
164 Use 4xx half-word multiply instructions.
172 Generate load/store multiple instructions.
203 Use vector/scalar (VSX) instructions.
[all …]
/netbsd/src/common/dist/zlib/contrib/vstudio/
Dreadme.txt1 Building instructions for the DLL versions of Zlib 1.3.1
17 Build instructions for Visual Studio 2008 (32 bits or 64 bits)
23 Build instructions for Visual Studio 2010 (32 bits or 64 bits)
28 Build instructions for Visual Studio 2012 (32 bits or 64 bits)
33 Build instructions for Visual Studio 2013 (32 bits or 64 bits)
38 Build instructions for Visual Studio 2015 (32 bits or 64 bits)
43 Build instructions for Visual Studio 2022 (64 bits)
/netbsd/src/external/lgpl3/gmp/dist/mpn/x86/pentium4/
DREADME37 The mmx subdirectory has routines using MMX instructions, the sse2
38 subdirectory has routines using SSE2 instructions. All P4s have these, the
68 instructions do not trigger the same hardware problems. Unfortunately,
70 instructions to help. Perhaps future chip steppings will be better.
77 Many traditional x86 instructions run very slowly, requiring use of
78 alterative instructions for acceptable performance.
86 previous flags-setting instructions.
89 integer instructions (addl, subl, orl, andl, and some more). shldl and
/netbsd/src/external/gpl3/binutils/dist/gas/
DNEWS24 * Add support for the AArch64 Load-Acquire RCpc instructions version 3 (LRCPC3).
37 '+wfxt' flags to enable existing AArch64 instructions.
52 * Add support for Intel USER_MSR instructions.
56 * Add support for Intel PBNDKB instructions.
58 * Add support for Intel SM4 instructions.
60 * Add support for Intel SM3 instructions.
62 * Add support for Intel SHA512 instructions.
64 * Add support for Intel AVX-VNNI-INT16 instructions.
66 * On RISC-V macro instructions expanding to AUIPC and a load, store, or branch
83 * Add support for LoongArch v1.10 new instructions: estimated reciprocal
[all …]

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