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Searched refs:fw_based (Results 1 – 9 of 9) sorted by relevance

/openbsd/src/sys/dev/pci/drm/amd/amdgpu/
Dvcn_v1_0.c1267 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { in vcn_v1_0_pause_dpg_mode()
1269 adev->vcn.inst[inst_idx].pause_state.fw_based, in vcn_v1_0_pause_dpg_mode()
1271 new_state->fw_based, new_state->jpeg); in vcn_v1_0_pause_dpg_mode()
1276 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { in vcn_v1_0_pause_dpg_mode()
1319 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; in vcn_v1_0_pause_dpg_mode()
1325 adev->vcn.inst[inst_idx].pause_state.fw_based, in vcn_v1_0_pause_dpg_mode()
1327 new_state->fw_based, new_state->jpeg); in vcn_v1_0_pause_dpg_mode()
1848 new_state.fw_based = VCN_DPG_STATE__PAUSE; in vcn_v1_0_idle_work_handler()
1850 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; in vcn_v1_0_idle_work_handler()
1910 new_state.fw_based = VCN_DPG_STATE__PAUSE; in vcn_v1_0_set_pg_for_begin_use()
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Dvcn_v5_0_0.c916 struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__UNPAUSE}; in vcn_v5_0_0_stop_dpg_mode()
1035 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { in vcn_v5_0_0_pause_dpg_mode()
1037 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); in vcn_v5_0_0_pause_dpg_mode()
1041 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { in vcn_v5_0_0_pause_dpg_mode()
1060 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; in vcn_v5_0_0_pause_dpg_mode()
Dvcn_v4_0_5.c1304 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { in vcn_v4_0_5_pause_dpg_mode()
1306 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); in vcn_v4_0_5_pause_dpg_mode()
1310 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { in vcn_v4_0_5_pause_dpg_mode()
1333 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; in vcn_v4_0_5_pause_dpg_mode()
Dvcn_v4_0.c1519 struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__UNPAUSE}; in vcn_v4_0_stop_dpg_mode()
1641 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { in vcn_v4_0_pause_dpg_mode()
1643 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); in vcn_v4_0_pause_dpg_mode()
1647 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { in vcn_v4_0_pause_dpg_mode()
1669 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; in vcn_v4_0_pause_dpg_mode()
Dvcn_v2_0.c1149 struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__UNPAUSE}; in vcn_v2_0_stop_dpg_mode()
1253 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { in vcn_v2_0_pause_dpg_mode()
1255 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); in vcn_v2_0_pause_dpg_mode()
1259 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { in vcn_v2_0_pause_dpg_mode()
1316 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; in vcn_v2_0_pause_dpg_mode()
Damdgpu_vcn.c399 new_state.fw_based = VCN_DPG_STATE__PAUSE; in amdgpu_vcn_idle_work_handler()
401 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; in amdgpu_vcn_idle_work_handler()
447 new_state.fw_based = VCN_DPG_STATE__PAUSE; in amdgpu_vcn_ring_begin_use()
456 new_state.fw_based = VCN_DPG_STATE__PAUSE; in amdgpu_vcn_ring_begin_use()
458 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; in amdgpu_vcn_ring_begin_use()
Dvcn_v3_0.c1539 struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__UNPAUSE}; in vcn_v3_0_stop_dpg_mode()
1652 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { in vcn_v3_0_pause_dpg_mode()
1654 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); in vcn_v3_0_pause_dpg_mode()
1658 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { in vcn_v3_0_pause_dpg_mode()
1718 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; in vcn_v3_0_pause_dpg_mode()
Dvcn_v2_5.c1504 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { in vcn_v2_5_pause_dpg_mode()
1506 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); in vcn_v2_5_pause_dpg_mode()
1510 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { in vcn_v2_5_pause_dpg_mode()
1565 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; in vcn_v2_5_pause_dpg_mode()
Damdgpu_vcn.h256 enum internal_dpg_state fw_based; member