1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/firmware.h>
25
26 #include "amdgpu.h"
27 #include "amdgpu_cs.h"
28 #include "amdgpu_vcn.h"
29 #include "amdgpu_pm.h"
30 #include "soc15.h"
31 #include "soc15d.h"
32 #include "soc15_common.h"
33
34 #include "vcn/vcn_1_0_offset.h"
35 #include "vcn/vcn_1_0_sh_mask.h"
36 #include "mmhub/mmhub_9_1_offset.h"
37 #include "mmhub/mmhub_9_1_sh_mask.h"
38
39 #include "ivsrcid/vcn/irqsrcs_vcn_1_0.h"
40 #include "jpeg_v1_0.h"
41 #include "vcn_v1_0.h"
42
43 #define mmUVD_RBC_XX_IB_REG_CHECK_1_0 0x05ab
44 #define mmUVD_RBC_XX_IB_REG_CHECK_1_0_BASE_IDX 1
45 #define mmUVD_REG_XX_MASK_1_0 0x05ac
46 #define mmUVD_REG_XX_MASK_1_0_BASE_IDX 1
47
48 static const struct amdgpu_hwip_reg_entry vcn_reg_list_1_0[] = {
49 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_POWER_STATUS),
50 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_STATUS),
51 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID),
52 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID2),
53 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA0),
54 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA1),
55 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_CMD),
56 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI),
57 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO),
58 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI2),
59 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO2),
60 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI3),
61 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO3),
62 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI4),
63 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO4),
64 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR),
65 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR),
66 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR2),
67 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR2),
68 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR3),
69 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR3),
70 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR4),
71 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR4),
72 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE),
73 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE2),
74 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE3),
75 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE4),
76 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_CONFIG),
77 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_STATUS),
78 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_CTL),
79 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_DATA),
80 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_MASK),
81 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_PAUSE)
82 };
83
84 static int vcn_v1_0_stop(struct amdgpu_device *adev);
85 static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev);
86 static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev);
87 static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev);
88 static int vcn_v1_0_set_powergating_state(void *handle, enum amd_powergating_state state);
89 static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev,
90 int inst_idx, struct dpg_pause_state *new_state);
91
92 static void vcn_v1_0_idle_work_handler(struct work_struct *work);
93 static void vcn_v1_0_ring_begin_use(struct amdgpu_ring *ring);
94
95 /**
96 * vcn_v1_0_early_init - set function pointers and load microcode
97 *
98 * @handle: amdgpu_device pointer
99 *
100 * Set ring and irq function pointers
101 * Load microcode from filesystem
102 */
vcn_v1_0_early_init(void * handle)103 static int vcn_v1_0_early_init(void *handle)
104 {
105 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
106
107 adev->vcn.num_enc_rings = 2;
108
109 vcn_v1_0_set_dec_ring_funcs(adev);
110 vcn_v1_0_set_enc_ring_funcs(adev);
111 vcn_v1_0_set_irq_funcs(adev);
112
113 jpeg_v1_0_early_init(handle);
114
115 return amdgpu_vcn_early_init(adev);
116 }
117
118 /**
119 * vcn_v1_0_sw_init - sw init for VCN block
120 *
121 * @handle: amdgpu_device pointer
122 *
123 * Load firmware and sw initialization
124 */
vcn_v1_0_sw_init(void * handle)125 static int vcn_v1_0_sw_init(void *handle)
126 {
127 struct amdgpu_ring *ring;
128 int i, r;
129 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_1_0);
130 uint32_t *ptr;
131 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
132
133 /* VCN DEC TRAP */
134 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
135 VCN_1_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst->irq);
136 if (r)
137 return r;
138
139 /* VCN ENC TRAP */
140 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
141 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, i + VCN_1_0__SRCID__UVD_ENC_GENERAL_PURPOSE,
142 &adev->vcn.inst->irq);
143 if (r)
144 return r;
145 }
146
147 r = amdgpu_vcn_sw_init(adev);
148 if (r)
149 return r;
150
151 /* Override the work func */
152 #ifdef __linux__
153 adev->vcn.idle_work.work.func = vcn_v1_0_idle_work_handler;
154 #else
155 task_set(&adev->vcn.idle_work.work.task,
156 (void (*)(void *))vcn_v1_0_idle_work_handler,
157 &adev->vcn.idle_work.work);
158 #endif
159
160 amdgpu_vcn_setup_ucode(adev);
161
162 r = amdgpu_vcn_resume(adev);
163 if (r)
164 return r;
165
166 ring = &adev->vcn.inst->ring_dec;
167 ring->vm_hub = AMDGPU_MMHUB0(0);
168 snprintf(ring->name, sizeof(ring->name), "vcn_dec");
169 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0,
170 AMDGPU_RING_PRIO_DEFAULT, NULL);
171 if (r)
172 return r;
173
174 adev->vcn.internal.scratch9 = adev->vcn.inst->external.scratch9 =
175 SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9);
176 adev->vcn.internal.data0 = adev->vcn.inst->external.data0 =
177 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0);
178 adev->vcn.internal.data1 = adev->vcn.inst->external.data1 =
179 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1);
180 adev->vcn.internal.cmd = adev->vcn.inst->external.cmd =
181 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD);
182 adev->vcn.internal.nop = adev->vcn.inst->external.nop =
183 SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP);
184
185 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
186 enum amdgpu_ring_priority_level hw_prio = amdgpu_vcn_get_enc_ring_prio(i);
187
188 ring = &adev->vcn.inst->ring_enc[i];
189 ring->vm_hub = AMDGPU_MMHUB0(0);
190 snprintf(ring->name, sizeof(ring->name), "vcn_enc%d", i);
191 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0,
192 hw_prio, NULL);
193 if (r)
194 return r;
195 }
196
197 adev->vcn.pause_dpg_mode = vcn_v1_0_pause_dpg_mode;
198
199 if (amdgpu_vcnfw_log) {
200 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr;
201
202 fw_shared->present_flag_0 = 0;
203 amdgpu_vcn_fwlog_init(adev->vcn.inst);
204 }
205
206 r = jpeg_v1_0_sw_init(handle);
207
208 /* Allocate memory for VCN IP Dump buffer */
209 ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL);
210 if (!ptr) {
211 DRM_ERROR("Failed to allocate memory for VCN IP Dump\n");
212 adev->vcn.ip_dump = NULL;
213 } else {
214 adev->vcn.ip_dump = ptr;
215 }
216 return r;
217 }
218
219 /**
220 * vcn_v1_0_sw_fini - sw fini for VCN block
221 *
222 * @handle: amdgpu_device pointer
223 *
224 * VCN suspend and free up sw allocation
225 */
vcn_v1_0_sw_fini(void * handle)226 static int vcn_v1_0_sw_fini(void *handle)
227 {
228 int r;
229 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
230
231 r = amdgpu_vcn_suspend(adev);
232 if (r)
233 return r;
234
235 jpeg_v1_0_sw_fini(handle);
236
237 r = amdgpu_vcn_sw_fini(adev);
238
239 kfree(adev->vcn.ip_dump);
240
241 return r;
242 }
243
244 /**
245 * vcn_v1_0_hw_init - start and test VCN block
246 *
247 * @handle: amdgpu_device pointer
248 *
249 * Initialize the hardware, boot up the VCPU and do some testing
250 */
vcn_v1_0_hw_init(void * handle)251 static int vcn_v1_0_hw_init(void *handle)
252 {
253 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
254 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
255 int i, r;
256
257 r = amdgpu_ring_test_helper(ring);
258 if (r)
259 return r;
260
261 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
262 ring = &adev->vcn.inst->ring_enc[i];
263 r = amdgpu_ring_test_helper(ring);
264 if (r)
265 return r;
266 }
267
268 ring = adev->jpeg.inst->ring_dec;
269 r = amdgpu_ring_test_helper(ring);
270
271 return r;
272 }
273
274 /**
275 * vcn_v1_0_hw_fini - stop the hardware block
276 *
277 * @handle: amdgpu_device pointer
278 *
279 * Stop the VCN block, mark ring as not ready any more
280 */
vcn_v1_0_hw_fini(void * handle)281 static int vcn_v1_0_hw_fini(void *handle)
282 {
283 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
284
285 cancel_delayed_work_sync(&adev->vcn.idle_work);
286
287 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
288 (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
289 RREG32_SOC15(VCN, 0, mmUVD_STATUS))) {
290 vcn_v1_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
291 }
292
293 return 0;
294 }
295
296 /**
297 * vcn_v1_0_suspend - suspend VCN block
298 *
299 * @handle: amdgpu_device pointer
300 *
301 * HW fini and suspend VCN block
302 */
vcn_v1_0_suspend(void * handle)303 static int vcn_v1_0_suspend(void *handle)
304 {
305 int r;
306 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
307 bool idle_work_unexecuted;
308
309 idle_work_unexecuted = cancel_delayed_work_sync(&adev->vcn.idle_work);
310 if (idle_work_unexecuted) {
311 if (adev->pm.dpm_enabled)
312 amdgpu_dpm_enable_uvd(adev, false);
313 }
314
315 r = vcn_v1_0_hw_fini(adev);
316 if (r)
317 return r;
318
319 r = amdgpu_vcn_suspend(adev);
320
321 return r;
322 }
323
324 /**
325 * vcn_v1_0_resume - resume VCN block
326 *
327 * @handle: amdgpu_device pointer
328 *
329 * Resume firmware and hw init VCN block
330 */
vcn_v1_0_resume(void * handle)331 static int vcn_v1_0_resume(void *handle)
332 {
333 int r;
334 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
335
336 r = amdgpu_vcn_resume(adev);
337 if (r)
338 return r;
339
340 r = vcn_v1_0_hw_init(adev);
341
342 return r;
343 }
344
345 /**
346 * vcn_v1_0_mc_resume_spg_mode - memory controller programming
347 *
348 * @adev: amdgpu_device pointer
349 *
350 * Let the VCN memory controller know it's offsets
351 */
vcn_v1_0_mc_resume_spg_mode(struct amdgpu_device * adev)352 static void vcn_v1_0_mc_resume_spg_mode(struct amdgpu_device *adev)
353 {
354 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[0]->size + 4);
355 uint32_t offset;
356
357 /* cache window 0: fw */
358 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
359 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
360 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo));
361 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
362 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi));
363 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0);
364 offset = 0;
365 } else {
366 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
367 lower_32_bits(adev->vcn.inst->gpu_addr));
368 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
369 upper_32_bits(adev->vcn.inst->gpu_addr));
370 offset = size;
371 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
372 AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
373 }
374
375 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size);
376
377 /* cache window 1: stack */
378 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
379 lower_32_bits(adev->vcn.inst->gpu_addr + offset));
380 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
381 upper_32_bits(adev->vcn.inst->gpu_addr + offset));
382 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0);
383 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);
384
385 /* cache window 2: context */
386 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
387 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
388 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
389 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
390 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0);
391 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
392
393 WREG32_SOC15(UVD, 0, mmUVD_UDEC_ADDR_CONFIG,
394 adev->gfx.config.gb_addr_config);
395 WREG32_SOC15(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG,
396 adev->gfx.config.gb_addr_config);
397 WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG,
398 adev->gfx.config.gb_addr_config);
399 WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_UV_ADDR_CONFIG,
400 adev->gfx.config.gb_addr_config);
401 WREG32_SOC15(UVD, 0, mmUVD_MIF_CURR_ADDR_CONFIG,
402 adev->gfx.config.gb_addr_config);
403 WREG32_SOC15(UVD, 0, mmUVD_MIF_CURR_UV_ADDR_CONFIG,
404 adev->gfx.config.gb_addr_config);
405 WREG32_SOC15(UVD, 0, mmUVD_MIF_RECON1_ADDR_CONFIG,
406 adev->gfx.config.gb_addr_config);
407 WREG32_SOC15(UVD, 0, mmUVD_MIF_RECON1_UV_ADDR_CONFIG,
408 adev->gfx.config.gb_addr_config);
409 WREG32_SOC15(UVD, 0, mmUVD_MIF_REF_ADDR_CONFIG,
410 adev->gfx.config.gb_addr_config);
411 WREG32_SOC15(UVD, 0, mmUVD_MIF_REF_UV_ADDR_CONFIG,
412 adev->gfx.config.gb_addr_config);
413 WREG32_SOC15(UVD, 0, mmUVD_JPEG_ADDR_CONFIG,
414 adev->gfx.config.gb_addr_config);
415 WREG32_SOC15(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG,
416 adev->gfx.config.gb_addr_config);
417 }
418
vcn_v1_0_mc_resume_dpg_mode(struct amdgpu_device * adev)419 static void vcn_v1_0_mc_resume_dpg_mode(struct amdgpu_device *adev)
420 {
421 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[0]->size + 4);
422 uint32_t offset;
423
424 /* cache window 0: fw */
425 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
426 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
427 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo),
428 0xFFFFFFFF, 0);
429 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
430 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi),
431 0xFFFFFFFF, 0);
432 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0,
433 0xFFFFFFFF, 0);
434 offset = 0;
435 } else {
436 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
437 lower_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0);
438 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
439 upper_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0);
440 offset = size;
441 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
442 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0xFFFFFFFF, 0);
443 }
444
445 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size, 0xFFFFFFFF, 0);
446
447 /* cache window 1: stack */
448 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
449 lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0xFFFFFFFF, 0);
450 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
451 upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0xFFFFFFFF, 0);
452 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0,
453 0xFFFFFFFF, 0);
454 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE,
455 0xFFFFFFFF, 0);
456
457 /* cache window 2: context */
458 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
459 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE),
460 0xFFFFFFFF, 0);
461 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
462 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE),
463 0xFFFFFFFF, 0);
464 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0, 0xFFFFFFFF, 0);
465 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE,
466 0xFFFFFFFF, 0);
467
468 /* VCN global tiling registers */
469 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_ADDR_CONFIG,
470 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
471 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG,
472 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
473 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG,
474 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
475 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_DBW_UV_ADDR_CONFIG,
476 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
477 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_CURR_ADDR_CONFIG,
478 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
479 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_CURR_UV_ADDR_CONFIG,
480 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
481 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_RECON1_ADDR_CONFIG,
482 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
483 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_RECON1_UV_ADDR_CONFIG,
484 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
485 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_REF_ADDR_CONFIG,
486 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
487 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_REF_UV_ADDR_CONFIG,
488 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
489 }
490
491 /**
492 * vcn_v1_0_disable_clock_gating - disable VCN clock gating
493 *
494 * @adev: amdgpu_device pointer
495 *
496 * Disable clock gating for VCN block
497 */
vcn_v1_0_disable_clock_gating(struct amdgpu_device * adev)498 static void vcn_v1_0_disable_clock_gating(struct amdgpu_device *adev)
499 {
500 uint32_t data;
501
502 /* JPEG disable CGC */
503 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL);
504
505 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
506 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
507 else
508 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE_MASK;
509
510 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
511 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
512 WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data);
513
514 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE);
515 data &= ~(JPEG_CGC_GATE__JPEG_MASK | JPEG_CGC_GATE__JPEG2_MASK);
516 WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data);
517
518 /* UVD disable CGC */
519 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
520 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
521 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
522 else
523 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
524
525 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
526 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
527 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
528
529 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE);
530 data &= ~(UVD_CGC_GATE__SYS_MASK
531 | UVD_CGC_GATE__UDEC_MASK
532 | UVD_CGC_GATE__MPEG2_MASK
533 | UVD_CGC_GATE__REGS_MASK
534 | UVD_CGC_GATE__RBC_MASK
535 | UVD_CGC_GATE__LMI_MC_MASK
536 | UVD_CGC_GATE__LMI_UMC_MASK
537 | UVD_CGC_GATE__IDCT_MASK
538 | UVD_CGC_GATE__MPRD_MASK
539 | UVD_CGC_GATE__MPC_MASK
540 | UVD_CGC_GATE__LBSI_MASK
541 | UVD_CGC_GATE__LRBBM_MASK
542 | UVD_CGC_GATE__UDEC_RE_MASK
543 | UVD_CGC_GATE__UDEC_CM_MASK
544 | UVD_CGC_GATE__UDEC_IT_MASK
545 | UVD_CGC_GATE__UDEC_DB_MASK
546 | UVD_CGC_GATE__UDEC_MP_MASK
547 | UVD_CGC_GATE__WCB_MASK
548 | UVD_CGC_GATE__VCPU_MASK
549 | UVD_CGC_GATE__SCPU_MASK);
550 WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data);
551
552 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
553 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK
554 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
555 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
556 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
557 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
558 | UVD_CGC_CTRL__SYS_MODE_MASK
559 | UVD_CGC_CTRL__UDEC_MODE_MASK
560 | UVD_CGC_CTRL__MPEG2_MODE_MASK
561 | UVD_CGC_CTRL__REGS_MODE_MASK
562 | UVD_CGC_CTRL__RBC_MODE_MASK
563 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
564 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
565 | UVD_CGC_CTRL__IDCT_MODE_MASK
566 | UVD_CGC_CTRL__MPRD_MODE_MASK
567 | UVD_CGC_CTRL__MPC_MODE_MASK
568 | UVD_CGC_CTRL__LBSI_MODE_MASK
569 | UVD_CGC_CTRL__LRBBM_MODE_MASK
570 | UVD_CGC_CTRL__WCB_MODE_MASK
571 | UVD_CGC_CTRL__VCPU_MODE_MASK
572 | UVD_CGC_CTRL__SCPU_MODE_MASK);
573 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
574
575 /* turn on */
576 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE);
577 data |= (UVD_SUVD_CGC_GATE__SRE_MASK
578 | UVD_SUVD_CGC_GATE__SIT_MASK
579 | UVD_SUVD_CGC_GATE__SMP_MASK
580 | UVD_SUVD_CGC_GATE__SCM_MASK
581 | UVD_SUVD_CGC_GATE__SDB_MASK
582 | UVD_SUVD_CGC_GATE__SRE_H264_MASK
583 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
584 | UVD_SUVD_CGC_GATE__SIT_H264_MASK
585 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
586 | UVD_SUVD_CGC_GATE__SCM_H264_MASK
587 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
588 | UVD_SUVD_CGC_GATE__SDB_H264_MASK
589 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
590 | UVD_SUVD_CGC_GATE__SCLR_MASK
591 | UVD_SUVD_CGC_GATE__UVD_SC_MASK
592 | UVD_SUVD_CGC_GATE__ENT_MASK
593 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
594 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
595 | UVD_SUVD_CGC_GATE__SITE_MASK
596 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK
597 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK
598 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
599 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK
600 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK);
601 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data);
602
603 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);
604 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
605 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
606 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
607 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
608 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
609 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
610 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
611 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
612 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
613 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
614 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);
615 }
616
617 /**
618 * vcn_v1_0_enable_clock_gating - enable VCN clock gating
619 *
620 * @adev: amdgpu_device pointer
621 *
622 * Enable clock gating for VCN block
623 */
vcn_v1_0_enable_clock_gating(struct amdgpu_device * adev)624 static void vcn_v1_0_enable_clock_gating(struct amdgpu_device *adev)
625 {
626 uint32_t data = 0;
627
628 /* enable JPEG CGC */
629 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL);
630 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
631 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
632 else
633 data |= 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
634 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
635 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
636 WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data);
637
638 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE);
639 data |= (JPEG_CGC_GATE__JPEG_MASK | JPEG_CGC_GATE__JPEG2_MASK);
640 WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data);
641
642 /* enable UVD CGC */
643 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
644 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
645 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
646 else
647 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
648 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
649 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
650 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
651
652 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
653 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK
654 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
655 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
656 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
657 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
658 | UVD_CGC_CTRL__SYS_MODE_MASK
659 | UVD_CGC_CTRL__UDEC_MODE_MASK
660 | UVD_CGC_CTRL__MPEG2_MODE_MASK
661 | UVD_CGC_CTRL__REGS_MODE_MASK
662 | UVD_CGC_CTRL__RBC_MODE_MASK
663 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
664 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
665 | UVD_CGC_CTRL__IDCT_MODE_MASK
666 | UVD_CGC_CTRL__MPRD_MODE_MASK
667 | UVD_CGC_CTRL__MPC_MODE_MASK
668 | UVD_CGC_CTRL__LBSI_MODE_MASK
669 | UVD_CGC_CTRL__LRBBM_MODE_MASK
670 | UVD_CGC_CTRL__WCB_MODE_MASK
671 | UVD_CGC_CTRL__VCPU_MODE_MASK
672 | UVD_CGC_CTRL__SCPU_MODE_MASK);
673 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
674
675 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);
676 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
677 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
678 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
679 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
680 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
681 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
682 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
683 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
684 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
685 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
686 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);
687 }
688
vcn_v1_0_clock_gating_dpg_mode(struct amdgpu_device * adev,uint8_t sram_sel)689 static void vcn_v1_0_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel)
690 {
691 uint32_t reg_data = 0;
692
693 /* disable JPEG CGC */
694 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
695 reg_data = 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
696 else
697 reg_data = 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
698 reg_data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
699 reg_data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
700 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmJPEG_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel);
701
702 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmJPEG_CGC_GATE, 0, 0xFFFFFFFF, sram_sel);
703
704 /* enable sw clock gating control */
705 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
706 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
707 else
708 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
709 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
710 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
711 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
712 UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
713 UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
714 UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
715 UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
716 UVD_CGC_CTRL__SYS_MODE_MASK |
717 UVD_CGC_CTRL__UDEC_MODE_MASK |
718 UVD_CGC_CTRL__MPEG2_MODE_MASK |
719 UVD_CGC_CTRL__REGS_MODE_MASK |
720 UVD_CGC_CTRL__RBC_MODE_MASK |
721 UVD_CGC_CTRL__LMI_MC_MODE_MASK |
722 UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
723 UVD_CGC_CTRL__IDCT_MODE_MASK |
724 UVD_CGC_CTRL__MPRD_MODE_MASK |
725 UVD_CGC_CTRL__MPC_MODE_MASK |
726 UVD_CGC_CTRL__LBSI_MODE_MASK |
727 UVD_CGC_CTRL__LRBBM_MODE_MASK |
728 UVD_CGC_CTRL__WCB_MODE_MASK |
729 UVD_CGC_CTRL__VCPU_MODE_MASK |
730 UVD_CGC_CTRL__SCPU_MODE_MASK);
731 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel);
732
733 /* turn off clock gating */
734 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_CGC_GATE, 0, 0xFFFFFFFF, sram_sel);
735
736 /* turn on SUVD clock gating */
737 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SUVD_CGC_GATE, 1, 0xFFFFFFFF, sram_sel);
738
739 /* turn on sw mode in UVD_SUVD_CGC_CTRL */
740 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SUVD_CGC_CTRL, 0, 0xFFFFFFFF, sram_sel);
741 }
742
vcn_1_0_disable_static_power_gating(struct amdgpu_device * adev)743 static void vcn_1_0_disable_static_power_gating(struct amdgpu_device *adev)
744 {
745 uint32_t data = 0;
746
747 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
748 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
749 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
750 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
751 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
752 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
753 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
754 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
755 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
756 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
757 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
758 | 2 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT);
759
760 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
761 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON, 0xFFFFFF);
762 } else {
763 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
764 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
765 | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
766 | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
767 | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
768 | 1 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
769 | 1 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
770 | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
771 | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
772 | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
773 | 1 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT);
774 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
775 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0, 0xFFFFFFFF);
776 }
777
778 /* polling UVD_PGFSM_STATUS to confirm UVDM_PWR_STATUS , UVDU_PWR_STATUS are 0 (power on) */
779
780 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);
781 data &= ~0x103;
782 if (adev->pg_flags & AMD_PG_SUPPORT_VCN)
783 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | UVD_POWER_STATUS__UVD_PG_EN_MASK;
784
785 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);
786 }
787
vcn_1_0_enable_static_power_gating(struct amdgpu_device * adev)788 static void vcn_1_0_enable_static_power_gating(struct amdgpu_device *adev)
789 {
790 uint32_t data = 0;
791
792 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
793 /* Before power off, this indicator has to be turned on */
794 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);
795 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK;
796 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF;
797 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);
798
799
800 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
801 | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
802 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
803 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
804 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
805 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
806 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
807 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
808 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
809 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
810 | 2 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT);
811
812 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
813
814 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT
815 | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT
816 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT
817 | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT
818 | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT
819 | 2 << UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT
820 | 2 << UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT
821 | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT
822 | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT
823 | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT
824 | 2 << UVD_PGFSM_STATUS__UVDW_PWR_STATUS__SHIFT);
825 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFFFFF);
826 }
827 }
828
829 /**
830 * vcn_v1_0_start_spg_mode - start VCN block
831 *
832 * @adev: amdgpu_device pointer
833 *
834 * Setup and start the VCN block
835 */
vcn_v1_0_start_spg_mode(struct amdgpu_device * adev)836 static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev)
837 {
838 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
839 uint32_t rb_bufsz, tmp;
840 uint32_t lmi_swap_cntl;
841 int i, j, r;
842
843 /* disable byte swapping */
844 lmi_swap_cntl = 0;
845
846 vcn_1_0_disable_static_power_gating(adev);
847
848 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;
849 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp);
850
851 /* disable clock gating */
852 vcn_v1_0_disable_clock_gating(adev);
853
854 /* disable interupt */
855 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,
856 ~UVD_MASTINT_EN__VCPU_EN_MASK);
857
858 /* initialize VCN memory controller */
859 tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL);
860 WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp |
861 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
862 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
863 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
864 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
865
866 #ifdef __BIG_ENDIAN
867 /* swap (8 in 32) RB and IB */
868 lmi_swap_cntl = 0xa;
869 #endif
870 WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
871
872 tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL);
873 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
874 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
875 WREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL, tmp);
876
877 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0,
878 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
879 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
880 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
881 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
882
883 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0,
884 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
885 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
886 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
887 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
888
889 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX,
890 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
891 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
892 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
893
894 vcn_v1_0_mc_resume_spg_mode(adev);
895
896 WREG32_SOC15(UVD, 0, mmUVD_REG_XX_MASK_1_0, 0x10);
897 WREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK_1_0,
898 RREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK_1_0) | 0x3);
899
900 /* enable VCPU clock */
901 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK);
902
903 /* boot up the VCPU */
904 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
905 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
906
907 /* enable UMC */
908 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
909 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
910
911 tmp = RREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET);
912 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
913 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
914 WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, tmp);
915
916 for (i = 0; i < 10; ++i) {
917 uint32_t status;
918
919 for (j = 0; j < 100; ++j) {
920 status = RREG32_SOC15(UVD, 0, mmUVD_STATUS);
921 if (status & UVD_STATUS__IDLE)
922 break;
923 mdelay(10);
924 }
925 r = 0;
926 if (status & UVD_STATUS__IDLE)
927 break;
928
929 DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n");
930 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
931 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
932 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
933 mdelay(10);
934 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
935 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
936 mdelay(10);
937 r = -1;
938 }
939
940 if (r) {
941 DRM_ERROR("VCN decode not responding, giving up!!!\n");
942 return r;
943 }
944 /* enable master interrupt */
945 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),
946 UVD_MASTINT_EN__VCPU_EN_MASK, ~UVD_MASTINT_EN__VCPU_EN_MASK);
947
948 /* enable system interrupt for JRBC, TODO: move to set interrupt*/
949 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SYS_INT_EN),
950 UVD_SYS_INT_EN__UVD_JRBC_EN_MASK,
951 ~UVD_SYS_INT_EN__UVD_JRBC_EN_MASK);
952
953 /* clear the busy bit of UVD_STATUS */
954 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) & ~UVD_STATUS__UVD_BUSY;
955 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp);
956
957 /* force RBC into idle state */
958 rb_bufsz = order_base_2(ring->ring_size);
959 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
960 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
961 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
962 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
963 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
964 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
965
966 /* set the write pointer delay */
967 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0);
968
969 /* set the wb address */
970 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR,
971 (upper_32_bits(ring->gpu_addr) >> 2));
972
973 /* program the RB_BASE for ring buffer */
974 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
975 lower_32_bits(ring->gpu_addr));
976 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
977 upper_32_bits(ring->gpu_addr));
978
979 /* Initialize the ring buffer's read and write pointers */
980 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
981
982 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0);
983
984 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
985 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
986 lower_32_bits(ring->wptr));
987
988 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0,
989 ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
990
991 ring = &adev->vcn.inst->ring_enc[0];
992 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
993 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
994 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
995 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
996 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
997
998 ring = &adev->vcn.inst->ring_enc[1];
999 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1000 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1001 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1002 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1003 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
1004
1005 jpeg_v1_0_start(adev, 0);
1006
1007 return 0;
1008 }
1009
vcn_v1_0_start_dpg_mode(struct amdgpu_device * adev)1010 static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev)
1011 {
1012 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
1013 uint32_t rb_bufsz, tmp;
1014 uint32_t lmi_swap_cntl;
1015
1016 /* disable byte swapping */
1017 lmi_swap_cntl = 0;
1018
1019 vcn_1_0_enable_static_power_gating(adev);
1020
1021 /* enable dynamic power gating mode */
1022 tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);
1023 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
1024 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK;
1025 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp);
1026
1027 /* enable clock gating */
1028 vcn_v1_0_clock_gating_dpg_mode(adev, 0);
1029
1030 /* enable VCPU clock */
1031 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
1032 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
1033 tmp |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK;
1034 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CNTL, tmp, 0xFFFFFFFF, 0);
1035
1036 /* disable interupt */
1037 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MASTINT_EN,
1038 0, UVD_MASTINT_EN__VCPU_EN_MASK, 0);
1039
1040 /* initialize VCN memory controller */
1041 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_CTRL,
1042 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
1043 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
1044 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
1045 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
1046 UVD_LMI_CTRL__REQ_MODE_MASK |
1047 UVD_LMI_CTRL__CRC_RESET_MASK |
1048 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
1049 0x00100000L, 0xFFFFFFFF, 0);
1050
1051 #ifdef __BIG_ENDIAN
1052 /* swap (8 in 32) RB and IB */
1053 lmi_swap_cntl = 0xa;
1054 #endif
1055 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl, 0xFFFFFFFF, 0);
1056
1057 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_CNTL,
1058 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0xFFFFFFFF, 0);
1059
1060 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_SET_MUXA0,
1061 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
1062 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
1063 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
1064 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0xFFFFFFFF, 0);
1065
1066 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_SET_MUXB0,
1067 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
1068 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
1069 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
1070 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0xFFFFFFFF, 0);
1071
1072 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_SET_MUX,
1073 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
1074 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
1075 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0xFFFFFFFF, 0);
1076
1077 vcn_v1_0_mc_resume_dpg_mode(adev);
1078
1079 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_REG_XX_MASK, 0x10, 0xFFFFFFFF, 0);
1080 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK, 0x3, 0xFFFFFFFF, 0);
1081
1082 /* boot up the VCPU */
1083 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SOFT_RESET, 0, 0xFFFFFFFF, 0);
1084
1085 /* enable UMC */
1086 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_CTRL2,
1087 0x1F << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT,
1088 0xFFFFFFFF, 0);
1089
1090 /* enable master interrupt */
1091 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MASTINT_EN,
1092 UVD_MASTINT_EN__VCPU_EN_MASK, UVD_MASTINT_EN__VCPU_EN_MASK, 0);
1093
1094 vcn_v1_0_clock_gating_dpg_mode(adev, 1);
1095 /* setup mmUVD_LMI_CTRL */
1096 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_CTRL,
1097 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
1098 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
1099 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
1100 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
1101 UVD_LMI_CTRL__REQ_MODE_MASK |
1102 UVD_LMI_CTRL__CRC_RESET_MASK |
1103 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
1104 0x00100000L, 0xFFFFFFFF, 1);
1105
1106 tmp = adev->gfx.config.gb_addr_config;
1107 /* setup VCN global tiling registers */
1108 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_JPEG_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1);
1109 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1);
1110
1111 /* enable System Interrupt for JRBC */
1112 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SYS_INT_EN,
1113 UVD_SYS_INT_EN__UVD_JRBC_EN_MASK, 0xFFFFFFFF, 1);
1114
1115 /* force RBC into idle state */
1116 rb_bufsz = order_base_2(ring->ring_size);
1117 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
1118 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1119 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1120 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1121 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1122 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
1123
1124 /* set the write pointer delay */
1125 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0);
1126
1127 /* set the wb address */
1128 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR,
1129 (upper_32_bits(ring->gpu_addr) >> 2));
1130
1131 /* program the RB_BASE for ring buffer */
1132 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
1133 lower_32_bits(ring->gpu_addr));
1134 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
1135 upper_32_bits(ring->gpu_addr));
1136
1137 /* Initialize the ring buffer's read and write pointers */
1138 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
1139
1140 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0);
1141
1142 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1143 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
1144 lower_32_bits(ring->wptr));
1145
1146 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0,
1147 ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
1148
1149 jpeg_v1_0_start(adev, 1);
1150
1151 return 0;
1152 }
1153
vcn_v1_0_start(struct amdgpu_device * adev)1154 static int vcn_v1_0_start(struct amdgpu_device *adev)
1155 {
1156 return (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ?
1157 vcn_v1_0_start_dpg_mode(adev) : vcn_v1_0_start_spg_mode(adev);
1158 }
1159
1160 /**
1161 * vcn_v1_0_stop_spg_mode - stop VCN block
1162 *
1163 * @adev: amdgpu_device pointer
1164 *
1165 * stop the VCN block
1166 */
vcn_v1_0_stop_spg_mode(struct amdgpu_device * adev)1167 static int vcn_v1_0_stop_spg_mode(struct amdgpu_device *adev)
1168 {
1169 int tmp;
1170
1171 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7);
1172
1173 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
1174 UVD_LMI_STATUS__READ_CLEAN_MASK |
1175 UVD_LMI_STATUS__WRITE_CLEAN_MASK |
1176 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
1177 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp);
1178
1179 /* stall UMC channel */
1180 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2),
1181 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
1182 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
1183
1184 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |
1185 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
1186 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp);
1187
1188 /* disable VCPU clock */
1189 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0,
1190 ~UVD_VCPU_CNTL__CLK_EN_MASK);
1191
1192 /* reset LMI UMC/LMI */
1193 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1194 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK,
1195 ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
1196
1197 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1198 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK,
1199 ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK);
1200
1201 /* put VCPU into reset */
1202 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1203 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
1204 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1205
1206 WREG32_SOC15(UVD, 0, mmUVD_STATUS, 0);
1207
1208 vcn_v1_0_enable_clock_gating(adev);
1209 vcn_1_0_enable_static_power_gating(adev);
1210 return 0;
1211 }
1212
vcn_v1_0_stop_dpg_mode(struct amdgpu_device * adev)1213 static int vcn_v1_0_stop_dpg_mode(struct amdgpu_device *adev)
1214 {
1215 uint32_t tmp;
1216
1217 /* Wait for power status to be UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF */
1218 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1219 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
1220 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1221
1222 /* wait for read ptr to be equal to write ptr */
1223 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
1224 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF);
1225
1226 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
1227 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF);
1228
1229 tmp = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
1230 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_JRBC_RB_RPTR, tmp, 0xFFFFFFFF);
1231
1232 tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;
1233 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF);
1234
1235 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1236 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
1237 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1238
1239 /* disable dynamic power gating mode */
1240 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0,
1241 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
1242
1243 return 0;
1244 }
1245
vcn_v1_0_stop(struct amdgpu_device * adev)1246 static int vcn_v1_0_stop(struct amdgpu_device *adev)
1247 {
1248 int r;
1249
1250 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
1251 r = vcn_v1_0_stop_dpg_mode(adev);
1252 else
1253 r = vcn_v1_0_stop_spg_mode(adev);
1254
1255 return r;
1256 }
1257
vcn_v1_0_pause_dpg_mode(struct amdgpu_device * adev,int inst_idx,struct dpg_pause_state * new_state)1258 static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev,
1259 int inst_idx, struct dpg_pause_state *new_state)
1260 {
1261 int ret_code;
1262 uint32_t reg_data = 0;
1263 uint32_t reg_data2 = 0;
1264 struct amdgpu_ring *ring;
1265
1266 /* pause/unpause if state is changed */
1267 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {
1268 DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d",
1269 adev->vcn.inst[inst_idx].pause_state.fw_based,
1270 adev->vcn.inst[inst_idx].pause_state.jpeg,
1271 new_state->fw_based, new_state->jpeg);
1272
1273 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) &
1274 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1275
1276 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) {
1277 ret_code = 0;
1278
1279 if (!(reg_data & UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK))
1280 ret_code = SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1281 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
1282 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1283
1284 if (!ret_code) {
1285 /* pause DPG non-jpeg */
1286 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1287 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
1288 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE,
1289 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK,
1290 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1291
1292 /* Restore */
1293 ring = &adev->vcn.inst->ring_enc[0];
1294 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
1295 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1296 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
1297 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1298 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1299
1300 ring = &adev->vcn.inst->ring_enc[1];
1301 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1302 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1303 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
1304 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1305 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1306
1307 ring = &adev->vcn.inst->ring_dec;
1308 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
1309 RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF);
1310 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1311 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON,
1312 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1313 }
1314 } else {
1315 /* unpause dpg non-jpeg, no need to wait */
1316 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1317 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
1318 }
1319 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;
1320 }
1321
1322 /* pause/unpause if state is changed */
1323 if (adev->vcn.inst[inst_idx].pause_state.jpeg != new_state->jpeg) {
1324 DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d",
1325 adev->vcn.inst[inst_idx].pause_state.fw_based,
1326 adev->vcn.inst[inst_idx].pause_state.jpeg,
1327 new_state->fw_based, new_state->jpeg);
1328
1329 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) &
1330 (~UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK);
1331
1332 if (new_state->jpeg == VCN_DPG_STATE__PAUSE) {
1333 ret_code = 0;
1334
1335 if (!(reg_data & UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK))
1336 ret_code = SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1337 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
1338 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1339
1340 if (!ret_code) {
1341 /* Make sure JPRG Snoop is disabled before sending the pause */
1342 reg_data2 = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);
1343 reg_data2 |= UVD_POWER_STATUS__JRBC_SNOOP_DIS_MASK;
1344 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, reg_data2);
1345
1346 /* pause DPG jpeg */
1347 reg_data |= UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK;
1348 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
1349 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE,
1350 UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK,
1351 UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK);
1352
1353 /* Restore */
1354 ring = adev->jpeg.inst->ring_dec;
1355 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
1356 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL,
1357 UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK |
1358 UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
1359 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
1360 lower_32_bits(ring->gpu_addr));
1361 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
1362 upper_32_bits(ring->gpu_addr));
1363 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, ring->wptr);
1364 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, ring->wptr);
1365 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL,
1366 UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
1367
1368 ring = &adev->vcn.inst->ring_dec;
1369 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
1370 RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF);
1371 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1372 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON,
1373 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1374 }
1375 } else {
1376 /* unpause dpg jpeg, no need to wait */
1377 reg_data &= ~UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK;
1378 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
1379 }
1380 adev->vcn.inst[inst_idx].pause_state.jpeg = new_state->jpeg;
1381 }
1382
1383 return 0;
1384 }
1385
vcn_v1_0_is_idle(void * handle)1386 static bool vcn_v1_0_is_idle(void *handle)
1387 {
1388 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1389
1390 return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE);
1391 }
1392
vcn_v1_0_wait_for_idle(void * handle)1393 static int vcn_v1_0_wait_for_idle(void *handle)
1394 {
1395 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1396 int ret;
1397
1398 ret = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE,
1399 UVD_STATUS__IDLE);
1400
1401 return ret;
1402 }
1403
vcn_v1_0_set_clockgating_state(void * handle,enum amd_clockgating_state state)1404 static int vcn_v1_0_set_clockgating_state(void *handle,
1405 enum amd_clockgating_state state)
1406 {
1407 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1408 bool enable = (state == AMD_CG_STATE_GATE);
1409
1410 if (enable) {
1411 /* wait for STATUS to clear */
1412 if (!vcn_v1_0_is_idle(handle))
1413 return -EBUSY;
1414 vcn_v1_0_enable_clock_gating(adev);
1415 } else {
1416 /* disable HW gating and enable Sw gating */
1417 vcn_v1_0_disable_clock_gating(adev);
1418 }
1419 return 0;
1420 }
1421
1422 /**
1423 * vcn_v1_0_dec_ring_get_rptr - get read pointer
1424 *
1425 * @ring: amdgpu_ring pointer
1426 *
1427 * Returns the current hardware read pointer
1428 */
vcn_v1_0_dec_ring_get_rptr(struct amdgpu_ring * ring)1429 static uint64_t vcn_v1_0_dec_ring_get_rptr(struct amdgpu_ring *ring)
1430 {
1431 struct amdgpu_device *adev = ring->adev;
1432
1433 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1434 }
1435
1436 /**
1437 * vcn_v1_0_dec_ring_get_wptr - get write pointer
1438 *
1439 * @ring: amdgpu_ring pointer
1440 *
1441 * Returns the current hardware write pointer
1442 */
vcn_v1_0_dec_ring_get_wptr(struct amdgpu_ring * ring)1443 static uint64_t vcn_v1_0_dec_ring_get_wptr(struct amdgpu_ring *ring)
1444 {
1445 struct amdgpu_device *adev = ring->adev;
1446
1447 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR);
1448 }
1449
1450 /**
1451 * vcn_v1_0_dec_ring_set_wptr - set write pointer
1452 *
1453 * @ring: amdgpu_ring pointer
1454 *
1455 * Commits the write pointer to the hardware
1456 */
vcn_v1_0_dec_ring_set_wptr(struct amdgpu_ring * ring)1457 static void vcn_v1_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
1458 {
1459 struct amdgpu_device *adev = ring->adev;
1460
1461 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
1462 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2,
1463 lower_32_bits(ring->wptr) | 0x80000000);
1464
1465 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
1466 }
1467
1468 /**
1469 * vcn_v1_0_dec_ring_insert_start - insert a start command
1470 *
1471 * @ring: amdgpu_ring pointer
1472 *
1473 * Write a start command to the ring.
1474 */
vcn_v1_0_dec_ring_insert_start(struct amdgpu_ring * ring)1475 static void vcn_v1_0_dec_ring_insert_start(struct amdgpu_ring *ring)
1476 {
1477 struct amdgpu_device *adev = ring->adev;
1478
1479 amdgpu_ring_write(ring,
1480 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1481 amdgpu_ring_write(ring, 0);
1482 amdgpu_ring_write(ring,
1483 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1484 amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_START << 1);
1485 }
1486
1487 /**
1488 * vcn_v1_0_dec_ring_insert_end - insert a end command
1489 *
1490 * @ring: amdgpu_ring pointer
1491 *
1492 * Write a end command to the ring.
1493 */
vcn_v1_0_dec_ring_insert_end(struct amdgpu_ring * ring)1494 static void vcn_v1_0_dec_ring_insert_end(struct amdgpu_ring *ring)
1495 {
1496 struct amdgpu_device *adev = ring->adev;
1497
1498 amdgpu_ring_write(ring,
1499 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1500 amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_END << 1);
1501 }
1502
1503 /**
1504 * vcn_v1_0_dec_ring_emit_fence - emit an fence & trap command
1505 *
1506 * @ring: amdgpu_ring pointer
1507 * @addr: address
1508 * @seq: sequence number
1509 * @flags: fence related flags
1510 *
1511 * Write a fence and a trap command to the ring.
1512 */
vcn_v1_0_dec_ring_emit_fence(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned flags)1513 static void vcn_v1_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
1514 unsigned flags)
1515 {
1516 struct amdgpu_device *adev = ring->adev;
1517
1518 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1519
1520 amdgpu_ring_write(ring,
1521 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0));
1522 amdgpu_ring_write(ring, seq);
1523 amdgpu_ring_write(ring,
1524 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1525 amdgpu_ring_write(ring, addr & 0xffffffff);
1526 amdgpu_ring_write(ring,
1527 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1528 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
1529 amdgpu_ring_write(ring,
1530 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1531 amdgpu_ring_write(ring, VCN_DEC_CMD_FENCE << 1);
1532
1533 amdgpu_ring_write(ring,
1534 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1535 amdgpu_ring_write(ring, 0);
1536 amdgpu_ring_write(ring,
1537 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1538 amdgpu_ring_write(ring, 0);
1539 amdgpu_ring_write(ring,
1540 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1541 amdgpu_ring_write(ring, VCN_DEC_CMD_TRAP << 1);
1542 }
1543
1544 /**
1545 * vcn_v1_0_dec_ring_emit_ib - execute indirect buffer
1546 *
1547 * @ring: amdgpu_ring pointer
1548 * @job: job to retrieve vmid from
1549 * @ib: indirect buffer to execute
1550 * @flags: unused
1551 *
1552 * Write ring commands to execute the indirect buffer
1553 */
vcn_v1_0_dec_ring_emit_ib(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)1554 static void vcn_v1_0_dec_ring_emit_ib(struct amdgpu_ring *ring,
1555 struct amdgpu_job *job,
1556 struct amdgpu_ib *ib,
1557 uint32_t flags)
1558 {
1559 struct amdgpu_device *adev = ring->adev;
1560 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
1561
1562 amdgpu_ring_write(ring,
1563 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_VMID), 0));
1564 amdgpu_ring_write(ring, vmid);
1565
1566 amdgpu_ring_write(ring,
1567 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0));
1568 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1569 amdgpu_ring_write(ring,
1570 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0));
1571 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1572 amdgpu_ring_write(ring,
1573 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_IB_SIZE), 0));
1574 amdgpu_ring_write(ring, ib->length_dw);
1575 }
1576
vcn_v1_0_dec_ring_emit_reg_wait(struct amdgpu_ring * ring,uint32_t reg,uint32_t val,uint32_t mask)1577 static void vcn_v1_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring,
1578 uint32_t reg, uint32_t val,
1579 uint32_t mask)
1580 {
1581 struct amdgpu_device *adev = ring->adev;
1582
1583 amdgpu_ring_write(ring,
1584 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1585 amdgpu_ring_write(ring, reg << 2);
1586 amdgpu_ring_write(ring,
1587 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1588 amdgpu_ring_write(ring, val);
1589 amdgpu_ring_write(ring,
1590 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GP_SCRATCH8), 0));
1591 amdgpu_ring_write(ring, mask);
1592 amdgpu_ring_write(ring,
1593 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1594 amdgpu_ring_write(ring, VCN_DEC_CMD_REG_READ_COND_WAIT << 1);
1595 }
1596
vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring * ring,unsigned vmid,uint64_t pd_addr)1597 static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
1598 unsigned vmid, uint64_t pd_addr)
1599 {
1600 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub];
1601 uint32_t data0, data1, mask;
1602
1603 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1604
1605 /* wait for register write */
1606 data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance;
1607 data1 = lower_32_bits(pd_addr);
1608 mask = 0xffffffff;
1609 vcn_v1_0_dec_ring_emit_reg_wait(ring, data0, data1, mask);
1610 }
1611
vcn_v1_0_dec_ring_emit_wreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t val)1612 static void vcn_v1_0_dec_ring_emit_wreg(struct amdgpu_ring *ring,
1613 uint32_t reg, uint32_t val)
1614 {
1615 struct amdgpu_device *adev = ring->adev;
1616
1617 amdgpu_ring_write(ring,
1618 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1619 amdgpu_ring_write(ring, reg << 2);
1620 amdgpu_ring_write(ring,
1621 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1622 amdgpu_ring_write(ring, val);
1623 amdgpu_ring_write(ring,
1624 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1625 amdgpu_ring_write(ring, VCN_DEC_CMD_WRITE_REG << 1);
1626 }
1627
1628 /**
1629 * vcn_v1_0_enc_ring_get_rptr - get enc read pointer
1630 *
1631 * @ring: amdgpu_ring pointer
1632 *
1633 * Returns the current hardware enc read pointer
1634 */
vcn_v1_0_enc_ring_get_rptr(struct amdgpu_ring * ring)1635 static uint64_t vcn_v1_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
1636 {
1637 struct amdgpu_device *adev = ring->adev;
1638
1639 if (ring == &adev->vcn.inst->ring_enc[0])
1640 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR);
1641 else
1642 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2);
1643 }
1644
1645 /**
1646 * vcn_v1_0_enc_ring_get_wptr - get enc write pointer
1647 *
1648 * @ring: amdgpu_ring pointer
1649 *
1650 * Returns the current hardware enc write pointer
1651 */
vcn_v1_0_enc_ring_get_wptr(struct amdgpu_ring * ring)1652 static uint64_t vcn_v1_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
1653 {
1654 struct amdgpu_device *adev = ring->adev;
1655
1656 if (ring == &adev->vcn.inst->ring_enc[0])
1657 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
1658 else
1659 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
1660 }
1661
1662 /**
1663 * vcn_v1_0_enc_ring_set_wptr - set enc write pointer
1664 *
1665 * @ring: amdgpu_ring pointer
1666 *
1667 * Commits the enc write pointer to the hardware
1668 */
vcn_v1_0_enc_ring_set_wptr(struct amdgpu_ring * ring)1669 static void vcn_v1_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
1670 {
1671 struct amdgpu_device *adev = ring->adev;
1672
1673 if (ring == &adev->vcn.inst->ring_enc[0])
1674 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR,
1675 lower_32_bits(ring->wptr));
1676 else
1677 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2,
1678 lower_32_bits(ring->wptr));
1679 }
1680
1681 /**
1682 * vcn_v1_0_enc_ring_emit_fence - emit an enc fence & trap command
1683 *
1684 * @ring: amdgpu_ring pointer
1685 * @addr: address
1686 * @seq: sequence number
1687 * @flags: fence related flags
1688 *
1689 * Write enc a fence and a trap command to the ring.
1690 */
vcn_v1_0_enc_ring_emit_fence(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned flags)1691 static void vcn_v1_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1692 u64 seq, unsigned flags)
1693 {
1694 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1695
1696 amdgpu_ring_write(ring, VCN_ENC_CMD_FENCE);
1697 amdgpu_ring_write(ring, addr);
1698 amdgpu_ring_write(ring, upper_32_bits(addr));
1699 amdgpu_ring_write(ring, seq);
1700 amdgpu_ring_write(ring, VCN_ENC_CMD_TRAP);
1701 }
1702
vcn_v1_0_enc_ring_insert_end(struct amdgpu_ring * ring)1703 static void vcn_v1_0_enc_ring_insert_end(struct amdgpu_ring *ring)
1704 {
1705 amdgpu_ring_write(ring, VCN_ENC_CMD_END);
1706 }
1707
1708 /**
1709 * vcn_v1_0_enc_ring_emit_ib - enc execute indirect buffer
1710 *
1711 * @ring: amdgpu_ring pointer
1712 * @job: job to retrive vmid from
1713 * @ib: indirect buffer to execute
1714 * @flags: unused
1715 *
1716 * Write enc ring commands to execute the indirect buffer
1717 */
vcn_v1_0_enc_ring_emit_ib(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)1718 static void vcn_v1_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
1719 struct amdgpu_job *job,
1720 struct amdgpu_ib *ib,
1721 uint32_t flags)
1722 {
1723 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
1724
1725 amdgpu_ring_write(ring, VCN_ENC_CMD_IB);
1726 amdgpu_ring_write(ring, vmid);
1727 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1728 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1729 amdgpu_ring_write(ring, ib->length_dw);
1730 }
1731
vcn_v1_0_enc_ring_emit_reg_wait(struct amdgpu_ring * ring,uint32_t reg,uint32_t val,uint32_t mask)1732 static void vcn_v1_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring,
1733 uint32_t reg, uint32_t val,
1734 uint32_t mask)
1735 {
1736 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT);
1737 amdgpu_ring_write(ring, reg << 2);
1738 amdgpu_ring_write(ring, mask);
1739 amdgpu_ring_write(ring, val);
1740 }
1741
vcn_v1_0_enc_ring_emit_vm_flush(struct amdgpu_ring * ring,unsigned int vmid,uint64_t pd_addr)1742 static void vcn_v1_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
1743 unsigned int vmid, uint64_t pd_addr)
1744 {
1745 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub];
1746
1747 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1748
1749 /* wait for reg writes */
1750 vcn_v1_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 +
1751 vmid * hub->ctx_addr_distance,
1752 lower_32_bits(pd_addr), 0xffffffff);
1753 }
1754
vcn_v1_0_enc_ring_emit_wreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t val)1755 static void vcn_v1_0_enc_ring_emit_wreg(struct amdgpu_ring *ring,
1756 uint32_t reg, uint32_t val)
1757 {
1758 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE);
1759 amdgpu_ring_write(ring, reg << 2);
1760 amdgpu_ring_write(ring, val);
1761 }
1762
vcn_v1_0_set_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)1763 static int vcn_v1_0_set_interrupt_state(struct amdgpu_device *adev,
1764 struct amdgpu_irq_src *source,
1765 unsigned type,
1766 enum amdgpu_interrupt_state state)
1767 {
1768 return 0;
1769 }
1770
vcn_v1_0_process_interrupt(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1771 static int vcn_v1_0_process_interrupt(struct amdgpu_device *adev,
1772 struct amdgpu_irq_src *source,
1773 struct amdgpu_iv_entry *entry)
1774 {
1775 DRM_DEBUG("IH: VCN TRAP\n");
1776
1777 switch (entry->src_id) {
1778 case 124:
1779 amdgpu_fence_process(&adev->vcn.inst->ring_dec);
1780 break;
1781 case 119:
1782 amdgpu_fence_process(&adev->vcn.inst->ring_enc[0]);
1783 break;
1784 case 120:
1785 amdgpu_fence_process(&adev->vcn.inst->ring_enc[1]);
1786 break;
1787 default:
1788 DRM_ERROR("Unhandled interrupt: %d %d\n",
1789 entry->src_id, entry->src_data[0]);
1790 break;
1791 }
1792
1793 return 0;
1794 }
1795
vcn_v1_0_dec_ring_insert_nop(struct amdgpu_ring * ring,uint32_t count)1796 static void vcn_v1_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
1797 {
1798 struct amdgpu_device *adev = ring->adev;
1799 int i;
1800
1801 WARN_ON(ring->wptr % 2 || count % 2);
1802
1803 for (i = 0; i < count / 2; i++) {
1804 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0));
1805 amdgpu_ring_write(ring, 0);
1806 }
1807 }
1808
vcn_v1_0_set_powergating_state(void * handle,enum amd_powergating_state state)1809 static int vcn_v1_0_set_powergating_state(void *handle,
1810 enum amd_powergating_state state)
1811 {
1812 /* This doesn't actually powergate the VCN block.
1813 * That's done in the dpm code via the SMC. This
1814 * just re-inits the block as necessary. The actual
1815 * gating still happens in the dpm code. We should
1816 * revisit this when there is a cleaner line between
1817 * the smc and the hw blocks
1818 */
1819 int ret;
1820 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1821
1822 if (state == adev->vcn.cur_state)
1823 return 0;
1824
1825 if (state == AMD_PG_STATE_GATE)
1826 ret = vcn_v1_0_stop(adev);
1827 else
1828 ret = vcn_v1_0_start(adev);
1829
1830 if (!ret)
1831 adev->vcn.cur_state = state;
1832 return ret;
1833 }
1834
vcn_v1_0_idle_work_handler(struct work_struct * work)1835 static void vcn_v1_0_idle_work_handler(struct work_struct *work)
1836 {
1837 struct amdgpu_device *adev =
1838 container_of(work, struct amdgpu_device, vcn.idle_work.work);
1839 unsigned int fences = 0, i;
1840
1841 for (i = 0; i < adev->vcn.num_enc_rings; ++i)
1842 fences += amdgpu_fence_count_emitted(&adev->vcn.inst->ring_enc[i]);
1843
1844 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1845 struct dpg_pause_state new_state;
1846
1847 if (fences)
1848 new_state.fw_based = VCN_DPG_STATE__PAUSE;
1849 else
1850 new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
1851
1852 if (amdgpu_fence_count_emitted(adev->jpeg.inst->ring_dec))
1853 new_state.jpeg = VCN_DPG_STATE__PAUSE;
1854 else
1855 new_state.jpeg = VCN_DPG_STATE__UNPAUSE;
1856
1857 adev->vcn.pause_dpg_mode(adev, 0, &new_state);
1858 }
1859
1860 fences += amdgpu_fence_count_emitted(adev->jpeg.inst->ring_dec);
1861 fences += amdgpu_fence_count_emitted(&adev->vcn.inst->ring_dec);
1862
1863 if (fences == 0) {
1864 amdgpu_gfx_off_ctrl(adev, true);
1865 if (adev->pm.dpm_enabled)
1866 amdgpu_dpm_enable_uvd(adev, false);
1867 else
1868 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
1869 AMD_PG_STATE_GATE);
1870 } else {
1871 schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
1872 }
1873 }
1874
vcn_v1_0_ring_begin_use(struct amdgpu_ring * ring)1875 static void vcn_v1_0_ring_begin_use(struct amdgpu_ring *ring)
1876 {
1877 struct amdgpu_device *adev = ring->adev;
1878 bool set_clocks = !cancel_delayed_work_sync(&adev->vcn.idle_work);
1879
1880 mutex_lock(&adev->vcn.vcn1_jpeg1_workaround);
1881
1882 if (amdgpu_fence_wait_empty(ring->adev->jpeg.inst->ring_dec))
1883 DRM_ERROR("VCN dec: jpeg dec ring may not be empty\n");
1884
1885 vcn_v1_0_set_pg_for_begin_use(ring, set_clocks);
1886
1887 }
1888
vcn_v1_0_set_pg_for_begin_use(struct amdgpu_ring * ring,bool set_clocks)1889 void vcn_v1_0_set_pg_for_begin_use(struct amdgpu_ring *ring, bool set_clocks)
1890 {
1891 struct amdgpu_device *adev = ring->adev;
1892
1893 if (set_clocks) {
1894 amdgpu_gfx_off_ctrl(adev, false);
1895 if (adev->pm.dpm_enabled)
1896 amdgpu_dpm_enable_uvd(adev, true);
1897 else
1898 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
1899 AMD_PG_STATE_UNGATE);
1900 }
1901
1902 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1903 struct dpg_pause_state new_state;
1904 unsigned int fences = 0, i;
1905
1906 for (i = 0; i < adev->vcn.num_enc_rings; ++i)
1907 fences += amdgpu_fence_count_emitted(&adev->vcn.inst->ring_enc[i]);
1908
1909 if (fences)
1910 new_state.fw_based = VCN_DPG_STATE__PAUSE;
1911 else
1912 new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
1913
1914 if (amdgpu_fence_count_emitted(adev->jpeg.inst->ring_dec))
1915 new_state.jpeg = VCN_DPG_STATE__PAUSE;
1916 else
1917 new_state.jpeg = VCN_DPG_STATE__UNPAUSE;
1918
1919 if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC)
1920 new_state.fw_based = VCN_DPG_STATE__PAUSE;
1921 else if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG)
1922 new_state.jpeg = VCN_DPG_STATE__PAUSE;
1923
1924 adev->vcn.pause_dpg_mode(adev, 0, &new_state);
1925 }
1926 }
1927
vcn_v1_0_ring_end_use(struct amdgpu_ring * ring)1928 void vcn_v1_0_ring_end_use(struct amdgpu_ring *ring)
1929 {
1930 schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
1931 mutex_unlock(&ring->adev->vcn.vcn1_jpeg1_workaround);
1932 }
1933
vcn_v1_0_print_ip_state(void * handle,struct drm_printer * p)1934 static void vcn_v1_0_print_ip_state(void *handle, struct drm_printer *p)
1935 {
1936 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1937 int i, j;
1938 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_1_0);
1939 uint32_t inst_off, is_powered;
1940
1941 if (!adev->vcn.ip_dump)
1942 return;
1943
1944 drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst);
1945 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1946 if (adev->vcn.harvest_config & (1 << i)) {
1947 drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i);
1948 continue;
1949 }
1950
1951 inst_off = i * reg_count;
1952 is_powered = (adev->vcn.ip_dump[inst_off] &
1953 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
1954
1955 if (is_powered) {
1956 drm_printf(p, "\nActive Instance:VCN%d\n", i);
1957 for (j = 0; j < reg_count; j++)
1958 drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_1_0[j].reg_name,
1959 adev->vcn.ip_dump[inst_off + j]);
1960 } else {
1961 drm_printf(p, "\nInactive Instance:VCN%d\n", i);
1962 }
1963 }
1964 }
1965
vcn_v1_0_dump_ip_state(void * handle)1966 static void vcn_v1_0_dump_ip_state(void *handle)
1967 {
1968 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1969 int i, j;
1970 bool is_powered;
1971 uint32_t inst_off;
1972 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_1_0);
1973
1974 if (!adev->vcn.ip_dump)
1975 return;
1976
1977 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1978 if (adev->vcn.harvest_config & (1 << i))
1979 continue;
1980
1981 inst_off = i * reg_count;
1982 /* mmUVD_POWER_STATUS is always readable and is first element of the array */
1983 adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, mmUVD_POWER_STATUS);
1984 is_powered = (adev->vcn.ip_dump[inst_off] &
1985 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
1986
1987 if (is_powered)
1988 for (j = 1; j < reg_count; j++)
1989 adev->vcn.ip_dump[inst_off + j] =
1990 RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_1_0[j], i));
1991 }
1992 }
1993
1994 static const struct amd_ip_funcs vcn_v1_0_ip_funcs = {
1995 .name = "vcn_v1_0",
1996 .early_init = vcn_v1_0_early_init,
1997 .late_init = NULL,
1998 .sw_init = vcn_v1_0_sw_init,
1999 .sw_fini = vcn_v1_0_sw_fini,
2000 .hw_init = vcn_v1_0_hw_init,
2001 .hw_fini = vcn_v1_0_hw_fini,
2002 .suspend = vcn_v1_0_suspend,
2003 .resume = vcn_v1_0_resume,
2004 .is_idle = vcn_v1_0_is_idle,
2005 .wait_for_idle = vcn_v1_0_wait_for_idle,
2006 .check_soft_reset = NULL /* vcn_v1_0_check_soft_reset */,
2007 .pre_soft_reset = NULL /* vcn_v1_0_pre_soft_reset */,
2008 .soft_reset = NULL /* vcn_v1_0_soft_reset */,
2009 .post_soft_reset = NULL /* vcn_v1_0_post_soft_reset */,
2010 .set_clockgating_state = vcn_v1_0_set_clockgating_state,
2011 .set_powergating_state = vcn_v1_0_set_powergating_state,
2012 .dump_ip_state = vcn_v1_0_dump_ip_state,
2013 .print_ip_state = vcn_v1_0_print_ip_state,
2014 };
2015
2016 /*
2017 * It is a hardware issue that VCN can't handle a GTT TMZ buffer on
2018 * CHIP_RAVEN series ASIC. Move such a GTT TMZ buffer to VRAM domain
2019 * before command submission as a workaround.
2020 */
vcn_v1_0_validate_bo(struct amdgpu_cs_parser * parser,struct amdgpu_job * job,uint64_t addr)2021 static int vcn_v1_0_validate_bo(struct amdgpu_cs_parser *parser,
2022 struct amdgpu_job *job,
2023 uint64_t addr)
2024 {
2025 struct ttm_operation_ctx ctx = { false, false };
2026 struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
2027 struct amdgpu_vm *vm = &fpriv->vm;
2028 struct amdgpu_bo_va_mapping *mapping;
2029 struct amdgpu_bo *bo;
2030 int r;
2031
2032 addr &= AMDGPU_GMC_HOLE_MASK;
2033 if (addr & 0x7) {
2034 DRM_ERROR("VCN messages must be 8 byte aligned!\n");
2035 return -EINVAL;
2036 }
2037
2038 mapping = amdgpu_vm_bo_lookup_mapping(vm, addr/AMDGPU_GPU_PAGE_SIZE);
2039 if (!mapping || !mapping->bo_va || !mapping->bo_va->base.bo)
2040 return -EINVAL;
2041
2042 bo = mapping->bo_va->base.bo;
2043 if (!(bo->flags & AMDGPU_GEM_CREATE_ENCRYPTED))
2044 return 0;
2045
2046 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM);
2047 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
2048 if (r) {
2049 DRM_ERROR("Failed to validate the VCN message BO (%d)!\n", r);
2050 return r;
2051 }
2052
2053 return r;
2054 }
2055
vcn_v1_0_ring_patch_cs_in_place(struct amdgpu_cs_parser * p,struct amdgpu_job * job,struct amdgpu_ib * ib)2056 static int vcn_v1_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p,
2057 struct amdgpu_job *job,
2058 struct amdgpu_ib *ib)
2059 {
2060 uint32_t msg_lo = 0, msg_hi = 0;
2061 int i, r;
2062
2063 if (!(ib->flags & AMDGPU_IB_FLAGS_SECURE))
2064 return 0;
2065
2066 for (i = 0; i < ib->length_dw; i += 2) {
2067 uint32_t reg = amdgpu_ib_get_value(ib, i);
2068 uint32_t val = amdgpu_ib_get_value(ib, i + 1);
2069
2070 if (reg == PACKET0(p->adev->vcn.internal.data0, 0)) {
2071 msg_lo = val;
2072 } else if (reg == PACKET0(p->adev->vcn.internal.data1, 0)) {
2073 msg_hi = val;
2074 } else if (reg == PACKET0(p->adev->vcn.internal.cmd, 0)) {
2075 r = vcn_v1_0_validate_bo(p, job,
2076 ((u64)msg_hi) << 32 | msg_lo);
2077 if (r)
2078 return r;
2079 }
2080 }
2081
2082 return 0;
2083 }
2084
2085 static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = {
2086 .type = AMDGPU_RING_TYPE_VCN_DEC,
2087 .align_mask = 0xf,
2088 .support_64bit_ptrs = false,
2089 .no_user_fence = true,
2090 .secure_submission_supported = true,
2091 .get_rptr = vcn_v1_0_dec_ring_get_rptr,
2092 .get_wptr = vcn_v1_0_dec_ring_get_wptr,
2093 .set_wptr = vcn_v1_0_dec_ring_set_wptr,
2094 .patch_cs_in_place = vcn_v1_0_ring_patch_cs_in_place,
2095 .emit_frame_size =
2096 6 + 6 + /* hdp invalidate / flush */
2097 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
2098 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
2099 8 + /* vcn_v1_0_dec_ring_emit_vm_flush */
2100 14 + 14 + /* vcn_v1_0_dec_ring_emit_fence x2 vm fence */
2101 6,
2102 .emit_ib_size = 8, /* vcn_v1_0_dec_ring_emit_ib */
2103 .emit_ib = vcn_v1_0_dec_ring_emit_ib,
2104 .emit_fence = vcn_v1_0_dec_ring_emit_fence,
2105 .emit_vm_flush = vcn_v1_0_dec_ring_emit_vm_flush,
2106 .test_ring = amdgpu_vcn_dec_ring_test_ring,
2107 .test_ib = amdgpu_vcn_dec_ring_test_ib,
2108 .insert_nop = vcn_v1_0_dec_ring_insert_nop,
2109 .insert_start = vcn_v1_0_dec_ring_insert_start,
2110 .insert_end = vcn_v1_0_dec_ring_insert_end,
2111 .pad_ib = amdgpu_ring_generic_pad_ib,
2112 .begin_use = vcn_v1_0_ring_begin_use,
2113 .end_use = vcn_v1_0_ring_end_use,
2114 .emit_wreg = vcn_v1_0_dec_ring_emit_wreg,
2115 .emit_reg_wait = vcn_v1_0_dec_ring_emit_reg_wait,
2116 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2117 };
2118
2119 static const struct amdgpu_ring_funcs vcn_v1_0_enc_ring_vm_funcs = {
2120 .type = AMDGPU_RING_TYPE_VCN_ENC,
2121 .align_mask = 0x3f,
2122 .nop = VCN_ENC_CMD_NO_OP,
2123 .support_64bit_ptrs = false,
2124 .no_user_fence = true,
2125 .get_rptr = vcn_v1_0_enc_ring_get_rptr,
2126 .get_wptr = vcn_v1_0_enc_ring_get_wptr,
2127 .set_wptr = vcn_v1_0_enc_ring_set_wptr,
2128 .emit_frame_size =
2129 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2130 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
2131 4 + /* vcn_v1_0_enc_ring_emit_vm_flush */
2132 5 + 5 + /* vcn_v1_0_enc_ring_emit_fence x2 vm fence */
2133 1, /* vcn_v1_0_enc_ring_insert_end */
2134 .emit_ib_size = 5, /* vcn_v1_0_enc_ring_emit_ib */
2135 .emit_ib = vcn_v1_0_enc_ring_emit_ib,
2136 .emit_fence = vcn_v1_0_enc_ring_emit_fence,
2137 .emit_vm_flush = vcn_v1_0_enc_ring_emit_vm_flush,
2138 .test_ring = amdgpu_vcn_enc_ring_test_ring,
2139 .test_ib = amdgpu_vcn_enc_ring_test_ib,
2140 .insert_nop = amdgpu_ring_insert_nop,
2141 .insert_end = vcn_v1_0_enc_ring_insert_end,
2142 .pad_ib = amdgpu_ring_generic_pad_ib,
2143 .begin_use = vcn_v1_0_ring_begin_use,
2144 .end_use = vcn_v1_0_ring_end_use,
2145 .emit_wreg = vcn_v1_0_enc_ring_emit_wreg,
2146 .emit_reg_wait = vcn_v1_0_enc_ring_emit_reg_wait,
2147 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2148 };
2149
vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device * adev)2150 static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev)
2151 {
2152 adev->vcn.inst->ring_dec.funcs = &vcn_v1_0_dec_ring_vm_funcs;
2153 }
2154
vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device * adev)2155 static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev)
2156 {
2157 int i;
2158
2159 for (i = 0; i < adev->vcn.num_enc_rings; ++i)
2160 adev->vcn.inst->ring_enc[i].funcs = &vcn_v1_0_enc_ring_vm_funcs;
2161 }
2162
2163 static const struct amdgpu_irq_src_funcs vcn_v1_0_irq_funcs = {
2164 .set = vcn_v1_0_set_interrupt_state,
2165 .process = vcn_v1_0_process_interrupt,
2166 };
2167
vcn_v1_0_set_irq_funcs(struct amdgpu_device * adev)2168 static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev)
2169 {
2170 adev->vcn.inst->irq.num_types = adev->vcn.num_enc_rings + 2;
2171 adev->vcn.inst->irq.funcs = &vcn_v1_0_irq_funcs;
2172 }
2173
2174 const struct amdgpu_ip_block_version vcn_v1_0_ip_block = {
2175 .type = AMD_IP_BLOCK_TYPE_VCN,
2176 .major = 1,
2177 .minor = 0,
2178 .rev = 0,
2179 .funcs = &vcn_v1_0_ip_funcs,
2180 };
2181