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Searched refs:inst_idx (Results 1 – 18 of 18) sorted by relevance

/openbsd/src/sys/dev/pci/drm/amd/amdgpu/
Dvcn_v4_0_5.c101 int inst_idx, struct dpg_pause_state *new_state);
431 static void vcn_v4_0_5_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) in vcn_v4_0_5_mc_resume_dpg_mode() argument
436 hdr = (const struct common_firmware_header *)adev->vcn.fw[inst_idx]->data; in vcn_v4_0_5_mc_resume_dpg_mode()
442 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_5_mc_resume_dpg_mode()
443 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), in vcn_v4_0_5_mc_resume_dpg_mode()
444 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), in vcn_v4_0_5_mc_resume_dpg_mode()
446 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_5_mc_resume_dpg_mode()
447 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), in vcn_v4_0_5_mc_resume_dpg_mode()
448 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), in vcn_v4_0_5_mc_resume_dpg_mode()
450 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_5_mc_resume_dpg_mode()
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Dvcn_v5_0_0.c84 int inst_idx, struct dpg_pause_state *new_state);
395 static void vcn_v5_0_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) in vcn_v5_0_0_mc_resume_dpg_mode() argument
400 hdr = (const struct common_firmware_header *)adev->vcn.fw[inst_idx]->data; in vcn_v5_0_0_mc_resume_dpg_mode()
406 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( in vcn_v5_0_0_mc_resume_dpg_mode()
407 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), in vcn_v5_0_0_mc_resume_dpg_mode()
408 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
409 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( in vcn_v5_0_0_mc_resume_dpg_mode()
410 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), in vcn_v5_0_0_mc_resume_dpg_mode()
411 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
412 WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( in vcn_v5_0_0_mc_resume_dpg_mode()
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Damdgpu_jpeg.h35 #define WREG32_SOC15_JPEG_DPG_MODE(inst_idx, offset, value, indirect) \ argument
38 WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx), \
41 JPEG, GET_INST(JPEG, inst_idx), \
47 *adev->jpeg.inst[inst_idx].dpg_sram_curr_addr++ = \
49 *adev->jpeg.inst[inst_idx].dpg_sram_curr_addr++ = \
54 #define RREG32_SOC15_JPEG_DPG_MODE(inst_idx, offset, mask_en) \ argument
56 WREG32_SOC15(JPEG, inst_idx, mmUVD_DPG_LMA_CTL, \
60 RREG32_SOC15(JPEG, inst_idx, mmUVD_DPG_LMA_DATA); \
63 #define WREG32_SOC24_JPEG_DPG_MODE(inst_idx, offset, value, indirect) \ argument
65 WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx), \
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Dvcn_v3_0.c111 int inst_idx, struct dpg_pause_state *new_state);
543 static void vcn_v3_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) in vcn_v3_0_mc_resume_dpg_mode() argument
545 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[inst_idx]->size + 4); in vcn_v3_0_mc_resume_dpg_mode()
551 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v3_0_mc_resume_dpg_mode()
552 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), in vcn_v3_0_mc_resume_dpg_mode()
553 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
554 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v3_0_mc_resume_dpg_mode()
555 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), in vcn_v3_0_mc_resume_dpg_mode()
556 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
557 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v3_0_mc_resume_dpg_mode()
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Dvcn_v4_0.c102 int inst_idx, struct dpg_pause_state *new_state);
139 static int vcn_v4_0_fw_shared_init(struct amdgpu_device *adev, int inst_idx) in vcn_v4_0_fw_shared_init() argument
143 fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; in vcn_v4_0_fw_shared_init()
159 amdgpu_vcn_fwlog_init(&adev->vcn.inst[inst_idx]); in vcn_v4_0_fw_shared_init()
483 static void vcn_v4_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) in vcn_v4_0_mc_resume_dpg_mode() argument
487 hdr = (const struct common_firmware_header *)adev->vcn.fw[inst_idx]->data; in vcn_v4_0_mc_resume_dpg_mode()
493 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_mc_resume_dpg_mode()
494 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), in vcn_v4_0_mc_resume_dpg_mode()
495 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
496 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_mc_resume_dpg_mode()
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Damdgpu_vcn.h81 #define RREG32_SOC15_DPG_MODE_1_0(ip, inst_idx, reg, mask, sram_sel) \ argument
82 ({ WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_MASK, mask); \
83 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_CTL, \
85 ((adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg) \
88 RREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_DATA); \
91 #define WREG32_SOC15_DPG_MODE_1_0(ip, inst_idx, reg, value, mask, sram_sel) \ argument
93 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_DATA, value); \
94 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_MASK, mask); \
95 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_CTL, \
97 ((adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg) \
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Dvcn_v2_5.c101 int inst_idx, struct dpg_pause_state *new_state);
517 static void vcn_v2_5_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) in vcn_v2_5_mc_resume_dpg_mode() argument
519 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[inst_idx]->size + 4); in vcn_v2_5_mc_resume_dpg_mode()
525 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v2_5_mc_resume_dpg_mode()
527 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
528 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v2_5_mc_resume_dpg_mode()
530 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
531 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v2_5_mc_resume_dpg_mode()
534 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v2_5_mc_resume_dpg_mode()
536 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v2_5_mc_resume_dpg_mode()
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Dvcn_v4_0_3.c93 int inst_idx, struct dpg_pause_state *new_state);
97 int inst_idx, bool indirect);
119 static int vcn_v4_0_3_fw_shared_init(struct amdgpu_device *adev, int inst_idx) in vcn_v4_0_3_fw_shared_init() argument
123 fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; in vcn_v4_0_3_fw_shared_init()
128 amdgpu_vcn_fwlog_init(&adev->vcn.inst[inst_idx]); in vcn_v4_0_3_fw_shared_init()
391 static void vcn_v4_0_3_mc_resume(struct amdgpu_device *adev, int inst_idx) in vcn_v4_0_3_mc_resume() argument
396 hdr = (const struct common_firmware_header *)adev->vcn.fw[inst_idx]->data; in vcn_v4_0_3_mc_resume()
399 vcn_inst = GET_INST(VCN, inst_idx); in vcn_v4_0_3_mc_resume()
404 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx] in vcn_v4_0_3_mc_resume()
408 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx] in vcn_v4_0_3_mc_resume()
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Djpeg_v5_0_0.c279 int inst_idx, uint8_t indirect) in jpeg_engine_5_0_0_dpg_clock_gating_mode() argument
293 ADD_SOC24_JPEG_TO_DPG_SRAM(inst_idx, vcnipJPEG_CGC_CTRL, data, indirect); in jpeg_engine_5_0_0_dpg_clock_gating_mode()
297 ADD_SOC24_JPEG_TO_DPG_SRAM(inst_idx, vcnipJPEG_CGC_GATE, data, indirect); in jpeg_engine_5_0_0_dpg_clock_gating_mode()
299 WREG32_SOC24_JPEG_DPG_MODE(inst_idx, vcnipJPEG_CGC_CTRL, data, indirect); in jpeg_engine_5_0_0_dpg_clock_gating_mode()
303 WREG32_SOC24_JPEG_DPG_MODE(inst_idx, vcnipJPEG_CGC_GATE, data, indirect); in jpeg_engine_5_0_0_dpg_clock_gating_mode()
316 static int jpeg_v5_0_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) in jpeg_v5_0_0_start_dpg_mode() argument
318 struct amdgpu_ring *ring = adev->jpeg.inst[inst_idx].ring_dec; in jpeg_v5_0_0_start_dpg_mode()
324 reg_data = RREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS); in jpeg_v5_0_0_start_dpg_mode()
326 WREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS, reg_data); in jpeg_v5_0_0_start_dpg_mode()
329 adev->jpeg.inst[inst_idx].dpg_sram_curr_addr = in jpeg_v5_0_0_start_dpg_mode()
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Djpeg_v4_0_5.c328 int inst_idx, uint8_t indirect) in jpeg_engine_4_0_5_dpg_clock_gating_mode() argument
339 WREG32_SOC15_JPEG_DPG_MODE(inst_idx, regJPEG_CGC_CTRL_INTERNAL_OFFSET, data, indirect); in jpeg_engine_4_0_5_dpg_clock_gating_mode()
342 WREG32_SOC15_JPEG_DPG_MODE(inst_idx, regJPEG_CGC_GATE_INTERNAL_OFFSET, in jpeg_engine_4_0_5_dpg_clock_gating_mode()
393 static void jpeg_v4_0_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) in jpeg_v4_0_5_start_dpg_mode() argument
395 struct amdgpu_ring *ring = adev->jpeg.inst[inst_idx].ring_dec; in jpeg_v4_0_5_start_dpg_mode()
399 reg_data = RREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS); in jpeg_v4_0_5_start_dpg_mode()
402 WREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS, reg_data); in jpeg_v4_0_5_start_dpg_mode()
405 WREG32(SOC15_REG_OFFSET(JPEG, inst_idx, regUVD_IPX_DLDO_CONFIG), in jpeg_v4_0_5_start_dpg_mode()
407 SOC15_WAIT_ON_RREG(JPEG, inst_idx, regUVD_IPX_DLDO_STATUS, in jpeg_v4_0_5_start_dpg_mode()
412 reg_data = RREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS); in jpeg_v4_0_5_start_dpg_mode()
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Damdgpu_jpeg.c334 int amdgpu_jpeg_psp_update_sram(struct amdgpu_device *adev, int inst_idx, in amdgpu_jpeg_psp_update_sram() argument
339 .mc_addr = adev->jpeg.inst[inst_idx].dpg_sram_gpu_addr, in amdgpu_jpeg_psp_update_sram()
340 .ucode_size = ((uintptr_t)adev->jpeg.inst[inst_idx].dpg_sram_curr_addr - in amdgpu_jpeg_psp_update_sram()
341 (uintptr_t)adev->jpeg.inst[inst_idx].dpg_sram_cpu_addr), in amdgpu_jpeg_psp_update_sram()
Dvcn_v1_0.c90 int inst_idx, struct dpg_pause_state *new_state);
1259 int inst_idx, struct dpg_pause_state *new_state) in vcn_v1_0_pause_dpg_mode() argument
1267 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { in vcn_v1_0_pause_dpg_mode()
1269 adev->vcn.inst[inst_idx].pause_state.fw_based, in vcn_v1_0_pause_dpg_mode()
1270 adev->vcn.inst[inst_idx].pause_state.jpeg, in vcn_v1_0_pause_dpg_mode()
1319 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; in vcn_v1_0_pause_dpg_mode()
1323 if (adev->vcn.inst[inst_idx].pause_state.jpeg != new_state->jpeg) { in vcn_v1_0_pause_dpg_mode()
1325 adev->vcn.inst[inst_idx].pause_state.fw_based, in vcn_v1_0_pause_dpg_mode()
1326 adev->vcn.inst[inst_idx].pause_state.jpeg, in vcn_v1_0_pause_dpg_mode()
1380 adev->vcn.inst[inst_idx].pause_state.jpeg = new_state->jpeg; in vcn_v1_0_pause_dpg_mode()
Damdgpu_vcn.c1267 int amdgpu_vcn_psp_update_sram(struct amdgpu_device *adev, int inst_idx, in amdgpu_vcn_psp_update_sram() argument
1272 (inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM : in amdgpu_vcn_psp_update_sram()
1274 .mc_addr = adev->vcn.inst[inst_idx].dpg_sram_gpu_addr, in amdgpu_vcn_psp_update_sram()
1275 .ucode_size = ((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr - in amdgpu_vcn_psp_update_sram()
1276 (uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr), in amdgpu_vcn_psp_update_sram()
Djpeg_v4_0_3.c422 static void jpeg_v4_0_3_disable_clock_gating(struct amdgpu_device *adev, int inst_idx) in jpeg_v4_0_3_disable_clock_gating() argument
427 jpeg_inst = GET_INST(JPEG, inst_idx); in jpeg_v4_0_3_disable_clock_gating()
447 static void jpeg_v4_0_3_enable_clock_gating(struct amdgpu_device *adev, int inst_idx) in jpeg_v4_0_3_enable_clock_gating() argument
452 jpeg_inst = GET_INST(JPEG, inst_idx); in jpeg_v4_0_3_enable_clock_gating()
Dvcn_v2_0.c98 int inst_idx, struct dpg_pause_state *new_state);
1246 int inst_idx, struct dpg_pause_state *new_state) in vcn_v2_0_pause_dpg_mode() argument
1253 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { in vcn_v2_0_pause_dpg_mode()
1255 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); in vcn_v2_0_pause_dpg_mode()
1316 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; in vcn_v2_0_pause_dpg_mode()
Daqua_vanjaram.c71 uint32_t inst_idx, struct amdgpu_ring *ring) in aqua_vanjaram_set_xcp_id() argument
83 inst_mask = 1 << inst_idx; in aqua_vanjaram_set_xcp_id()
/openbsd/src/gnu/llvm/lldb/examples/python/
Dsymbolication.py580 for inst_idx, inst in enumerate(instructions):
583 pc_index = inst_idx
606 end_idx = inst_idx
609 if end_idx > inst_idx:
610 end_idx = inst_idx
/openbsd/src/gnu/llvm/lldb/source/Core/
DIOHandlerCursesGUI.cpp7132 const uint32_t inst_idx = m_first_visible_line + i; in WindowDelegateDraw() local
7133 Instruction *inst = insts.GetInstructionAtIndex(inst_idx).get(); in WindowDelegateDraw()
7139 const bool is_pc_line = frame_sp && inst_idx == pc_idx; in WindowDelegateDraw()
7140 const bool line_is_selected = m_selected_line == inst_idx; in WindowDelegateDraw()