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Searched refs:num_vcn_inst (Results 1 – 21 of 21) sorted by relevance

/openbsd/src/sys/dev/pci/drm/amd/amdgpu/
Dvcn_v2_5.c123 adev->vcn.num_vcn_inst = 2; in vcn_v2_5_early_init()
130 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v2_5_early_init()
166 for (j = 0; j < adev->vcn.num_vcn_inst; j++) { in vcn_v2_5_sw_init()
200 for (j = 0; j < adev->vcn.num_vcn_inst; j++) { in vcn_v2_5_sw_init()
284 ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL); in vcn_v2_5_sw_init()
309 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v2_5_sw_fini()
349 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { in vcn_v2_5_hw_init()
395 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v2_5_hw_fini()
466 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v2_5_mc_resume()
625 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v2_5_disable_clock_gating()
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Dvcn_v4_0_3.c164 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v4_0_3_sw_init()
208 ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL); in vcn_v4_0_3_sw_init()
232 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v4_0_3_sw_fini()
274 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v4_0_3_hw_init()
282 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v4_0_3_hw_init()
943 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v4_0_3_start_sriov()
1113 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v4_0_3_start()
1317 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v4_0_3_stop()
1552 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v4_0_3_set_unified_ring_funcs()
1573 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v4_0_3_is_idle()
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Dvcn_v5_0_0.c133 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v5_0_0_sw_init()
177 ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL); in vcn_v5_0_0_sw_init()
200 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v5_0_0_sw_fini()
238 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v5_0_0_hw_init()
269 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v5_0_0_hw_fini()
769 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v5_0_0_start()
949 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v5_0_0_stop()
1165 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v5_0_0_set_unified_ring_funcs()
1186 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v5_0_0_is_idle()
1208 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v5_0_0_wait_for_idle()
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Dvcn_v4_0_5.c149 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v4_0_5_sw_init()
210 ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL); in vcn_v4_0_5_sw_init()
233 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v4_0_5_sw_fini()
274 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v4_0_5_hw_init()
305 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v4_0_5_hw_fini()
1008 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v4_0_5_start()
1215 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v4_0_5_stop()
1438 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v4_0_5_set_unified_ring_funcs()
1459 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v4_0_5_is_idle()
1481 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v4_0_5_wait_for_idle()
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Dvcn_v4_0.c121 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v4_0_early_init()
189 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v4_0_sw_init()
242 ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL); in vcn_v4_0_sw_init()
266 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v4_0_sw_fini()
312 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v4_0_hw_init()
323 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v4_0_hw_init()
355 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v4_0_hw_fini()
1096 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v4_0_start()
1324 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v4_0_start_sriov()
1552 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v4_0_stop()
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Dvcn_v3_0.c129 adev->vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID; in vcn_v3_0_early_init()
192 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v3_0_sw_init()
288 ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL); in vcn_v3_0_sw_init()
312 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v3_0_sw_fini()
357 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v3_0_hw_init()
388 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v3_0_hw_init()
427 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v3_0_hw_fini()
1149 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v3_0_start()
1368 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v3_0_start_sriov()
1573 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v3_0_stop()
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Damdgpu_vcn.c100 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in amdgpu_vcn_early_init()
125 for (i = 0; i < adev->vcn.num_vcn_inst; i++) in amdgpu_vcn_sw_init()
204 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in amdgpu_vcn_sw_init()
253 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { in amdgpu_vcn_sw_fini()
312 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in amdgpu_vcn_suspend()
339 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in amdgpu_vcn_resume()
385 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { in amdgpu_vcn_idle_work_handler()
1056 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in amdgpu_vcn_setup_ucode()
1223 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in amdgpu_vcn_ras_late_init()
Damdgpu_discovery.c1358 if (adev->vcn.num_vcn_inst < in amdgpu_discovery_reg_base_init()
1360 adev->vcn.vcn_config[adev->vcn.num_vcn_inst] = in amdgpu_discovery_reg_base_init()
1362 adev->vcn.num_vcn_inst++; in amdgpu_discovery_reg_base_init()
1369 adev->vcn.num_vcn_inst + 1, in amdgpu_discovery_reg_base_init()
1506 if (vcn_harvest_count == adev->vcn.num_vcn_inst) { in amdgpu_discovery_harvest_ip()
1706 if (adev->vcn.num_vcn_inst > VCN_INFO_TABLE_MAX_NUM_INSTANCES) { in amdgpu_discovery_get_vcn_info()
1724 for (v = 0; v < adev->vcn.num_vcn_inst; v++) { in amdgpu_discovery_get_vcn_info()
2496 adev->vcn.num_vcn_inst = 1; in amdgpu_discovery_set_ip_blocks()
2558 adev->vcn.num_vcn_inst = 2; in amdgpu_discovery_set_ip_blocks()
2586 adev->vcn.num_vcn_inst = 2; in amdgpu_discovery_set_ip_blocks()
Daqua_vanjaram.c67 return (adev->xcp_mgr->num_xcps > adev->vcn.num_vcn_inst); in aqua_vanjaram_xcp_vcn_shared()
401 num_vcn = adev->vcn.num_vcn_inst; in __aqua_vanjaram_get_xcp_ip_info()
706 adev->vcn.num_vcn_inst = hweight32(adev->vcn.inst_mask); in aqua_vanjaram_init_soc_config()
Damdgpu_vcn.h314 uint8_t num_vcn_inst; member
Dvcn_v2_0.c226 ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL); in vcn_v2_0_sw_init()
2047 drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst); in vcn_v2_0_print_ip_state()
2048 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v2_0_print_ip_state()
2080 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v2_0_dump_ip_state()
Dvcn_v1_0.c209 ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL); in vcn_v1_0_sw_init()
1944 drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst); in vcn_v1_0_print_ip_state()
1945 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v1_0_print_ip_state()
1977 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v1_0_dump_ip_state()
Dsoc24.c77 if (adev->vcn.num_vcn_inst == hweight8(adev->vcn.harvest_config)) in soc24_query_video_codecs()
Damdgpu_kms.c446 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in amdgpu_hw_ip_info()
458 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in amdgpu_hw_ip_info()
668 count = adev->vcn.num_vcn_inst; in amdgpu_info_ioctl()
Dsoc21.c153 if (adev->vcn.num_vcn_inst == hweight8(adev->vcn.harvest_config)) in soc21_query_video_codecs()
Dnv.c213 if (adev->vcn.num_vcn_inst == hweight8(adev->vcn.harvest_config)) in nv_query_video_codecs()
Djpeg_v4_0_3.c316 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in jpeg_v4_0_3_hw_init()
Damdgpu_debugfs.c2085 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in amdgpu_debugfs_init()
Damdgpu_ras.c383 mask = GENMASK(adev->vcn.num_vcn_inst - 1, 0); in amdgpu_ras_instance_mask_check()
/openbsd/src/sys/dev/pci/drm/amd/pm/
Damdgpu_pm.c2168 gc_ver == IP_VERSION(11, 0, 3)) && adev->vcn.num_vcn_inst >= 2)) in pp_dpm_clk_default_attr_update()
2190 gc_ver == IP_VERSION(11, 0, 3)) && adev->vcn.num_vcn_inst >= 2)) in pp_dpm_clk_default_attr_update()
/openbsd/src/sys/dev/pci/drm/amd/pm/swsmu/smu11/
Dsienna_cichlid_ppt.c1036 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in sienna_cichlid_set_default_dpm_table()
1059 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in sienna_cichlid_set_default_dpm_table()
1160 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in sienna_cichlid_dpm_set_vcn_enable()