1 //===- AMDGPUMCInstLower.cpp - Lower AMDGPU MachineInstr to an MCInst -----===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief Code to lower AMDGPU MachineInstrs to their corresponding MCInst.
12 //
13 //===----------------------------------------------------------------------===//
14 //
15
16 #include "AMDGPUMCInstLower.h"
17 #include "AMDGPUAsmPrinter.h"
18 #include "AMDGPUTargetMachine.h"
19 #include "InstPrinter/AMDGPUInstPrinter.h"
20 #include "R600InstrInfo.h"
21 #include "SIInstrInfo.h"
22 #include "llvm/CodeGen/MachineBasicBlock.h"
23 #include "llvm/CodeGen/MachineInstr.h"
24 #include "llvm/IR/Constants.h"
25 #include "llvm/IR/Function.h"
26 #include "llvm/IR/GlobalVariable.h"
27 #include "llvm/MC/MCCodeEmitter.h"
28 #include "llvm/MC/MCContext.h"
29 #include "llvm/MC/MCExpr.h"
30 #include "llvm/MC/MCInst.h"
31 #include "llvm/MC/MCObjectStreamer.h"
32 #include "llvm/MC/MCStreamer.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/Format.h"
35 #include <algorithm>
36
37 using namespace llvm;
38
AMDGPUMCInstLower(MCContext & ctx,const AMDGPUSubtarget & st)39 AMDGPUMCInstLower::AMDGPUMCInstLower(MCContext &ctx, const AMDGPUSubtarget &st):
40 Ctx(ctx), ST(st)
41 { }
42
lower(const MachineInstr * MI,MCInst & OutMI) const43 void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
44
45 int MCOpcode = ST.getInstrInfo()->pseudoToMCOpcode(MI->getOpcode());
46
47 if (MCOpcode == -1) {
48 LLVMContext &C = MI->getParent()->getParent()->getFunction()->getContext();
49 C.emitError("AMDGPUMCInstLower::lower - Pseudo instruction doesn't have "
50 "a target-specific version: " + Twine(MI->getOpcode()));
51 }
52
53 OutMI.setOpcode(MCOpcode);
54
55 for (const MachineOperand &MO : MI->explicit_operands()) {
56 MCOperand MCOp;
57 switch (MO.getType()) {
58 default:
59 llvm_unreachable("unknown operand type");
60 case MachineOperand::MO_Immediate:
61 MCOp = MCOperand::createImm(MO.getImm());
62 break;
63 case MachineOperand::MO_Register:
64 MCOp = MCOperand::createReg(MO.getReg());
65 break;
66 case MachineOperand::MO_MachineBasicBlock:
67 MCOp = MCOperand::createExpr(MCSymbolRefExpr::create(
68 MO.getMBB()->getSymbol(), Ctx));
69 break;
70 case MachineOperand::MO_GlobalAddress: {
71 const GlobalValue *GV = MO.getGlobal();
72 MCSymbol *Sym = Ctx.getOrCreateSymbol(StringRef(GV->getName()));
73 MCOp = MCOperand::createExpr(MCSymbolRefExpr::create(Sym, Ctx));
74 break;
75 }
76 case MachineOperand::MO_TargetIndex: {
77 assert(MO.getIndex() == AMDGPU::TI_CONSTDATA_START);
78 MCSymbol *Sym = Ctx.getOrCreateSymbol(StringRef(END_OF_TEXT_LABEL_NAME));
79 const MCSymbolRefExpr *Expr = MCSymbolRefExpr::create(Sym, Ctx);
80 MCOp = MCOperand::createExpr(Expr);
81 break;
82 }
83 case MachineOperand::MO_ExternalSymbol: {
84 MCSymbol *Sym = Ctx.getOrCreateSymbol(StringRef(MO.getSymbolName()));
85 const MCSymbolRefExpr *Expr = MCSymbolRefExpr::create(Sym, Ctx);
86 MCOp = MCOperand::createExpr(Expr);
87 break;
88 }
89 }
90 OutMI.addOperand(MCOp);
91 }
92 }
93
EmitInstruction(const MachineInstr * MI)94 void AMDGPUAsmPrinter::EmitInstruction(const MachineInstr *MI) {
95 const AMDGPUSubtarget &STI = MF->getSubtarget<AMDGPUSubtarget>();
96 AMDGPUMCInstLower MCInstLowering(OutContext, STI);
97
98 #ifdef _DEBUG
99 StringRef Err;
100 if (!STI.getInstrInfo()->verifyInstruction(MI, Err)) {
101 errs() << "Warning: Illegal instruction detected: " << Err << "\n";
102 MI->dump();
103 }
104 #endif
105 if (MI->isBundle()) {
106 const MachineBasicBlock *MBB = MI->getParent();
107 MachineBasicBlock::const_instr_iterator I = MI;
108 ++I;
109 while (I != MBB->end() && I->isInsideBundle()) {
110 EmitInstruction(I);
111 ++I;
112 }
113 } else {
114 MCInst TmpInst;
115 MCInstLowering.lower(MI, TmpInst);
116 EmitToStreamer(*OutStreamer, TmpInst);
117
118 if (STI.dumpCode()) {
119 // Disassemble instruction/operands to text.
120 DisasmLines.resize(DisasmLines.size() + 1);
121 std::string &DisasmLine = DisasmLines.back();
122 raw_string_ostream DisasmStream(DisasmLine);
123
124 AMDGPUInstPrinter InstPrinter(*TM.getMCAsmInfo(),
125 *MF->getSubtarget().getInstrInfo(),
126 *MF->getSubtarget().getRegisterInfo());
127 InstPrinter.printInst(&TmpInst, DisasmStream, StringRef(),
128 MF->getSubtarget());
129
130 // Disassemble instruction/operands to hex representation.
131 SmallVector<MCFixup, 4> Fixups;
132 SmallVector<char, 16> CodeBytes;
133 raw_svector_ostream CodeStream(CodeBytes);
134
135 auto &ObjStreamer = static_cast<MCObjectStreamer&>(*OutStreamer);
136 MCCodeEmitter &InstEmitter = ObjStreamer.getAssembler().getEmitter();
137 InstEmitter.encodeInstruction(TmpInst, CodeStream, Fixups,
138 MF->getSubtarget<MCSubtargetInfo>());
139 CodeStream.flush();
140
141 HexLines.resize(HexLines.size() + 1);
142 std::string &HexLine = HexLines.back();
143 raw_string_ostream HexStream(HexLine);
144
145 for (size_t i = 0; i < CodeBytes.size(); i += 4) {
146 unsigned int CodeDWord = *(unsigned int *)&CodeBytes[i];
147 HexStream << format("%s%08X", (i > 0 ? " " : ""), CodeDWord);
148 }
149
150 DisasmStream.flush();
151 DisasmLineMaxLen = std::max(DisasmLineMaxLen, DisasmLine.size());
152 }
153 }
154 }
155