xref: /NextBSD/contrib/llvm/lib/Target/AMDGPU/SIInstrFormats.td (revision 84d351007654069f9643c8e4b4802a7f5f08ee42) 
1//===-- SIInstrFormats.td - SI Instruction Encodings ----------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// SI Instruction format definitions.
11//
12//===----------------------------------------------------------------------===//
13
14class InstSI <dag outs, dag ins, string asm, list<dag> pattern> :
15    AMDGPUInst<outs, ins, asm, pattern>, PredicateControl {
16
17  field bits<1> VM_CNT = 0;
18  field bits<1> EXP_CNT = 0;
19  field bits<1> LGKM_CNT = 0;
20
21  field bits<1> SALU = 0;
22  field bits<1> VALU = 0;
23
24  field bits<1> SOP1 = 0;
25  field bits<1> SOP2 = 0;
26  field bits<1> SOPC = 0;
27  field bits<1> SOPK = 0;
28  field bits<1> SOPP = 0;
29
30  field bits<1> VOP1 = 0;
31  field bits<1> VOP2 = 0;
32  field bits<1> VOP3 = 0;
33  field bits<1> VOPC = 0;
34
35  field bits<1> MUBUF = 0;
36  field bits<1> MTBUF = 0;
37  field bits<1> SMRD = 0;
38  field bits<1> DS = 0;
39  field bits<1> MIMG = 0;
40  field bits<1> FLAT = 0;
41  field bits<1> WQM = 0;
42  field bits<1> VGPRSpill = 0;
43
44  // These need to be kept in sync with the enum in SIInstrFlags.
45  let TSFlags{0} = VM_CNT;
46  let TSFlags{1} = EXP_CNT;
47  let TSFlags{2} = LGKM_CNT;
48
49  let TSFlags{3} = SALU;
50  let TSFlags{4} = VALU;
51
52  let TSFlags{5} = SOP1;
53  let TSFlags{6} = SOP2;
54  let TSFlags{7} = SOPC;
55  let TSFlags{8} = SOPK;
56  let TSFlags{9} = SOPP;
57
58  let TSFlags{10} = VOP1;
59  let TSFlags{11} = VOP2;
60  let TSFlags{12} = VOP3;
61  let TSFlags{13} = VOPC;
62
63  let TSFlags{14} = MUBUF;
64  let TSFlags{15} = MTBUF;
65  let TSFlags{16} = SMRD;
66  let TSFlags{17} = DS;
67  let TSFlags{18} = MIMG;
68  let TSFlags{19} = FLAT;
69  let TSFlags{20} = WQM;
70  let TSFlags{21} = VGPRSpill;
71
72  // Most instructions require adjustments after selection to satisfy
73  // operand requirements.
74  let hasPostISelHook = 1;
75  let SchedRW = [Write32Bit];
76}
77
78class Enc32 {
79  field bits<32> Inst;
80  int Size = 4;
81}
82
83class Enc64 {
84  field bits<64> Inst;
85  int Size = 8;
86}
87
88class VOPDstOperand <RegisterClass rc> : RegisterOperand <rc, "printVOPDst">;
89def VOPDstVCC : VOPDstOperand <VCCReg>;
90
91let Uses = [EXEC] in {
92
93class VOPAnyCommon <dag outs, dag ins, string asm, list<dag> pattern> :
94    InstSI <outs, ins, asm, pattern> {
95
96  let mayLoad = 0;
97  let mayStore = 0;
98  let hasSideEffects = 0;
99  let UseNamedOperandTable = 1;
100  let VALU = 1;
101}
102
103class VOPCCommon <dag ins, string asm, list<dag> pattern> :
104    VOPAnyCommon <(outs VOPDstVCC:$dst), ins, asm, pattern> {
105
106  let DisableEncoding = "$dst";
107  let VOPC = 1;
108  let Size = 4;
109}
110
111class VOP1Common <dag outs, dag ins, string asm, list<dag> pattern> :
112    VOPAnyCommon <outs, ins, asm, pattern> {
113
114  let VOP1 = 1;
115  let Size = 4;
116}
117
118class VOP2Common <dag outs, dag ins, string asm, list<dag> pattern> :
119    VOPAnyCommon <outs, ins, asm, pattern> {
120
121  let VOP2 = 1;
122  let Size = 4;
123}
124
125class VOP3Common <dag outs, dag ins, string asm, list<dag> pattern> :
126    VOPAnyCommon <outs, ins, asm, pattern> {
127
128  // Using complex patterns gives VOP3 patterns a very high complexity rating,
129  // but standalone patterns are almost always prefered, so we need to adjust the
130  // priority lower.  The goal is to use a high number to reduce complexity to
131  // zero (or less than zero).
132  let AddedComplexity = -1000;
133
134  let VOP3 = 1;
135  let VALU = 1;
136
137  let AsmMatchConverter = "cvtVOP3";
138  let isCodeGenOnly = 0;
139
140  int Size = 8;
141}
142
143} // End Uses = [EXEC]
144
145//===----------------------------------------------------------------------===//
146// Scalar operations
147//===----------------------------------------------------------------------===//
148
149class SOP1e <bits<8> op> : Enc32 {
150  bits<7> sdst;
151  bits<8> ssrc0;
152
153  let Inst{7-0} = ssrc0;
154  let Inst{15-8} = op;
155  let Inst{22-16} = sdst;
156  let Inst{31-23} = 0x17d; //encoding;
157}
158
159class SOP2e <bits<7> op> : Enc32 {
160  bits<7> sdst;
161  bits<8> ssrc0;
162  bits<8> ssrc1;
163
164  let Inst{7-0} = ssrc0;
165  let Inst{15-8} = ssrc1;
166  let Inst{22-16} = sdst;
167  let Inst{29-23} = op;
168  let Inst{31-30} = 0x2; // encoding
169}
170
171class SOPCe <bits<7> op> : Enc32 {
172  bits<8> ssrc0;
173  bits<8> ssrc1;
174
175  let Inst{7-0} = ssrc0;
176  let Inst{15-8} = ssrc1;
177  let Inst{22-16} = op;
178  let Inst{31-23} = 0x17e;
179}
180
181class SOPKe <bits<5> op> : Enc32 {
182  bits <7> sdst;
183  bits <16> simm16;
184
185  let Inst{15-0} = simm16;
186  let Inst{22-16} = sdst;
187  let Inst{27-23} = op;
188  let Inst{31-28} = 0xb; //encoding
189}
190
191class SOPK64e <bits<5> op> : Enc64 {
192  bits <7> sdst = 0;
193  bits <16> simm16;
194  bits <32> imm;
195
196  let Inst{15-0} = simm16;
197  let Inst{22-16} = sdst;
198  let Inst{27-23} = op;
199  let Inst{31-28} = 0xb;
200
201  let Inst{63-32} = imm;
202}
203
204class SOPPe <bits<7> op> : Enc32 {
205  bits <16> simm16;
206
207  let Inst{15-0} = simm16;
208  let Inst{22-16} = op;
209  let Inst{31-23} = 0x17f; // encoding
210}
211
212class SMRDe <bits<5> op, bits<1> imm> : Enc32 {
213  bits<7> sdst;
214  bits<7> sbase;
215  bits<8> offset;
216
217  let Inst{7-0} = offset;
218  let Inst{8} = imm;
219  let Inst{14-9} = sbase{6-1};
220  let Inst{21-15} = sdst;
221  let Inst{26-22} = op;
222  let Inst{31-27} = 0x18; //encoding
223}
224
225let SchedRW = [WriteSALU] in {
226class SOP1 <dag outs, dag ins, string asm, list<dag> pattern> :
227    InstSI<outs, ins, asm, pattern> {
228  let mayLoad = 0;
229  let mayStore = 0;
230  let hasSideEffects = 0;
231  let isCodeGenOnly = 0;
232  let SALU = 1;
233  let SOP1 = 1;
234}
235
236class SOP2 <dag outs, dag ins, string asm, list<dag> pattern> :
237    InstSI <outs, ins, asm, pattern> {
238
239  let mayLoad = 0;
240  let mayStore = 0;
241  let hasSideEffects = 0;
242  let isCodeGenOnly = 0;
243  let SALU = 1;
244  let SOP2 = 1;
245
246  let UseNamedOperandTable = 1;
247}
248
249class SOPC <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
250  InstSI<outs, ins, asm, pattern>, SOPCe <op> {
251
252  let DisableEncoding = "$dst";
253  let mayLoad = 0;
254  let mayStore = 0;
255  let hasSideEffects = 0;
256  let SALU = 1;
257  let SOPC = 1;
258  let isCodeGenOnly = 0;
259
260  let UseNamedOperandTable = 1;
261}
262
263class SOPK <dag outs, dag ins, string asm, list<dag> pattern> :
264   InstSI <outs, ins , asm, pattern> {
265
266  let mayLoad = 0;
267  let mayStore = 0;
268  let hasSideEffects = 0;
269  let SALU = 1;
270  let SOPK = 1;
271
272  let UseNamedOperandTable = 1;
273}
274
275class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern = []> :
276		InstSI <(outs), ins, asm, pattern >, SOPPe <op> {
277
278  let mayLoad = 0;
279  let mayStore = 0;
280  let hasSideEffects = 0;
281  let SALU = 1;
282  let SOPP = 1;
283
284  let UseNamedOperandTable = 1;
285}
286
287} // let SchedRW = [WriteSALU]
288
289class SMRD <dag outs, dag ins, string asm, list<dag> pattern> :
290    InstSI<outs, ins, asm, pattern> {
291
292  let LGKM_CNT = 1;
293  let SMRD = 1;
294  let mayStore = 0;
295  let mayLoad = 1;
296  let hasSideEffects = 0;
297  let UseNamedOperandTable = 1;
298  let SchedRW = [WriteSMEM];
299}
300
301//===----------------------------------------------------------------------===//
302// Vector ALU operations
303//===----------------------------------------------------------------------===//
304
305class VOP1e <bits<8> op> : Enc32 {
306  bits<8> vdst;
307  bits<9> src0;
308
309  let Inst{8-0} = src0;
310  let Inst{16-9} = op;
311  let Inst{24-17} = vdst;
312  let Inst{31-25} = 0x3f; //encoding
313}
314
315class VOP2e <bits<6> op> : Enc32 {
316  bits<8> vdst;
317  bits<9> src0;
318  bits<8> src1;
319
320  let Inst{8-0} = src0;
321  let Inst{16-9} = src1;
322  let Inst{24-17} = vdst;
323  let Inst{30-25} = op;
324  let Inst{31} = 0x0; //encoding
325}
326
327class VOP2_MADKe <bits<6> op> : Enc64 {
328
329  bits<8>  vdst;
330  bits<9>  src0;
331  bits<8>  vsrc1;
332  bits<32> src2;
333
334  let Inst{8-0} = src0;
335  let Inst{16-9} = vsrc1;
336  let Inst{24-17} = vdst;
337  let Inst{30-25} = op;
338  let Inst{31} = 0x0; // encoding
339  let Inst{63-32} = src2;
340}
341
342class VOP3e <bits<9> op> : Enc64 {
343  bits<8> vdst;
344  bits<2> src0_modifiers;
345  bits<9> src0;
346  bits<2> src1_modifiers;
347  bits<9> src1;
348  bits<2> src2_modifiers;
349  bits<9> src2;
350  bits<1> clamp;
351  bits<2> omod;
352
353  let Inst{7-0} = vdst;
354  let Inst{8} = src0_modifiers{1};
355  let Inst{9} = src1_modifiers{1};
356  let Inst{10} = src2_modifiers{1};
357  let Inst{11} = clamp;
358  let Inst{25-17} = op;
359  let Inst{31-26} = 0x34; //encoding
360  let Inst{40-32} = src0;
361  let Inst{49-41} = src1;
362  let Inst{58-50} = src2;
363  let Inst{60-59} = omod;
364  let Inst{61} = src0_modifiers{0};
365  let Inst{62} = src1_modifiers{0};
366  let Inst{63} = src2_modifiers{0};
367}
368
369class VOP3be <bits<9> op> : Enc64 {
370  bits<8> vdst;
371  bits<2> src0_modifiers;
372  bits<9> src0;
373  bits<2> src1_modifiers;
374  bits<9> src1;
375  bits<2> src2_modifiers;
376  bits<9> src2;
377  bits<7> sdst;
378  bits<2> omod;
379
380  let Inst{7-0} = vdst;
381  let Inst{14-8} = sdst;
382  let Inst{25-17} = op;
383  let Inst{31-26} = 0x34; //encoding
384  let Inst{40-32} = src0;
385  let Inst{49-41} = src1;
386  let Inst{58-50} = src2;
387  let Inst{60-59} = omod;
388  let Inst{61} = src0_modifiers{0};
389  let Inst{62} = src1_modifiers{0};
390  let Inst{63} = src2_modifiers{0};
391}
392
393class VOPCe <bits<8> op> : Enc32 {
394  bits<9> src0;
395  bits<8> vsrc1;
396
397  let Inst{8-0} = src0;
398  let Inst{16-9} = vsrc1;
399  let Inst{24-17} = op;
400  let Inst{31-25} = 0x3e;
401}
402
403class VINTRPe <bits<2> op> : Enc32 {
404  bits<8> vdst;
405  bits<8> vsrc;
406  bits<2> attrchan;
407  bits<6> attr;
408
409  let Inst{7-0} = vsrc;
410  let Inst{9-8} = attrchan;
411  let Inst{15-10} = attr;
412  let Inst{17-16} = op;
413  let Inst{25-18} = vdst;
414  let Inst{31-26} = 0x32; // encoding
415}
416
417class DSe <bits<8> op> : Enc64 {
418  bits<8> vdst;
419  bits<1> gds;
420  bits<8> addr;
421  bits<8> data0;
422  bits<8> data1;
423  bits<8> offset0;
424  bits<8> offset1;
425
426  let Inst{7-0} = offset0;
427  let Inst{15-8} = offset1;
428  let Inst{17} = gds;
429  let Inst{25-18} = op;
430  let Inst{31-26} = 0x36; //encoding
431  let Inst{39-32} = addr;
432  let Inst{47-40} = data0;
433  let Inst{55-48} = data1;
434  let Inst{63-56} = vdst;
435}
436
437class MUBUFe <bits<7> op> : Enc64 {
438  bits<12> offset;
439  bits<1> offen;
440  bits<1> idxen;
441  bits<1> glc;
442  bits<1> addr64;
443  bits<1> lds;
444  bits<8> vaddr;
445  bits<8> vdata;
446  bits<7> srsrc;
447  bits<1> slc;
448  bits<1> tfe;
449  bits<8> soffset;
450
451  let Inst{11-0} = offset;
452  let Inst{12} = offen;
453  let Inst{13} = idxen;
454  let Inst{14} = glc;
455  let Inst{15} = addr64;
456  let Inst{16} = lds;
457  let Inst{24-18} = op;
458  let Inst{31-26} = 0x38; //encoding
459  let Inst{39-32} = vaddr;
460  let Inst{47-40} = vdata;
461  let Inst{52-48} = srsrc{6-2};
462  let Inst{54} = slc;
463  let Inst{55} = tfe;
464  let Inst{63-56} = soffset;
465}
466
467class MTBUFe <bits<3> op> : Enc64 {
468  bits<8> vdata;
469  bits<12> offset;
470  bits<1> offen;
471  bits<1> idxen;
472  bits<1> glc;
473  bits<1> addr64;
474  bits<4> dfmt;
475  bits<3> nfmt;
476  bits<8> vaddr;
477  bits<7> srsrc;
478  bits<1> slc;
479  bits<1> tfe;
480  bits<8> soffset;
481
482  let Inst{11-0} = offset;
483  let Inst{12} = offen;
484  let Inst{13} = idxen;
485  let Inst{14} = glc;
486  let Inst{15} = addr64;
487  let Inst{18-16} = op;
488  let Inst{22-19} = dfmt;
489  let Inst{25-23} = nfmt;
490  let Inst{31-26} = 0x3a; //encoding
491  let Inst{39-32} = vaddr;
492  let Inst{47-40} = vdata;
493  let Inst{52-48} = srsrc{6-2};
494  let Inst{54} = slc;
495  let Inst{55} = tfe;
496  let Inst{63-56} = soffset;
497}
498
499class MIMGe <bits<7> op> : Enc64 {
500  bits<8> vdata;
501  bits<4> dmask;
502  bits<1> unorm;
503  bits<1> glc;
504  bits<1> da;
505  bits<1> r128;
506  bits<1> tfe;
507  bits<1> lwe;
508  bits<1> slc;
509  bits<8> vaddr;
510  bits<7> srsrc;
511  bits<7> ssamp;
512
513  let Inst{11-8} = dmask;
514  let Inst{12} = unorm;
515  let Inst{13} = glc;
516  let Inst{14} = da;
517  let Inst{15} = r128;
518  let Inst{16} = tfe;
519  let Inst{17} = lwe;
520  let Inst{24-18} = op;
521  let Inst{25} = slc;
522  let Inst{31-26} = 0x3c;
523  let Inst{39-32} = vaddr;
524  let Inst{47-40} = vdata;
525  let Inst{52-48} = srsrc{6-2};
526  let Inst{57-53} = ssamp{6-2};
527}
528
529class FLATe<bits<7> op> : Enc64 {
530  bits<8> addr;
531  bits<8> data;
532  bits<8> vdst;
533  bits<1> slc;
534  bits<1> glc;
535  bits<1> tfe;
536
537  // 15-0 is reserved.
538  let Inst{16} = glc;
539  let Inst{17} = slc;
540  let Inst{24-18} = op;
541  let Inst{31-26} = 0x37; // Encoding.
542  let Inst{39-32} = addr;
543  let Inst{47-40} = data;
544  // 54-48 is reserved.
545  let Inst{55} = tfe;
546  let Inst{63-56} = vdst;
547}
548
549class EXPe : Enc64 {
550  bits<4> en;
551  bits<6> tgt;
552  bits<1> compr;
553  bits<1> done;
554  bits<1> vm;
555  bits<8> vsrc0;
556  bits<8> vsrc1;
557  bits<8> vsrc2;
558  bits<8> vsrc3;
559
560  let Inst{3-0} = en;
561  let Inst{9-4} = tgt;
562  let Inst{10} = compr;
563  let Inst{11} = done;
564  let Inst{12} = vm;
565  let Inst{31-26} = 0x3e;
566  let Inst{39-32} = vsrc0;
567  let Inst{47-40} = vsrc1;
568  let Inst{55-48} = vsrc2;
569  let Inst{63-56} = vsrc3;
570}
571
572let Uses = [EXEC] in {
573
574class VOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
575    VOP1Common <outs, ins, asm, pattern>,
576    VOP1e<op> {
577  let isCodeGenOnly = 0;
578}
579
580class VOP2 <bits<6> op, dag outs, dag ins, string asm, list<dag> pattern> :
581    VOP2Common <outs, ins, asm, pattern>, VOP2e<op> {
582  let isCodeGenOnly = 0;
583}
584
585class VOPC <bits<8> op, dag ins, string asm, list<dag> pattern> :
586    VOPCCommon <ins, asm, pattern>, VOPCe <op>;
587
588class VINTRPCommon <dag outs, dag ins, string asm, list<dag> pattern> :
589    InstSI <outs, ins, asm, pattern> {
590  let mayLoad = 1;
591  let mayStore = 0;
592  let hasSideEffects = 0;
593}
594
595} // End Uses = [EXEC]
596
597//===----------------------------------------------------------------------===//
598// Vector I/O operations
599//===----------------------------------------------------------------------===//
600
601let Uses = [EXEC] in {
602
603class DS <dag outs, dag ins, string asm, list<dag> pattern> :
604    InstSI <outs, ins, asm, pattern> {
605
606  let LGKM_CNT = 1;
607  let DS = 1;
608  let UseNamedOperandTable = 1;
609  let Uses = [M0];
610
611  // Most instruction load and store data, so set this as the default.
612  let mayLoad = 1;
613  let mayStore = 1;
614
615  let hasSideEffects = 0;
616  let AsmMatchConverter = "cvtDS";
617  let SchedRW = [WriteLDS];
618}
619
620class MUBUF <dag outs, dag ins, string asm, list<dag> pattern> :
621    InstSI<outs, ins, asm, pattern> {
622
623  let VM_CNT = 1;
624  let EXP_CNT = 1;
625  let MUBUF = 1;
626
627  let hasSideEffects = 0;
628  let UseNamedOperandTable = 1;
629  let AsmMatchConverter = "cvtMubuf";
630  let SchedRW = [WriteVMEM];
631}
632
633class MTBUF <dag outs, dag ins, string asm, list<dag> pattern> :
634    InstSI<outs, ins, asm, pattern> {
635
636  let VM_CNT = 1;
637  let EXP_CNT = 1;
638  let MTBUF = 1;
639
640  let hasSideEffects = 0;
641  let UseNamedOperandTable = 1;
642  let SchedRW = [WriteVMEM];
643}
644
645class FLAT <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
646    InstSI<outs, ins, asm, pattern>, FLATe <op> {
647  let FLAT = 1;
648  // Internally, FLAT instruction are executed as both an LDS and a
649  // Buffer instruction; so, they increment both VM_CNT and LGKM_CNT
650  // and are not considered done until both have been decremented.
651  let VM_CNT = 1;
652  let LGKM_CNT = 1;
653
654  let Uses = [EXEC, FLAT_SCR]; // M0
655
656  let UseNamedOperandTable = 1;
657  let hasSideEffects = 0;
658  let AsmMatchConverter = "cvtFlat";
659  let SchedRW = [WriteVMEM];
660}
661
662class MIMG <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
663    InstSI <outs, ins, asm, pattern>, MIMGe <op> {
664
665  let VM_CNT = 1;
666  let EXP_CNT = 1;
667  let MIMG = 1;
668
669  let hasSideEffects = 0; // XXX ????
670}
671
672
673} // End Uses = [EXEC]
674