1.\" Copyright (c) 2010 George Neville-Neil. All rights reserved. 2.\" 3.\" Redistribution and use in source and binary forms, with or without 4.\" modification, are permitted provided that the following conditions 5.\" are met: 6.\" 1. Redistributions of source code must retain the above copyright 7.\" notice, this list of conditions and the following disclaimer. 8.\" 2. Redistributions in binary form must reproduce the above copyright 9.\" notice, this list of conditions and the following disclaimer in the 10.\" documentation and/or other materials provided with the distribution. 11.\" 12.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 13.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 14.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 15.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 16.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 17.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 18.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 19.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 20.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 21.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 22.\" SUCH DAMAGE. 23.\" 24.\" $FreeBSD$ 25.\" 26.Dd March 24, 2012 27.Dt PMC.OCTEON 3 28.Os 29.Sh NAME 30.Nm pmc.octeon 31.Nd measurement events for 32.Tn Octeon 33family CPUs 34.Sh LIBRARY 35.Lb libpmc 36.Sh SYNOPSIS 37.In pmc.h 38.Sh DESCRIPTION 39There are two counters per core supported by the hardware and each is 64 bits 40wide. 41.Ss Event Specifiers (Programmable PMCs) 42MIPS programmable PMCs support the following events: 43.Bl -tag -width indent 44.It Li CLK 45.Pq Event 1 46Conditionally clocked cycles (as opposed to count/cvm_count which count even with no clocks) 47.It Li ISSUE 48.Pq Event 2 49Instructions issued but not retired 50.It Li RET 51.Pq Event 3 52Instructions retired 53.It Li NISSUE 54.Pq Event 4 55Cycles no issue 56.It Li SISSUE 57.Pq Event 5 58Cycles single issue 59.It Li DISSUE 60.Pq Event 6 61Cycles dual issue 62.It Li IFI 63.Pq Event 7 64Cycle ifetch issued (but not necessarily commit to pp_mem) 65.It Li BR 66.Pq Event 8 67Branches retired 68.It Li BRMIS 69.Pq Event 9 70Branch mispredicts 71.It Li J 72.Pq Event 10 73Jumps retired 74.It Li JMIS 75.Pq Event 11 76Jumps mispredicted 77.It Li REPLAY 78.Pq Event 12 79Mem Replays 80.It Li IUNA 81.Pq Event 13 82Cycles idle due to unaligned_replays 83.It Li TRAP 84.Pq Event 14 85trap_6a signal 86.It Li UULOAD 87.Pq Event 16 88Unexpected unaligned loads (REPUN=1) 89.It Li UUSTORE 90.Pq Event 17 91Unexpected unaligned store (REPUN=1) 92.It Li ULOAD 93.Pq Event 18 94Unaligned loads (REPUN=1 or USEUN=1) 95.It Li USTORE 96.Pq Event 19 97Unaligned store (REPUN=1 or USEUN=1) 98.It Li EC 99.Pq Event 20 100Exec clocks(must set CvmCtl[DISCE] for accurate timing) 101.It Li MC 102.Pq Event 21 103Mul clocks(must set CvmCtl[DISCE] for accurate timing) 104.It Li CC 105.Pq Event 22 106Crypto clocks(must set CvmCtl[DISCE] for accurate timing) 107.It Li CSRC 108.Pq Event 23 109Issue_csr clocks(must set CvmCtl[DISCE] for accurate timing) 110.It Li CFETCH 111.Pq Event 24 112Icache committed fetches (demand+prefetch) 113.It Li CPREF 114.Pq Event 25 115Icache committed prefetches 116.It Li ICA 117.Pq Event 26 118Icache aliases 119.It Li II 120.Pq Event 27 121Icache invalidates 122.It Li IP 123.Pq Event 28 124Icache parity error 125.It Li CIMISS 126.Pq Event 29 127Cycles idle due to imiss (must set CvmCtl[DISCE] for accurate timing) 128.It Li WBUF 129.Pq Event 32 130Number of write buffer entries created 131.It Li WDAT 132.Pq Event 33 133Number of write buffer data cycles used (may need to set CvmCtl[DISCE] for accurate counts) 134.It Li WBUFLD 135.Pq Event 34 136Number of write buffer entries forced out by loads 137.It Li WBUFFL 138.Pq Event 35 139Number of cycles that there was no available write buffer entry (may need to set CvmCtl[DISCE] and CvmMemCtl[MCLK] for accurate counts) 140.It Li WBUFTR 141.Pq Event 36 142Number of stores that found no available write buffer entries 143.It Li BADD 144.Pq Event 37 145Number of address bus cycles used (may need to set CvmCtl[DISCE] for accurate counts) 146.It Li BADDL2 147.Pq Event 38 148Number of address bus cycles not reflected (i.e. destined for L2) (may need to set CvmCtl[DISCE] for accurate counts) 149.It Li BFILL 150.Pq Event 39 151Number of fill bus cycles used (may need to set CvmCtl[DISCE] for accurate counts) 152.It Li DDIDS 153.Pq Event 40 154Number of Dstream DIDs created 155.It Li IDIDS 156.Pq Event 41 157Number of Istream DIDs created 158.It Li DIDNA 159.Pq Event 42 160Number of cycles that no DIDs were available (may need to set CvmCtl[DISCE] and CvmMemCtl[MCLK] for accurate counts) 161.It Li LDS 162.Pq Event 43 163Number of load issues 164.It Li LMLDS 165.Pq Event 44 166Number of local memory load 167.It Li IOLDS 168.Pq Event 45 169Number of I/O load issues 170.It Li DMLDS 171.Pq Event 46 172Number of loads that were not prefetches and missed in the cache 173.It Li STS 174.Pq Event 48 175Number of store issues 176.It Li LMSTS 177.Pq Event 49 178Number of local memory store issues 179.It Li IOSTS 180.Pq Event 50 181Number of I/O store issues 182.It Li IOBDMA 183.Pq Event 51 184Number of IOBDMAs 185.It Li DTLB 186.Pq Event 53 187Number of dstream TLB refill, invalid, or modified exceptions 188.It Li DTLBAD 189.Pq Event 54 190Number of dstream TLB address errors 191.It Li ITLB 192.Pq Event 55 193Number of istream TLB refill, invalid, or address error exceptions 194.It Li SYNC 195.Pq Event 56 196Number of SYNC stall cycles (may need to set CvmCtl[DISCE] for accurate counts) 197.It Li SYNCIOB 198.Pq Event 57 199Number of SYNCIOBDMA stall cycles (may need to set CvmCtl[DISCE] for accurate counts) 200.It Li SYNCW 201.Pq Event 58 202Number of SYNCWs 203.It Li ERETMIS 204.Pq Event 64 205D/eret mispredicts (CN63XX specific) 206.It Li LIKMIS 207.Pq Event 65 208Branch likely mispredicts (CN63XX specific) 209.It Li HAZTR 210.Pq Event 66 211Hazard traps due to *MTC0 to CvmCtl, Perf counter control, EntryHi, or CvmMemCtl registers (CN63XX specific) 212.El 213.Ss Event Name Aliases 214The following table shows the mapping between the PMC-independent 215aliases supported by 216.Lb libpmc 217and the underlying hardware events used. 218.Bl -column "branch-mispredicts" "cpu_clk_unhalted.core_p" 219.It Em Alias Ta Em Event 220.It Li instructions Ta Li RET 221.It Li branches Ta Li BR 222.It Li branch-mispredicts Ta Li BS 223.El 224.Sh SEE ALSO 225.Xr pmc 3 , 226.Xr pmc.atom 3 , 227.Xr pmc.core 3 , 228.Xr pmc.iaf 3 , 229.Xr pmc.k7 3 , 230.Xr pmc.k8 3 , 231.Xr pmc.mips24k 3 , 232.Xr pmc.p4 3 , 233.Xr pmc.p5 3 , 234.Xr pmc.p6 3 , 235.Xr pmc.soft 3 , 236.Xr pmc.tsc 3 , 237.Xr pmc_cpuinfo 3 , 238.Xr pmclog 3 , 239.Xr hwpmc 4 240.Sh HISTORY 241The 242.Nm pmc 243library first appeared in 244.Fx 6.0 . 245.Sh AUTHORS 246.An -nosplit 247The 248.Lb libpmc 249library was written by 250.An Joseph Koshy Aq Mt jkoshy@FreeBSD.org . 251MIPS support was added by 252.An George Neville-Neil Aq Mt gnn@FreeBSD.org . 253