1 /*- 2 * Copyright 2013-2015 John Wehle <john@feith.com> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #ifndef _ARM_AMLOGIC_AML8726_MMC_H 30 #define _ARM_AMLOGIC_AML8726_MMC_H 31 32 33 #define AML_MMC_ALIGN_DMA 4 34 #define AML_MMC_MAX_DMA 4096 35 36 /* 37 * Timeouts are in milliseconds 38 * 39 * Read and write are per section 4.6.2 of the: 40 * 41 * SD Specifications Part 1 42 * Physicaly Layer Simplified Specification 43 * Version 4.10 44 */ 45 #define AML_MMC_CMD_TIMEOUT 50 46 #define AML_MMC_READ_TIMEOUT 100 47 #define AML_MMC_WRITE_TIMEOUT 500 48 #define AML_MMC_MAX_TIMEOUT 5000 49 50 #define AML_MMC_CMD_ARGUMENT_REG 0 51 52 #define AML_MMC_CMD_SEND_REG 4 53 #define AML_MMC_CMD_REP_PKG_CNT_MASK (0xffU << 24) 54 #define AML_MMC_CMD_REP_PKG_CNT_SHIFT 24 55 #define AML_MMC_CMD_CMD_HAS_DATA (1 << 20) 56 #define AML_MMC_CMD_CHECK_DAT0_BUSY (1 << 19) 57 #define AML_MMC_CMD_RESP_CRC7_FROM_8 (1 << 18) 58 #define AML_MMC_CMD_RESP_HAS_DATA (1 << 17) 59 #define AML_MMC_CMD_RESP_NO_CRC7 (1 << 16) 60 #define AML_MMC_CMD_RESP_BITS_MASK (0xff << 8) 61 #define AML_MMC_CMD_RESP_BITS_SHIFT 8 62 #define AML_MMC_CMD_START_BIT (0 << 7) 63 #define AML_MMC_CMD_TRANS_BIT_HOST (1 << 6) 64 #define AML_MMC_CMD_INDEX_MASK 0x3f 65 #define AML_MMC_CMD_INDEX_SHIFT 0 66 67 #define AML_MMC_CONFIG_REG 8 68 #define AML_MMC_CONFIG_WR_CRC_STAT_MASK (7U << 29) 69 #define AML_MMC_CONFIG_WR_CRC_STAT_SHIFT 29 70 #define AML_MMC_CONFIG_WR_DELAY_MASK (0x3f << 23) 71 #define AML_MMC_CONFIG_WR_DELAY_SHIFT 23 72 #define AML_MMC_CONFIG_DMA_ENDIAN_MASK (3 << 21) 73 #define AML_MMC_CONFIG_DMA_ENDIAN_NC (0 << 21) 74 #define AML_MMC_CONFIG_DMA_ENDIAN_SB (1 << 21) 75 #define AML_MMC_CONFIG_DMA_ENDIAN_SW (2 << 21) 76 #define AML_MMC_CONFIG_DMA_ENDIAN_SBW (3 << 21) 77 #define AML_MMC_CONFIG_BUS_WIDTH_MASK (1 << 20) 78 #define AML_MMC_CONFIG_BUS_WIDTH_1 (0 << 20) 79 #define AML_MMC_CONFIG_BUS_WIDTH_4 (1 << 20) 80 #define AML_MMC_CONFIG_DATA_NEG_EDGE (1 << 19) 81 #define AML_MMC_CONFIG_DONT_DELAY_DATA (1 << 18) 82 #define AML_MMC_CONFIG_CMD_ARG_BITS_MASK (0x3f << 12) 83 #define AML_MMC_CONFIG_CMD_ARG_BITS_SHIFT 12 84 #define AML_MMC_CONFIG_CMD_POS_EDGE (1 << 11) 85 #define AML_MMC_CONFIG_CMD_NO_CRC (1 << 10) 86 #define AML_MMC_CONFIG_CMD_CLK_DIV_MASK 0x3ff 87 #define AML_MMC_CONFIG_CMD_CLK_DIV_SHIFT 0 88 89 #define AML_MMC_IRQ_STATUS_REG 12 90 #define AML_MMC_IRQ_STATUS_TIMER_CNT_MASK (0x1fffU << 19) 91 #define AML_MMC_IRQ_STATUS_TIMER_CNT_SHIFT 19 92 #define AML_MMC_IRQ_STATUS_TIMER_EN (1 << 18) 93 #define AML_MMC_IRQ_STATUS_TIMEOUT_IRQ (1 << 16) 94 #define AML_MMC_IRQ_STATUS_CMD_DONE_IRQ (1 << 9) 95 #define AML_MMC_IRQ_STATUS_WR_CRC16_OK (1 << 7) 96 #define AML_MMC_IRQ_STATUS_RD_CRC16_OK (1 << 6) 97 #define AML_MMC_IRQ_STATUS_RESP_CRC7_OK (1 << 5) 98 #define AML_MMC_IRQ_STATUS_CMD_BUSY (1 << 4) 99 #define AML_MMC_IRQ_STATUS_CLEAR_IRQ 0x10700 100 101 #define AML_MMC_IRQ_CONFIG_REG 16 102 #define AML_MMC_IRQ_CONFIG_SOFT_RESET (1 << 15) 103 #define AML_MMC_IRQ_CONFIG_CMD_DONE_EN (1 << 4) 104 105 #define AML_MMC_MULT_CONFIG_REG 20 106 #define AML_MMC_MULT_CONFIG_RESP_INDEX_MASK (0xf << 12) 107 #define AML_MMC_MULT_CONFIG_RESP_INDEX_SHIFT 12 108 #define AML_MMC_MULT_CONFIG_RESP_READOUT_EN (1 << 8) 109 #define AML_MMC_MULT_CONFIG_STREAM_8_MODE (1 << 5) 110 #define AML_MMC_MULT_CONFIG_STREAM_EN (1 << 4) 111 #define AML_MMC_MULT_CONFIG_PORT_MASK 3 112 #define AML_MMC_MULT_CONFIG_PORT_A 0 113 #define AML_MMC_MULT_CONFIG_PORT_B 1 114 #define AML_MMC_MULT_CONFIG_PORT_C 2 115 116 #define AML_MMC_DMA_ADDR_REG 24 117 118 #define AML_MMC_EXTENSION_REG 28 119 #define AML_MMC_EXTENSION_NO_CRC16 (1 << 30) 120 #define AML_MMC_EXTENSION_PKT_SIZE_MASK (0x3fff << 16) 121 #define AML_MMC_EXTENSION_PKT_SIZE_SHIFT 16 122 123 #endif /* _ARM_AMLOGIC_AML8726_MMC_H */ 124