1 /*-
2 * Copyright 2013-2015 John Wehle <john@feith.com>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 */
27
28 /*
29 * Amlogic aml8726 timer driver.
30 *
31 * 16 bit Timer A is used for the event timer / hard clock.
32 * 32 bit Timer E is used for the timecounter / DELAY.
33 *
34 * The current implementation doesn't use Timers B-D. Another approach is
35 * to split the timers between the cores implementing per cpu event timers.
36 *
37 * The timers all share the MUX register which requires a mutex to serialize
38 * access. The mutex is also used to avoid potential problems between the
39 * interrupt handler and timer_start / timer_stop.
40 */
41
42 #include <sys/cdefs.h>
43 __FBSDID("$FreeBSD$");
44
45 #include <sys/param.h>
46 #include <sys/systm.h>
47 #include <sys/bus.h>
48 #include <sys/kernel.h>
49 #include <sys/module.h>
50 #include <sys/malloc.h>
51 #include <sys/rman.h>
52 #include <sys/timetc.h>
53 #include <sys/timeet.h>
54
55 #include <machine/bus.h>
56 #include <machine/cpu.h>
57
58 #include <dev/fdt/fdt_common.h>
59 #include <dev/ofw/ofw_bus.h>
60 #include <dev/ofw/ofw_bus_subr.h>
61
62 struct aml8726_timer_softc {
63 device_t dev;
64 struct resource * res[2];
65 struct mtx mtx;
66 void * ih_cookie;
67 struct eventtimer et;
68 uint32_t first_ticks;
69 uint32_t period_ticks;
70 struct timecounter tc;
71 };
72
73 static struct resource_spec aml8726_timer_spec[] = {
74 { SYS_RES_MEMORY, 0, RF_ACTIVE },
75 { SYS_RES_IRQ, 0, RF_ACTIVE }, /* INT_TIMER_A */
76 { -1, 0 }
77 };
78
79 /*
80 * devclass_get_device / device_get_softc could be used
81 * to dynamically locate this, however the timers are a
82 * required device which can't be unloaded so there's
83 * no need for the overhead.
84 */
85 static struct aml8726_timer_softc *aml8726_timer_sc = NULL;
86
87 #define AML_TIMER_LOCK(sc) mtx_lock_spin(&(sc)->mtx)
88 #define AML_TIMER_UNLOCK(sc) mtx_unlock_spin(&(sc)->mtx)
89 #define AML_TIMER_LOCK_INIT(sc) \
90 mtx_init(&(sc)->mtx, device_get_nameunit((sc)->dev), \
91 "timer", MTX_SPIN)
92 #define AML_TIMER_LOCK_DESTROY(sc) mtx_destroy(&(sc)->mtx);
93
94 #define AML_TIMER_MUX_REG 0
95 #define AML_TIMER_INPUT_1us 0
96 #define AML_TIMER_INPUT_10us 1
97 #define AML_TIMER_INPUT_100us 2
98 #define AML_TIMER_INPUT_1ms 3
99 #define AML_TIMER_INPUT_MASK 3
100 #define AML_TIMER_A_INPUT_MASK 3
101 #define AML_TIMER_A_INPUT_SHIFT 0
102 #define AML_TIMER_B_INPUT_MASK (3 << 2)
103 #define AML_TIMER_B_INPUT_SHIFT 2
104 #define AML_TIMER_C_INPUT_MASK (3 << 4)
105 #define AML_TIMER_C_INPUT_SHIFT 4
106 #define AML_TIMER_D_INPUT_MASK (3 << 6)
107 #define AML_TIMER_D_INPUT_SHIFT 6
108 #define AML_TIMER_E_INPUT_SYS 0
109 #define AML_TIMER_E_INPUT_1us 1
110 #define AML_TIMER_E_INPUT_10us 2
111 #define AML_TIMER_E_INPUT_100us 3
112 #define AML_TIMER_E_INPUT_1ms 4
113 #define AML_TIMER_E_INPUT_MASK (7 << 8)
114 #define AML_TIMER_E_INPUT_SHIFT 8
115 #define AML_TIMER_A_PERIODIC (1 << 12)
116 #define AML_TIMER_B_PERIODIC (1 << 13)
117 #define AML_TIMER_C_PERIODIC (1 << 14)
118 #define AML_TIMER_D_PERIODIC (1 << 15)
119 #define AML_TIMER_A_EN (1 << 16)
120 #define AML_TIMER_B_EN (1 << 17)
121 #define AML_TIMER_C_EN (1 << 18)
122 #define AML_TIMER_D_EN (1 << 19)
123 #define AML_TIMER_E_EN (1 << 20)
124 #define AML_TIMER_A_REG 4
125 #define AML_TIMER_B_REG 8
126 #define AML_TIMER_C_REG 12
127 #define AML_TIMER_D_REG 16
128 #define AML_TIMER_E_REG 20
129
130 #define CSR_WRITE_4(sc, reg, val) bus_write_4((sc)->res[0], reg, (val))
131 #define CSR_READ_4(sc, reg) bus_read_4((sc)->res[0], reg)
132
133 static unsigned
aml8726_get_timecount(struct timecounter * tc)134 aml8726_get_timecount(struct timecounter *tc)
135 {
136 struct aml8726_timer_softc *sc =
137 (struct aml8726_timer_softc *)tc->tc_priv;
138
139 return CSR_READ_4(sc, AML_TIMER_E_REG);
140 }
141
142 static int
aml8726_hardclock(void * arg)143 aml8726_hardclock(void *arg)
144 {
145 struct aml8726_timer_softc *sc = (struct aml8726_timer_softc *)arg;
146
147 AML_TIMER_LOCK(sc);
148
149 if (sc->first_ticks != 0 && sc->period_ticks != 0) {
150 sc->first_ticks = 0;
151
152 CSR_WRITE_4(sc, AML_TIMER_A_REG, sc->period_ticks);
153 CSR_WRITE_4(sc, AML_TIMER_MUX_REG,
154 (CSR_READ_4(sc, AML_TIMER_MUX_REG) |
155 AML_TIMER_A_PERIODIC | AML_TIMER_A_EN));
156 }
157
158 AML_TIMER_UNLOCK(sc);
159
160 if (sc->et.et_active)
161 sc->et.et_event_cb(&sc->et, sc->et.et_arg);
162
163 return (FILTER_HANDLED);
164 }
165
166 static int
aml8726_timer_start(struct eventtimer * et,sbintime_t first,sbintime_t period)167 aml8726_timer_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
168 {
169 struct aml8726_timer_softc *sc =
170 (struct aml8726_timer_softc *)et->et_priv;
171 uint32_t first_ticks;
172 uint32_t period_ticks;
173 uint32_t periodic;
174 uint32_t ticks;
175
176 first_ticks = (first * et->et_frequency) / SBT_1S;
177 period_ticks = (period * et->et_frequency) / SBT_1S;
178
179 if (first_ticks != 0) {
180 ticks = first_ticks;
181 periodic = 0;
182
183 } else {
184 ticks = period_ticks;
185 periodic = AML_TIMER_A_PERIODIC;
186 }
187
188 if (ticks == 0)
189 return (EINVAL);
190
191 AML_TIMER_LOCK(sc);
192
193 sc->first_ticks = first_ticks;
194 sc->period_ticks = period_ticks;
195
196 CSR_WRITE_4(sc, AML_TIMER_A_REG, ticks);
197 CSR_WRITE_4(sc, AML_TIMER_MUX_REG,
198 ((CSR_READ_4(sc, AML_TIMER_MUX_REG) & ~AML_TIMER_A_PERIODIC) |
199 AML_TIMER_A_EN | periodic));
200
201 AML_TIMER_UNLOCK(sc);
202
203 return (0);
204 }
205
206 static int
aml8726_timer_stop(struct eventtimer * et)207 aml8726_timer_stop(struct eventtimer *et)
208 {
209 struct aml8726_timer_softc *sc =
210 (struct aml8726_timer_softc *)et->et_priv;
211
212 AML_TIMER_LOCK(sc);
213
214 CSR_WRITE_4(sc, AML_TIMER_MUX_REG,
215 (CSR_READ_4(sc, AML_TIMER_MUX_REG) & ~AML_TIMER_A_EN));
216
217 AML_TIMER_UNLOCK(sc);
218
219 return (0);
220 }
221
222 static int
aml8726_timer_probe(device_t dev)223 aml8726_timer_probe(device_t dev)
224 {
225
226 if (!ofw_bus_status_okay(dev))
227 return (ENXIO);
228
229 if (!ofw_bus_is_compatible(dev, "amlogic,meson6-timer"))
230 return (ENXIO);
231
232 device_set_desc(dev, "Amlogic aml8726 timer");
233
234 return (BUS_PROBE_DEFAULT);
235 }
236
237 static int
aml8726_timer_attach(device_t dev)238 aml8726_timer_attach(device_t dev)
239 {
240 struct aml8726_timer_softc *sc = device_get_softc(dev);
241
242 /* There should be exactly one instance. */
243 if (aml8726_timer_sc != NULL)
244 return (ENXIO);
245
246 sc->dev = dev;
247
248 if (bus_alloc_resources(dev, aml8726_timer_spec, sc->res)) {
249 device_printf(dev, "can not allocate resources for device\n");
250 return (ENXIO);
251 }
252
253 /*
254 * Disable the timers, select the input for each timer,
255 * clear timer E, and then enable timer E.
256 */
257 CSR_WRITE_4(sc, AML_TIMER_MUX_REG,
258 ((CSR_READ_4(sc, AML_TIMER_MUX_REG) &
259 ~(AML_TIMER_A_EN | AML_TIMER_A_INPUT_MASK |
260 AML_TIMER_E_EN | AML_TIMER_E_INPUT_MASK)) |
261 (AML_TIMER_INPUT_1us << AML_TIMER_A_INPUT_SHIFT) |
262 (AML_TIMER_E_INPUT_1us << AML_TIMER_E_INPUT_SHIFT)));
263
264 CSR_WRITE_4(sc, AML_TIMER_E_REG, 0);
265
266 CSR_WRITE_4(sc, AML_TIMER_MUX_REG,
267 (CSR_READ_4(sc, AML_TIMER_MUX_REG) | AML_TIMER_E_EN));
268
269 /*
270 * Initialize the mutex prior to installing the interrupt handler
271 * in case of a spurious interrupt.
272 */
273 AML_TIMER_LOCK_INIT(sc);
274
275 if (bus_setup_intr(dev, sc->res[1], INTR_TYPE_CLK,
276 aml8726_hardclock, NULL, sc, &sc->ih_cookie)) {
277 device_printf(dev, "could not setup interrupt handler\n");
278 bus_release_resources(dev, aml8726_timer_spec, sc->res);
279 AML_TIMER_LOCK_DESTROY(sc);
280 return (ENXIO);
281 }
282
283 aml8726_timer_sc = sc;
284
285 sc->et.et_name = "aml8726 timer A";
286 sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT;
287 sc->et.et_frequency = 1000000;
288 sc->et.et_quality = 1000;
289 sc->et.et_min_period = (0x00000002LLU * SBT_1S) / sc->et.et_frequency;
290 sc->et.et_max_period = (0x0000fffeLLU * SBT_1S) / sc->et.et_frequency;
291 sc->et.et_start = aml8726_timer_start;
292 sc->et.et_stop = aml8726_timer_stop;
293 sc->et.et_priv = sc;
294
295 et_register(&sc->et);
296
297 sc->tc.tc_get_timecount = aml8726_get_timecount;
298 sc->tc.tc_name = "aml8726 timer E";
299 sc->tc.tc_frequency = 1000000;
300 sc->tc.tc_counter_mask = ~0u;
301 sc->tc.tc_quality = 1000;
302 sc->tc.tc_priv = sc;
303
304 tc_init(&sc->tc);
305
306 return (0);
307 }
308
309 static int
aml8726_timer_detach(device_t dev)310 aml8726_timer_detach(device_t dev)
311 {
312
313 return (EBUSY);
314 }
315
316 static device_method_t aml8726_timer_methods[] = {
317 /* Device interface */
318 DEVMETHOD(device_probe, aml8726_timer_probe),
319 DEVMETHOD(device_attach, aml8726_timer_attach),
320 DEVMETHOD(device_detach, aml8726_timer_detach),
321
322 DEVMETHOD_END
323 };
324
325 static driver_t aml8726_timer_driver = {
326 "timer",
327 aml8726_timer_methods,
328 sizeof(struct aml8726_timer_softc),
329 };
330
331 static devclass_t aml8726_timer_devclass;
332
333 EARLY_DRIVER_MODULE(timer, simplebus, aml8726_timer_driver,
334 aml8726_timer_devclass, 0, 0, BUS_PASS_TIMER);
335
336 void
DELAY(int usec)337 DELAY(int usec)
338 {
339 uint32_t counter;
340 uint32_t delta, now, previous, remaining;
341
342 /* Timer has not yet been initialized */
343 if (aml8726_timer_sc == NULL) {
344 for (; usec > 0; usec--)
345 for (counter = 200; counter > 0; counter--) {
346 /* Prevent gcc from optimizing out the loop */
347 cpufunc_nullop();
348 }
349 return;
350 }
351
352 /*
353 * Some of the other timers in the source tree do this calculation as:
354 *
355 * usec * ((sc->tc.tc_frequency / 1000000) + 1)
356 *
357 * which gives a fairly pessimistic result when tc_frequency is an exact
358 * multiple of 1000000. Given the data type and typical values for
359 * tc_frequency adding 999999 shouldn't overflow.
360 */
361 remaining = usec * ((aml8726_timer_sc->tc.tc_frequency + 999999) /
362 1000000);
363
364 /*
365 * We add one since the first iteration may catch the counter just
366 * as it is changing.
367 */
368 remaining += 1;
369
370 previous = aml8726_get_timecount(&aml8726_timer_sc->tc);
371
372 for ( ; ; ) {
373 now = aml8726_get_timecount(&aml8726_timer_sc->tc);
374
375 /*
376 * If the timer has rolled over, then we have the case:
377 *
378 * if (previous > now) {
379 * delta = (0 - previous) + now
380 * }
381 *
382 * which is really no different then the normal case.
383 * Both cases are simply:
384 *
385 * delta = now - previous.
386 */
387 delta = now - previous;
388
389 if (delta >= remaining)
390 break;
391
392 previous = now;
393 remaining -= delta;
394 }
395 }
396