1 /* $NetBSD: imx51_ccmreg.h,v 1.1 2012/04/17 09:33:31 bsh Exp $ */ 2 /* 3 * Copyright (c) 2011, 2012 Genetec Corporation. All rights reserved. 4 * Written by Hashimoto Kenichi for Genetec Corporation. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 17 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 18 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 19 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 /*- 29 * Copyright (c) 2012, 2013 The FreeBSD Foundation 30 * All rights reserved. 31 * 32 * Portions of this software were developed by Oleksandr Rybalko 33 * under sponsorship from the FreeBSD Foundation. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 44 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 45 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 46 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 47 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 48 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 49 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 50 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 51 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 52 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 53 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 54 * SUCH DAMAGE. 55 * 56 * $FreeBSD$ 57 */ 58 59 #ifndef _IMX51_CCMREG_H 60 #define _IMX51_CCMREG_H 61 62 #include <sys/cdefs.h> 63 64 /* register offset address */ 65 66 #define CCMC_BASE 0x73fd4000 67 #define CCMC_CCR 0x0000 68 #define CCR_FPM_MULT 0x00001000 69 #define CCMC_CCDR 0x0004 70 #define CCMC_CSR 0x0008 71 #define CCMC_CCSR 0x000c 72 #define CCSR_LP_APM 0x00000200 73 #define CCSR_STEP_SEL_SHIFT 7 74 #define CCSR_STEP_SEL_MASK 0x00000180 75 #define CCSR_PLL2_DIV_PODF_SHIFT 5 76 #define CCSR_PLL2_DIV_PODF_MASK 0x00000060 77 #define CCSR_PLL3_DIV_PODF_SHIFT 3 78 #define CCSR_PLL3_DIV_PODF_MASK 0x00000030 79 #define CCSR_PLL1_SW_CLK_SEL 0x00000004 80 #define CCSR_PLL2_SW_CLK_SEL 0x00000002 81 #define CCSR_PLL3_SW_CLK_SEL 0x00000001 82 #define CCMC_CACRR 0x0010 83 #define CCMC_CBCDR 0x0014 84 #define CBCDR_DDR_HIGH_FREQ_CLK_SEL 0x40000000 85 #define CBCDR_DDR_CLK_PODF_SHIFT 27 86 #define CBCDR_DDR_CLK_PODF_MASK 0x38000000 87 #define CBCDR_EMI_CLK_SEL 0x04000000 88 #define CBCDR_PERIPH_CLK_SEL 0x02000000 89 #define CBCDR_EMI_SLOW_PODF_SHIFT 22 90 #define CBCDR_EMI_SLOW_PODF_MASK 0x01c00000 91 #define CBCDR_AXI_B_PODF_SHIFT 19 92 #define CBCDR_AXI_B_PODF_MASK 0x00380000 93 #define CBCDR_AXI_A_PODF_SHIFT 16 94 #define CBCDR_AXI_A_PODF_MASK 0x1fff0000 95 #define CBCDR_NFC_PODF_SHIFT 13 96 #define CBCDR_NFC_PODF_MASK 0x00018000 97 #define CBCDR_AHB_PODF_SHIFT 10 98 #define CBCDR_AHB_PODF_MASK 0x00001c00 99 #define CBCDR_IPG_PODF_SHIFT 8 100 #define CBCDR_IPG_PODF_MASK 0x00000300 101 #define CBCDR_PERCLK_PRED1_SHIFT 6 102 #define CBCDR_PERCLK_PRED1_MASK 0x000000c0 103 #define CBCDR_PERCLK_PRED2_SHIFT 3 104 #define CBCDR_PERCLK_PRED2_MASK 0x00000038 105 #define CBCDR_PERCLK_PODF_SHIFT 0 106 #define CBCDR_PERCLK_PODF_MASK 0x00000007 107 #define CCMC_CBCMR 0x0018 108 #define CBCMR_PERIPH_APM_SEL_SHIFT 12 109 #define CBCMR_PERIPH_APM_SEL_MASK 0x00003000 110 #define CBCMR_IPU_HSP_CLK_SEL_SHIFT 6 111 #define CBCMR_IPU_HSP_CLK_SEL_MASK 0x000000c0 112 #define CBCMR_PERCLK_LP_APM_SEL 0x00000002 113 #define CBCMR_PERCLK_IPG_SEL 0x00000001 114 #define CCMC_CSCMR1 0x001c 115 #define CSCMR1_UART_CLK_SEL_SHIFT 24 116 #define CSCMR1_UART_CLK_SEL_MASK 0x03000000 117 #define CSCMR1_USBPHY_CLK_SEL_SHIFT 26 118 #define CSCMR1_USBPHY_CLK_SEL_MASK 0x04000000 119 #define CSCMR1_USBOH3_CLK_SEL_SHIFT 22 120 #define CSCMR1_USBOH3_CLK_SEL_MASK 0x00c00000 121 #define CCMC_CSCMR2 0x0020 122 #define CCMC_CSCDR1 0x0024 123 #define CSCDR1_UART_CLK_PRED_SHIFT 3 124 #define CSCDR1_UART_CLK_PRED_MASK 0x00000038 125 #define CSCDR1_UART_CLK_PODF_SHIFT 0 126 #define CSCDR1_UART_CLK_PODF_MASK 0x00000007 127 #define CSCDR1_USBOH3_CLK_PRED_SHIFT 8 128 #define CSCDR1_USBOH3_CLK_PRED_MASK 0x00000700 129 #define CSCDR1_USBOH3_CLK_PODF_SHIFT 6 130 #define CSCDR1_USBOH3_CLK_PODF_MASK 0x000000c0 131 #define CCMC_CS1CDR 0x0028 132 #define CCMC_CS2CDR 0x002c 133 #define CCMC_CDCDR 0x0030 134 #define CCMC_CSCDR2 0x0038 135 #define CCMC_CSCDR3 0x003c 136 #define CCMC_CSCDR4 0x0040 137 #define CCMC_CWDR 0x0044 138 #define CCMC_CDHIPR 0x0048 139 #define CCMC_CDCR 0x004c 140 #define CDCR_PERIPH_CLK_DVFS_PODF_SHIFT 0 141 #define CDCR_PERIPH_CLK_DVFS_PODF_MASK 0x00000003 142 #define CCMC_CTOR 0x0050 143 #define CCMC_CLPCR 0x0054 144 #define CCMC_CISR 0x0058 145 #define CCMC_CIMR 0x005c 146 #define CCMC_CCOSR 0x0060 147 #define CCMC_CGPR 0x0064 148 #define CCMC_CCGR(n) (0x0068 + (n) * 4) 149 #define CCMC_CMEOR 0x0084 150 151 #define CCMC_SIZE 0x88 152 153 /* CCGR Clock Gate Register */ 154 155 #define CCMR_CCGR_NSOURCE 16 156 #define CCMR_CCGR_NGROUPS 7 157 #define CCMR_CCGR_MODULE(clk) ((clk) / CCMR_CCGR_NSOURCE) 158 #define __CCGR_NUM(a, b) ((a) * 16 + (b)) 159 160 #define CCGR_ARM_BUS_CLK __CCGR_NUM(0, 0) 161 #define CCGR_ARM_AXI_CLK __CCGR_NUM(0, 1) 162 #define CCGR_ARM_DEBUG_CLK __CCGR_NUM(0, 2) 163 #define CCGR_TZIC_CLK __CCGR_NUM(0, 3) 164 #define CCGR_DAP_CLK __CCGR_NUM(0, 4) 165 #define CCGR_TPIU_CLK __CCGR_NUM(0, 5) 166 #define CCGR_CTI2_CLK __CCGR_NUM(0, 6) 167 #define CCGR_CTI3_CLK __CCGR_NUM(0, 7) 168 #define CCGR_AHBMUX1_CLK __CCGR_NUM(0, 8) 169 #define CCGR_AHBMUX2_CLK __CCGR_NUM(0, 9) 170 #define CCGR_ROMCP_CLK __CCGR_NUM(0, 10) 171 #define CCGR_ROM_CLK __CCGR_NUM(0, 11) 172 #define CCGR_AIPS_TZ1_CLK __CCGR_NUM(0, 12) 173 #define CCGR_AIPS_TZ2_CLK __CCGR_NUM(0, 13) 174 #define CCGR_AHB_MAX_CLK __CCGR_NUM(0, 14) 175 #define CCGR_IIM_CLK __CCGR_NUM(0, 15) 176 #define CCGR_TMAX1_CLK __CCGR_NUM(1, 0) 177 #define CCGR_TMAX2_CLK __CCGR_NUM(1, 1) 178 #define CCGR_TMAX3_CLK __CCGR_NUM(1, 2) 179 #define CCGR_UART1_CLK __CCGR_NUM(1, 3) 180 #define CCGR_UART1_SERIAL_CLK __CCGR_NUM(1, 4) 181 #define CCGR_UART2_CLK __CCGR_NUM(1, 5) 182 #define CCGR_UART2_SERIAL_CLK __CCGR_NUM(1, 6) 183 #define CCGR_UART3_CLK __CCGR_NUM(1, 7) 184 #define CCGR_UART3_SERIAL_CLK __CCGR_NUM(1, 8) 185 #define CCGR_I2C1_SERIAL_CLK __CCGR_NUM(1, 9) 186 #define CCGR_I2C2_SERIAL_CLK __CCGR_NUM(1, 10) 187 #define CCGR_HSI2C_CLK __CCGR_NUM(1, 11) 188 #define CCGR_HSI2C_SERIAL_CLK __CCGR_NUM(1, 12) 189 #define CCGR_FIRI_CLK __CCGR_NUM(1, 13) 190 #define CCGR_FIRI_SERIAL_CLK __CCGR_NUM(1, 14) 191 #define CCGR_SCC_CLK __CCGR_NUM(1, 15) 192 193 #define CCGR_USB_PHY_CLK __CCGR_NUM(2, 0) 194 #define CCGR_EPIT1_CLK __CCGR_NUM(2, 1) 195 #define CCGR_EPIT1_SERIAL_CLK __CCGR_NUM(2, 2) 196 #define CCGR_EPIT2_CLK __CCGR_NUM(2, 3) 197 #define CCGR_EPIT2_SERIAL_CLK __CCGR_NUM(2, 4) 198 #define CCGR_PWM1_CLK __CCGR_NUM(2, 5) 199 #define CCGR_PWM1_SERIAL_CLK __CCGR_NUM(2, 6) 200 #define CCGR_PWM2_CLK __CCGR_NUM(2, 7) 201 #define CCGR_PWM2_SERIAL_CLK __CCGR_NUM(2, 8) 202 #define CCGR_GPT_CLK __CCGR_NUM(2, 9) 203 #define CCGR_GPT_SERIAL_CLK __CCGR_NUM(2, 10) 204 #define CCGR_OWIRE_CLK __CCGR_NUM(2, 11) 205 #define CCGR_FEC_CLK __CCGR_NUM(2, 12) 206 #define CCGR_USBOH3_IPG_AHB_CLK __CCGR_NUM(2, 13) 207 #define CCGR_USBOH3_60M_CLK __CCGR_NUM(2, 14) 208 #define CCGR_TVE_CLK __CCGR_NUM(2, 15) 209 210 #define CCGR_ESDHC1_CLK __CCGR_NUM(3, 0) 211 #define CCGR_ESDHC1_SERIAL_CLK __CCGR_NUM(3, 1) 212 #define CCGR_ESDHC2_CLK __CCGR_NUM(3, 2) 213 #define CCGR_ESDHC2_SERIAL_CLK __CCGR_NUM(3, 3) 214 #define CCGR_ESDHC3_CLK __CCGR_NUM(3, 4) 215 #define CCGR_ESDHC3_SERIAL_CLK __CCGR_NUM(3, 5) 216 #define CCGR_ESDHC4_CLK __CCGR_NUM(3, 6) 217 #define CCGR_ESDHC4_SERIAL_CLK __CCGR_NUM(3, 7) 218 #define CCGR_SSI1_CLK __CCGR_NUM(3, 8) 219 #define CCGR_SSI1_SERIAL_CLK __CCGR_NUM(3, 9) 220 #define CCGR_SSI2_CLK __CCGR_NUM(3, 10) 221 #define CCGR_SSI2_SERIAL_CLK __CCGR_NUM(3, 11) 222 #define CCGR_SSI3_CLK __CCGR_NUM(3, 12) 223 #define CCGR_SSI3_SERIAL_CLK __CCGR_NUM(3, 13) 224 #define CCGR_SSI_EXT1_CLK __CCGR_NUM(3, 14) 225 #define CCGR_SSI_EXT2_CLK __CCGR_NUM(3, 15) 226 227 #define CCGR_PATA_CLK __CCGR_NUM(4, 0) 228 #define CCGR_SIM_CLK __CCGR_NUM(4, 1) 229 #define CCGR_SIM_SERIAL_CLK __CCGR_NUM(4, 2) 230 #define CCGR_SAHARA_CLK __CCGR_NUM(4, 3) 231 #define CCGR_RTIC_CLK __CCGR_NUM(4, 4) 232 #define CCGR_ECSPI1_CLK __CCGR_NUM(4, 5) 233 #define CCGR_ECSPI1_SERIAL_CLK __CCGR_NUM(4, 6) 234 #define CCGR_ECSPI2_CLK __CCGR_NUM(4, 7) 235 #define CCGR_ECSPI2_SERIAL_CLK __CCGR_NUM(4, 8) 236 #define CCGR_CSPI_CLK __CCGR_NUM(4, 9) 237 #define CCGR_SRTC_CLK __CCGR_NUM(4, 10) 238 #define CCGR_SDMA_CLK __CCGR_NUM(4, 11) 239 240 #define CCGR_SPBA_CLK __CCGR_NUM(5, 0) 241 #define CCGR_GPU_CLK __CCGR_NUM(5, 1) 242 #define CCGR_GARB_CLK __CCGR_NUM(5, 2) 243 #define CCGR_VPU_CLK __CCGR_NUM(5, 3) 244 #define CCGR_VPU_SERIAL_CLK __CCGR_NUM(5, 4) 245 #define CCGR_IPU_CLK __CCGR_NUM(5, 5) 246 #define CCGR_EMI_GARB_CLK __CCGR_NUM(6, 0) 247 #define CCGR_IPU_DI0_CLK __CCGR_NUM(6, 1) 248 #define CCGR_IPU_DI1_CLK __CCGR_NUM(6, 2) 249 #define CCGR_GPU2D_CLK __CCGR_NUM(6, 3) 250 #define CCGR_SLIMBUS_CLK __CCGR_NUM(6, 4) 251 #define CCGR_SLIMBUS_SERIAL_CLK __CCGR_NUM(6, 5) 252 253 #define CCGR_CLK_MODE_OFF 0 254 #define CCGR_CLK_MODE_RUNMODE 1 255 #define CCGR_CLK_MODE_ALWAYS 3 256 257 #endif /* _IMX51_CCMREG_H */ 258 259