1 /*- 2 * Copyright (c) 2012, 2013 The FreeBSD Foundation 3 * All rights reserved. 4 * 5 * This software was developed by Oleksandr Rybalko under sponsorship 6 * from the FreeBSD Foundation. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 32 /* Registers definition for Freescale i.MX515 Synchronous Serial Interface */ 33 34 #define IMX51_SSI_STX0_REG 0x0000 /* SSI TX Data Register 0 */ 35 #define IMX51_SSI_STX1_REG 0x0004 /* SSI TX Data Register 1 */ 36 #define IMX51_SSI_SRX0_REG 0x0008 /* SSI RX Data Register 0 */ 37 #define IMX51_SSI_SRX1_REG 0x000C /* SSI RX Data Register 1 */ 38 #define IMX51_SSI_SCR_REG 0x0010 /* SSI Control Register */ 39 #define SSI_SCR_RFR_CLK_DIS (1 << 11) /* RX FC Disable */ 40 #define SSI_SCR_TFR_CLK_DIS (1 << 10) /* TX FC Disable */ 41 #define SSI_SCR_CLK_IST (1 << 9) /* Clock Idle */ 42 #define SSI_SCR_TCH_EN (1 << 8) /* 2Chan Enable */ 43 #define SSI_SCR_SYS_CLK_EN (1 << 7) /* System Clock En */ 44 #define SSI_SCR_MODE_NORMAL (0 << 5) 45 #define SSI_SCR_MODE_I2S_MASTER (1 << 5) 46 #define SSI_SCR_MODE_I2S_SLAVE (2 << 5) 47 #define SSI_SCR_MODE_MASK (3 << 5) 48 #define SSI_SCR_SYN (1 << 4) /* Sync Mode */ 49 #define SSI_SCR_NET (1 << 3) /* Network Mode */ 50 #define SSI_SCR_RE (1 << 2) /* RX Enable */ 51 #define SSI_SCR_TE (1 << 1) /* TX Enable */ 52 #define SSI_SCR_SSIEN (1 << 0) /* SSI Enable */ 53 54 #define IMX51_SSI_SISR_REG 0x0014 /* SSI Interrupt Status Register */ 55 #define SSI_SISR_RFRC (1 << 24) /* RX Frame Complete */ 56 #define SSI_SIR_TFRC (1 << 23) /* TX Frame Complete */ 57 #define SSI_SIR_CMDAU (1 << 18) /* Command Address Updated */ 58 #define SSI_SIR_CMDDU (1 << 17) /* Command Data Updated */ 59 #define SSI_SIR_RXT (1 << 16) /* RX Tag Updated */ 60 #define SSI_SIR_RDR1 (1 << 15) /* RX Data Ready 1 */ 61 #define SSI_SIR_RDR0 (1 << 14) /* RX Data Ready 0 */ 62 #define SSI_SIR_TDE1 (1 << 13) /* TX Data Reg Empty 1 */ 63 #define SSI_SIR_TDE0 (1 << 12) /* TX Data Reg Empty 0 */ 64 #define SSI_SIR_ROE1 (1 << 11) /* RXer Overrun Error 1 */ 65 #define SSI_SIR_ROE0 (1 << 10) /* RXer Overrun Error 0 */ 66 #define SSI_SIR_TUE1 (1 << 9) /* TXer Underrun Error 1 */ 67 #define SSI_SIR_TUE0 (1 << 8) /* TXer Underrun Error 0 */ 68 #define SSI_SIR_TFS (1 << 7) /* TX Frame Sync */ 69 #define SSI_SIR_RFS (1 << 6) /* RX Frame Sync */ 70 #define SSI_SIR_TLS (1 << 5) /* TX Last Time Slot */ 71 #define SSI_SIR_RLS (1 << 4) /* RX Last Time Slot */ 72 #define SSI_SIR_RFF1 (1 << 3) /* RX FIFO Full 1 */ 73 #define SSI_SIR_RFF0 (1 << 2) /* RX FIFO Full 0 */ 74 #define SSI_SIR_TFE1 (1 << 1) /* TX FIFO Empty 1 */ 75 #define SSI_SIR_TFE0 (1 << 0) /* TX FIFO Empty 0 */ 76 77 #define IMX51_SSI_SIER_REG 0x0018 /* SSI Interrupt Enable Register */ 78 /* 24-23 Enable Bit (See SISR) */ 79 #define SSI_SIER_RDMAE (1 << 22) /* RX DMA Enable */ 80 #define SSI_SIER_RIE (1 << 21) /* RX Interrupt Enable */ 81 #define SSI_SIER_TDMAE (1 << 20) /* TX DMA Enable */ 82 #define SSI_SIER_TIE (1 << 19) /* TX Interrupt Enable */ 83 /* 18-0 Enable Bits (See SISR) */ 84 85 #define IMX51_SSI_STCR_REG 0x001C /* SSI TX Configuration Register */ 86 #define SSI_STCR_TXBIT0 (1 << 9) /* TX Bit 0 */ 87 #define SSI_STCR_TFEN1 (1 << 8) /* TX FIFO Enable 1 */ 88 #define SSI_STCR_TFEN0 (1 << 7) /* TX FIFO Enable 0 */ 89 #define SSI_STCR_TFDIR (1 << 6) /* TX Frame Direction */ 90 #define SSI_STCR_TXDIR (1 << 5) /* TX Clock Direction */ 91 #define SSI_STCR_TSHFD (1 << 4) /* TX Shift Direction */ 92 #define SSI_STCR_TSCKP (1 << 3) /* TX Clock Polarity */ 93 #define SSI_STCR_TFSI (1 << 2) /* TX Frame Sync Invert */ 94 #define SSI_STCR_TFSL (1 << 1) /* TX Frame Sync Length */ 95 #define SSI_STCR_TEFS (1 << 0) /* TX Early Frame Sync */ 96 97 #define IMX51_SSI_SRCR_REG 0x0020 /* SSI RX Configuration Register */ 98 #define SSI_SRCR_RXEXT (1 << 10) /* RX Data Extension */ 99 #define SSI_SRCR_RXBIT0 (1 << 9) /* RX Bit 0 */ 100 #define SSI_SRCR_RFEN1 (1 << 8) /* RX FIFO Enable 1 */ 101 #define SSI_SRCR_RFEN0 (1 << 7) /* RX FIFO Enable 0 */ 102 #define SSI_SRCR_RFDIR (1 << 6) /* RX Frame Direction */ 103 #define SSI_SRCR_RXDIR (1 << 5) /* RX Clock Direction */ 104 #define SSI_SRCR_RSHFD (1 << 4) /* RX Shift Direction */ 105 #define SSI_SRCR_RSCKP (1 << 3) /* RX Clock Polarity */ 106 #define SSI_SRCR_RFSI (1 << 2) /* RX Frame Sync Invert */ 107 #define SSI_SRCR_RFSL (1 << 1) /* RX Frame Sync Length */ 108 #define SSI_SRCR_REFS (1 << 0) /* RX Early Frame Sync */ 109 110 #define IMX51_SSI_STCCR_REG 0x0024 /* TX Clock Control */ 111 #define IMX51_SSI_SRCCR_REG 0x0028 /* RX Clock Control */ 112 #define SSI_SXCCR_DIV2 (1 << 18) /* Divide By 2 */ 113 #define SSI_SXCCR_PSR (1 << 17) /* Prescaler Range */ 114 #define SSI_SXCCR_WL_MASK 0x0001e000 115 #define SSI_SXCCR_WL_SHIFT 13 /* Word Length Control */ 116 #define SSI_SXCCR_DC_MASK 0x00001f00 117 #define SSI_SXCCR_DC_SHIFT 8 /* Frame Rate Divider */ 118 #define SSI_SXCCR_PM_MASK 0x000000ff 119 #define SSI_SXCCR_PM_SHIFT 0 /* Prescaler Modulus */ 120 121 #define IMX51_SSI_SFCSR_REG 0x002C /* SSI FIFO Control/Status Register */ 122 #define SSI_SFCSR_RFCNT1_MASK 0xf0000000 123 #define SSI_SFCSR_RFCNT1_SHIFT 28 /* RX FIFO Counter 1 */ 124 #define SSI_SFCSR_TFCNT1_MASK 0x0f000000 125 #define SSI_SFCSR_TFCNT1_SHIFT 24 /* TX FIFO Counter 1 */ 126 #define SSI_SFCSR_RFWM1_MASK 0x00f00000 127 #define SSI_SFCSR_RFWM1_SHIFT 20 /* RX FIFO Full WaterMark 1 */ 128 #define SSI_SFCSR_TFWM1_MASK 0x000f0000 129 #define SSI_SFCSR_TFWM1_SHIFT 16 /* TX FIFO Empty WaterMark 1 */ 130 #define SSI_SFCSR_RFCNT0_MASK 0x0000f000 131 #define SSI_SFCSR_RFCNT0_SHIFT 12 /* RX FIFO Counter 0 */ 132 #define SSI_SFCSR_TFCNT0_MASK 0x00000f00 133 #define SSI_SFCSR_TFCNT0_SHIFT 8 /* TX FIFO Counter 0 */ 134 #define SSI_SFCSR_RFWM0_MASK 0x000000f0 135 #define SSI_SFCSR_RFWM0_SHIFT 4 /* RX FIFO Full WaterMark 0 */ 136 #define SSI_SFCSR_TFWM0_MASK 0x0000000f 137 #define SSI_SFCSR_TFWM0_SHIFT 0 /* TX FIFO Empty WaterMark 0 */ 138 139 #define IMX51_SSI_STR_REG 0x0030 /* SSI Test Register1 */ 140 #define SSI_STR_TEST (1 << 15) /* Test Mode */ 141 #define SSI_STR_RCK2TCK (1 << 14) /* RX<->TX Clock Loop Back */ 142 #define SSI_STR_RFS2TFS (1 << 13) /* RX<->TX Frame Loop Back */ 143 #define SSI_STR_RXSTATE_MASK 0x00001f00 144 #define SSI_STR_RXSTATE_SHIFT 8 /* RXer State Machine Status */ 145 #define SSI_STR_TXD2RXD (1 << 7) /* TX<->RX Data Loop Back */ 146 #define SSI_STR_TCK2RCK (1 << 6) /* TX<->RX Clock Loop Back */ 147 #define SSI_STR_TFS2RFS (1 << 5) /* TX<->RX Frame Loop Back */ 148 #define SSI_STR_TXSTATE_MASK 0x0000001f 149 #define SSI_STR_TXSTATE_SHIFT 0 /* TXer State Machine Status */ 150 151 #define IMX51_SSI_SOR_REG 0x0034 /* SSI Option Register2 */ 152 #define SSI_SOR_CLKOFF (1 << 6) /* Clock Off */ 153 #define SSI_SOR_RX_CLR (1 << 5) /* RXer Clear */ 154 #define SSI_SOR_TX_CLR (1 << 4) /* TXer Clear */ 155 #define SSI_SOR_INIT (1 << 3) /* Initialize */ 156 #define SSI_SOR_WAIT_MASK 0x00000006 157 #define SSI_SOR_INIT_SHIFT 1 /* Wait */ 158 #define SSI_SOR_SYNRST (1 << 0) /* Frame Sync Reset */ 159 160 #define IMX51_SSI_SACNT_REG 0x0038 /* SSI AC97 Control Register */ 161 #define SSI_SACNT_FRDIV_MASK 0x000007e0 162 #define SSI_SACNT_FRDIV_SHIFT 5 /* Frame Rate Divider */ 163 #define SSI_SACNT_WR (1 << 4) /* Write Command */ 164 #define SSI_SACNT_RD (1 << 3) /* Read Command */ 165 #define SSI_SACNT_TIF (1 << 2) /* Tag in FIFO */ 166 #define SSI_SACNT_FV (1 << 1) /* Fixed/Variable Operation */ 167 #define SSI_SACNT_AC97EN (1 << 0) /* AC97 Mode Enable */ 168 169 #define IMX51_SSI_SACADD_REG 0x003C /* SSI AC97 Command Address Register */ 170 #define SSI_SACADD_MASK 0x0007ffff 171 #define IMX51_SSI_SACDAT_REG 0x0040 /* SSI AC97 Command Data Register */ 172 #define SSI_SACDAT_MASK 0x000fffff 173 #define IMX51_SSI_SATAG_REG 0x0044 /* SSI AC97 Tag Register */ 174 #define SSI_SATAG_MASK 0x0000ffff 175 #define IMX51_SSI_STMSK_REG 0x0048 /* SSI TX Time Slot Mask Register */ 176 #define IMX51_SSI_SRMSK_REG 0x004C /* SSI RX Time Slot Mask Register */ 177 #define IMX51_SSI_SACCST_REG 0x0050 /* SSI AC97 Channel Status Register */ 178 #define IMX51_SSI_SACCEN_REG 0x0054 /* SSI AC97 Channel Enable Register */ 179 #define IMX51_SSI_SACCDIS_REG 0x0058 /* SSI AC97 Channel Disable Register */ 180 #define SSI_SAC_MASK 0x000003ff /* SACCST,SACCEN,SACCDIS */ 181