1 /*-
2 * Copyright (C) 2008-2009 Semihalf, Michal Hajduk
3 * Copyright (c) 2012, 2013 The FreeBSD Foundation
4 * Copyright (c) 2015 Ian Lepore <ian@FreeBSD.org>
5 * All rights reserved.
6 *
7 * Portions of this software were developed by Oleksandr Rybalko
8 * under sponsorship from the FreeBSD Foundation.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 */
31
32 /*
33 * I2C driver for Freescale i.MX hardware.
34 *
35 * Note that the hardware is capable of running as both a master and a slave.
36 * This driver currently implements only master-mode operations.
37 *
38 * This driver supports multi-master i2c busses, by detecting bus arbitration
39 * loss and returning IIC_EBUSBSY status. Notably, it does not do any kind of
40 * retries if some other master jumps onto the bus and interrupts one of our
41 * transfer cycles resulting in arbitration loss in mid-transfer. The caller
42 * must handle retries in a way that makes sense for the slave being addressed.
43 */
44
45 #include <sys/cdefs.h>
46 __FBSDID("$FreeBSD$");
47
48 #include <sys/param.h>
49 #include <sys/systm.h>
50 #include <sys/bus.h>
51 #include <sys/kernel.h>
52 #include <sys/limits.h>
53 #include <sys/module.h>
54 #include <sys/resource.h>
55
56 #include <machine/bus.h>
57 #include <machine/resource.h>
58 #include <sys/rman.h>
59
60 #include <arm/freescale/imx/imx_ccmvar.h>
61
62 #include <dev/iicbus/iiconf.h>
63 #include <dev/iicbus/iicbus.h>
64 #include "iicbus_if.h"
65
66 #include <dev/fdt/fdt_common.h>
67 #include <dev/ofw/openfirm.h>
68 #include <dev/ofw/ofw_bus.h>
69 #include <dev/ofw/ofw_bus_subr.h>
70
71 #define I2C_ADDR_REG 0x00 /* I2C slave address register */
72 #define I2C_FDR_REG 0x04 /* I2C frequency divider register */
73 #define I2C_CONTROL_REG 0x08 /* I2C control register */
74 #define I2C_STATUS_REG 0x0C /* I2C status register */
75 #define I2C_DATA_REG 0x10 /* I2C data register */
76 #define I2C_DFSRR_REG 0x14 /* I2C Digital Filter Sampling rate */
77
78 #define I2CCR_MEN (1 << 7) /* Module enable */
79 #define I2CCR_MSTA (1 << 5) /* Master/slave mode */
80 #define I2CCR_MTX (1 << 4) /* Transmit/receive mode */
81 #define I2CCR_TXAK (1 << 3) /* Transfer acknowledge */
82 #define I2CCR_RSTA (1 << 2) /* Repeated START */
83
84 #define I2CSR_MCF (1 << 7) /* Data transfer */
85 #define I2CSR_MASS (1 << 6) /* Addressed as a slave */
86 #define I2CSR_MBB (1 << 5) /* Bus busy */
87 #define I2CSR_MAL (1 << 4) /* Arbitration lost */
88 #define I2CSR_SRW (1 << 2) /* Slave read/write */
89 #define I2CSR_MIF (1 << 1) /* Module interrupt */
90 #define I2CSR_RXAK (1 << 0) /* Received acknowledge */
91
92 #define I2C_BAUD_RATE_FAST 0x31
93 #define I2C_BAUD_RATE_DEF 0x3F
94 #define I2C_DFSSR_DIV 0x10
95
96 /*
97 * A table of available divisors and the associated coded values to put in the
98 * FDR register to achieve that divisor.. There is no algorithmic relationship I
99 * can see between divisors and the codes that go into the register. The table
100 * begins and ends with entries that handle insane configuration values.
101 */
102 struct clkdiv {
103 u_int divisor;
104 u_int regcode;
105 };
106 static struct clkdiv clkdiv_table[] = {
107 { 0, 0x20 }, { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 },
108 { 28, 0x23 }, { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 },
109 { 40, 0x26 }, { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 },
110 { 52, 0x05 }, { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2a },
111 { 72, 0x2b }, { 80, 0x2c }, { 88, 0x09 }, { 96, 0x2d },
112 { 104, 0x0a }, { 112, 0x2e }, { 128, 0x2f }, { 144, 0x0c },
113 { 160, 0x30 }, { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0f },
114 { 256, 0x33 }, { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 },
115 { 448, 0x36 }, { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 },
116 { 640, 0x38 }, { 768, 0x39 }, { 896, 0x3a }, { 960, 0x17 },
117 { 1024, 0x3b }, { 1152, 0x18 }, { 1280, 0x3c }, { 1536, 0x3d },
118 { 1792, 0x3e }, { 1920, 0x1b }, { 2048, 0x3f }, { 2304, 0x1c },
119 { 2560, 0x1d }, { 3072, 0x1e }, { 3840, 0x1f }, {UINT_MAX, 0x1f}
120 };
121
122 static struct ofw_compat_data compat_data[] = {
123 {"fsl,imx6q-i2c", 1},
124 {"fsl,imx-i2c", 1},
125 {NULL, 0}
126 };
127
128 struct i2c_softc {
129 device_t dev;
130 device_t iicbus;
131 struct resource *res;
132 int rid;
133 sbintime_t byte_time_sbt;
134 };
135
136 static phandle_t i2c_get_node(device_t, device_t);
137 static int i2c_probe(device_t);
138 static int i2c_attach(device_t);
139
140 static int i2c_repeated_start(device_t, u_char, int);
141 static int i2c_start(device_t, u_char, int);
142 static int i2c_stop(device_t);
143 static int i2c_reset(device_t, u_char, u_char, u_char *);
144 static int i2c_read(device_t, char *, int, int *, int, int);
145 static int i2c_write(device_t, const char *, int, int *, int);
146
147 static device_method_t i2c_methods[] = {
148 DEVMETHOD(device_probe, i2c_probe),
149 DEVMETHOD(device_attach, i2c_attach),
150
151 /* OFW methods */
152 DEVMETHOD(ofw_bus_get_node, i2c_get_node),
153
154 DEVMETHOD(iicbus_callback, iicbus_null_callback),
155 DEVMETHOD(iicbus_repeated_start, i2c_repeated_start),
156 DEVMETHOD(iicbus_start, i2c_start),
157 DEVMETHOD(iicbus_stop, i2c_stop),
158 DEVMETHOD(iicbus_reset, i2c_reset),
159 DEVMETHOD(iicbus_read, i2c_read),
160 DEVMETHOD(iicbus_write, i2c_write),
161 DEVMETHOD(iicbus_transfer, iicbus_transfer_gen),
162
163 DEVMETHOD_END
164 };
165
166 static driver_t i2c_driver = {
167 "iichb",
168 i2c_methods,
169 sizeof(struct i2c_softc),
170 };
171 static devclass_t i2c_devclass;
172
173 DRIVER_MODULE(i2c, simplebus, i2c_driver, i2c_devclass, 0, 0);
174 DRIVER_MODULE(iicbus, i2c, iicbus_driver, iicbus_devclass, 0, 0);
175
176 static phandle_t
i2c_get_node(device_t bus,device_t dev)177 i2c_get_node(device_t bus, device_t dev)
178 {
179 /*
180 * Share controller node with iicbus device
181 */
182 return ofw_bus_get_node(bus);
183 }
184
185 static __inline void
i2c_write_reg(struct i2c_softc * sc,bus_size_t off,uint8_t val)186 i2c_write_reg(struct i2c_softc *sc, bus_size_t off, uint8_t val)
187 {
188
189 bus_write_1(sc->res, off, val);
190 }
191
192 static __inline uint8_t
i2c_read_reg(struct i2c_softc * sc,bus_size_t off)193 i2c_read_reg(struct i2c_softc *sc, bus_size_t off)
194 {
195
196 return (bus_read_1(sc->res, off));
197 }
198
199 static __inline void
i2c_flag_set(struct i2c_softc * sc,bus_size_t off,uint8_t mask)200 i2c_flag_set(struct i2c_softc *sc, bus_size_t off, uint8_t mask)
201 {
202 uint8_t status;
203
204 status = i2c_read_reg(sc, off);
205 status |= mask;
206 i2c_write_reg(sc, off, status);
207 }
208
209 /* Wait for bus to become busy or not-busy. */
210 static int
wait_for_busbusy(struct i2c_softc * sc,int wantbusy)211 wait_for_busbusy(struct i2c_softc *sc, int wantbusy)
212 {
213 int retry, srb;
214
215 retry = 1000;
216 while (retry --) {
217 srb = i2c_read_reg(sc, I2C_STATUS_REG) & I2CSR_MBB;
218 if ((srb && wantbusy) || (!srb && !wantbusy))
219 return (IIC_NOERR);
220 DELAY(1);
221 }
222 return (IIC_ETIMEOUT);
223 }
224
225 /* Wait for transfer to complete, optionally check RXAK. */
226 static int
wait_for_xfer(struct i2c_softc * sc,int checkack)227 wait_for_xfer(struct i2c_softc *sc, int checkack)
228 {
229 int retry, sr;
230
231 /*
232 * Sleep for about the time it takes to transfer a byte (with precision
233 * set to tolerate 5% oversleep). We calculate the approximate byte
234 * transfer time when we set the bus speed divisor. Slaves are allowed
235 * to do clock-stretching so the actual transfer time can be larger, but
236 * this gets the bulk of the waiting out of the way without tying up the
237 * processor the whole time.
238 */
239 pause_sbt("imxi2c", sc->byte_time_sbt, sc->byte_time_sbt / 20, 0);
240
241 retry = 10000;
242 while (retry --) {
243 sr = i2c_read_reg(sc, I2C_STATUS_REG);
244 if (sr & I2CSR_MIF) {
245 if (sr & I2CSR_MAL)
246 return (IIC_EBUSERR);
247 else if (checkack && (sr & I2CSR_RXAK))
248 return (IIC_ENOACK);
249 else
250 return (IIC_NOERR);
251 }
252 DELAY(1);
253 }
254 return (IIC_ETIMEOUT);
255 }
256
257 /*
258 * Implement the error handling shown in the state diagram of the imx6 reference
259 * manual. If there was an error, then:
260 * - Clear master mode (MSTA and MTX).
261 * - Wait for the bus to become free or for a timeout to happen.
262 * - Disable the controller.
263 */
264 static int
i2c_error_handler(struct i2c_softc * sc,int error)265 i2c_error_handler(struct i2c_softc *sc, int error)
266 {
267
268 if (error != 0) {
269 i2c_write_reg(sc, I2C_STATUS_REG, 0);
270 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN);
271 wait_for_busbusy(sc, false);
272 i2c_write_reg(sc, I2C_CONTROL_REG, 0);
273 }
274 return (error);
275 }
276
277 static int
i2c_probe(device_t dev)278 i2c_probe(device_t dev)
279 {
280
281 if (!ofw_bus_status_okay(dev))
282 return (ENXIO);
283
284 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
285 return (ENXIO);
286
287 device_set_desc(dev, "Freescale i.MX I2C");
288
289 return (BUS_PROBE_DEFAULT);
290 }
291
292 static int
i2c_attach(device_t dev)293 i2c_attach(device_t dev)
294 {
295 struct i2c_softc *sc;
296
297 sc = device_get_softc(dev);
298 sc->dev = dev;
299 sc->rid = 0;
300
301 sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->rid,
302 RF_ACTIVE);
303 if (sc->res == NULL) {
304 device_printf(dev, "could not allocate resources");
305 return (ENXIO);
306 }
307
308 sc->iicbus = device_add_child(dev, "iicbus", -1);
309 if (sc->iicbus == NULL) {
310 device_printf(dev, "could not add iicbus child");
311 return (ENXIO);
312 }
313
314 bus_generic_attach(dev);
315 return (0);
316 }
317
318 static int
i2c_repeated_start(device_t dev,u_char slave,int timeout)319 i2c_repeated_start(device_t dev, u_char slave, int timeout)
320 {
321 struct i2c_softc *sc;
322 int error;
323
324 sc = device_get_softc(dev);
325
326 if ((i2c_read_reg(sc, I2C_STATUS_REG) & I2CSR_MBB) == 0) {
327 return (IIC_EBUSERR);
328 }
329
330 /*
331 * Set repeated start condition, delay (per reference manual, min 156nS)
332 * before writing slave address, wait for ack after write.
333 */
334 i2c_flag_set(sc, I2C_CONTROL_REG, I2CCR_RSTA);
335 DELAY(1);
336 i2c_write_reg(sc, I2C_STATUS_REG, 0x0);
337 i2c_write_reg(sc, I2C_DATA_REG, slave);
338 error = wait_for_xfer(sc, true);
339 return (i2c_error_handler(sc, error));
340 }
341
342 static int
i2c_start(device_t dev,u_char slave,int timeout)343 i2c_start(device_t dev, u_char slave, int timeout)
344 {
345 struct i2c_softc *sc;
346 int error;
347
348 sc = device_get_softc(dev);
349
350 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN);
351 DELAY(10); /* Delay for controller to sample bus state. */
352 if (i2c_read_reg(sc, I2C_STATUS_REG) & I2CSR_MBB) {
353 return (i2c_error_handler(sc, IIC_EBUSERR));
354 }
355 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | I2CCR_MSTA | I2CCR_MTX);
356 if ((error = wait_for_busbusy(sc, true)) != IIC_NOERR)
357 return (i2c_error_handler(sc, error));
358 i2c_write_reg(sc, I2C_STATUS_REG, 0);
359 i2c_write_reg(sc, I2C_DATA_REG, slave);
360 error = wait_for_xfer(sc, true);
361 return (i2c_error_handler(sc, error));
362 }
363
364 static int
i2c_stop(device_t dev)365 i2c_stop(device_t dev)
366 {
367 struct i2c_softc *sc;
368
369 sc = device_get_softc(dev);
370
371 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN);
372 wait_for_busbusy(sc, false);
373 i2c_write_reg(sc, I2C_CONTROL_REG, 0);
374 return (IIC_NOERR);
375 }
376
377 static int
i2c_reset(device_t dev,u_char speed,u_char addr,u_char * oldadr)378 i2c_reset(device_t dev, u_char speed, u_char addr, u_char *oldadr)
379 {
380 struct i2c_softc *sc;
381 u_int busfreq, div, i, ipgfreq;
382
383 sc = device_get_softc(dev);
384
385 /*
386 * Look up the divisor that gives the nearest speed that doesn't exceed
387 * the configured value for the bus.
388 */
389 ipgfreq = imx_ccm_ipg_hz();
390 busfreq = IICBUS_GET_FREQUENCY(sc->iicbus, speed);
391 div = (ipgfreq + busfreq - 1) / busfreq;
392 for (i = 0; i < nitems(clkdiv_table); i++) {
393 if (clkdiv_table[i].divisor >= div)
394 break;
395 }
396
397 /*
398 * Calculate roughly how long it will take to transfer a byte (which
399 * requires 9 clock cycles) at the new bus speed. This value is used to
400 * pause() while waiting for transfer-complete. With a 66MHz IPG clock
401 * and the actual i2c bus speeds that leads to, for nominal 100KHz and
402 * 400KHz bus speeds the transfer times are roughly 104uS and 22uS.
403 */
404 busfreq = ipgfreq / clkdiv_table[i].divisor;
405 sc->byte_time_sbt = SBT_1US * (9000000 / busfreq);
406
407 /*
408 * Disable the controller (do the reset), and set the new clock divisor.
409 */
410 i2c_write_reg(sc, I2C_STATUS_REG, 0x0);
411 i2c_write_reg(sc, I2C_CONTROL_REG, 0x0);
412 i2c_write_reg(sc, I2C_FDR_REG, (uint8_t)clkdiv_table[i].regcode);
413 return (IIC_NOERR);
414 }
415
416 static int
i2c_read(device_t dev,char * buf,int len,int * read,int last,int delay)417 i2c_read(device_t dev, char *buf, int len, int *read, int last, int delay)
418 {
419 struct i2c_softc *sc;
420 int error, reg;
421
422 sc = device_get_softc(dev);
423 *read = 0;
424
425 if (len) {
426 if (len == 1)
427 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN |
428 I2CCR_MSTA | I2CCR_TXAK);
429 else
430 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN |
431 I2CCR_MSTA);
432 /* Dummy read to prime the receiver. */
433 i2c_write_reg(sc, I2C_STATUS_REG, 0x0);
434 i2c_read_reg(sc, I2C_DATA_REG);
435 }
436
437 error = 0;
438 *read = 0;
439 while (*read < len) {
440 if ((error = wait_for_xfer(sc, false)) != IIC_NOERR)
441 break;
442 i2c_write_reg(sc, I2C_STATUS_REG, 0x0);
443 if (last) {
444 if (*read == len - 2) {
445 /* NO ACK on last byte */
446 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN |
447 I2CCR_MSTA | I2CCR_TXAK);
448 } else if (*read == len - 1) {
449 /* Transfer done, signal stop. */
450 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN |
451 I2CCR_TXAK);
452 wait_for_busbusy(sc, false);
453 }
454 }
455 reg = i2c_read_reg(sc, I2C_DATA_REG);
456 *buf++ = reg;
457 (*read)++;
458 }
459
460 return (i2c_error_handler(sc, error));
461 }
462
463 static int
i2c_write(device_t dev,const char * buf,int len,int * sent,int timeout)464 i2c_write(device_t dev, const char *buf, int len, int *sent, int timeout)
465 {
466 struct i2c_softc *sc;
467 int error;
468
469 sc = device_get_softc(dev);
470
471 error = 0;
472 *sent = 0;
473 while (*sent < len) {
474 i2c_write_reg(sc, I2C_STATUS_REG, 0x0);
475 i2c_write_reg(sc, I2C_DATA_REG, *buf++);
476 if ((error = wait_for_xfer(sc, true)) != IIC_NOERR)
477 break;
478 (*sent)++;
479 }
480
481 return (i2c_error_handler(sc, error));
482 }
483