1 /*
2 * Copyright (c) 2014 The DragonFly Project. All rights reserved.
3 *
4 * This code is derived from software contributed to The DragonFly Project
5 * by Matthew Dillon <dillon@backplane.com> and was subsequently ported
6 * to FreeBSD by Michael Gmelin <freebsd@grem.de>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 *
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in
16 * the documentation and/or other materials provided with the
17 * distribution.
18 * 3. Neither the name of The DragonFly Project nor the names of its
19 * contributors may be used to endorse or promote products derived
20 * from this software without specific, prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
25 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
26 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
32 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * SUCH DAMAGE.
34 */
35
36 #include <sys/cdefs.h>
37 __FBSDID("$FreeBSD$");
38
39 /*
40 * Intel fourth generation mobile cpus integrated I2C device, smbus driver.
41 *
42 * See ig4_reg.h for datasheet reference and notes.
43 * See ig4_var.h for locking semantics.
44 */
45
46 #include <sys/param.h>
47 #include <sys/systm.h>
48 #include <sys/kernel.h>
49 #include <sys/module.h>
50 #include <sys/errno.h>
51 #include <sys/lock.h>
52 #include <sys/mutex.h>
53 #include <sys/sx.h>
54 #include <sys/syslog.h>
55 #include <sys/bus.h>
56 #include <sys/sysctl.h>
57
58 #include <machine/bus.h>
59 #include <sys/rman.h>
60
61 #include <dev/pci/pcivar.h>
62 #include <dev/pci/pcireg.h>
63 #include <dev/smbus/smbconf.h>
64
65 #include <dev/ichiic/ig4_reg.h>
66 #include <dev/ichiic/ig4_var.h>
67
68 #define TRANS_NORMAL 1
69 #define TRANS_PCALL 2
70 #define TRANS_BLOCK 3
71
72 static void ig4iic_start(void *xdev);
73 static void ig4iic_intr(void *cookie);
74 static void ig4iic_dump(ig4iic_softc_t *sc);
75
76 static int ig4_dump;
77 SYSCTL_INT(_debug, OID_AUTO, ig4_dump, CTLFLAG_RW,
78 &ig4_dump, 0, "Dump controller registers");
79
80 /*
81 * Low-level inline support functions
82 */
83 static __inline void
reg_write(ig4iic_softc_t * sc,uint32_t reg,uint32_t value)84 reg_write(ig4iic_softc_t *sc, uint32_t reg, uint32_t value)
85 {
86 bus_write_4(sc->regs_res, reg, value);
87 bus_barrier(sc->regs_res, reg, 4, BUS_SPACE_BARRIER_WRITE);
88 }
89
90 static __inline uint32_t
reg_read(ig4iic_softc_t * sc,uint32_t reg)91 reg_read(ig4iic_softc_t *sc, uint32_t reg)
92 {
93 uint32_t value;
94
95 bus_barrier(sc->regs_res, reg, 4, BUS_SPACE_BARRIER_READ);
96 value = bus_read_4(sc->regs_res, reg);
97 return (value);
98 }
99
100 /*
101 * Enable or disable the controller and wait for the controller to acknowledge
102 * the state change.
103 */
104 static int
set_controller(ig4iic_softc_t * sc,uint32_t ctl)105 set_controller(ig4iic_softc_t *sc, uint32_t ctl)
106 {
107 int retry;
108 int error;
109 uint32_t v;
110
111 reg_write(sc, IG4_REG_I2C_EN, ctl);
112 error = SMB_ETIMEOUT;
113
114 for (retry = 100; retry > 0; --retry) {
115 v = reg_read(sc, IG4_REG_ENABLE_STATUS);
116 if (((v ^ ctl) & IG4_I2C_ENABLE) == 0) {
117 error = 0;
118 break;
119 }
120 mtx_sleep(sc, &sc->io_lock, 0, "i2cslv", 1);
121 }
122 return (error);
123 }
124
125 /*
126 * Wait up to 25ms for the requested status using a 25uS polling loop.
127 */
128 static int
wait_status(ig4iic_softc_t * sc,uint32_t status)129 wait_status(ig4iic_softc_t *sc, uint32_t status)
130 {
131 uint32_t v;
132 int error;
133 int txlvl = -1;
134 u_int count_us = 0;
135 u_int limit_us = 25000; /* 25ms */
136
137 error = SMB_ETIMEOUT;
138
139 for (;;) {
140 /*
141 * Check requested status
142 */
143 v = reg_read(sc, IG4_REG_I2C_STA);
144 if (v & status) {
145 error = 0;
146 break;
147 }
148
149 /*
150 * When waiting for receive data break-out if the interrupt
151 * loaded data into the FIFO.
152 */
153 if (status & IG4_STATUS_RX_NOTEMPTY) {
154 if (sc->rpos != sc->rnext) {
155 error = 0;
156 break;
157 }
158 }
159
160 /*
161 * When waiting for the transmit FIFO to become empty,
162 * reset the timeout if we see a change in the transmit
163 * FIFO level as progress is being made.
164 */
165 if (status & IG4_STATUS_TX_EMPTY) {
166 v = reg_read(sc, IG4_REG_TXFLR) & IG4_FIFOLVL_MASK;
167 if (txlvl != v) {
168 txlvl = v;
169 count_us = 0;
170 }
171 }
172
173 /*
174 * Stop if we've run out of time.
175 */
176 if (count_us >= limit_us)
177 break;
178
179 /*
180 * When waiting for receive data let the interrupt do its
181 * work, otherwise poll with the lock held.
182 */
183 if (status & IG4_STATUS_RX_NOTEMPTY) {
184 mtx_sleep(sc, &sc->io_lock, 0, "i2cwait",
185 (hz + 99) / 100); /* sleep up to 10ms */
186 count_us += 10000;
187 } else {
188 DELAY(25);
189 count_us += 25;
190 }
191 }
192
193 return (error);
194 }
195
196 /*
197 * Read I2C data. The data might have already been read by
198 * the interrupt code, otherwise it is sitting in the data
199 * register.
200 */
201 static uint8_t
data_read(ig4iic_softc_t * sc)202 data_read(ig4iic_softc_t *sc)
203 {
204 uint8_t c;
205
206 if (sc->rpos == sc->rnext) {
207 c = (uint8_t)reg_read(sc, IG4_REG_DATA_CMD);
208 } else {
209 c = sc->rbuf[sc->rpos & IG4_RBUFMASK];
210 ++sc->rpos;
211 }
212 return (c);
213 }
214
215 /*
216 * Set the slave address. The controller must be disabled when
217 * changing the address.
218 *
219 * This operation does not issue anything to the I2C bus but sets
220 * the target address for when the controller later issues a START.
221 */
222 static void
set_slave_addr(ig4iic_softc_t * sc,uint8_t slave,int trans_op)223 set_slave_addr(ig4iic_softc_t *sc, uint8_t slave, int trans_op)
224 {
225 uint32_t tar;
226 uint32_t ctl;
227 int use_10bit;
228
229 use_10bit = sc->use_10bit;
230 if (trans_op & SMB_TRANS_7BIT)
231 use_10bit = 0;
232 if (trans_op & SMB_TRANS_10BIT)
233 use_10bit = 1;
234
235 if (sc->slave_valid && sc->last_slave == slave &&
236 sc->use_10bit == use_10bit) {
237 return;
238 }
239 sc->use_10bit = use_10bit;
240
241 /*
242 * Wait for TXFIFO to drain before disabling the controller.
243 *
244 * If a write message has not been completed it's really a
245 * programming error, but for now in that case issue an extra
246 * byte + STOP.
247 *
248 * If a read message has not been completed it's also a programming
249 * error, for now just ignore it.
250 */
251 wait_status(sc, IG4_STATUS_TX_NOTFULL);
252 if (sc->write_started) {
253 reg_write(sc, IG4_REG_DATA_CMD, IG4_DATA_STOP);
254 sc->write_started = 0;
255 }
256 if (sc->read_started)
257 sc->read_started = 0;
258 wait_status(sc, IG4_STATUS_TX_EMPTY);
259
260 set_controller(sc, 0);
261 ctl = reg_read(sc, IG4_REG_CTL);
262 ctl &= ~IG4_CTL_10BIT;
263 ctl |= IG4_CTL_RESTARTEN;
264
265 tar = slave;
266 if (sc->use_10bit) {
267 tar |= IG4_TAR_10BIT;
268 ctl |= IG4_CTL_10BIT;
269 }
270 reg_write(sc, IG4_REG_CTL, ctl);
271 reg_write(sc, IG4_REG_TAR_ADD, tar);
272 set_controller(sc, IG4_I2C_ENABLE);
273 sc->slave_valid = 1;
274 sc->last_slave = slave;
275 }
276
277 /*
278 * Issue START with byte command, possible count, and a variable length
279 * read or write buffer, then possible turn-around read. The read also
280 * has a possible count received.
281 *
282 * For SMBUS -
283 *
284 * Quick: START+ADDR+RD/WR STOP
285 *
286 * Normal: START+ADDR+WR CMD DATA..DATA STOP
287 *
288 * START+ADDR+RD CMD
289 * RESTART+ADDR RDATA..RDATA STOP
290 * (can also be used for I2C transactions)
291 *
292 * Process Call: START+ADDR+WR CMD DATAL DATAH
293 * RESTART+ADDR+RD RDATAL RDATAH STOP
294 *
295 * Block: START+ADDR+RD CMD
296 * RESTART+ADDR+RD RCOUNT DATA... STOP
297 *
298 * START+ADDR+WR CMD
299 * RESTART+ADDR+WR WCOUNT DATA... STOP
300 *
301 * For I2C - basically, no *COUNT fields, possibly no *CMD field. If the
302 * sender needs to issue a 2-byte command it will incorporate it
303 * into the write buffer and also set NOCMD.
304 *
305 * Generally speaking, the START+ADDR / RESTART+ADDR is handled automatically
306 * by the controller at the beginning of a command sequence or on a data
307 * direction turn-around, and we only need to tell it when to issue the STOP.
308 */
309 static int
smb_transaction(ig4iic_softc_t * sc,char cmd,int op,char * wbuf,int wcount,char * rbuf,int rcount,int * actualp)310 smb_transaction(ig4iic_softc_t *sc, char cmd, int op,
311 char *wbuf, int wcount, char *rbuf, int rcount, int *actualp)
312 {
313 int error;
314 int unit;
315 uint32_t last;
316
317 /*
318 * Debugging - dump registers
319 */
320 if (ig4_dump) {
321 unit = device_get_unit(sc->dev);
322 if (ig4_dump & (1 << unit)) {
323 ig4_dump &= ~(1 << unit);
324 ig4iic_dump(sc);
325 }
326 }
327
328 /*
329 * Issue START or RESTART with next data byte, clear any previous
330 * abort condition that may have been holding the txfifo in reset.
331 */
332 last = IG4_DATA_RESTART;
333 reg_read(sc, IG4_REG_CLR_TX_ABORT);
334 if (actualp)
335 *actualp = 0;
336
337 /*
338 * Issue command if not told otherwise (smbus).
339 */
340 if ((op & SMB_TRANS_NOCMD) == 0) {
341 error = wait_status(sc, IG4_STATUS_TX_NOTFULL);
342 if (error)
343 goto done;
344 last |= (u_char)cmd;
345 if (wcount == 0 && rcount == 0 && (op & SMB_TRANS_NOSTOP) == 0)
346 last |= IG4_DATA_STOP;
347 reg_write(sc, IG4_REG_DATA_CMD, last);
348 last = 0;
349 }
350
351 /*
352 * Clean out any previously received data.
353 */
354 if (sc->rpos != sc->rnext &&
355 (op & SMB_TRANS_NOREPORT) == 0) {
356 device_printf(sc->dev,
357 "discarding %d bytes of spurious data\n",
358 sc->rnext - sc->rpos);
359 }
360 sc->rpos = 0;
361 sc->rnext = 0;
362
363 /*
364 * If writing and not told otherwise, issue the write count (smbus).
365 */
366 if (wcount && (op & SMB_TRANS_NOCNT) == 0) {
367 error = wait_status(sc, IG4_STATUS_TX_NOTFULL);
368 if (error)
369 goto done;
370 last |= (u_char)cmd;
371 reg_write(sc, IG4_REG_DATA_CMD, last);
372 last = 0;
373 }
374
375 /*
376 * Bulk write (i2c)
377 */
378 while (wcount) {
379 error = wait_status(sc, IG4_STATUS_TX_NOTFULL);
380 if (error)
381 goto done;
382 last |= (u_char)*wbuf;
383 if (wcount == 1 && rcount == 0 && (op & SMB_TRANS_NOSTOP) == 0)
384 last |= IG4_DATA_STOP;
385 reg_write(sc, IG4_REG_DATA_CMD, last);
386 --wcount;
387 ++wbuf;
388 last = 0;
389 }
390
391 /*
392 * Issue reads to xmit FIFO (strange, I know) to tell the controller
393 * to clock in data. At the moment just issue one read ahead to
394 * pipeline the incoming data.
395 *
396 * NOTE: In the case of NOCMD and wcount == 0 we still issue a
397 * RESTART here, even if the data direction has not changed
398 * from the previous CHAINing call. This we force the RESTART.
399 * (A new START is issued automatically by the controller in
400 * the other nominal cases such as a data direction change or
401 * a previous STOP was issued).
402 *
403 * If this will be the last byte read we must also issue the STOP
404 * at the end of the read.
405 */
406 if (rcount) {
407 last = IG4_DATA_RESTART | IG4_DATA_COMMAND_RD;
408 if (rcount == 1 &&
409 (op & (SMB_TRANS_NOSTOP | SMB_TRANS_NOCNT)) ==
410 SMB_TRANS_NOCNT) {
411 last |= IG4_DATA_STOP;
412 }
413 reg_write(sc, IG4_REG_DATA_CMD, last);
414 last = IG4_DATA_COMMAND_RD;
415 }
416
417 /*
418 * Bulk read (i2c) and count field handling (smbus)
419 */
420 while (rcount) {
421 /*
422 * Maintain a pipeline by queueing the allowance for the next
423 * read before waiting for the current read.
424 */
425 if (rcount > 1) {
426 if (op & SMB_TRANS_NOCNT)
427 last = (rcount == 2) ? IG4_DATA_STOP : 0;
428 else
429 last = 0;
430 reg_write(sc, IG4_REG_DATA_CMD, IG4_DATA_COMMAND_RD |
431 last);
432 }
433 error = wait_status(sc, IG4_STATUS_RX_NOTEMPTY);
434 if (error) {
435 if ((op & SMB_TRANS_NOREPORT) == 0) {
436 device_printf(sc->dev,
437 "rx timeout addr 0x%02x\n",
438 sc->last_slave);
439 }
440 goto done;
441 }
442 last = data_read(sc);
443
444 if (op & SMB_TRANS_NOCNT) {
445 *rbuf = (u_char)last;
446 ++rbuf;
447 --rcount;
448 if (actualp)
449 ++*actualp;
450 } else {
451 /*
452 * Handle count field (smbus), which is not part of
453 * the rcount'ed buffer. The first read data in a
454 * bulk transfer is the count.
455 *
456 * XXX if rcount is loaded as 0 how do I generate a
457 * STOP now without issuing another RD or WR?
458 */
459 if (rcount > (u_char)last)
460 rcount = (u_char)last;
461 op |= SMB_TRANS_NOCNT;
462 }
463 }
464 error = 0;
465 done:
466 /* XXX wait for xmit buffer to become empty */
467 last = reg_read(sc, IG4_REG_TX_ABRT_SOURCE);
468
469 return (error);
470 }
471
472 /*
473 * SMBUS API FUNCTIONS
474 *
475 * Called from ig4iic_pci_attach/detach()
476 */
477 int
ig4iic_attach(ig4iic_softc_t * sc)478 ig4iic_attach(ig4iic_softc_t *sc)
479 {
480 int error;
481 uint32_t v;
482
483 v = reg_read(sc, IG4_REG_COMP_TYPE);
484 v = reg_read(sc, IG4_REG_COMP_PARAM1);
485 v = reg_read(sc, IG4_REG_GENERAL);
486 if ((v & IG4_GENERAL_SWMODE) == 0) {
487 v |= IG4_GENERAL_SWMODE;
488 reg_write(sc, IG4_REG_GENERAL, v);
489 v = reg_read(sc, IG4_REG_GENERAL);
490 }
491
492 v = reg_read(sc, IG4_REG_SW_LTR_VALUE);
493 v = reg_read(sc, IG4_REG_AUTO_LTR_VALUE);
494
495 v = reg_read(sc, IG4_REG_COMP_VER);
496 if (v != IG4_COMP_VER) {
497 error = ENXIO;
498 goto done;
499 }
500 v = reg_read(sc, IG4_REG_SS_SCL_HCNT);
501 v = reg_read(sc, IG4_REG_SS_SCL_LCNT);
502 v = reg_read(sc, IG4_REG_FS_SCL_HCNT);
503 v = reg_read(sc, IG4_REG_FS_SCL_LCNT);
504 v = reg_read(sc, IG4_REG_SDA_HOLD);
505
506 v = reg_read(sc, IG4_REG_SS_SCL_HCNT);
507 reg_write(sc, IG4_REG_FS_SCL_HCNT, v);
508 v = reg_read(sc, IG4_REG_SS_SCL_LCNT);
509 reg_write(sc, IG4_REG_FS_SCL_LCNT, v);
510
511 /*
512 * Program based on a 25000 Hz clock. This is a bit of a
513 * hack (obviously). The defaults are 400 and 470 for standard
514 * and 60 and 130 for fast. The defaults for standard fail
515 * utterly (presumably cause an abort) because the clock time
516 * is ~18.8ms by default. This brings it down to ~4ms (for now).
517 */
518 reg_write(sc, IG4_REG_SS_SCL_HCNT, 100);
519 reg_write(sc, IG4_REG_SS_SCL_LCNT, 125);
520 reg_write(sc, IG4_REG_FS_SCL_HCNT, 100);
521 reg_write(sc, IG4_REG_FS_SCL_LCNT, 125);
522
523 /*
524 * Use a threshold of 1 so we get interrupted on each character,
525 * allowing us to use mtx_sleep() in our poll code. Not perfect
526 * but this is better than using DELAY() for receiving data.
527 *
528 * See ig4_var.h for details on interrupt handler synchronization.
529 */
530 reg_write(sc, IG4_REG_RX_TL, 1);
531
532 reg_write(sc, IG4_REG_CTL,
533 IG4_CTL_MASTER |
534 IG4_CTL_SLAVE_DISABLE |
535 IG4_CTL_RESTARTEN |
536 IG4_CTL_SPEED_STD);
537
538 sc->smb = device_add_child(sc->dev, "smbus", -1);
539 if (sc->smb == NULL) {
540 device_printf(sc->dev, "smbus driver not found\n");
541 error = ENXIO;
542 goto done;
543 }
544
545 #if 0
546 /*
547 * Don't do this, it blows up the PCI config
548 */
549 reg_write(sc, IG4_REG_RESETS, IG4_RESETS_ASSERT);
550 reg_write(sc, IG4_REG_RESETS, IG4_RESETS_DEASSERT);
551 #endif
552
553 /*
554 * Interrupt on STOP detect or receive character ready
555 */
556 reg_write(sc, IG4_REG_INTR_MASK, IG4_INTR_STOP_DET |
557 IG4_INTR_RX_FULL);
558 mtx_lock(&sc->io_lock);
559 if (set_controller(sc, 0))
560 device_printf(sc->dev, "controller error during attach-1\n");
561 if (set_controller(sc, IG4_I2C_ENABLE))
562 device_printf(sc->dev, "controller error during attach-2\n");
563 mtx_unlock(&sc->io_lock);
564 error = bus_setup_intr(sc->dev, sc->intr_res, INTR_TYPE_MISC | INTR_MPSAFE,
565 NULL, ig4iic_intr, sc, &sc->intr_handle);
566 if (error) {
567 device_printf(sc->dev,
568 "Unable to setup irq: error %d\n", error);
569 }
570
571 sc->enum_hook.ich_func = ig4iic_start;
572 sc->enum_hook.ich_arg = sc->dev;
573
574 /* We have to wait until interrupts are enabled. I2C read and write
575 * only works if the interrupts are available.
576 */
577 if (config_intrhook_establish(&sc->enum_hook) != 0)
578 error = ENOMEM;
579 else
580 error = 0;
581
582 done:
583 return (error);
584 }
585
586 void
ig4iic_start(void * xdev)587 ig4iic_start(void *xdev)
588 {
589 int error;
590 ig4iic_softc_t *sc;
591 device_t dev = (device_t)xdev;
592
593 sc = device_get_softc(dev);
594
595 config_intrhook_disestablish(&sc->enum_hook);
596
597 /* Attach us to the smbus */
598 error = bus_generic_attach(sc->dev);
599 if (error) {
600 device_printf(sc->dev,
601 "failed to attach child: error %d\n", error);
602 }
603 }
604
605
606
607 int
ig4iic_detach(ig4iic_softc_t * sc)608 ig4iic_detach(ig4iic_softc_t *sc)
609 {
610 int error;
611
612 if (device_is_attached(sc->dev)) {
613 error = bus_generic_detach(sc->dev);
614 if (error)
615 return (error);
616 }
617 if (sc->smb)
618 device_delete_child(sc->dev, sc->smb);
619 if (sc->intr_handle)
620 bus_teardown_intr(sc->dev, sc->intr_res, sc->intr_handle);
621
622 sx_xlock(&sc->call_lock);
623 mtx_lock(&sc->io_lock);
624
625 sc->smb = NULL;
626 sc->intr_handle = NULL;
627 reg_write(sc, IG4_REG_INTR_MASK, 0);
628 reg_read(sc, IG4_REG_CLR_INTR);
629 set_controller(sc, 0);
630
631 mtx_unlock(&sc->io_lock);
632 sx_xunlock(&sc->call_lock);
633 return (0);
634 }
635
636 int
ig4iic_smb_callback(device_t dev,int index,void * data)637 ig4iic_smb_callback(device_t dev, int index, void *data)
638 {
639 int error;
640
641 switch (index) {
642 case SMB_REQUEST_BUS:
643 error = 0;
644 break;
645 case SMB_RELEASE_BUS:
646 error = 0;
647 break;
648 default:
649 error = SMB_EABORT;
650 break;
651 }
652
653 return (error);
654 }
655
656 /*
657 * Quick command. i.e. START + cmd + R/W + STOP and no data. It is
658 * unclear to me how I could implement this with the intel i2c controller
659 * because the controler sends STARTs and STOPs automatically with data.
660 */
661 int
ig4iic_smb_quick(device_t dev,u_char slave,int how)662 ig4iic_smb_quick(device_t dev, u_char slave, int how)
663 {
664
665 return (SMB_ENOTSUPP);
666 }
667
668 /*
669 * Incremental send byte without stop (?). It is unclear why the slave
670 * address is specified if this presumably is used in combination with
671 * ig4iic_smb_quick().
672 *
673 * (Also, how would this work anyway? Issue the last byte with writeb()?)
674 */
675 int
ig4iic_smb_sendb(device_t dev,u_char slave,char byte)676 ig4iic_smb_sendb(device_t dev, u_char slave, char byte)
677 {
678 ig4iic_softc_t *sc = device_get_softc(dev);
679 uint32_t cmd;
680 int error;
681
682 sx_xlock(&sc->call_lock);
683 mtx_lock(&sc->io_lock);
684
685 set_slave_addr(sc, slave, 0);
686 cmd = byte;
687 if (wait_status(sc, IG4_STATUS_TX_NOTFULL) == 0) {
688 reg_write(sc, IG4_REG_DATA_CMD, cmd);
689 error = 0;
690 } else {
691 error = SMB_ETIMEOUT;
692 }
693
694 mtx_unlock(&sc->io_lock);
695 sx_xunlock(&sc->call_lock);
696 return (error);
697 }
698
699 /*
700 * Incremental receive byte without stop (?). It is unclear why the slave
701 * address is specified if this presumably is used in combination with
702 * ig4iic_smb_quick().
703 */
704 int
ig4iic_smb_recvb(device_t dev,u_char slave,char * byte)705 ig4iic_smb_recvb(device_t dev, u_char slave, char *byte)
706 {
707 ig4iic_softc_t *sc = device_get_softc(dev);
708 int error;
709
710 sx_xlock(&sc->call_lock);
711 mtx_lock(&sc->io_lock);
712
713 set_slave_addr(sc, slave, 0);
714 reg_write(sc, IG4_REG_DATA_CMD, IG4_DATA_COMMAND_RD);
715 if (wait_status(sc, IG4_STATUS_RX_NOTEMPTY) == 0) {
716 *byte = data_read(sc);
717 error = 0;
718 } else {
719 *byte = 0;
720 error = SMB_ETIMEOUT;
721 }
722
723 mtx_unlock(&sc->io_lock);
724 sx_xunlock(&sc->call_lock);
725 return (error);
726 }
727
728 /*
729 * Write command and single byte in transaction.
730 */
731 int
ig4iic_smb_writeb(device_t dev,u_char slave,char cmd,char byte)732 ig4iic_smb_writeb(device_t dev, u_char slave, char cmd, char byte)
733 {
734 ig4iic_softc_t *sc = device_get_softc(dev);
735 int error;
736
737 sx_xlock(&sc->call_lock);
738 mtx_lock(&sc->io_lock);
739
740 set_slave_addr(sc, slave, 0);
741 error = smb_transaction(sc, cmd, SMB_TRANS_NOCNT,
742 &byte, 1, NULL, 0, NULL);
743
744 mtx_unlock(&sc->io_lock);
745 sx_xunlock(&sc->call_lock);
746 return (error);
747 }
748
749 /*
750 * Write command and single word in transaction.
751 */
752 int
ig4iic_smb_writew(device_t dev,u_char slave,char cmd,short word)753 ig4iic_smb_writew(device_t dev, u_char slave, char cmd, short word)
754 {
755 ig4iic_softc_t *sc = device_get_softc(dev);
756 char buf[2];
757 int error;
758
759 sx_xlock(&sc->call_lock);
760 mtx_lock(&sc->io_lock);
761
762 set_slave_addr(sc, slave, 0);
763 buf[0] = word & 0xFF;
764 buf[1] = word >> 8;
765 error = smb_transaction(sc, cmd, SMB_TRANS_NOCNT,
766 buf, 2, NULL, 0, NULL);
767
768 mtx_unlock(&sc->io_lock);
769 sx_xunlock(&sc->call_lock);
770 return (error);
771 }
772
773 /*
774 * write command and read single byte in transaction.
775 */
776 int
ig4iic_smb_readb(device_t dev,u_char slave,char cmd,char * byte)777 ig4iic_smb_readb(device_t dev, u_char slave, char cmd, char *byte)
778 {
779 ig4iic_softc_t *sc = device_get_softc(dev);
780 int error;
781
782 sx_xlock(&sc->call_lock);
783 mtx_lock(&sc->io_lock);
784
785 set_slave_addr(sc, slave, 0);
786 error = smb_transaction(sc, cmd, SMB_TRANS_NOCNT,
787 NULL, 0, byte, 1, NULL);
788
789 mtx_unlock(&sc->io_lock);
790 sx_xunlock(&sc->call_lock);
791 return (error);
792 }
793
794 /*
795 * write command and read word in transaction.
796 */
797 int
ig4iic_smb_readw(device_t dev,u_char slave,char cmd,short * word)798 ig4iic_smb_readw(device_t dev, u_char slave, char cmd, short *word)
799 {
800 ig4iic_softc_t *sc = device_get_softc(dev);
801 char buf[2];
802 int error;
803
804 sx_xlock(&sc->call_lock);
805 mtx_lock(&sc->io_lock);
806
807 set_slave_addr(sc, slave, 0);
808 if ((error = smb_transaction(sc, cmd, SMB_TRANS_NOCNT,
809 NULL, 0, buf, 2, NULL)) == 0) {
810 *word = (u_char)buf[0] | ((u_char)buf[1] << 8);
811 }
812
813 mtx_unlock(&sc->io_lock);
814 sx_xunlock(&sc->call_lock);
815 return (error);
816 }
817
818 /*
819 * write command and word and read word in transaction
820 */
821 int
ig4iic_smb_pcall(device_t dev,u_char slave,char cmd,short sdata,short * rdata)822 ig4iic_smb_pcall(device_t dev, u_char slave, char cmd,
823 short sdata, short *rdata)
824 {
825 ig4iic_softc_t *sc = device_get_softc(dev);
826 char rbuf[2];
827 char wbuf[2];
828 int error;
829
830 sx_xlock(&sc->call_lock);
831 mtx_lock(&sc->io_lock);
832
833 set_slave_addr(sc, slave, 0);
834 wbuf[0] = sdata & 0xFF;
835 wbuf[1] = sdata >> 8;
836 if ((error = smb_transaction(sc, cmd, SMB_TRANS_NOCNT,
837 wbuf, 2, rbuf, 2, NULL)) == 0) {
838 *rdata = (u_char)rbuf[0] | ((u_char)rbuf[1] << 8);
839 }
840
841 mtx_unlock(&sc->io_lock);
842 sx_xunlock(&sc->call_lock);
843 return (error);
844 }
845
846 int
ig4iic_smb_bwrite(device_t dev,u_char slave,char cmd,u_char wcount,char * buf)847 ig4iic_smb_bwrite(device_t dev, u_char slave, char cmd,
848 u_char wcount, char *buf)
849 {
850 ig4iic_softc_t *sc = device_get_softc(dev);
851 int error;
852
853 sx_xlock(&sc->call_lock);
854 mtx_lock(&sc->io_lock);
855
856 set_slave_addr(sc, slave, 0);
857 error = smb_transaction(sc, cmd, 0,
858 buf, wcount, NULL, 0, NULL);
859
860 mtx_unlock(&sc->io_lock);
861 sx_xunlock(&sc->call_lock);
862 return (error);
863 }
864
865 int
ig4iic_smb_bread(device_t dev,u_char slave,char cmd,u_char * countp_char,char * buf)866 ig4iic_smb_bread(device_t dev, u_char slave, char cmd,
867 u_char *countp_char, char *buf)
868 {
869 ig4iic_softc_t *sc = device_get_softc(dev);
870 int rcount = *countp_char;
871 int error;
872
873 sx_xlock(&sc->call_lock);
874 mtx_lock(&sc->io_lock);
875
876 set_slave_addr(sc, slave, 0);
877 error = smb_transaction(sc, cmd, 0,
878 NULL, 0, buf, rcount, &rcount);
879 *countp_char = rcount;
880
881 mtx_unlock(&sc->io_lock);
882 sx_xunlock(&sc->call_lock);
883 return (error);
884 }
885
886 int
ig4iic_smb_trans(device_t dev,int slave,char cmd,int op,char * wbuf,int wcount,char * rbuf,int rcount,int * actualp)887 ig4iic_smb_trans(device_t dev, int slave, char cmd, int op,
888 char *wbuf, int wcount, char *rbuf, int rcount,
889 int *actualp)
890 {
891 ig4iic_softc_t *sc = device_get_softc(dev);
892 int error;
893
894 sx_xlock(&sc->call_lock);
895 mtx_lock(&sc->io_lock);
896
897 set_slave_addr(sc, slave, op);
898 error = smb_transaction(sc, cmd, op,
899 wbuf, wcount, rbuf, rcount, actualp);
900
901 mtx_unlock(&sc->io_lock);
902 sx_xunlock(&sc->call_lock);
903 return (error);
904 }
905
906 /*
907 * Interrupt Operation, see ig4_var.h for locking semantics.
908 */
909 static void
ig4iic_intr(void * cookie)910 ig4iic_intr(void *cookie)
911 {
912 ig4iic_softc_t *sc = cookie;
913 uint32_t status;
914
915 mtx_lock(&sc->io_lock);
916 /* reg_write(sc, IG4_REG_INTR_MASK, IG4_INTR_STOP_DET);*/
917 status = reg_read(sc, IG4_REG_I2C_STA);
918 while (status & IG4_STATUS_RX_NOTEMPTY) {
919 sc->rbuf[sc->rnext & IG4_RBUFMASK] =
920 (uint8_t)reg_read(sc, IG4_REG_DATA_CMD);
921 ++sc->rnext;
922 status = reg_read(sc, IG4_REG_I2C_STA);
923 }
924 reg_read(sc, IG4_REG_CLR_INTR);
925 wakeup(sc);
926 mtx_unlock(&sc->io_lock);
927 }
928
929 #define REGDUMP(sc, reg) \
930 device_printf(sc->dev, " %-23s %08x\n", #reg, reg_read(sc, reg))
931
932 static void
ig4iic_dump(ig4iic_softc_t * sc)933 ig4iic_dump(ig4iic_softc_t *sc)
934 {
935 device_printf(sc->dev, "ig4iic register dump:\n");
936 REGDUMP(sc, IG4_REG_CTL);
937 REGDUMP(sc, IG4_REG_TAR_ADD);
938 REGDUMP(sc, IG4_REG_SS_SCL_HCNT);
939 REGDUMP(sc, IG4_REG_SS_SCL_LCNT);
940 REGDUMP(sc, IG4_REG_FS_SCL_HCNT);
941 REGDUMP(sc, IG4_REG_FS_SCL_LCNT);
942 REGDUMP(sc, IG4_REG_INTR_STAT);
943 REGDUMP(sc, IG4_REG_INTR_MASK);
944 REGDUMP(sc, IG4_REG_RAW_INTR_STAT);
945 REGDUMP(sc, IG4_REG_RX_TL);
946 REGDUMP(sc, IG4_REG_TX_TL);
947 REGDUMP(sc, IG4_REG_I2C_EN);
948 REGDUMP(sc, IG4_REG_I2C_STA);
949 REGDUMP(sc, IG4_REG_TXFLR);
950 REGDUMP(sc, IG4_REG_RXFLR);
951 REGDUMP(sc, IG4_REG_SDA_HOLD);
952 REGDUMP(sc, IG4_REG_TX_ABRT_SOURCE);
953 REGDUMP(sc, IG4_REG_SLV_DATA_NACK);
954 REGDUMP(sc, IG4_REG_DMA_CTRL);
955 REGDUMP(sc, IG4_REG_DMA_TDLR);
956 REGDUMP(sc, IG4_REG_DMA_RDLR);
957 REGDUMP(sc, IG4_REG_SDA_SETUP);
958 REGDUMP(sc, IG4_REG_ENABLE_STATUS);
959 REGDUMP(sc, IG4_REG_COMP_PARAM1);
960 REGDUMP(sc, IG4_REG_COMP_VER);
961 REGDUMP(sc, IG4_REG_COMP_TYPE);
962 REGDUMP(sc, IG4_REG_CLK_PARMS);
963 REGDUMP(sc, IG4_REG_RESETS);
964 REGDUMP(sc, IG4_REG_GENERAL);
965 REGDUMP(sc, IG4_REG_SW_LTR_VALUE);
966 REGDUMP(sc, IG4_REG_AUTO_LTR_VALUE);
967 }
968 #undef REGDUMP
969
970 DRIVER_MODULE(smbus, ig4iic, smbus_driver, smbus_devclass, NULL, NULL);
971