1 /*-
2 * Copyright (c) 2000
3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
35
36 /*
37 * Driver for the Broadcom BCM54xx/57xx 1000baseTX PHY.
38 */
39
40 #include <sys/param.h>
41 #include <sys/systm.h>
42 #include <sys/kernel.h>
43 #include <sys/module.h>
44 #include <sys/socket.h>
45 #include <sys/bus.h>
46 #include <sys/taskqueue.h>
47
48 #include <net/if.h>
49 #include <net/if_var.h>
50 #include <net/ethernet.h>
51 #include <net/if_media.h>
52
53 #include <dev/mii/mii.h>
54 #include <dev/mii/miivar.h>
55 #include "miidevs.h"
56
57 #include <dev/mii/brgphyreg.h>
58 #include <net/if_arp.h>
59 #include <machine/bus.h>
60 #include <dev/bge/if_bgereg.h>
61 #include <dev/bce/if_bcereg.h>
62
63 #include <dev/pci/pcireg.h>
64 #include <dev/pci/pcivar.h>
65
66 #include "miibus_if.h"
67
68 static int brgphy_probe(device_t);
69 static int brgphy_attach(device_t);
70
71 struct brgphy_softc {
72 struct mii_softc mii_sc;
73 int serdes_flags; /* Keeps track of the serdes type used */
74 #define BRGPHY_5706S 0x0001
75 #define BRGPHY_5708S 0x0002
76 #define BRGPHY_NOANWAIT 0x0004
77 #define BRGPHY_5709S 0x0008
78 int bce_phy_flags; /* PHY flags transferred from the MAC driver */
79 };
80
81 static device_method_t brgphy_methods[] = {
82 /* device interface */
83 DEVMETHOD(device_probe, brgphy_probe),
84 DEVMETHOD(device_attach, brgphy_attach),
85 DEVMETHOD(device_detach, mii_phy_detach),
86 DEVMETHOD(device_shutdown, bus_generic_shutdown),
87 DEVMETHOD_END
88 };
89
90 static devclass_t brgphy_devclass;
91
92 static driver_t brgphy_driver = {
93 "brgphy",
94 brgphy_methods,
95 sizeof(struct brgphy_softc)
96 };
97
98 DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0);
99
100 static int brgphy_service(struct mii_softc *, struct mii_data *, int);
101 static void brgphy_setmedia(struct mii_softc *, int);
102 static void brgphy_status(struct mii_softc *);
103 static void brgphy_mii_phy_auto(struct mii_softc *, int);
104 static void brgphy_reset(struct mii_softc *);
105 static void brgphy_enable_loopback(struct mii_softc *);
106 static void bcm5401_load_dspcode(struct mii_softc *);
107 static void bcm5411_load_dspcode(struct mii_softc *);
108 static void bcm54k2_load_dspcode(struct mii_softc *);
109 static void brgphy_fixup_5704_a0_bug(struct mii_softc *);
110 static void brgphy_fixup_adc_bug(struct mii_softc *);
111 static void brgphy_fixup_adjust_trim(struct mii_softc *);
112 static void brgphy_fixup_ber_bug(struct mii_softc *);
113 static void brgphy_fixup_crc_bug(struct mii_softc *);
114 static void brgphy_fixup_jitter_bug(struct mii_softc *);
115 static void brgphy_ethernet_wirespeed(struct mii_softc *);
116 static void brgphy_jumbo_settings(struct mii_softc *, u_long);
117
118 static const struct mii_phydesc brgphys[] = {
119 MII_PHY_DESC(BROADCOM, BCM5400),
120 MII_PHY_DESC(BROADCOM, BCM5401),
121 MII_PHY_DESC(BROADCOM, BCM5402),
122 MII_PHY_DESC(BROADCOM, BCM5411),
123 MII_PHY_DESC(BROADCOM, BCM5404),
124 MII_PHY_DESC(BROADCOM, BCM5424),
125 MII_PHY_DESC(BROADCOM, BCM54K2),
126 MII_PHY_DESC(BROADCOM, BCM5701),
127 MII_PHY_DESC(BROADCOM, BCM5703),
128 MII_PHY_DESC(BROADCOM, BCM5704),
129 MII_PHY_DESC(BROADCOM, BCM5705),
130 MII_PHY_DESC(BROADCOM, BCM5706),
131 MII_PHY_DESC(BROADCOM, BCM5714),
132 MII_PHY_DESC(BROADCOM, BCM5421),
133 MII_PHY_DESC(BROADCOM, BCM5750),
134 MII_PHY_DESC(BROADCOM, BCM5752),
135 MII_PHY_DESC(BROADCOM, BCM5780),
136 MII_PHY_DESC(BROADCOM, BCM5708C),
137 MII_PHY_DESC(BROADCOM, BCM5466),
138 MII_PHY_DESC(BROADCOM2, BCM5478),
139 MII_PHY_DESC(BROADCOM2, BCM5488),
140 MII_PHY_DESC(BROADCOM2, BCM5482),
141 MII_PHY_DESC(BROADCOM2, BCM5708S),
142 MII_PHY_DESC(BROADCOM2, BCM5709C),
143 MII_PHY_DESC(BROADCOM2, BCM5709S),
144 MII_PHY_DESC(BROADCOM2, BCM5709CAX),
145 MII_PHY_DESC(BROADCOM2, BCM5722),
146 MII_PHY_DESC(BROADCOM2, BCM5755),
147 MII_PHY_DESC(BROADCOM2, BCM5754),
148 MII_PHY_DESC(BROADCOM2, BCM5761),
149 MII_PHY_DESC(BROADCOM2, BCM5784),
150 #ifdef notyet /* better handled by ukphy(4) until WARs are implemented */
151 MII_PHY_DESC(BROADCOM2, BCM5785),
152 #endif
153 MII_PHY_DESC(BROADCOM3, BCM5717C),
154 MII_PHY_DESC(BROADCOM3, BCM5719C),
155 MII_PHY_DESC(BROADCOM3, BCM5720C),
156 MII_PHY_DESC(BROADCOM3, BCM57765),
157 MII_PHY_DESC(BROADCOM3, BCM57780),
158 MII_PHY_DESC(BROADCOM4, BCM5725C),
159 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5906),
160 MII_PHY_END
161 };
162
163 static const struct mii_phy_funcs brgphy_funcs = {
164 brgphy_service,
165 brgphy_status,
166 brgphy_reset
167 };
168
169 static const struct hs21_type {
170 const uint32_t id;
171 const char *prod;
172 } hs21_type_lists[] = {
173 { 0x57081021, "IBM eServer BladeCenter HS21" },
174 { 0x57081011, "IBM eServer BladeCenter HS21 -[8853PAU]-" },
175 };
176
177 static int
detect_hs21(struct bce_softc * bce_sc)178 detect_hs21(struct bce_softc *bce_sc)
179 {
180 char *sysenv;
181 int found, i;
182
183 found = 0;
184 sysenv = kern_getenv("smbios.system.product");
185 if (sysenv == NULL)
186 return (found);
187 for (i = 0; i < nitems(hs21_type_lists); i++) {
188 if (bce_sc->bce_chipid == hs21_type_lists[i].id &&
189 strncmp(sysenv, hs21_type_lists[i].prod,
190 strlen(hs21_type_lists[i].prod)) == 0) {
191 found++;
192 break;
193 }
194 }
195 freeenv(sysenv);
196 return (found);
197 }
198
199 /* Search for our PHY in the list of known PHYs */
200 static int
brgphy_probe(device_t dev)201 brgphy_probe(device_t dev)
202 {
203
204 return (mii_phy_dev_probe(dev, brgphys, BUS_PROBE_DEFAULT));
205 }
206
207 /* Attach the PHY to the MII bus */
208 static int
brgphy_attach(device_t dev)209 brgphy_attach(device_t dev)
210 {
211 struct brgphy_softc *bsc;
212 struct bge_softc *bge_sc = NULL;
213 struct bce_softc *bce_sc = NULL;
214 struct mii_softc *sc;
215
216 bsc = device_get_softc(dev);
217 sc = &bsc->mii_sc;
218
219 mii_phy_dev_attach(dev, MIIF_NOISOLATE | MIIF_NOMANPAUSE,
220 &brgphy_funcs, 0);
221
222 bsc->serdes_flags = 0;
223
224 /* Find the MAC driver associated with this PHY. */
225 if (mii_dev_mac_match(dev, "bge"))
226 bge_sc = mii_dev_mac_softc(dev);
227 else if (mii_dev_mac_match(dev, "bce"))
228 bce_sc = mii_dev_mac_softc(dev);
229
230 /* Handle any special cases based on the PHY ID */
231 switch (sc->mii_mpd_oui) {
232 case MII_OUI_BROADCOM:
233 switch (sc->mii_mpd_model) {
234 case MII_MODEL_BROADCOM_BCM5706:
235 case MII_MODEL_BROADCOM_BCM5714:
236 /*
237 * The 5464 PHY used in the 5706 supports both copper
238 * and fiber interfaces over GMII. Need to check the
239 * shadow registers to see which mode is actually
240 * in effect, and therefore whether we have 5706C or
241 * 5706S.
242 */
243 PHY_WRITE(sc, BRGPHY_MII_SHADOW_1C,
244 BRGPHY_SHADOW_1C_MODE_CTRL);
245 if (PHY_READ(sc, BRGPHY_MII_SHADOW_1C) &
246 BRGPHY_SHADOW_1C_ENA_1000X) {
247 bsc->serdes_flags |= BRGPHY_5706S;
248 sc->mii_flags |= MIIF_HAVEFIBER;
249 }
250 break;
251 }
252 break;
253 case MII_OUI_BROADCOM2:
254 switch (sc->mii_mpd_model) {
255 case MII_MODEL_BROADCOM2_BCM5708S:
256 bsc->serdes_flags |= BRGPHY_5708S;
257 sc->mii_flags |= MIIF_HAVEFIBER;
258 break;
259 case MII_MODEL_BROADCOM2_BCM5709S:
260 /*
261 * XXX
262 * 5720S and 5709S shares the same PHY id.
263 * Assume 5720S PHY if parent device is bge(4).
264 */
265 if (bge_sc != NULL)
266 bsc->serdes_flags |= BRGPHY_5708S;
267 else
268 bsc->serdes_flags |= BRGPHY_5709S;
269 sc->mii_flags |= MIIF_HAVEFIBER;
270 break;
271 }
272 break;
273 }
274
275 PHY_RESET(sc);
276
277 /* Read the PHY's capabilities. */
278 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & sc->mii_capmask;
279 if (sc->mii_capabilities & BMSR_EXTSTAT)
280 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
281 device_printf(dev, " ");
282
283 /* Add the supported media types */
284 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
285 mii_phy_add_media(sc);
286 printf("\n");
287 } else {
288 sc->mii_anegticks = MII_ANEGTICKS_GIGE;
289 ifmedia_add(&sc->mii_pdata->mii_media,
290 IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, sc->mii_inst),
291 0, NULL);
292 printf("1000baseSX-FDX, ");
293 /*
294 * 2.5G support is a software enabled feature
295 * on the 5708S and 5709S.
296 */
297 if (bce_sc && (bce_sc->bce_phy_flags &
298 BCE_PHY_2_5G_CAPABLE_FLAG)) {
299 ifmedia_add(&sc->mii_pdata->mii_media,
300 IFM_MAKEWORD(IFM_ETHER, IFM_2500_SX, IFM_FDX,
301 sc->mii_inst), 0, NULL);
302 printf("2500baseSX-FDX, ");
303 } else if ((bsc->serdes_flags & BRGPHY_5708S) && bce_sc &&
304 (detect_hs21(bce_sc) != 0)) {
305 /*
306 * There appears to be certain silicon revision
307 * in IBM HS21 blades that is having issues with
308 * this driver wating for the auto-negotiation to
309 * complete. This happens with a specific chip id
310 * only and when the 1000baseSX-FDX is the only
311 * mode. Workaround this issue since it's unlikely
312 * to be ever addressed.
313 */
314 printf("auto-neg workaround, ");
315 bsc->serdes_flags |= BRGPHY_NOANWAIT;
316 }
317 ifmedia_add(&sc->mii_pdata->mii_media, IFM_MAKEWORD(IFM_ETHER,
318 IFM_AUTO, 0, sc->mii_inst), 0, NULL);
319 printf("auto\n");
320 }
321
322 MIIBUS_MEDIAINIT(sc->mii_dev);
323 return (0);
324 }
325
326 static int
brgphy_service(struct mii_softc * sc,struct mii_data * mii,int cmd)327 brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
328 {
329 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
330 int val;
331
332 switch (cmd) {
333 case MII_POLLSTAT:
334 break;
335 case MII_MEDIACHG:
336 /* Todo: Why is this here? Is it really needed? */
337 PHY_RESET(sc); /* XXX hardware bug work-around */
338
339 switch (IFM_SUBTYPE(ife->ifm_media)) {
340 case IFM_AUTO:
341 brgphy_mii_phy_auto(sc, ife->ifm_media);
342 break;
343 case IFM_2500_SX:
344 case IFM_1000_SX:
345 case IFM_1000_T:
346 case IFM_100_TX:
347 case IFM_10_T:
348 brgphy_setmedia(sc, ife->ifm_media);
349 break;
350 default:
351 return (EINVAL);
352 }
353 break;
354 case MII_TICK:
355 /* Bail if autoneg isn't in process. */
356 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
357 sc->mii_ticks = 0;
358 break;
359 }
360
361 /*
362 * Check to see if we have link. If we do, we don't
363 * need to restart the autonegotiation process.
364 */
365 val = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
366 if (val & BMSR_LINK) {
367 sc->mii_ticks = 0; /* Reset autoneg timer. */
368 break;
369 }
370
371 /* Announce link loss right after it happens. */
372 if (sc->mii_ticks++ == 0)
373 break;
374
375 /* Only retry autonegotiation every mii_anegticks seconds. */
376 if (sc->mii_ticks <= sc->mii_anegticks)
377 break;
378
379
380 /* Retry autonegotiation */
381 sc->mii_ticks = 0;
382 brgphy_mii_phy_auto(sc, ife->ifm_media);
383 break;
384 }
385
386 /* Update the media status. */
387 PHY_STATUS(sc);
388
389 /*
390 * Callback if something changed. Note that we need to poke
391 * the DSP on the Broadcom PHYs if the media changes.
392 */
393 if (sc->mii_media_active != mii->mii_media_active ||
394 sc->mii_media_status != mii->mii_media_status ||
395 cmd == MII_MEDIACHG) {
396 switch (sc->mii_mpd_oui) {
397 case MII_OUI_BROADCOM:
398 switch (sc->mii_mpd_model) {
399 case MII_MODEL_BROADCOM_BCM5400:
400 bcm5401_load_dspcode(sc);
401 break;
402 case MII_MODEL_BROADCOM_BCM5401:
403 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3)
404 bcm5401_load_dspcode(sc);
405 break;
406 case MII_MODEL_BROADCOM_BCM5411:
407 bcm5411_load_dspcode(sc);
408 break;
409 case MII_MODEL_BROADCOM_BCM54K2:
410 bcm54k2_load_dspcode(sc);
411 break;
412 }
413 break;
414 }
415 }
416 mii_phy_update(sc, cmd);
417 return (0);
418 }
419
420 /****************************************************************************/
421 /* Sets the PHY link speed. */
422 /* */
423 /* Returns: */
424 /* None */
425 /****************************************************************************/
426 static void
brgphy_setmedia(struct mii_softc * sc,int media)427 brgphy_setmedia(struct mii_softc *sc, int media)
428 {
429 int bmcr = 0, gig;
430
431 switch (IFM_SUBTYPE(media)) {
432 case IFM_2500_SX:
433 break;
434 case IFM_1000_SX:
435 case IFM_1000_T:
436 bmcr = BRGPHY_S1000;
437 break;
438 case IFM_100_TX:
439 bmcr = BRGPHY_S100;
440 break;
441 case IFM_10_T:
442 default:
443 bmcr = BRGPHY_S10;
444 break;
445 }
446
447 if ((media & IFM_FDX) != 0) {
448 bmcr |= BRGPHY_BMCR_FDX;
449 gig = BRGPHY_1000CTL_AFD;
450 } else {
451 gig = BRGPHY_1000CTL_AHD;
452 }
453
454 /* Force loopback to disconnect PHY from Ethernet medium. */
455 brgphy_enable_loopback(sc);
456
457 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0);
458 PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE);
459
460 if (IFM_SUBTYPE(media) != IFM_1000_T &&
461 IFM_SUBTYPE(media) != IFM_1000_SX) {
462 PHY_WRITE(sc, BRGPHY_MII_BMCR, bmcr);
463 return;
464 }
465
466 if (IFM_SUBTYPE(media) == IFM_1000_T) {
467 gig |= BRGPHY_1000CTL_MSE;
468 if ((media & IFM_ETH_MASTER) != 0)
469 gig |= BRGPHY_1000CTL_MSC;
470 }
471 PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig);
472 PHY_WRITE(sc, BRGPHY_MII_BMCR,
473 bmcr | BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG);
474 }
475
476 /****************************************************************************/
477 /* Set the media status based on the PHY settings. */
478 /* */
479 /* Returns: */
480 /* None */
481 /****************************************************************************/
482 static void
brgphy_status(struct mii_softc * sc)483 brgphy_status(struct mii_softc *sc)
484 {
485 struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
486 struct mii_data *mii = sc->mii_pdata;
487 int aux, bmcr, bmsr, val, xstat;
488 u_int flowstat;
489
490 mii->mii_media_status = IFM_AVALID;
491 mii->mii_media_active = IFM_ETHER;
492
493 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR) | PHY_READ(sc, BRGPHY_MII_BMSR);
494 bmcr = PHY_READ(sc, BRGPHY_MII_BMCR);
495
496 if (bmcr & BRGPHY_BMCR_LOOP) {
497 mii->mii_media_active |= IFM_LOOP;
498 }
499
500 if ((bmcr & BRGPHY_BMCR_AUTOEN) &&
501 (bmsr & BRGPHY_BMSR_ACOMP) == 0 &&
502 (bsc->serdes_flags & BRGPHY_NOANWAIT) == 0) {
503 /* Erg, still trying, I guess... */
504 mii->mii_media_active |= IFM_NONE;
505 return;
506 }
507
508 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
509 /*
510 * NB: reading the ANAR, ANLPAR or 1000STS after the AUXSTS
511 * wedges at least the PHY of BCM5704 (but not others).
512 */
513 flowstat = mii_phy_flowstatus(sc);
514 xstat = PHY_READ(sc, BRGPHY_MII_1000STS);
515 aux = PHY_READ(sc, BRGPHY_MII_AUXSTS);
516
517 /* If copper link is up, get the negotiated speed/duplex. */
518 if (aux & BRGPHY_AUXSTS_LINK) {
519 mii->mii_media_status |= IFM_ACTIVE;
520 switch (aux & BRGPHY_AUXSTS_AN_RES) {
521 case BRGPHY_RES_1000FD:
522 mii->mii_media_active |= IFM_1000_T | IFM_FDX; break;
523 case BRGPHY_RES_1000HD:
524 mii->mii_media_active |= IFM_1000_T | IFM_HDX; break;
525 case BRGPHY_RES_100FD:
526 mii->mii_media_active |= IFM_100_TX | IFM_FDX; break;
527 case BRGPHY_RES_100T4:
528 mii->mii_media_active |= IFM_100_T4; break;
529 case BRGPHY_RES_100HD:
530 mii->mii_media_active |= IFM_100_TX | IFM_HDX; break;
531 case BRGPHY_RES_10FD:
532 mii->mii_media_active |= IFM_10_T | IFM_FDX; break;
533 case BRGPHY_RES_10HD:
534 mii->mii_media_active |= IFM_10_T | IFM_HDX; break;
535 default:
536 mii->mii_media_active |= IFM_NONE; break;
537 }
538
539 if ((mii->mii_media_active & IFM_FDX) != 0)
540 mii->mii_media_active |= flowstat;
541
542 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T &&
543 (xstat & BRGPHY_1000STS_MSR) != 0)
544 mii->mii_media_active |= IFM_ETH_MASTER;
545 }
546 } else {
547 /* Todo: Add support for flow control. */
548 /* If serdes link is up, get the negotiated speed/duplex. */
549 if (bmsr & BRGPHY_BMSR_LINK) {
550 mii->mii_media_status |= IFM_ACTIVE;
551 }
552
553 /* Check the link speed/duplex based on the PHY type. */
554 if (bsc->serdes_flags & BRGPHY_5706S) {
555 mii->mii_media_active |= IFM_1000_SX;
556
557 /* If autoneg enabled, read negotiated duplex settings */
558 if (bmcr & BRGPHY_BMCR_AUTOEN) {
559 val = PHY_READ(sc, BRGPHY_SERDES_ANAR) & PHY_READ(sc, BRGPHY_SERDES_ANLPAR);
560 if (val & BRGPHY_SERDES_ANAR_FDX)
561 mii->mii_media_active |= IFM_FDX;
562 else
563 mii->mii_media_active |= IFM_HDX;
564 }
565 } else if (bsc->serdes_flags & BRGPHY_5708S) {
566 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0);
567 xstat = PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1);
568
569 /* Check for MRBE auto-negotiated speed results. */
570 switch (xstat & BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK) {
571 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10:
572 mii->mii_media_active |= IFM_10_FL; break;
573 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100:
574 mii->mii_media_active |= IFM_100_FX; break;
575 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G:
576 mii->mii_media_active |= IFM_1000_SX; break;
577 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G:
578 mii->mii_media_active |= IFM_2500_SX; break;
579 }
580
581 /* Check for MRBE auto-negotiated duplex results. */
582 if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_FDX)
583 mii->mii_media_active |= IFM_FDX;
584 else
585 mii->mii_media_active |= IFM_HDX;
586 } else if (bsc->serdes_flags & BRGPHY_5709S) {
587 /* Select GP Status Block of the AN MMD, get autoneg results. */
588 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_GP_STATUS);
589 xstat = PHY_READ(sc, BRGPHY_GP_STATUS_TOP_ANEG_STATUS);
590
591 /* Restore IEEE0 block (assumed in all brgphy(4) code). */
592 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
593
594 /* Check for MRBE auto-negotiated speed results. */
595 switch (xstat & BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK) {
596 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10:
597 mii->mii_media_active |= IFM_10_FL; break;
598 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100:
599 mii->mii_media_active |= IFM_100_FX; break;
600 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G:
601 mii->mii_media_active |= IFM_1000_SX; break;
602 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G:
603 mii->mii_media_active |= IFM_2500_SX; break;
604 }
605
606 /* Check for MRBE auto-negotiated duplex results. */
607 if (xstat & BRGPHY_GP_STATUS_TOP_ANEG_FDX)
608 mii->mii_media_active |= IFM_FDX;
609 else
610 mii->mii_media_active |= IFM_HDX;
611 }
612 }
613 }
614
615 static void
brgphy_mii_phy_auto(struct mii_softc * sc,int media)616 brgphy_mii_phy_auto(struct mii_softc *sc, int media)
617 {
618 int anar, ktcr = 0;
619
620 PHY_RESET(sc);
621
622 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
623 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA;
624 if ((media & IFM_FLOW) != 0 ||
625 (sc->mii_flags & MIIF_FORCEPAUSE) != 0)
626 anar |= BRGPHY_ANAR_PC | BRGPHY_ANAR_ASP;
627 PHY_WRITE(sc, BRGPHY_MII_ANAR, anar);
628 ktcr = BRGPHY_1000CTL_AFD | BRGPHY_1000CTL_AHD;
629 if (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5701)
630 ktcr |= BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC;
631 PHY_WRITE(sc, BRGPHY_MII_1000CTL, ktcr);
632 PHY_READ(sc, BRGPHY_MII_1000CTL);
633 } else {
634 anar = BRGPHY_SERDES_ANAR_FDX | BRGPHY_SERDES_ANAR_HDX;
635 if ((media & IFM_FLOW) != 0 ||
636 (sc->mii_flags & MIIF_FORCEPAUSE) != 0)
637 anar |= BRGPHY_SERDES_ANAR_BOTH_PAUSE;
638 PHY_WRITE(sc, BRGPHY_SERDES_ANAR, anar);
639 }
640
641 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_AUTOEN |
642 BRGPHY_BMCR_STARTNEG);
643 PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00);
644 }
645
646 /* Enable loopback to force the link down. */
647 static void
brgphy_enable_loopback(struct mii_softc * sc)648 brgphy_enable_loopback(struct mii_softc *sc)
649 {
650 int i;
651
652 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP);
653 for (i = 0; i < 15000; i++) {
654 if (!(PHY_READ(sc, BRGPHY_MII_BMSR) & BRGPHY_BMSR_LINK))
655 break;
656 DELAY(10);
657 }
658 }
659
660 /* Turn off tap power management on 5401. */
661 static void
bcm5401_load_dspcode(struct mii_softc * sc)662 bcm5401_load_dspcode(struct mii_softc *sc)
663 {
664 static const struct {
665 int reg;
666 uint16_t val;
667 } dspcode[] = {
668 { BRGPHY_MII_AUXCTL, 0x0c20 },
669 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 },
670 { BRGPHY_MII_DSP_RW_PORT, 0x1804 },
671 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 },
672 { BRGPHY_MII_DSP_RW_PORT, 0x1204 },
673 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 },
674 { BRGPHY_MII_DSP_RW_PORT, 0x0132 },
675 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 },
676 { BRGPHY_MII_DSP_RW_PORT, 0x0232 },
677 { BRGPHY_MII_DSP_ADDR_REG, 0x201f },
678 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 },
679 { 0, 0 },
680 };
681 int i;
682
683 for (i = 0; dspcode[i].reg != 0; i++)
684 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
685 DELAY(40);
686 }
687
688 static void
bcm5411_load_dspcode(struct mii_softc * sc)689 bcm5411_load_dspcode(struct mii_softc *sc)
690 {
691 static const struct {
692 int reg;
693 uint16_t val;
694 } dspcode[] = {
695 { 0x1c, 0x8c23 },
696 { 0x1c, 0x8ca3 },
697 { 0x1c, 0x8c23 },
698 { 0, 0 },
699 };
700 int i;
701
702 for (i = 0; dspcode[i].reg != 0; i++)
703 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
704 }
705
706 void
bcm54k2_load_dspcode(struct mii_softc * sc)707 bcm54k2_load_dspcode(struct mii_softc *sc)
708 {
709 static const struct {
710 int reg;
711 uint16_t val;
712 } dspcode[] = {
713 { 4, 0x01e1 },
714 { 9, 0x0300 },
715 { 0, 0 },
716 };
717 int i;
718
719 for (i = 0; dspcode[i].reg != 0; i++)
720 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
721
722 }
723
724 static void
brgphy_fixup_5704_a0_bug(struct mii_softc * sc)725 brgphy_fixup_5704_a0_bug(struct mii_softc *sc)
726 {
727 static const struct {
728 int reg;
729 uint16_t val;
730 } dspcode[] = {
731 { 0x1c, 0x8d68 },
732 { 0x1c, 0x8d68 },
733 { 0, 0 },
734 };
735 int i;
736
737 for (i = 0; dspcode[i].reg != 0; i++)
738 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
739 }
740
741 static void
brgphy_fixup_adc_bug(struct mii_softc * sc)742 brgphy_fixup_adc_bug(struct mii_softc *sc)
743 {
744 static const struct {
745 int reg;
746 uint16_t val;
747 } dspcode[] = {
748 { BRGPHY_MII_AUXCTL, 0x0c00 },
749 { BRGPHY_MII_DSP_ADDR_REG, 0x201f },
750 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa },
751 { 0, 0 },
752 };
753 int i;
754
755 for (i = 0; dspcode[i].reg != 0; i++)
756 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
757 }
758
759 static void
brgphy_fixup_adjust_trim(struct mii_softc * sc)760 brgphy_fixup_adjust_trim(struct mii_softc *sc)
761 {
762 static const struct {
763 int reg;
764 uint16_t val;
765 } dspcode[] = {
766 { BRGPHY_MII_AUXCTL, 0x0c00 },
767 { BRGPHY_MII_DSP_ADDR_REG, 0x000a },
768 { BRGPHY_MII_DSP_RW_PORT, 0x110b },
769 { BRGPHY_MII_TEST1, 0x0014 },
770 { BRGPHY_MII_AUXCTL, 0x0400 },
771 { 0, 0 },
772 };
773 int i;
774
775 for (i = 0; dspcode[i].reg != 0; i++)
776 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
777 }
778
779 static void
brgphy_fixup_ber_bug(struct mii_softc * sc)780 brgphy_fixup_ber_bug(struct mii_softc *sc)
781 {
782 static const struct {
783 int reg;
784 uint16_t val;
785 } dspcode[] = {
786 { BRGPHY_MII_AUXCTL, 0x0c00 },
787 { BRGPHY_MII_DSP_ADDR_REG, 0x000a },
788 { BRGPHY_MII_DSP_RW_PORT, 0x310b },
789 { BRGPHY_MII_DSP_ADDR_REG, 0x201f },
790 { BRGPHY_MII_DSP_RW_PORT, 0x9506 },
791 { BRGPHY_MII_DSP_ADDR_REG, 0x401f },
792 { BRGPHY_MII_DSP_RW_PORT, 0x14e2 },
793 { BRGPHY_MII_AUXCTL, 0x0400 },
794 { 0, 0 },
795 };
796 int i;
797
798 for (i = 0; dspcode[i].reg != 0; i++)
799 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
800 }
801
802 static void
brgphy_fixup_crc_bug(struct mii_softc * sc)803 brgphy_fixup_crc_bug(struct mii_softc *sc)
804 {
805 static const struct {
806 int reg;
807 uint16_t val;
808 } dspcode[] = {
809 { BRGPHY_MII_DSP_RW_PORT, 0x0a75 },
810 { 0x1c, 0x8c68 },
811 { 0x1c, 0x8d68 },
812 { 0x1c, 0x8c68 },
813 { 0, 0 },
814 };
815 int i;
816
817 for (i = 0; dspcode[i].reg != 0; i++)
818 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
819 }
820
821 static void
brgphy_fixup_jitter_bug(struct mii_softc * sc)822 brgphy_fixup_jitter_bug(struct mii_softc *sc)
823 {
824 static const struct {
825 int reg;
826 uint16_t val;
827 } dspcode[] = {
828 { BRGPHY_MII_AUXCTL, 0x0c00 },
829 { BRGPHY_MII_DSP_ADDR_REG, 0x000a },
830 { BRGPHY_MII_DSP_RW_PORT, 0x010b },
831 { BRGPHY_MII_AUXCTL, 0x0400 },
832 { 0, 0 },
833 };
834 int i;
835
836 for (i = 0; dspcode[i].reg != 0; i++)
837 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
838 }
839
840 static void
brgphy_fixup_disable_early_dac(struct mii_softc * sc)841 brgphy_fixup_disable_early_dac(struct mii_softc *sc)
842 {
843 uint32_t val;
844
845 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x0f08);
846 val = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT);
847 val &= ~(1 << 8);
848 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, val);
849
850 }
851
852 static void
brgphy_ethernet_wirespeed(struct mii_softc * sc)853 brgphy_ethernet_wirespeed(struct mii_softc *sc)
854 {
855 uint32_t val;
856
857 /* Enable Ethernet@WireSpeed. */
858 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007);
859 val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
860 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4));
861 }
862
863 static void
brgphy_jumbo_settings(struct mii_softc * sc,u_long mtu)864 brgphy_jumbo_settings(struct mii_softc *sc, u_long mtu)
865 {
866 uint32_t val;
867
868 /* Set or clear jumbo frame settings in the PHY. */
869 if (mtu > ETHER_MAX_LEN) {
870 if (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5401) {
871 /* BCM5401 PHY cannot read-modify-write. */
872 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20);
873 } else {
874 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7);
875 val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
876 PHY_WRITE(sc, BRGPHY_MII_AUXCTL,
877 val | BRGPHY_AUXCTL_LONG_PKT);
878 }
879
880 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL);
881 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
882 val | BRGPHY_PHY_EXTCTL_HIGH_LA);
883 } else {
884 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7);
885 val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
886 PHY_WRITE(sc, BRGPHY_MII_AUXCTL,
887 val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7));
888
889 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL);
890 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
891 val & ~BRGPHY_PHY_EXTCTL_HIGH_LA);
892 }
893 }
894
895 static void
brgphy_reset(struct mii_softc * sc)896 brgphy_reset(struct mii_softc *sc)
897 {
898 struct bge_softc *bge_sc = NULL;
899 struct bce_softc *bce_sc = NULL;
900 if_t ifp;
901 int i, val;
902
903 /*
904 * Perform a reset. Note that at least some Broadcom PHYs default to
905 * being powered down as well as isolated after a reset but don't work
906 * if one or both of these bits are cleared. However, they just work
907 * fine if both bits remain set, so we don't use mii_phy_reset() here.
908 */
909 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET);
910
911 /* Wait 100ms for it to complete. */
912 for (i = 0; i < 100; i++) {
913 if ((PHY_READ(sc, BRGPHY_MII_BMCR) & BRGPHY_BMCR_RESET) == 0)
914 break;
915 DELAY(1000);
916 }
917
918 /* Handle any PHY specific procedures following the reset. */
919 switch (sc->mii_mpd_oui) {
920 case MII_OUI_BROADCOM:
921 switch (sc->mii_mpd_model) {
922 case MII_MODEL_BROADCOM_BCM5400:
923 bcm5401_load_dspcode(sc);
924 break;
925 case MII_MODEL_BROADCOM_BCM5401:
926 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3)
927 bcm5401_load_dspcode(sc);
928 break;
929 case MII_MODEL_BROADCOM_BCM5411:
930 bcm5411_load_dspcode(sc);
931 break;
932 case MII_MODEL_BROADCOM_BCM54K2:
933 bcm54k2_load_dspcode(sc);
934 break;
935 }
936 break;
937 case MII_OUI_BROADCOM3:
938 switch (sc->mii_mpd_model) {
939 case MII_MODEL_BROADCOM3_BCM5717C:
940 case MII_MODEL_BROADCOM3_BCM5719C:
941 case MII_MODEL_BROADCOM3_BCM5720C:
942 case MII_MODEL_BROADCOM3_BCM57765:
943 return;
944 }
945 break;
946 case MII_OUI_BROADCOM4:
947 return;
948 }
949
950 ifp = sc->mii_pdata->mii_ifp;
951
952 /* Find the driver associated with this PHY. */
953 if (mii_phy_mac_match(sc, "bge"))
954 bge_sc = mii_phy_mac_softc(sc);
955 else if (mii_phy_mac_match(sc, "bce"))
956 bce_sc = mii_phy_mac_softc(sc);
957
958 if (bge_sc) {
959 /* Fix up various bugs */
960 if (bge_sc->bge_phy_flags & BGE_PHY_5704_A0_BUG)
961 brgphy_fixup_5704_a0_bug(sc);
962 if (bge_sc->bge_phy_flags & BGE_PHY_ADC_BUG)
963 brgphy_fixup_adc_bug(sc);
964 if (bge_sc->bge_phy_flags & BGE_PHY_ADJUST_TRIM)
965 brgphy_fixup_adjust_trim(sc);
966 if (bge_sc->bge_phy_flags & BGE_PHY_BER_BUG)
967 brgphy_fixup_ber_bug(sc);
968 if (bge_sc->bge_phy_flags & BGE_PHY_CRC_BUG)
969 brgphy_fixup_crc_bug(sc);
970 if (bge_sc->bge_phy_flags & BGE_PHY_JITTER_BUG)
971 brgphy_fixup_jitter_bug(sc);
972
973 if (bge_sc->bge_flags & BGE_FLAG_JUMBO)
974 brgphy_jumbo_settings(sc, if_getmtu(ifp));
975
976 if ((bge_sc->bge_phy_flags & BGE_PHY_NO_WIRESPEED) == 0)
977 brgphy_ethernet_wirespeed(sc);
978
979 /* Enable Link LED on Dell boxes */
980 if (bge_sc->bge_phy_flags & BGE_PHY_NO_3LED) {
981 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
982 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) &
983 ~BRGPHY_PHY_EXTCTL_3_LED);
984 }
985
986 /* Adjust output voltage (From Linux driver) */
987 if (bge_sc->bge_asicrev == BGE_ASICREV_BCM5906)
988 PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12);
989 } else if (bce_sc) {
990 if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5708 &&
991 (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) {
992
993 /* Store autoneg capabilities/results in digital block (Page 0) */
994 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2);
995 PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0,
996 BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE);
997 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0);
998
999 /* Enable fiber mode and autodetection */
1000 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1,
1001 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1) |
1002 BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN |
1003 BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE);
1004
1005 /* Enable parallel detection */
1006 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2,
1007 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2) |
1008 BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN);
1009
1010 /* Advertise 2.5G support through next page during autoneg */
1011 if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
1012 PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1,
1013 PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1) |
1014 BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G);
1015
1016 /* Increase TX signal amplitude */
1017 if ((BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_A0) ||
1018 (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B0) ||
1019 (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B1)) {
1020 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
1021 BRGPHY_5708S_TX_MISC_PG5);
1022 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1,
1023 PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1) & ~0x30);
1024 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
1025 BRGPHY_5708S_DIG_PG0);
1026 }
1027
1028 /* Backplanes use special driver/pre-driver/pre-emphasis values. */
1029 if ((bce_sc->bce_shared_hw_cfg & BCE_SHARED_HW_CFG_PHY_BACKPLANE) &&
1030 (bce_sc->bce_port_hw_cfg & BCE_PORT_HW_CFG_CFG_TXCTL3_MASK)) {
1031 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
1032 BRGPHY_5708S_TX_MISC_PG5);
1033 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3,
1034 bce_sc->bce_port_hw_cfg &
1035 BCE_PORT_HW_CFG_CFG_TXCTL3_MASK);
1036 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
1037 BRGPHY_5708S_DIG_PG0);
1038 }
1039 } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709 &&
1040 (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) {
1041
1042 /* Select the SerDes Digital block of the AN MMD. */
1043 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_SERDES_DIG);
1044 val = PHY_READ(sc, BRGPHY_SERDES_DIG_1000X_CTL1);
1045 val &= ~BRGPHY_SD_DIG_1000X_CTL1_AUTODET;
1046 val |= BRGPHY_SD_DIG_1000X_CTL1_FIBER;
1047 PHY_WRITE(sc, BRGPHY_SERDES_DIG_1000X_CTL1, val);
1048
1049 /* Select the Over 1G block of the AN MMD. */
1050 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_OVER_1G);
1051
1052 /* Enable autoneg "Next Page" to advertise 2.5G support. */
1053 val = PHY_READ(sc, BRGPHY_OVER_1G_UNFORMAT_PG1);
1054 if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
1055 val |= BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G;
1056 else
1057 val &= ~BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G;
1058 PHY_WRITE(sc, BRGPHY_OVER_1G_UNFORMAT_PG1, val);
1059
1060 /* Select the Multi-Rate Backplane Ethernet block of the AN MMD. */
1061 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_MRBE);
1062
1063 /* Enable MRBE speed autoneg. */
1064 val = PHY_READ(sc, BRGPHY_MRBE_MSG_PG5_NP);
1065 val |= BRGPHY_MRBE_MSG_PG5_NP_MBRE |
1066 BRGPHY_MRBE_MSG_PG5_NP_T2;
1067 PHY_WRITE(sc, BRGPHY_MRBE_MSG_PG5_NP, val);
1068
1069 /* Select the Clause 73 User B0 block of the AN MMD. */
1070 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_CL73_USER_B0);
1071
1072 /* Enable MRBE speed autoneg. */
1073 PHY_WRITE(sc, BRGPHY_CL73_USER_B0_MBRE_CTL1,
1074 BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP |
1075 BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR |
1076 BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG);
1077
1078 /* Restore IEEE0 block (assumed in all brgphy(4) code). */
1079 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
1080 } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709) {
1081 if ((BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Ax) ||
1082 (BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Bx))
1083 brgphy_fixup_disable_early_dac(sc);
1084
1085 brgphy_jumbo_settings(sc, if_getmtu(ifp));
1086 brgphy_ethernet_wirespeed(sc);
1087 } else {
1088 brgphy_fixup_ber_bug(sc);
1089 brgphy_jumbo_settings(sc, if_getmtu(ifp));
1090 brgphy_ethernet_wirespeed(sc);
1091 }
1092 }
1093 }
1094