1 /*-
2 * Copyright (c) 2003 Marcel Moolenaar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
29
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <sys/bus.h>
33 #include <sys/conf.h>
34 #include <machine/bus.h>
35 #include <machine/fdt.h>
36
37 #include <dev/uart/uart.h>
38 #include <dev/uart/uart_cpu.h>
39 #include <dev/uart/uart_cpu_fdt.h>
40 #include <dev/uart/uart_bus.h>
41
42 #include <dev/ic/ns16550.h>
43 #include <arm/lpc/lpcreg.h>
44
45 #include "uart_if.h"
46
47 #define DEFAULT_RCLK (13 * 1000 * 1000)
48
49 static bus_space_handle_t bsh_clkpwr;
50
51 #define lpc_ns8250_get_clkreg(_bas, _reg) \
52 bus_space_read_4(fdtbus_bs_tag, bsh_clkpwr, (_reg))
53 #define lpc_ns8250_set_clkreg(_bas, _reg, _val) \
54 bus_space_write_4(fdtbus_bs_tag, bsh_clkpwr, (_reg), (_val))
55
56 /*
57 * Clear pending interrupts. THRE is cleared by reading IIR. Data
58 * that may have been received gets lost here.
59 */
60 static void
lpc_ns8250_clrint(struct uart_bas * bas)61 lpc_ns8250_clrint(struct uart_bas *bas)
62 {
63 uint8_t iir, lsr;
64
65 iir = uart_getreg(bas, REG_IIR);
66 while ((iir & IIR_NOPEND) == 0) {
67 iir &= IIR_IMASK;
68 if (iir == IIR_RLS) {
69 lsr = uart_getreg(bas, REG_LSR);
70 if (lsr & (LSR_BI|LSR_FE|LSR_PE))
71 (void)uart_getreg(bas, REG_DATA);
72 } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT)
73 (void)uart_getreg(bas, REG_DATA);
74 else if (iir == IIR_MLSC)
75 (void)uart_getreg(bas, REG_MSR);
76 uart_barrier(bas);
77 iir = uart_getreg(bas, REG_IIR);
78 }
79 }
80
81 static int
lpc_ns8250_delay(struct uart_bas * bas)82 lpc_ns8250_delay(struct uart_bas *bas)
83 {
84 uint32_t uclk;
85 int x, y;
86
87 uclk = lpc_ns8250_get_clkreg(bas, LPC_CLKPWR_UART_U5CLK);
88
89 x = (uclk >> 8) & 0xff;
90 y = uclk & 0xff;
91
92 return (16000000 / (bas->rclk * x / y));
93 }
94
95 static void
lpc_ns8250_divisor(int rclk,int baudrate,int * x,int * y)96 lpc_ns8250_divisor(int rclk, int baudrate, int *x, int *y)
97 {
98
99 switch (baudrate) {
100 case 2400:
101 *x = 1;
102 *y = 255;
103 return;
104 case 4800:
105 *x = 1;
106 *y = 169;
107 return;
108 case 9600:
109 *x = 3;
110 *y = 254;
111 return;
112 case 19200:
113 *x = 3;
114 *y = 127;
115 return;
116 case 38400:
117 *x = 6;
118 *y = 127;
119 return;
120 case 57600:
121 *x = 9;
122 *y = 127;
123 return;
124 default:
125 case 115200:
126 *x = 19;
127 *y = 134;
128 return;
129 case 230400:
130 *x = 19;
131 *y = 67;
132 return;
133 case 460800:
134 *x = 38;
135 *y = 67;
136 return;
137 }
138 }
139
140 static int
lpc_ns8250_drain(struct uart_bas * bas,int what)141 lpc_ns8250_drain(struct uart_bas *bas, int what)
142 {
143 int delay, limit;
144
145 delay = lpc_ns8250_delay(bas);
146
147 if (what & UART_DRAIN_TRANSMITTER) {
148 /*
149 * Pick an arbitrary high limit to avoid getting stuck in
150 * an infinite loop when the hardware is broken. Make the
151 * limit high enough to handle large FIFOs.
152 */
153 limit = 10*1024;
154 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
155 DELAY(delay);
156 if (limit == 0) {
157 /* printf("lpc_ns8250: transmitter appears stuck... "); */
158 return (EIO);
159 }
160 }
161
162 if (what & UART_DRAIN_RECEIVER) {
163 /*
164 * Pick an arbitrary high limit to avoid getting stuck in
165 * an infinite loop when the hardware is broken. Make the
166 * limit high enough to handle large FIFOs and integrated
167 * UARTs. The HP rx2600 for example has 3 UARTs on the
168 * management board that tend to get a lot of data send
169 * to it when the UART is first activated.
170 */
171 limit=10*4096;
172 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) {
173 (void)uart_getreg(bas, REG_DATA);
174 uart_barrier(bas);
175 DELAY(delay << 2);
176 }
177 if (limit == 0) {
178 /* printf("lpc_ns8250: receiver appears broken... "); */
179 return (EIO);
180 }
181 }
182
183 return (0);
184 }
185
186 /*
187 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be
188 * drained. WARNING: this function clobbers the FIFO setting!
189 */
190 static void
lpc_ns8250_flush(struct uart_bas * bas,int what)191 lpc_ns8250_flush(struct uart_bas *bas, int what)
192 {
193 uint8_t fcr;
194
195 fcr = FCR_ENABLE;
196 if (what & UART_FLUSH_TRANSMITTER)
197 fcr |= FCR_XMT_RST;
198 if (what & UART_FLUSH_RECEIVER)
199 fcr |= FCR_RCV_RST;
200 uart_setreg(bas, REG_FCR, fcr);
201 uart_barrier(bas);
202 }
203
204 static int
lpc_ns8250_param(struct uart_bas * bas,int baudrate,int databits,int stopbits,int parity)205 lpc_ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
206 int parity)
207 {
208 int xdiv, ydiv;
209 uint8_t lcr;
210
211 lcr = 0;
212 if (databits >= 8)
213 lcr |= LCR_8BITS;
214 else if (databits == 7)
215 lcr |= LCR_7BITS;
216 else if (databits == 6)
217 lcr |= LCR_6BITS;
218 else
219 lcr |= LCR_5BITS;
220 if (stopbits > 1)
221 lcr |= LCR_STOPB;
222 lcr |= parity << 3;
223
224 /* Set baudrate. */
225 if (baudrate > 0) {
226 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
227 uart_barrier(bas);
228 uart_setreg(bas, REG_DLL, 0x00);
229 uart_setreg(bas, REG_DLH, 0x00);
230 uart_barrier(bas);
231
232 lpc_ns8250_divisor(bas->rclk, baudrate, &xdiv, &ydiv);
233 lpc_ns8250_set_clkreg(bas,
234 LPC_CLKPWR_UART_U5CLK,
235 LPC_CLKPWR_UART_UCLK_X(xdiv) |
236 LPC_CLKPWR_UART_UCLK_Y(ydiv));
237 }
238
239 /* Set LCR and clear DLAB. */
240 uart_setreg(bas, REG_LCR, lcr);
241 uart_barrier(bas);
242 return (0);
243 }
244
245 /*
246 * Low-level UART interface.
247 */
248 static int lpc_ns8250_probe(struct uart_bas *bas);
249 static void lpc_ns8250_init(struct uart_bas *bas, int, int, int, int);
250 static void lpc_ns8250_term(struct uart_bas *bas);
251 static void lpc_ns8250_putc(struct uart_bas *bas, int);
252 static int lpc_ns8250_rxready(struct uart_bas *bas);
253 static int lpc_ns8250_getc(struct uart_bas *bas, struct mtx *);
254
255 static struct uart_ops uart_lpc_ns8250_ops = {
256 .probe = lpc_ns8250_probe,
257 .init = lpc_ns8250_init,
258 .term = lpc_ns8250_term,
259 .putc = lpc_ns8250_putc,
260 .rxready = lpc_ns8250_rxready,
261 .getc = lpc_ns8250_getc,
262 };
263
264 static int
lpc_ns8250_probe(struct uart_bas * bas)265 lpc_ns8250_probe(struct uart_bas *bas)
266 {
267 #if 0
268 u_char val;
269
270 /* Check known 0 bits that don't depend on DLAB. */
271 val = uart_getreg(bas, REG_IIR);
272 if (val & 0x30)
273 return (ENXIO);
274 /*
275 * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699
276 * chip, but otherwise doesn't seem to have a function. In
277 * other words, uart(4) works regardless. Ignore that bit so
278 * the probe succeeds.
279 */
280 val = uart_getreg(bas, REG_MCR);
281 if (val & 0xa0)
282 return (ENXIO);
283 #endif
284 return (0);
285 }
286
287 static void
lpc_ns8250_init(struct uart_bas * bas,int baudrate,int databits,int stopbits,int parity)288 lpc_ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
289 int parity)
290 {
291 u_char ier;
292 u_long clkmode;
293
294 /* Enable UART clock */
295 bus_space_map(fdtbus_bs_tag, LPC_CLKPWR_PHYS_BASE, LPC_CLKPWR_SIZE, 0,
296 &bsh_clkpwr);
297 clkmode = lpc_ns8250_get_clkreg(bas, LPC_UART_CLKMODE);
298 lpc_ns8250_set_clkreg(bas, LPC_UART_CLKMODE, clkmode |
299 LPC_UART_CLKMODE_UART5(1));
300
301 #if 0
302 /* Work around H/W bug */
303 uart_setreg(bas, REG_DATA, 0x00);
304 #endif
305 if (bas->rclk == 0)
306 bas->rclk = DEFAULT_RCLK;
307 lpc_ns8250_param(bas, baudrate, databits, stopbits, parity);
308
309 /* Disable all interrupt sources. */
310 /*
311 * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA
312 * UARTs split the receive time-out interrupt bit out separately as
313 * 0x10. This gets handled by ier_mask and ier_rxbits below.
314 */
315 ier = uart_getreg(bas, REG_IER) & 0xe0;
316 uart_setreg(bas, REG_IER, ier);
317 uart_barrier(bas);
318
319 /* Disable the FIFO (if present). */
320 uart_setreg(bas, REG_FCR, 0);
321 uart_barrier(bas);
322
323 /* Set RTS & DTR. */
324 uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR);
325 uart_barrier(bas);
326
327 lpc_ns8250_clrint(bas);
328 }
329
330 static void
lpc_ns8250_term(struct uart_bas * bas)331 lpc_ns8250_term(struct uart_bas *bas)
332 {
333
334 /* Clear RTS & DTR. */
335 uart_setreg(bas, REG_MCR, MCR_IE);
336 uart_barrier(bas);
337 }
338
339 static void
lpc_ns8250_putc(struct uart_bas * bas,int c)340 lpc_ns8250_putc(struct uart_bas *bas, int c)
341 {
342 int limit;
343
344 limit = 250000;
345 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit)
346 DELAY(4);
347 uart_setreg(bas, REG_DATA, c);
348 uart_barrier(bas);
349 limit = 250000;
350 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
351 DELAY(4);
352 }
353
354 static int
lpc_ns8250_rxready(struct uart_bas * bas)355 lpc_ns8250_rxready(struct uart_bas *bas)
356 {
357
358 return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0);
359 }
360
361 static int
lpc_ns8250_getc(struct uart_bas * bas,struct mtx * hwmtx)362 lpc_ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx)
363 {
364 int c;
365
366 uart_lock(hwmtx);
367
368 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) {
369 uart_unlock(hwmtx);
370 DELAY(4);
371 uart_lock(hwmtx);
372 }
373
374 c = uart_getreg(bas, REG_DATA);
375
376 uart_unlock(hwmtx);
377
378 return (c);
379 }
380
381 /*
382 * High-level UART interface.
383 */
384 struct lpc_ns8250_softc {
385 struct uart_softc base;
386 uint8_t fcr;
387 uint8_t ier;
388 uint8_t mcr;
389
390 uint8_t ier_mask;
391 uint8_t ier_rxbits;
392 };
393
394 static int lpc_ns8250_bus_attach(struct uart_softc *);
395 static int lpc_ns8250_bus_detach(struct uart_softc *);
396 static int lpc_ns8250_bus_flush(struct uart_softc *, int);
397 static int lpc_ns8250_bus_getsig(struct uart_softc *);
398 static int lpc_ns8250_bus_ioctl(struct uart_softc *, int, intptr_t);
399 static int lpc_ns8250_bus_ipend(struct uart_softc *);
400 static int lpc_ns8250_bus_param(struct uart_softc *, int, int, int, int);
401 static int lpc_ns8250_bus_probe(struct uart_softc *);
402 static int lpc_ns8250_bus_receive(struct uart_softc *);
403 static int lpc_ns8250_bus_setsig(struct uart_softc *, int);
404 static int lpc_ns8250_bus_transmit(struct uart_softc *);
405 static void lpc_ns8250_bus_grab(struct uart_softc *);
406 static void lpc_ns8250_bus_ungrab(struct uart_softc *);
407
408 static kobj_method_t lpc_ns8250_methods[] = {
409 KOBJMETHOD(uart_attach, lpc_ns8250_bus_attach),
410 KOBJMETHOD(uart_detach, lpc_ns8250_bus_detach),
411 KOBJMETHOD(uart_flush, lpc_ns8250_bus_flush),
412 KOBJMETHOD(uart_getsig, lpc_ns8250_bus_getsig),
413 KOBJMETHOD(uart_ioctl, lpc_ns8250_bus_ioctl),
414 KOBJMETHOD(uart_ipend, lpc_ns8250_bus_ipend),
415 KOBJMETHOD(uart_param, lpc_ns8250_bus_param),
416 KOBJMETHOD(uart_probe, lpc_ns8250_bus_probe),
417 KOBJMETHOD(uart_receive, lpc_ns8250_bus_receive),
418 KOBJMETHOD(uart_setsig, lpc_ns8250_bus_setsig),
419 KOBJMETHOD(uart_transmit, lpc_ns8250_bus_transmit),
420 KOBJMETHOD(uart_grab, lpc_ns8250_bus_grab),
421 KOBJMETHOD(uart_ungrab, lpc_ns8250_bus_ungrab),
422 { 0, 0 }
423 };
424
425 static struct uart_class uart_lpc_class = {
426 "lpc_ns8250",
427 lpc_ns8250_methods,
428 sizeof(struct lpc_ns8250_softc),
429 .uc_ops = &uart_lpc_ns8250_ops,
430 .uc_range = 8,
431 .uc_rclk = DEFAULT_RCLK,
432 .uc_rshift = 0
433 };
434
435 static struct ofw_compat_data compat_data[] = {
436 {"lpc,uart", (uintptr_t)&uart_lpc_class},
437 {NULL, (uintptr_t)NULL},
438 };
439 UART_FDT_CLASS_AND_DEVICE(compat_data);
440
441 #define SIGCHG(c, i, s, d) \
442 if (c) { \
443 i |= (i & s) ? s : s | d; \
444 } else { \
445 i = (i & s) ? (i & ~s) | d : i; \
446 }
447
448 static int
lpc_ns8250_bus_attach(struct uart_softc * sc)449 lpc_ns8250_bus_attach(struct uart_softc *sc)
450 {
451 struct lpc_ns8250_softc *lpc_ns8250 = (struct lpc_ns8250_softc*)sc;
452 struct uart_bas *bas;
453 unsigned int ivar;
454
455 bas = &sc->sc_bas;
456
457 lpc_ns8250->mcr = uart_getreg(bas, REG_MCR);
458 lpc_ns8250->fcr = FCR_ENABLE | FCR_DMA;
459 if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags",
460 &ivar)) {
461 if (UART_FLAGS_FCR_RX_LOW(ivar))
462 lpc_ns8250->fcr |= FCR_RX_LOW;
463 else if (UART_FLAGS_FCR_RX_MEDL(ivar))
464 lpc_ns8250->fcr |= FCR_RX_MEDL;
465 else if (UART_FLAGS_FCR_RX_HIGH(ivar))
466 lpc_ns8250->fcr |= FCR_RX_HIGH;
467 else
468 lpc_ns8250->fcr |= FCR_RX_MEDH;
469 } else
470 lpc_ns8250->fcr |= FCR_RX_HIGH;
471
472 /* Get IER mask */
473 ivar = 0xf0;
474 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask",
475 &ivar);
476 lpc_ns8250->ier_mask = (uint8_t)(ivar & 0xff);
477
478 /* Get IER RX interrupt bits */
479 ivar = IER_EMSC | IER_ERLS | IER_ERXRDY;
480 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits",
481 &ivar);
482 lpc_ns8250->ier_rxbits = (uint8_t)(ivar & 0xff);
483
484 uart_setreg(bas, REG_FCR, lpc_ns8250->fcr);
485 uart_barrier(bas);
486 lpc_ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
487
488 if (lpc_ns8250->mcr & MCR_DTR)
489 sc->sc_hwsig |= SER_DTR;
490 if (lpc_ns8250->mcr & MCR_RTS)
491 sc->sc_hwsig |= SER_RTS;
492 lpc_ns8250_bus_getsig(sc);
493
494 lpc_ns8250_clrint(bas);
495 lpc_ns8250->ier = uart_getreg(bas, REG_IER) & lpc_ns8250->ier_mask;
496 lpc_ns8250->ier |= lpc_ns8250->ier_rxbits;
497 uart_setreg(bas, REG_IER, lpc_ns8250->ier);
498 uart_barrier(bas);
499
500 return (0);
501 }
502
503 static int
lpc_ns8250_bus_detach(struct uart_softc * sc)504 lpc_ns8250_bus_detach(struct uart_softc *sc)
505 {
506 struct lpc_ns8250_softc *lpc_ns8250;
507 struct uart_bas *bas;
508 u_char ier;
509
510 lpc_ns8250 = (struct lpc_ns8250_softc *)sc;
511 bas = &sc->sc_bas;
512 ier = uart_getreg(bas, REG_IER) & lpc_ns8250->ier_mask;
513 uart_setreg(bas, REG_IER, ier);
514 uart_barrier(bas);
515 lpc_ns8250_clrint(bas);
516 return (0);
517 }
518
519 static int
lpc_ns8250_bus_flush(struct uart_softc * sc,int what)520 lpc_ns8250_bus_flush(struct uart_softc *sc, int what)
521 {
522 struct lpc_ns8250_softc *lpc_ns8250 = (struct lpc_ns8250_softc*)sc;
523 struct uart_bas *bas;
524 int error;
525
526 bas = &sc->sc_bas;
527 uart_lock(sc->sc_hwmtx);
528 if (sc->sc_rxfifosz > 1) {
529 lpc_ns8250_flush(bas, what);
530 uart_setreg(bas, REG_FCR, lpc_ns8250->fcr);
531 uart_barrier(bas);
532 error = 0;
533 } else
534 error = lpc_ns8250_drain(bas, what);
535 uart_unlock(sc->sc_hwmtx);
536 return (error);
537 }
538
539 static int
lpc_ns8250_bus_getsig(struct uart_softc * sc)540 lpc_ns8250_bus_getsig(struct uart_softc *sc)
541 {
542 uint32_t new, old, sig;
543 uint8_t msr;
544
545 do {
546 old = sc->sc_hwsig;
547 sig = old;
548 uart_lock(sc->sc_hwmtx);
549 msr = uart_getreg(&sc->sc_bas, REG_MSR);
550 uart_unlock(sc->sc_hwmtx);
551 SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR);
552 SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS);
553 SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD);
554 SIGCHG(msr & MSR_RI, sig, SER_RI, SER_DRI);
555 new = sig & ~SER_MASK_DELTA;
556 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
557 return (sig);
558 }
559
560 static int
lpc_ns8250_bus_ioctl(struct uart_softc * sc,int request,intptr_t data)561 lpc_ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
562 {
563 struct uart_bas *bas;
564 int baudrate, divisor, error;
565 uint8_t efr, lcr;
566
567 bas = &sc->sc_bas;
568 error = 0;
569 uart_lock(sc->sc_hwmtx);
570 switch (request) {
571 case UART_IOCTL_BREAK:
572 lcr = uart_getreg(bas, REG_LCR);
573 if (data)
574 lcr |= LCR_SBREAK;
575 else
576 lcr &= ~LCR_SBREAK;
577 uart_setreg(bas, REG_LCR, lcr);
578 uart_barrier(bas);
579 break;
580 case UART_IOCTL_IFLOW:
581 lcr = uart_getreg(bas, REG_LCR);
582 uart_barrier(bas);
583 uart_setreg(bas, REG_LCR, 0xbf);
584 uart_barrier(bas);
585 efr = uart_getreg(bas, REG_EFR);
586 if (data)
587 efr |= EFR_RTS;
588 else
589 efr &= ~EFR_RTS;
590 uart_setreg(bas, REG_EFR, efr);
591 uart_barrier(bas);
592 uart_setreg(bas, REG_LCR, lcr);
593 uart_barrier(bas);
594 break;
595 case UART_IOCTL_OFLOW:
596 lcr = uart_getreg(bas, REG_LCR);
597 uart_barrier(bas);
598 uart_setreg(bas, REG_LCR, 0xbf);
599 uart_barrier(bas);
600 efr = uart_getreg(bas, REG_EFR);
601 if (data)
602 efr |= EFR_CTS;
603 else
604 efr &= ~EFR_CTS;
605 uart_setreg(bas, REG_EFR, efr);
606 uart_barrier(bas);
607 uart_setreg(bas, REG_LCR, lcr);
608 uart_barrier(bas);
609 break;
610 case UART_IOCTL_BAUD:
611 lcr = uart_getreg(bas, REG_LCR);
612 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
613 uart_barrier(bas);
614 divisor = uart_getreg(bas, REG_DLL) |
615 (uart_getreg(bas, REG_DLH) << 8);
616 uart_barrier(bas);
617 uart_setreg(bas, REG_LCR, lcr);
618 uart_barrier(bas);
619 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0;
620 if (baudrate > 0)
621 *(int*)data = baudrate;
622 else
623 error = ENXIO;
624 break;
625 default:
626 error = EINVAL;
627 break;
628 }
629 uart_unlock(sc->sc_hwmtx);
630 return (error);
631 }
632
633 static int
lpc_ns8250_bus_ipend(struct uart_softc * sc)634 lpc_ns8250_bus_ipend(struct uart_softc *sc)
635 {
636 struct uart_bas *bas;
637 struct lpc_ns8250_softc *lpc_ns8250;
638 int ipend;
639 uint8_t iir, lsr;
640
641 lpc_ns8250 = (struct lpc_ns8250_softc *)sc;
642 bas = &sc->sc_bas;
643 uart_lock(sc->sc_hwmtx);
644 iir = uart_getreg(bas, REG_IIR);
645 if (iir & IIR_NOPEND) {
646 uart_unlock(sc->sc_hwmtx);
647 return (0);
648 }
649 ipend = 0;
650 if (iir & IIR_RXRDY) {
651 lsr = uart_getreg(bas, REG_LSR);
652 if (lsr & LSR_OE)
653 ipend |= SER_INT_OVERRUN;
654 if (lsr & LSR_BI)
655 ipend |= SER_INT_BREAK;
656 if (lsr & LSR_RXRDY)
657 ipend |= SER_INT_RXREADY;
658 } else {
659 if (iir & IIR_TXRDY) {
660 ipend |= SER_INT_TXIDLE;
661 uart_setreg(bas, REG_IER, lpc_ns8250->ier);
662 } else
663 ipend |= SER_INT_SIGCHG;
664 }
665 if (ipend == 0)
666 lpc_ns8250_clrint(bas);
667 uart_unlock(sc->sc_hwmtx);
668 return (ipend);
669 }
670
671 static int
lpc_ns8250_bus_param(struct uart_softc * sc,int baudrate,int databits,int stopbits,int parity)672 lpc_ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits,
673 int stopbits, int parity)
674 {
675 struct uart_bas *bas;
676 int error;
677
678 bas = &sc->sc_bas;
679 uart_lock(sc->sc_hwmtx);
680 error = lpc_ns8250_param(bas, baudrate, databits, stopbits, parity);
681 uart_unlock(sc->sc_hwmtx);
682 return (error);
683 }
684
685 static int
lpc_ns8250_bus_probe(struct uart_softc * sc)686 lpc_ns8250_bus_probe(struct uart_softc *sc)
687 {
688 struct lpc_ns8250_softc *lpc_ns8250;
689 struct uart_bas *bas;
690 int count, delay, error, limit;
691 uint8_t lsr, mcr, ier;
692
693 lpc_ns8250 = (struct lpc_ns8250_softc *)sc;
694 bas = &sc->sc_bas;
695
696 error = lpc_ns8250_probe(bas);
697 if (error)
698 return (error);
699
700 mcr = MCR_IE;
701 if (sc->sc_sysdev == NULL) {
702 /* By using lpc_ns8250_init() we also set DTR and RTS. */
703 lpc_ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE);
704 } else
705 mcr |= MCR_DTR | MCR_RTS;
706
707 error = lpc_ns8250_drain(bas, UART_DRAIN_TRANSMITTER);
708 if (error)
709 return (error);
710
711 /*
712 * Set loopback mode. This avoids having garbage on the wire and
713 * also allows us send and receive data. We set DTR and RTS to
714 * avoid the possibility that automatic flow-control prevents
715 * any data from being sent.
716 */
717 uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS);
718 uart_barrier(bas);
719
720 /*
721 * Enable FIFOs. And check that the UART has them. If not, we're
722 * done. Since this is the first time we enable the FIFOs, we reset
723 * them.
724 */
725 uart_setreg(bas, REG_FCR, FCR_ENABLE);
726 uart_barrier(bas);
727 if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) {
728 /*
729 * NS16450 or INS8250. We don't bother to differentiate
730 * between them. They're too old to be interesting.
731 */
732 uart_setreg(bas, REG_MCR, mcr);
733 uart_barrier(bas);
734 sc->sc_rxfifosz = sc->sc_txfifosz = 1;
735 device_set_desc(sc->sc_dev, "8250 or 16450 or compatible");
736 return (0);
737 }
738
739 uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST);
740 uart_barrier(bas);
741
742 count = 0;
743 delay = lpc_ns8250_delay(bas);
744
745 /* We have FIFOs. Drain the transmitter and receiver. */
746 error = lpc_ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER);
747 if (error) {
748 uart_setreg(bas, REG_MCR, mcr);
749 uart_setreg(bas, REG_FCR, 0);
750 uart_barrier(bas);
751 goto done;
752 }
753
754 /*
755 * We should have a sufficiently clean "pipe" to determine the
756 * size of the FIFOs. We send as much characters as is reasonable
757 * and wait for the overflow bit in the LSR register to be
758 * asserted, counting the characters as we send them. Based on
759 * that count we know the FIFO size.
760 */
761 do {
762 uart_setreg(bas, REG_DATA, 0);
763 uart_barrier(bas);
764 count++;
765
766 limit = 30;
767 lsr = 0;
768 /*
769 * LSR bits are cleared upon read, so we must accumulate
770 * them to be able to test LSR_OE below.
771 */
772 while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 &&
773 --limit)
774 DELAY(delay);
775 if (limit == 0) {
776 ier = uart_getreg(bas, REG_IER) & lpc_ns8250->ier_mask;
777 uart_setreg(bas, REG_IER, ier);
778 uart_setreg(bas, REG_MCR, mcr);
779 uart_setreg(bas, REG_FCR, 0);
780 uart_barrier(bas);
781 count = 0;
782 goto done;
783 }
784 } while ((lsr & LSR_OE) == 0 && count < 130);
785 count--;
786
787 uart_setreg(bas, REG_MCR, mcr);
788
789 /* Reset FIFOs. */
790 lpc_ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
791
792 done:
793 sc->sc_rxfifosz = 64;
794 device_set_desc(sc->sc_dev, "LPC32x0 UART with FIFOs");
795
796 /*
797 * Force the Tx FIFO size to 16 bytes for now. We don't program the
798 * Tx trigger. Also, we assume that all data has been sent when the
799 * interrupt happens.
800 */
801 sc->sc_txfifosz = 16;
802
803 #if 0
804 /*
805 * XXX there are some issues related to hardware flow control and
806 * it's likely that uart(4) is the cause. This basicly needs more
807 * investigation, but we avoid using for hardware flow control
808 * until then.
809 */
810 /* 16650s or higher have automatic flow control. */
811 if (sc->sc_rxfifosz > 16) {
812 sc->sc_hwiflow = 1;
813 sc->sc_hwoflow = 1;
814 }
815 #endif
816 return (0);
817 }
818
819 static int
lpc_ns8250_bus_receive(struct uart_softc * sc)820 lpc_ns8250_bus_receive(struct uart_softc *sc)
821 {
822 struct uart_bas *bas;
823 int xc;
824 uint8_t lsr;
825
826 bas = &sc->sc_bas;
827 uart_lock(sc->sc_hwmtx);
828 lsr = uart_getreg(bas, REG_LSR);
829 while (lsr & LSR_RXRDY) {
830 if (uart_rx_full(sc)) {
831 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
832 break;
833 }
834 xc = uart_getreg(bas, REG_DATA);
835 if (lsr & LSR_FE)
836 xc |= UART_STAT_FRAMERR;
837 if (lsr & LSR_PE)
838 xc |= UART_STAT_PARERR;
839 uart_rx_put(sc, xc);
840 lsr = uart_getreg(bas, REG_LSR);
841 }
842 /* Discard everything left in the Rx FIFO. */
843 while (lsr & LSR_RXRDY) {
844 (void)uart_getreg(bas, REG_DATA);
845 uart_barrier(bas);
846 lsr = uart_getreg(bas, REG_LSR);
847 }
848 uart_unlock(sc->sc_hwmtx);
849 return (0);
850 }
851
852 static int
lpc_ns8250_bus_setsig(struct uart_softc * sc,int sig)853 lpc_ns8250_bus_setsig(struct uart_softc *sc, int sig)
854 {
855 struct lpc_ns8250_softc *lpc_ns8250 = (struct lpc_ns8250_softc*)sc;
856 struct uart_bas *bas;
857 uint32_t new, old;
858
859 bas = &sc->sc_bas;
860 do {
861 old = sc->sc_hwsig;
862 new = old;
863 if (sig & SER_DDTR) {
864 SIGCHG(sig & SER_DTR, new, SER_DTR,
865 SER_DDTR);
866 }
867 if (sig & SER_DRTS) {
868 SIGCHG(sig & SER_RTS, new, SER_RTS,
869 SER_DRTS);
870 }
871 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
872 uart_lock(sc->sc_hwmtx);
873 lpc_ns8250->mcr &= ~(MCR_DTR|MCR_RTS);
874 if (new & SER_DTR)
875 lpc_ns8250->mcr |= MCR_DTR;
876 if (new & SER_RTS)
877 lpc_ns8250->mcr |= MCR_RTS;
878 uart_setreg(bas, REG_MCR, lpc_ns8250->mcr);
879 uart_barrier(bas);
880 uart_unlock(sc->sc_hwmtx);
881 return (0);
882 }
883
884 static int
lpc_ns8250_bus_transmit(struct uart_softc * sc)885 lpc_ns8250_bus_transmit(struct uart_softc *sc)
886 {
887 struct lpc_ns8250_softc *lpc_ns8250 = (struct lpc_ns8250_softc*)sc;
888 struct uart_bas *bas;
889 int i;
890
891 bas = &sc->sc_bas;
892 uart_lock(sc->sc_hwmtx);
893 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0)
894 ;
895 uart_setreg(bas, REG_IER, lpc_ns8250->ier | IER_ETXRDY);
896 uart_barrier(bas);
897 for (i = 0; i < sc->sc_txdatasz; i++) {
898 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]);
899 uart_barrier(bas);
900 }
901 sc->sc_txbusy = 1;
902 uart_unlock(sc->sc_hwmtx);
903 return (0);
904 }
905
906 void
lpc_ns8250_bus_grab(struct uart_softc * sc)907 lpc_ns8250_bus_grab(struct uart_softc *sc)
908 {
909 struct uart_bas *bas = &sc->sc_bas;
910
911 /*
912 * turn off all interrupts to enter polling mode. Leave the
913 * saved mask alone. We'll restore whatever it was in ungrab.
914 * All pending interupt signals are reset when IER is set to 0.
915 */
916 uart_lock(sc->sc_hwmtx);
917 uart_setreg(bas, REG_IER, 0);
918 uart_barrier(bas);
919 uart_unlock(sc->sc_hwmtx);
920 }
921
922 void
lpc_ns8250_bus_ungrab(struct uart_softc * sc)923 lpc_ns8250_bus_ungrab(struct uart_softc *sc)
924 {
925 struct lpc_ns8250_softc *lpc_ns8250 = (struct lpc_ns8250_softc*)sc;
926 struct uart_bas *bas = &sc->sc_bas;
927
928 /*
929 * Restore previous interrupt mask
930 */
931 uart_lock(sc->sc_hwmtx);
932 uart_setreg(bas, REG_IER, lpc_ns8250->ier);
933 uart_barrier(bas);
934 uart_unlock(sc->sc_hwmtx);
935 }
936