1 /*-
2 * Copyright (c) 2009, Oleksandr Tymoshenko <gonzo@FreeBSD.org>
3 * Copyright (c) 2011, Luiz Otavio O Souza.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice unmodified, this list of conditions, and the following
11 * disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
31
32 #include "opt_ar71xx.h"
33
34 #include <sys/param.h>
35 #include <sys/systm.h>
36
37 #include <sys/bus.h>
38 #include <sys/interrupt.h>
39 #include <sys/malloc.h>
40 #include <sys/kernel.h>
41 #include <sys/module.h>
42 #include <sys/rman.h>
43
44 #include <vm/vm.h>
45 #include <vm/pmap.h>
46 #include <vm/vm_extern.h>
47
48 #include <machine/bus.h>
49 #include <machine/cpu.h>
50 #include <machine/intr_machdep.h>
51 #include <machine/pmap.h>
52
53 #include <dev/pci/pcivar.h>
54 #include <dev/pci/pcireg.h>
55
56 #include <dev/pci/pcib_private.h>
57 #include "pcib_if.h"
58
59 #include <mips/atheros/ar71xxreg.h>
60 #include <mips/atheros/ar724xreg.h>
61 #include <mips/atheros/ar71xx_setup.h>
62 #include <mips/atheros/ar71xx_pci_bus_space.h>
63
64 #include <mips/atheros/ar71xx_cpudef.h>
65
66 #ifdef AR71XX_ATH_EEPROM
67 #include <mips/atheros/ar71xx_fixup.h>
68 #endif /* AR71XX_ATH_EEPROM */
69
70 #undef AR724X_PCI_DEBUG
71 #ifdef AR724X_PCI_DEBUG
72 #define dprintf printf
73 #else
74 #define dprintf(x, arg...)
75 #endif
76
77 struct ar71xx_pci_softc {
78 device_t sc_dev;
79
80 int sc_busno;
81 struct rman sc_mem_rman;
82 struct rman sc_irq_rman;
83
84 struct intr_event *sc_eventstab[AR71XX_PCI_NIRQS];
85 mips_intrcnt_t sc_intr_counter[AR71XX_PCI_NIRQS];
86 struct resource *sc_irq;
87 void *sc_ih;
88 };
89
90 static int ar724x_pci_setup_intr(device_t, device_t, struct resource *, int,
91 driver_filter_t *, driver_intr_t *, void *, void **);
92 static int ar724x_pci_teardown_intr(device_t, device_t, struct resource *,
93 void *);
94 static int ar724x_pci_intr(void *);
95
96 static void
ar724x_pci_write(uint32_t reg,uint32_t offset,uint32_t data,int bytes)97 ar724x_pci_write(uint32_t reg, uint32_t offset, uint32_t data, int bytes)
98 {
99 uint32_t val, mask, shift;
100
101 /* Register access is 32-bit aligned */
102 shift = (offset & 3) * 8;
103 if (bytes % 4)
104 mask = (1 << (bytes * 8)) - 1;
105 else
106 mask = 0xffffffff;
107
108 val = ATH_READ_REG(reg + (offset & ~3));
109 val &= ~(mask << shift);
110 val |= ((data & mask) << shift);
111 ATH_WRITE_REG(reg + (offset & ~3), val);
112
113 dprintf("%s: %#x/%#x addr=%#x, data=%#x(%#x), bytes=%d\n", __func__,
114 reg, reg + (offset & ~3), offset, data, val, bytes);
115 }
116
117 static uint32_t
ar724x_pci_read_config(device_t dev,u_int bus,u_int slot,u_int func,u_int reg,int bytes)118 ar724x_pci_read_config(device_t dev, u_int bus, u_int slot, u_int func,
119 u_int reg, int bytes)
120 {
121 uint32_t data, shift, mask;
122
123 /* Register access is 32-bit aligned */
124 shift = (reg & 3) * 8;
125
126 /* Create a mask based on the width, post-shift */
127 if (bytes == 2)
128 mask = 0xffff;
129 else if (bytes == 1)
130 mask = 0xff;
131 else
132 mask = 0xffffffff;
133
134 dprintf("%s: tag (%x, %x, %x) reg %d(%d)\n", __func__, bus, slot,
135 func, reg, bytes);
136
137 if ((bus == 0) && (slot == 0) && (func == 0))
138 data = ATH_READ_REG(AR724X_PCI_CFG_BASE + (reg & ~3));
139 else
140 data = -1;
141
142 /* Get request bytes from 32-bit word */
143 data = (data >> shift) & mask;
144
145 dprintf("%s: read 0x%x\n", __func__, data);
146
147 return (data);
148 }
149
150 static void
ar724x_pci_write_config(device_t dev,u_int bus,u_int slot,u_int func,u_int reg,uint32_t data,int bytes)151 ar724x_pci_write_config(device_t dev, u_int bus, u_int slot, u_int func,
152 u_int reg, uint32_t data, int bytes)
153 {
154
155 dprintf("%s: tag (%x, %x, %x) reg %d(%d): %x\n", __func__, bus, slot,
156 func, reg, bytes, data);
157
158 if ((bus != 0) || (slot != 0) || (func != 0))
159 return;
160
161 /*
162 * WAR for BAR issue on AR7240 - We are unable to access the PCI
163 * device space if we set the BAR with proper base address.
164 *
165 * However, we _do_ want to allow programming in the probe value
166 * (0xffffffff) so the PCI code can find out how big the memory
167 * map is for this device. Without it, it'll think the memory
168 * map is 32 bits wide, the PCI code will then end up thinking
169 * the register window is '0' and fail to allocate resources.
170 */
171 if (reg == PCIR_BAR(0) && bytes == 4
172 && ar71xx_soc == AR71XX_SOC_AR7240
173 && data != 0xffffffff)
174 ar724x_pci_write(AR724X_PCI_CFG_BASE, reg, 0xffff, bytes);
175 else
176 ar724x_pci_write(AR724X_PCI_CFG_BASE, reg, data, bytes);
177 }
178
179 static void
ar724x_pci_mask_irq(void * source)180 ar724x_pci_mask_irq(void *source)
181 {
182 uint32_t reg;
183 unsigned int irq = (unsigned int)source;
184
185 /* XXX - Only one interrupt ? Only one device ? */
186 if (irq != AR71XX_PCI_IRQ_START)
187 return;
188
189 /* Update the interrupt mask reg */
190 reg = ATH_READ_REG(AR724X_PCI_INTR_MASK);
191 ATH_WRITE_REG(AR724X_PCI_INTR_MASK,
192 reg & ~AR724X_PCI_INTR_DEV0);
193
194 /* Clear any pending interrupt */
195 reg = ATH_READ_REG(AR724X_PCI_INTR_STATUS);
196 ATH_WRITE_REG(AR724X_PCI_INTR_STATUS,
197 reg | AR724X_PCI_INTR_DEV0);
198 }
199
200 static void
ar724x_pci_unmask_irq(void * source)201 ar724x_pci_unmask_irq(void *source)
202 {
203 uint32_t reg;
204 unsigned int irq = (unsigned int)source;
205
206 /* XXX */
207 if (irq != AR71XX_PCI_IRQ_START)
208 return;
209
210 /* Update the interrupt mask reg */
211 reg = ATH_READ_REG(AR724X_PCI_INTR_MASK);
212 ATH_WRITE_REG(AR724X_PCI_INTR_MASK,
213 reg | AR724X_PCI_INTR_DEV0);
214 }
215
216 static int
ar724x_pci_setup(device_t dev)217 ar724x_pci_setup(device_t dev)
218 {
219 uint32_t reg;
220
221 /* setup COMMAND register */
222 reg = PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN | PCIM_CMD_SERRESPEN |
223 PCIM_CMD_BACKTOBACK | PCIM_CMD_PERRESPEN | PCIM_CMD_MWRICEN;
224
225 ar724x_pci_write(AR724X_PCI_CRP_BASE, PCIR_COMMAND, reg, 2);
226 ar724x_pci_write(AR724X_PCI_CRP_BASE, 0x20, 0x1ff01000, 4);
227 ar724x_pci_write(AR724X_PCI_CRP_BASE, 0x24, 0x1ff01000, 4);
228
229 reg = ATH_READ_REG(AR724X_PCI_RESET);
230 if (reg != 0x7) {
231 DELAY(100000);
232 ATH_WRITE_REG(AR724X_PCI_RESET, 0);
233 DELAY(100);
234 ATH_WRITE_REG(AR724X_PCI_RESET, 4);
235 DELAY(100000);
236 }
237
238 if (ar71xx_soc == AR71XX_SOC_AR7240)
239 reg = AR724X_PCI_APP_LTSSM_ENABLE;
240 else
241 reg = 0x1ffc1;
242 ATH_WRITE_REG(AR724X_PCI_APP, reg);
243 /* Flush write */
244 (void) ATH_READ_REG(AR724X_PCI_APP);
245
246 DELAY(1000);
247
248 reg = ATH_READ_REG(AR724X_PCI_RESET);
249 if ((reg & AR724X_PCI_RESET_LINK_UP) == 0) {
250 device_printf(dev, "no PCIe controller found\n");
251 return (ENXIO);
252 }
253
254 if (ar71xx_soc == AR71XX_SOC_AR7241 ||
255 ar71xx_soc == AR71XX_SOC_AR7242) {
256 reg = ATH_READ_REG(AR724X_PCI_APP);
257 reg |= (1 << 16);
258 ATH_WRITE_REG(AR724X_PCI_APP, reg);
259 }
260
261 return (0);
262 }
263
264 #ifdef AR71XX_ATH_EEPROM
265 #define AR5416_EEPROM_MAGIC 0xa55a
266
267 /*
268 * XXX - This should not be here ! And this looks like Atheros (if_ath) only.
269 */
270 static void
ar724x_pci_fixup(device_t dev,long flash_addr,int len)271 ar724x_pci_fixup(device_t dev, long flash_addr, int len)
272 {
273 uint32_t bar0, reg, val;
274 uint16_t *cal_data = (uint16_t *) MIPS_PHYS_TO_KSEG1(flash_addr);
275
276 #if 0
277 if (cal_data[0] != AR5416_EEPROM_MAGIC) {
278 device_printf(dev, "%s: Invalid calibration data from 0x%x\n",
279 __func__, (uintptr_t) flash_addr);
280 return;
281 }
282 #endif
283
284 /* Save bar(0) address - just to flush bar(0) (SoC WAR) ? */
285 bar0 = ar724x_pci_read_config(dev, 0, 0, 0, PCIR_BAR(0), 4);
286
287 /* Write temporary BAR0 to map the NIC into a fixed location */
288 ar724x_pci_write_config(dev, 0, 0, 0, PCIR_BAR(0),
289 AR71XX_PCI_MEM_BASE, 4);
290
291 val = ar724x_pci_read_config(dev, 0, 0, 0, PCIR_COMMAND, 2);
292 val |= (PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN);
293 ar724x_pci_write_config(dev, 0, 0, 0, PCIR_COMMAND, val, 2);
294
295 /* set pointer to first reg address */
296 cal_data += 3;
297 while (*cal_data != 0xffff) {
298 reg = *cal_data++;
299 val = *cal_data++;
300 val |= (*cal_data++) << 16;
301
302 if (bootverbose)
303 printf(" 0x%08x=0x%04x\n", reg, val);
304
305 /* Write eeprom fixup data to device memory */
306 ATH_WRITE_REG(AR71XX_PCI_MEM_BASE + reg, val);
307 DELAY(100);
308 }
309
310 val = ar724x_pci_read_config(dev, 0, 0, 0, PCIR_COMMAND, 2);
311 val &= ~(PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN);
312 ar724x_pci_write_config(dev, 0, 0, 0, PCIR_COMMAND, val, 2);
313
314 /* Write the saved bar(0) address */
315 ar724x_pci_write_config(dev, 0, 0, 0, PCIR_BAR(0), bar0, 4);
316 }
317 #undef AR5416_EEPROM_MAGIC
318
319 /*
320 * XXX This is (mostly) duplicated with ar71xx_pci.c.
321 * It should at some point be fixed.
322 */
323 static void
ar724x_pci_slot_fixup(device_t dev)324 ar724x_pci_slot_fixup(device_t dev)
325 {
326 long int flash_addr;
327 char buf[64];
328 int size;
329
330 /*
331 * Check whether the given slot has a hint to poke.
332 */
333 if (bootverbose)
334 device_printf(dev, "%s: checking dev %s, %d/%d/%d\n",
335 __func__, device_get_nameunit(dev), 0, 0, 0);
336
337 snprintf(buf, sizeof(buf), "bus.%d.%d.%d.ath_fixup_addr",
338 0, 0, 0);
339
340 if (resource_long_value(device_get_name(dev), device_get_unit(dev),
341 buf, &flash_addr) == 0) {
342 snprintf(buf, sizeof(buf), "bus.%d.%d.%d.ath_fixup_size",
343 0, 0, 0);
344 if (resource_int_value(device_get_name(dev),
345 device_get_unit(dev), buf, &size) != 0) {
346 device_printf(dev,
347 "%s: missing hint '%s', aborting EEPROM\n",
348 __func__, buf);
349 return;
350 }
351
352 device_printf(dev, "found EEPROM at 0x%lx on %d.%d.%d\n",
353 flash_addr, 0, 0, 0);
354 ar724x_pci_fixup(dev, flash_addr, size);
355 ar71xx_pci_slot_create_eeprom_firmware(dev, 0, 0, 0,
356 flash_addr, size);
357 }
358 }
359 #endif /* AR71XX_ATH_EEPROM */
360
361 static int
ar724x_pci_probe(device_t dev)362 ar724x_pci_probe(device_t dev)
363 {
364
365 return (BUS_PROBE_NOWILDCARD);
366 }
367
368 static int
ar724x_pci_attach(device_t dev)369 ar724x_pci_attach(device_t dev)
370 {
371 struct ar71xx_pci_softc *sc = device_get_softc(dev);
372 int rid = 0;
373
374 sc->sc_mem_rman.rm_type = RMAN_ARRAY;
375 sc->sc_mem_rman.rm_descr = "ar724x PCI memory window";
376 if (rman_init(&sc->sc_mem_rman) != 0 ||
377 rman_manage_region(&sc->sc_mem_rman, AR71XX_PCI_MEM_BASE,
378 AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1) != 0) {
379 panic("ar724x_pci_attach: failed to set up I/O rman");
380 }
381
382 sc->sc_irq_rman.rm_type = RMAN_ARRAY;
383 sc->sc_irq_rman.rm_descr = "ar724x PCI IRQs";
384 if (rman_init(&sc->sc_irq_rman) != 0 ||
385 rman_manage_region(&sc->sc_irq_rman, AR71XX_PCI_IRQ_START,
386 AR71XX_PCI_IRQ_END) != 0)
387 panic("ar724x_pci_attach: failed to set up IRQ rman");
388
389 /* Disable interrupts */
390 ATH_WRITE_REG(AR724X_PCI_INTR_STATUS, 0);
391 ATH_WRITE_REG(AR724X_PCI_INTR_MASK, 0);
392
393 /* Hook up our interrupt handler. */
394 if ((sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
395 RF_SHAREABLE | RF_ACTIVE)) == NULL) {
396 device_printf(dev, "unable to allocate IRQ resource\n");
397 return (ENXIO);
398 }
399
400 if ((bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_MISC,
401 ar724x_pci_intr, NULL, sc, &sc->sc_ih))) {
402 device_printf(dev,
403 "WARNING: unable to register interrupt handler\n");
404 return (ENXIO);
405 }
406
407 /* Reset PCIe core and PCIe PHY */
408 ar71xx_device_stop(AR724X_RESET_PCIE);
409 ar71xx_device_stop(AR724X_RESET_PCIE_PHY);
410 ar71xx_device_stop(AR724X_RESET_PCIE_PHY_SERIAL);
411 DELAY(100);
412
413 ar71xx_device_start(AR724X_RESET_PCIE_PHY_SERIAL);
414 DELAY(100);
415 ar71xx_device_start(AR724X_RESET_PCIE_PHY);
416 ar71xx_device_start(AR724X_RESET_PCIE);
417
418 if (ar724x_pci_setup(dev))
419 return (ENXIO);
420
421 #ifdef AR71XX_ATH_EEPROM
422 ar724x_pci_slot_fixup(dev);
423 #endif /* AR71XX_ATH_EEPROM */
424
425 /* Fixup internal PCI bridge */
426 ar724x_pci_write_config(dev, 0, 0, 0, PCIR_COMMAND,
427 PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN
428 | PCIM_CMD_SERRESPEN | PCIM_CMD_BACKTOBACK
429 | PCIM_CMD_PERRESPEN | PCIM_CMD_MWRICEN, 2);
430
431 device_add_child(dev, "pci", -1);
432 return (bus_generic_attach(dev));
433 }
434
435 static int
ar724x_pci_read_ivar(device_t dev,device_t child,int which,uintptr_t * result)436 ar724x_pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
437 {
438 struct ar71xx_pci_softc *sc = device_get_softc(dev);
439
440 switch (which) {
441 case PCIB_IVAR_DOMAIN:
442 *result = 0;
443 return (0);
444 case PCIB_IVAR_BUS:
445 *result = sc->sc_busno;
446 return (0);
447 }
448
449 return (ENOENT);
450 }
451
452 static int
ar724x_pci_write_ivar(device_t dev,device_t child,int which,uintptr_t result)453 ar724x_pci_write_ivar(device_t dev, device_t child, int which, uintptr_t result)
454 {
455 struct ar71xx_pci_softc * sc = device_get_softc(dev);
456
457 switch (which) {
458 case PCIB_IVAR_BUS:
459 sc->sc_busno = result;
460 return (0);
461 }
462
463 return (ENOENT);
464 }
465
466 static struct resource *
ar724x_pci_alloc_resource(device_t bus,device_t child,int type,int * rid,u_long start,u_long end,u_long count,u_int flags)467 ar724x_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
468 u_long start, u_long end, u_long count, u_int flags)
469 {
470 struct ar71xx_pci_softc *sc = device_get_softc(bus);
471 struct resource *rv;
472 struct rman *rm;
473
474 switch (type) {
475 case SYS_RES_IRQ:
476 rm = &sc->sc_irq_rman;
477 break;
478 case SYS_RES_MEMORY:
479 rm = &sc->sc_mem_rman;
480 break;
481 default:
482 return (NULL);
483 }
484
485 rv = rman_reserve_resource(rm, start, end, count, flags, child);
486
487 if (rv == NULL)
488 return (NULL);
489
490 rman_set_rid(rv, *rid);
491
492 if (flags & RF_ACTIVE) {
493 if (bus_activate_resource(child, type, *rid, rv)) {
494 rman_release_resource(rv);
495 return (NULL);
496 }
497 }
498
499 return (rv);
500 }
501
502 static int
ar724x_pci_activate_resource(device_t bus,device_t child,int type,int rid,struct resource * r)503 ar724x_pci_activate_resource(device_t bus, device_t child, int type, int rid,
504 struct resource *r)
505 {
506 int res = (BUS_ACTIVATE_RESOURCE(device_get_parent(bus),
507 child, type, rid, r));
508
509 if (!res) {
510 switch(type) {
511 case SYS_RES_MEMORY:
512 case SYS_RES_IOPORT:
513
514 rman_set_bustag(r, ar71xx_bus_space_pcimem);
515 break;
516 }
517 }
518
519 return (res);
520 }
521
522 static int
ar724x_pci_setup_intr(device_t bus,device_t child,struct resource * ires,int flags,driver_filter_t * filt,driver_intr_t * handler,void * arg,void ** cookiep)523 ar724x_pci_setup_intr(device_t bus, device_t child, struct resource *ires,
524 int flags, driver_filter_t *filt, driver_intr_t *handler,
525 void *arg, void **cookiep)
526 {
527 struct ar71xx_pci_softc *sc = device_get_softc(bus);
528 struct intr_event *event;
529 int irq, error;
530
531 irq = rman_get_start(ires);
532 if (irq > AR71XX_PCI_IRQ_END)
533 panic("%s: bad irq %d", __func__, irq);
534
535 event = sc->sc_eventstab[irq];
536 if (event == NULL) {
537 error = intr_event_create(&event, (void *)irq, 0, irq,
538 ar724x_pci_mask_irq, ar724x_pci_unmask_irq, NULL, NULL,
539 "pci intr%d:", irq);
540
541 if (error == 0) {
542 sc->sc_eventstab[irq] = event;
543 sc->sc_intr_counter[irq] =
544 mips_intrcnt_create(event->ie_name);
545 }
546 else
547 return error;
548 }
549
550 intr_event_add_handler(event, device_get_nameunit(child), filt,
551 handler, arg, intr_priority(flags), flags, cookiep);
552 mips_intrcnt_setname(sc->sc_intr_counter[irq], event->ie_fullname);
553
554 ar724x_pci_unmask_irq((void*)irq);
555
556 return (0);
557 }
558
559 static int
ar724x_pci_teardown_intr(device_t dev,device_t child,struct resource * ires,void * cookie)560 ar724x_pci_teardown_intr(device_t dev, device_t child, struct resource *ires,
561 void *cookie)
562 {
563 struct ar71xx_pci_softc *sc = device_get_softc(dev);
564 int irq, result;
565
566 irq = rman_get_start(ires);
567 if (irq > AR71XX_PCI_IRQ_END)
568 panic("%s: bad irq %d", __func__, irq);
569
570 if (sc->sc_eventstab[irq] == NULL)
571 panic("Trying to teardown unoccupied IRQ");
572
573 ar724x_pci_mask_irq((void*)irq);
574
575 result = intr_event_remove_handler(cookie);
576 if (!result)
577 sc->sc_eventstab[irq] = NULL;
578
579 return (result);
580 }
581
582 static int
ar724x_pci_intr(void * arg)583 ar724x_pci_intr(void *arg)
584 {
585 struct ar71xx_pci_softc *sc = arg;
586 struct intr_event *event;
587 uint32_t reg, irq, mask;
588
589
590 reg = ATH_READ_REG(AR724X_PCI_INTR_STATUS);
591 mask = ATH_READ_REG(AR724X_PCI_INTR_MASK);
592 /*
593 * Handle only unmasked interrupts
594 */
595 reg &= mask;
596 if (reg & AR724X_PCI_INTR_DEV0) {
597
598 irq = AR71XX_PCI_IRQ_START;
599 event = sc->sc_eventstab[irq];
600 if (!event || TAILQ_EMPTY(&event->ie_handlers)) {
601 printf("Stray IRQ %d\n", irq);
602 return (FILTER_STRAY);
603 }
604
605 /* Flush pending memory transactions */
606 ar71xx_device_flush_ddr(AR71XX_CPU_DDR_FLUSH_PCIE);
607
608 /* TODO: frame instead of NULL? */
609 intr_event_handle(event, NULL);
610 mips_intrcnt_inc(sc->sc_intr_counter[irq]);
611 }
612
613 return (FILTER_HANDLED);
614 }
615
616 static int
ar724x_pci_maxslots(device_t dev)617 ar724x_pci_maxslots(device_t dev)
618 {
619
620 return (PCI_SLOTMAX);
621 }
622
623 static int
ar724x_pci_route_interrupt(device_t pcib,device_t device,int pin)624 ar724x_pci_route_interrupt(device_t pcib, device_t device, int pin)
625 {
626
627 return (pci_get_slot(device));
628 }
629
630 static device_method_t ar724x_pci_methods[] = {
631 /* Device interface */
632 DEVMETHOD(device_probe, ar724x_pci_probe),
633 DEVMETHOD(device_attach, ar724x_pci_attach),
634 DEVMETHOD(device_shutdown, bus_generic_shutdown),
635 DEVMETHOD(device_suspend, bus_generic_suspend),
636 DEVMETHOD(device_resume, bus_generic_resume),
637
638 /* Bus interface */
639 DEVMETHOD(bus_read_ivar, ar724x_pci_read_ivar),
640 DEVMETHOD(bus_write_ivar, ar724x_pci_write_ivar),
641 DEVMETHOD(bus_alloc_resource, ar724x_pci_alloc_resource),
642 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
643 DEVMETHOD(bus_activate_resource, ar724x_pci_activate_resource),
644 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
645 DEVMETHOD(bus_setup_intr, ar724x_pci_setup_intr),
646 DEVMETHOD(bus_teardown_intr, ar724x_pci_teardown_intr),
647
648 /* pcib interface */
649 DEVMETHOD(pcib_maxslots, ar724x_pci_maxslots),
650 DEVMETHOD(pcib_read_config, ar724x_pci_read_config),
651 DEVMETHOD(pcib_write_config, ar724x_pci_write_config),
652 DEVMETHOD(pcib_route_interrupt, ar724x_pci_route_interrupt),
653
654 DEVMETHOD_END
655 };
656
657 static driver_t ar724x_pci_driver = {
658 "pcib",
659 ar724x_pci_methods,
660 sizeof(struct ar71xx_pci_softc),
661 };
662
663 static devclass_t ar724x_pci_devclass;
664
665 DRIVER_MODULE(ar724x_pci, nexus, ar724x_pci_driver, ar724x_pci_devclass, 0, 0);
666