1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
4 2011, 2012 Free Software Foundation, Inc.
5
6 This file is part of GCC.
7
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
11 version.
12
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
21
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
25
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
31
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
35
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
41
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
44
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
51
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
55
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
60 REG_DEAD note is lost
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
63 linking
64
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
68
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
76 combine anyway. */
77
78 #include "config.h"
79 #include "system.h"
80 #include "coretypes.h"
81 #include "tm.h"
82 #include "rtl.h"
83 #include "tree.h"
84 #include "tm_p.h"
85 #include "flags.h"
86 #include "regs.h"
87 #include "hard-reg-set.h"
88 #include "basic-block.h"
89 #include "insn-config.h"
90 #include "function.h"
91 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
92 #include "expr.h"
93 #include "insn-attr.h"
94 #include "recog.h"
95 #include "diagnostic-core.h"
96 #include "target.h"
97 #include "optabs.h"
98 #include "insn-codes.h"
99 #include "rtlhooks-def.h"
100 /* Include output.h for dump_file. */
101 #include "output.h"
102 #include "params.h"
103 #include "timevar.h"
104 #include "tree-pass.h"
105 #include "df.h"
106 #include "cgraph.h"
107 #include "obstack.h"
108
109 /* Number of attempts to combine instructions in this function. */
110
111 static int combine_attempts;
112
113 /* Number of attempts that got as far as substitution in this function. */
114
115 static int combine_merges;
116
117 /* Number of instructions combined with added SETs in this function. */
118
119 static int combine_extras;
120
121 /* Number of instructions combined in this function. */
122
123 static int combine_successes;
124
125 /* Totals over entire compilation. */
126
127 static int total_attempts, total_merges, total_extras, total_successes;
128
129 /* combine_instructions may try to replace the right hand side of the
130 second instruction with the value of an associated REG_EQUAL note
131 before throwing it at try_combine. That is problematic when there
132 is a REG_DEAD note for a register used in the old right hand side
133 and can cause distribute_notes to do wrong things. This is the
134 second instruction if it has been so modified, null otherwise. */
135
136 static rtx i2mod;
137
138 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
139
140 static rtx i2mod_old_rhs;
141
142 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
143
144 static rtx i2mod_new_rhs;
145
146 typedef struct reg_stat_struct {
147 /* Record last point of death of (hard or pseudo) register n. */
148 rtx last_death;
149
150 /* Record last point of modification of (hard or pseudo) register n. */
151 rtx last_set;
152
153 /* The next group of fields allows the recording of the last value assigned
154 to (hard or pseudo) register n. We use this information to see if an
155 operation being processed is redundant given a prior operation performed
156 on the register. For example, an `and' with a constant is redundant if
157 all the zero bits are already known to be turned off.
158
159 We use an approach similar to that used by cse, but change it in the
160 following ways:
161
162 (1) We do not want to reinitialize at each label.
163 (2) It is useful, but not critical, to know the actual value assigned
164 to a register. Often just its form is helpful.
165
166 Therefore, we maintain the following fields:
167
168 last_set_value the last value assigned
169 last_set_label records the value of label_tick when the
170 register was assigned
171 last_set_table_tick records the value of label_tick when a
172 value using the register is assigned
173 last_set_invalid set to nonzero when it is not valid
174 to use the value of this register in some
175 register's value
176
177 To understand the usage of these tables, it is important to understand
178 the distinction between the value in last_set_value being valid and
179 the register being validly contained in some other expression in the
180 table.
181
182 (The next two parameters are out of date).
183
184 reg_stat[i].last_set_value is valid if it is nonzero, and either
185 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
186
187 Register I may validly appear in any expression returned for the value
188 of another register if reg_n_sets[i] is 1. It may also appear in the
189 value for register J if reg_stat[j].last_set_invalid is zero, or
190 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
191
192 If an expression is found in the table containing a register which may
193 not validly appear in an expression, the register is replaced by
194 something that won't match, (clobber (const_int 0)). */
195
196 /* Record last value assigned to (hard or pseudo) register n. */
197
198 rtx last_set_value;
199
200 /* Record the value of label_tick when an expression involving register n
201 is placed in last_set_value. */
202
203 int last_set_table_tick;
204
205 /* Record the value of label_tick when the value for register n is placed in
206 last_set_value. */
207
208 int last_set_label;
209
210 /* These fields are maintained in parallel with last_set_value and are
211 used to store the mode in which the register was last set, the bits
212 that were known to be zero when it was last set, and the number of
213 sign bits copies it was known to have when it was last set. */
214
215 unsigned HOST_WIDE_INT last_set_nonzero_bits;
216 char last_set_sign_bit_copies;
217 ENUM_BITFIELD(machine_mode) last_set_mode : 8;
218
219 /* Set nonzero if references to register n in expressions should not be
220 used. last_set_invalid is set nonzero when this register is being
221 assigned to and last_set_table_tick == label_tick. */
222
223 char last_set_invalid;
224
225 /* Some registers that are set more than once and used in more than one
226 basic block are nevertheless always set in similar ways. For example,
227 a QImode register may be loaded from memory in two places on a machine
228 where byte loads zero extend.
229
230 We record in the following fields if a register has some leading bits
231 that are always equal to the sign bit, and what we know about the
232 nonzero bits of a register, specifically which bits are known to be
233 zero.
234
235 If an entry is zero, it means that we don't know anything special. */
236
237 unsigned char sign_bit_copies;
238
239 unsigned HOST_WIDE_INT nonzero_bits;
240
241 /* Record the value of the label_tick when the last truncation
242 happened. The field truncated_to_mode is only valid if
243 truncation_label == label_tick. */
244
245 int truncation_label;
246
247 /* Record the last truncation seen for this register. If truncation
248 is not a nop to this mode we might be able to save an explicit
249 truncation if we know that value already contains a truncated
250 value. */
251
252 ENUM_BITFIELD(machine_mode) truncated_to_mode : 8;
253 } reg_stat_type;
254
255 DEF_VEC_O(reg_stat_type);
256 DEF_VEC_ALLOC_O(reg_stat_type,heap);
257
258 static VEC(reg_stat_type,heap) *reg_stat;
259
260 /* Record the luid of the last insn that invalidated memory
261 (anything that writes memory, and subroutine calls, but not pushes). */
262
263 static int mem_last_set;
264
265 /* Record the luid of the last CALL_INSN
266 so we can tell whether a potential combination crosses any calls. */
267
268 static int last_call_luid;
269
270 /* When `subst' is called, this is the insn that is being modified
271 (by combining in a previous insn). The PATTERN of this insn
272 is still the old pattern partially modified and it should not be
273 looked at, but this may be used to examine the successors of the insn
274 to judge whether a simplification is valid. */
275
276 static rtx subst_insn;
277
278 /* This is the lowest LUID that `subst' is currently dealing with.
279 get_last_value will not return a value if the register was set at or
280 after this LUID. If not for this mechanism, we could get confused if
281 I2 or I1 in try_combine were an insn that used the old value of a register
282 to obtain a new value. In that case, we might erroneously get the
283 new value of the register when we wanted the old one. */
284
285 static int subst_low_luid;
286
287 /* This contains any hard registers that are used in newpat; reg_dead_at_p
288 must consider all these registers to be always live. */
289
290 static HARD_REG_SET newpat_used_regs;
291
292 /* This is an insn to which a LOG_LINKS entry has been added. If this
293 insn is the earlier than I2 or I3, combine should rescan starting at
294 that location. */
295
296 static rtx added_links_insn;
297
298 /* Basic block in which we are performing combines. */
299 static basic_block this_basic_block;
300 static bool optimize_this_for_speed_p;
301
302
303 /* Length of the currently allocated uid_insn_cost array. */
304
305 static int max_uid_known;
306
307 /* The following array records the insn_rtx_cost for every insn
308 in the instruction stream. */
309
310 static int *uid_insn_cost;
311
312 /* The following array records the LOG_LINKS for every insn in the
313 instruction stream as struct insn_link pointers. */
314
315 struct insn_link {
316 rtx insn;
317 struct insn_link *next;
318 };
319
320 static struct insn_link **uid_log_links;
321
322 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
323 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
324
325 #define FOR_EACH_LOG_LINK(L, INSN) \
326 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
327
328 /* Links for LOG_LINKS are allocated from this obstack. */
329
330 static struct obstack insn_link_obstack;
331
332 /* Allocate a link. */
333
334 static inline struct insn_link *
alloc_insn_link(rtx insn,struct insn_link * next)335 alloc_insn_link (rtx insn, struct insn_link *next)
336 {
337 struct insn_link *l
338 = (struct insn_link *) obstack_alloc (&insn_link_obstack,
339 sizeof (struct insn_link));
340 l->insn = insn;
341 l->next = next;
342 return l;
343 }
344
345 /* Incremented for each basic block. */
346
347 static int label_tick;
348
349 /* Reset to label_tick for each extended basic block in scanning order. */
350
351 static int label_tick_ebb_start;
352
353 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
354 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
355
356 static enum machine_mode nonzero_bits_mode;
357
358 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
359 be safely used. It is zero while computing them and after combine has
360 completed. This former test prevents propagating values based on
361 previously set values, which can be incorrect if a variable is modified
362 in a loop. */
363
364 static int nonzero_sign_valid;
365
366
367 /* Record one modification to rtl structure
368 to be undone by storing old_contents into *where. */
369
370 enum undo_kind { UNDO_RTX, UNDO_INT, UNDO_MODE, UNDO_LINKS };
371
372 struct undo
373 {
374 struct undo *next;
375 enum undo_kind kind;
376 union { rtx r; int i; enum machine_mode m; struct insn_link *l; } old_contents;
377 union { rtx *r; int *i; struct insn_link **l; } where;
378 };
379
380 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
381 num_undo says how many are currently recorded.
382
383 other_insn is nonzero if we have modified some other insn in the process
384 of working on subst_insn. It must be verified too. */
385
386 struct undobuf
387 {
388 struct undo *undos;
389 struct undo *frees;
390 rtx other_insn;
391 };
392
393 static struct undobuf undobuf;
394
395 /* Number of times the pseudo being substituted for
396 was found and replaced. */
397
398 static int n_occurrences;
399
400 static rtx reg_nonzero_bits_for_combine (const_rtx, enum machine_mode, const_rtx,
401 enum machine_mode,
402 unsigned HOST_WIDE_INT,
403 unsigned HOST_WIDE_INT *);
404 static rtx reg_num_sign_bit_copies_for_combine (const_rtx, enum machine_mode, const_rtx,
405 enum machine_mode,
406 unsigned int, unsigned int *);
407 static void do_SUBST (rtx *, rtx);
408 static void do_SUBST_INT (int *, int);
409 static void init_reg_last (void);
410 static void setup_incoming_promotions (rtx);
411 static void set_nonzero_bits_and_sign_copies (rtx, const_rtx, void *);
412 static int cant_combine_insn_p (rtx);
413 static int can_combine_p (rtx, rtx, rtx, rtx, rtx, rtx, rtx *, rtx *);
414 static int combinable_i3pat (rtx, rtx *, rtx, rtx, rtx, int, int, rtx *);
415 static int contains_muldiv (rtx);
416 static rtx try_combine (rtx, rtx, rtx, rtx, int *, rtx);
417 static void undo_all (void);
418 static void undo_commit (void);
419 static rtx *find_split_point (rtx *, rtx, bool);
420 static rtx subst (rtx, rtx, rtx, int, int, int);
421 static rtx combine_simplify_rtx (rtx, enum machine_mode, int, int);
422 static rtx simplify_if_then_else (rtx);
423 static rtx simplify_set (rtx);
424 static rtx simplify_logical (rtx);
425 static rtx expand_compound_operation (rtx);
426 static const_rtx expand_field_assignment (const_rtx);
427 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
428 rtx, unsigned HOST_WIDE_INT, int, int, int);
429 static rtx extract_left_shift (rtx, int);
430 static rtx make_compound_operation (rtx, enum rtx_code);
431 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
432 unsigned HOST_WIDE_INT *);
433 static rtx canon_reg_for_combine (rtx, rtx);
434 static rtx force_to_mode (rtx, enum machine_mode,
435 unsigned HOST_WIDE_INT, int);
436 static rtx if_then_else_cond (rtx, rtx *, rtx *);
437 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
438 static int rtx_equal_for_field_assignment_p (rtx, rtx);
439 static rtx make_field_assignment (rtx);
440 static rtx apply_distributive_law (rtx);
441 static rtx distribute_and_simplify_rtx (rtx, int);
442 static rtx simplify_and_const_int_1 (enum machine_mode, rtx,
443 unsigned HOST_WIDE_INT);
444 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
445 unsigned HOST_WIDE_INT);
446 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
447 HOST_WIDE_INT, enum machine_mode, int *);
448 static rtx simplify_shift_const_1 (enum rtx_code, enum machine_mode, rtx, int);
449 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
450 int);
451 static int recog_for_combine (rtx *, rtx, rtx *);
452 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
453 static enum rtx_code simplify_compare_const (enum rtx_code, rtx, rtx *);
454 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
455 static void update_table_tick (rtx);
456 static void record_value_for_reg (rtx, rtx, rtx);
457 static void check_promoted_subreg (rtx, rtx);
458 static void record_dead_and_set_regs_1 (rtx, const_rtx, void *);
459 static void record_dead_and_set_regs (rtx);
460 static int get_last_value_validate (rtx *, rtx, int, int);
461 static rtx get_last_value (const_rtx);
462 static int use_crosses_set_p (const_rtx, int);
463 static void reg_dead_at_p_1 (rtx, const_rtx, void *);
464 static int reg_dead_at_p (rtx, rtx);
465 static void move_deaths (rtx, rtx, int, rtx, rtx *);
466 static int reg_bitfield_target_p (rtx, rtx);
467 static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx, rtx);
468 static void distribute_links (struct insn_link *);
469 static void mark_used_regs_combine (rtx);
470 static void record_promoted_value (rtx, rtx);
471 static int unmentioned_reg_p_1 (rtx *, void *);
472 static bool unmentioned_reg_p (rtx, rtx);
473 static int record_truncated_value (rtx *, void *);
474 static void record_truncated_values (rtx *, void *);
475 static bool reg_truncated_to_mode (enum machine_mode, const_rtx);
476 static rtx gen_lowpart_or_truncate (enum machine_mode, rtx);
477
478
479 /* It is not safe to use ordinary gen_lowpart in combine.
480 See comments in gen_lowpart_for_combine. */
481 #undef RTL_HOOKS_GEN_LOWPART
482 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
483
484 /* Our implementation of gen_lowpart never emits a new pseudo. */
485 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
486 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
487
488 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
489 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
490
491 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
492 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
493
494 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
495 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
496
497 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
498
499
500 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
501 PATTERN can not be split. Otherwise, it returns an insn sequence.
502 This is a wrapper around split_insns which ensures that the
503 reg_stat vector is made larger if the splitter creates a new
504 register. */
505
506 static rtx
combine_split_insns(rtx pattern,rtx insn)507 combine_split_insns (rtx pattern, rtx insn)
508 {
509 rtx ret;
510 unsigned int nregs;
511
512 ret = split_insns (pattern, insn);
513 nregs = max_reg_num ();
514 if (nregs > VEC_length (reg_stat_type, reg_stat))
515 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
516 return ret;
517 }
518
519 /* This is used by find_single_use to locate an rtx in LOC that
520 contains exactly one use of DEST, which is typically either a REG
521 or CC0. It returns a pointer to the innermost rtx expression
522 containing DEST. Appearances of DEST that are being used to
523 totally replace it are not counted. */
524
525 static rtx *
find_single_use_1(rtx dest,rtx * loc)526 find_single_use_1 (rtx dest, rtx *loc)
527 {
528 rtx x = *loc;
529 enum rtx_code code = GET_CODE (x);
530 rtx *result = NULL;
531 rtx *this_result;
532 int i;
533 const char *fmt;
534
535 switch (code)
536 {
537 case CONST_INT:
538 case CONST:
539 case LABEL_REF:
540 case SYMBOL_REF:
541 case CONST_DOUBLE:
542 case CONST_VECTOR:
543 case CLOBBER:
544 return 0;
545
546 case SET:
547 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
548 of a REG that occupies all of the REG, the insn uses DEST if
549 it is mentioned in the destination or the source. Otherwise, we
550 need just check the source. */
551 if (GET_CODE (SET_DEST (x)) != CC0
552 && GET_CODE (SET_DEST (x)) != PC
553 && !REG_P (SET_DEST (x))
554 && ! (GET_CODE (SET_DEST (x)) == SUBREG
555 && REG_P (SUBREG_REG (SET_DEST (x)))
556 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
557 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
558 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
559 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))))
560 break;
561
562 return find_single_use_1 (dest, &SET_SRC (x));
563
564 case MEM:
565 case SUBREG:
566 return find_single_use_1 (dest, &XEXP (x, 0));
567
568 default:
569 break;
570 }
571
572 /* If it wasn't one of the common cases above, check each expression and
573 vector of this code. Look for a unique usage of DEST. */
574
575 fmt = GET_RTX_FORMAT (code);
576 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
577 {
578 if (fmt[i] == 'e')
579 {
580 if (dest == XEXP (x, i)
581 || (REG_P (dest) && REG_P (XEXP (x, i))
582 && REGNO (dest) == REGNO (XEXP (x, i))))
583 this_result = loc;
584 else
585 this_result = find_single_use_1 (dest, &XEXP (x, i));
586
587 if (result == NULL)
588 result = this_result;
589 else if (this_result)
590 /* Duplicate usage. */
591 return NULL;
592 }
593 else if (fmt[i] == 'E')
594 {
595 int j;
596
597 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
598 {
599 if (XVECEXP (x, i, j) == dest
600 || (REG_P (dest)
601 && REG_P (XVECEXP (x, i, j))
602 && REGNO (XVECEXP (x, i, j)) == REGNO (dest)))
603 this_result = loc;
604 else
605 this_result = find_single_use_1 (dest, &XVECEXP (x, i, j));
606
607 if (result == NULL)
608 result = this_result;
609 else if (this_result)
610 return NULL;
611 }
612 }
613 }
614
615 return result;
616 }
617
618
619 /* See if DEST, produced in INSN, is used only a single time in the
620 sequel. If so, return a pointer to the innermost rtx expression in which
621 it is used.
622
623 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
624
625 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
626 care about REG_DEAD notes or LOG_LINKS.
627
628 Otherwise, we find the single use by finding an insn that has a
629 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
630 only referenced once in that insn, we know that it must be the first
631 and last insn referencing DEST. */
632
633 static rtx *
find_single_use(rtx dest,rtx insn,rtx * ploc)634 find_single_use (rtx dest, rtx insn, rtx *ploc)
635 {
636 basic_block bb;
637 rtx next;
638 rtx *result;
639 struct insn_link *link;
640
641 #ifdef HAVE_cc0
642 if (dest == cc0_rtx)
643 {
644 next = NEXT_INSN (insn);
645 if (next == 0
646 || (!NONJUMP_INSN_P (next) && !JUMP_P (next)))
647 return 0;
648
649 result = find_single_use_1 (dest, &PATTERN (next));
650 if (result && ploc)
651 *ploc = next;
652 return result;
653 }
654 #endif
655
656 if (!REG_P (dest))
657 return 0;
658
659 bb = BLOCK_FOR_INSN (insn);
660 for (next = NEXT_INSN (insn);
661 next && BLOCK_FOR_INSN (next) == bb;
662 next = NEXT_INSN (next))
663 if (INSN_P (next) && dead_or_set_p (next, dest))
664 {
665 FOR_EACH_LOG_LINK (link, next)
666 if (link->insn == insn)
667 break;
668
669 if (link)
670 {
671 result = find_single_use_1 (dest, &PATTERN (next));
672 if (ploc)
673 *ploc = next;
674 return result;
675 }
676 }
677
678 return 0;
679 }
680
681 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
682 insn. The substitution can be undone by undo_all. If INTO is already
683 set to NEWVAL, do not record this change. Because computing NEWVAL might
684 also call SUBST, we have to compute it before we put anything into
685 the undo table. */
686
687 static void
do_SUBST(rtx * into,rtx newval)688 do_SUBST (rtx *into, rtx newval)
689 {
690 struct undo *buf;
691 rtx oldval = *into;
692
693 if (oldval == newval)
694 return;
695
696 /* We'd like to catch as many invalid transformations here as
697 possible. Unfortunately, there are way too many mode changes
698 that are perfectly valid, so we'd waste too much effort for
699 little gain doing the checks here. Focus on catching invalid
700 transformations involving integer constants. */
701 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
702 && CONST_INT_P (newval))
703 {
704 /* Sanity check that we're replacing oldval with a CONST_INT
705 that is a valid sign-extension for the original mode. */
706 gcc_assert (INTVAL (newval)
707 == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
708
709 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
710 CONST_INT is not valid, because after the replacement, the
711 original mode would be gone. Unfortunately, we can't tell
712 when do_SUBST is called to replace the operand thereof, so we
713 perform this test on oldval instead, checking whether an
714 invalid replacement took place before we got here. */
715 gcc_assert (!(GET_CODE (oldval) == SUBREG
716 && CONST_INT_P (SUBREG_REG (oldval))));
717 gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
718 && CONST_INT_P (XEXP (oldval, 0))));
719 }
720
721 if (undobuf.frees)
722 buf = undobuf.frees, undobuf.frees = buf->next;
723 else
724 buf = XNEW (struct undo);
725
726 buf->kind = UNDO_RTX;
727 buf->where.r = into;
728 buf->old_contents.r = oldval;
729 *into = newval;
730
731 buf->next = undobuf.undos, undobuf.undos = buf;
732 }
733
734 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
735
736 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
737 for the value of a HOST_WIDE_INT value (including CONST_INT) is
738 not safe. */
739
740 static void
do_SUBST_INT(int * into,int newval)741 do_SUBST_INT (int *into, int newval)
742 {
743 struct undo *buf;
744 int oldval = *into;
745
746 if (oldval == newval)
747 return;
748
749 if (undobuf.frees)
750 buf = undobuf.frees, undobuf.frees = buf->next;
751 else
752 buf = XNEW (struct undo);
753
754 buf->kind = UNDO_INT;
755 buf->where.i = into;
756 buf->old_contents.i = oldval;
757 *into = newval;
758
759 buf->next = undobuf.undos, undobuf.undos = buf;
760 }
761
762 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
763
764 /* Similar to SUBST, but just substitute the mode. This is used when
765 changing the mode of a pseudo-register, so that any other
766 references to the entry in the regno_reg_rtx array will change as
767 well. */
768
769 static void
do_SUBST_MODE(rtx * into,enum machine_mode newval)770 do_SUBST_MODE (rtx *into, enum machine_mode newval)
771 {
772 struct undo *buf;
773 enum machine_mode oldval = GET_MODE (*into);
774
775 if (oldval == newval)
776 return;
777
778 if (undobuf.frees)
779 buf = undobuf.frees, undobuf.frees = buf->next;
780 else
781 buf = XNEW (struct undo);
782
783 buf->kind = UNDO_MODE;
784 buf->where.r = into;
785 buf->old_contents.m = oldval;
786 adjust_reg_mode (*into, newval);
787
788 buf->next = undobuf.undos, undobuf.undos = buf;
789 }
790
791 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE(&(INTO), (NEWVAL))
792
793 #ifndef HAVE_cc0
794 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
795
796 static void
do_SUBST_LINK(struct insn_link ** into,struct insn_link * newval)797 do_SUBST_LINK (struct insn_link **into, struct insn_link *newval)
798 {
799 struct undo *buf;
800 struct insn_link * oldval = *into;
801
802 if (oldval == newval)
803 return;
804
805 if (undobuf.frees)
806 buf = undobuf.frees, undobuf.frees = buf->next;
807 else
808 buf = XNEW (struct undo);
809
810 buf->kind = UNDO_LINKS;
811 buf->where.l = into;
812 buf->old_contents.l = oldval;
813 *into = newval;
814
815 buf->next = undobuf.undos, undobuf.undos = buf;
816 }
817
818 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
819 #endif
820
821 /* Subroutine of try_combine. Determine whether the replacement patterns
822 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
823 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
824 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
825 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
826 of all the instructions can be estimated and the replacements are more
827 expensive than the original sequence. */
828
829 static bool
combine_validate_cost(rtx i0,rtx i1,rtx i2,rtx i3,rtx newpat,rtx newi2pat,rtx newotherpat)830 combine_validate_cost (rtx i0, rtx i1, rtx i2, rtx i3, rtx newpat,
831 rtx newi2pat, rtx newotherpat)
832 {
833 int i0_cost, i1_cost, i2_cost, i3_cost;
834 int new_i2_cost, new_i3_cost;
835 int old_cost, new_cost;
836
837 /* Lookup the original insn_rtx_costs. */
838 i2_cost = INSN_COST (i2);
839 i3_cost = INSN_COST (i3);
840
841 if (i1)
842 {
843 i1_cost = INSN_COST (i1);
844 if (i0)
845 {
846 i0_cost = INSN_COST (i0);
847 old_cost = (i0_cost > 0 && i1_cost > 0 && i2_cost > 0 && i3_cost > 0
848 ? i0_cost + i1_cost + i2_cost + i3_cost : 0);
849 }
850 else
851 {
852 old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0
853 ? i1_cost + i2_cost + i3_cost : 0);
854 i0_cost = 0;
855 }
856 }
857 else
858 {
859 old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
860 i1_cost = i0_cost = 0;
861 }
862
863 /* Calculate the replacement insn_rtx_costs. */
864 new_i3_cost = insn_rtx_cost (newpat, optimize_this_for_speed_p);
865 if (newi2pat)
866 {
867 new_i2_cost = insn_rtx_cost (newi2pat, optimize_this_for_speed_p);
868 new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
869 ? new_i2_cost + new_i3_cost : 0;
870 }
871 else
872 {
873 new_cost = new_i3_cost;
874 new_i2_cost = 0;
875 }
876
877 if (undobuf.other_insn)
878 {
879 int old_other_cost, new_other_cost;
880
881 old_other_cost = INSN_COST (undobuf.other_insn);
882 new_other_cost = insn_rtx_cost (newotherpat, optimize_this_for_speed_p);
883 if (old_other_cost > 0 && new_other_cost > 0)
884 {
885 old_cost += old_other_cost;
886 new_cost += new_other_cost;
887 }
888 else
889 old_cost = 0;
890 }
891
892 /* Disallow this combination if both new_cost and old_cost are greater than
893 zero, and new_cost is greater than old cost. */
894 if (old_cost > 0 && new_cost > old_cost)
895 {
896 if (dump_file)
897 {
898 if (i0)
899 {
900 fprintf (dump_file,
901 "rejecting combination of insns %d, %d, %d and %d\n",
902 INSN_UID (i0), INSN_UID (i1), INSN_UID (i2),
903 INSN_UID (i3));
904 fprintf (dump_file, "original costs %d + %d + %d + %d = %d\n",
905 i0_cost, i1_cost, i2_cost, i3_cost, old_cost);
906 }
907 else if (i1)
908 {
909 fprintf (dump_file,
910 "rejecting combination of insns %d, %d and %d\n",
911 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
912 fprintf (dump_file, "original costs %d + %d + %d = %d\n",
913 i1_cost, i2_cost, i3_cost, old_cost);
914 }
915 else
916 {
917 fprintf (dump_file,
918 "rejecting combination of insns %d and %d\n",
919 INSN_UID (i2), INSN_UID (i3));
920 fprintf (dump_file, "original costs %d + %d = %d\n",
921 i2_cost, i3_cost, old_cost);
922 }
923
924 if (newi2pat)
925 {
926 fprintf (dump_file, "replacement costs %d + %d = %d\n",
927 new_i2_cost, new_i3_cost, new_cost);
928 }
929 else
930 fprintf (dump_file, "replacement cost %d\n", new_cost);
931 }
932
933 return false;
934 }
935
936 /* Update the uid_insn_cost array with the replacement costs. */
937 INSN_COST (i2) = new_i2_cost;
938 INSN_COST (i3) = new_i3_cost;
939 if (i1)
940 {
941 INSN_COST (i1) = 0;
942 if (i0)
943 INSN_COST (i0) = 0;
944 }
945
946 return true;
947 }
948
949
950 /* Delete any insns that copy a register to itself. */
951
952 static void
delete_noop_moves(void)953 delete_noop_moves (void)
954 {
955 rtx insn, next;
956 basic_block bb;
957
958 FOR_EACH_BB (bb)
959 {
960 for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); insn = next)
961 {
962 next = NEXT_INSN (insn);
963 if (INSN_P (insn) && noop_move_p (insn))
964 {
965 if (dump_file)
966 fprintf (dump_file, "deleting noop move %d\n", INSN_UID (insn));
967
968 delete_insn_and_edges (insn);
969 }
970 }
971 }
972 }
973
974
975 /* Fill in log links field for all insns. */
976
977 static void
create_log_links(void)978 create_log_links (void)
979 {
980 basic_block bb;
981 rtx *next_use, insn;
982 df_ref *def_vec, *use_vec;
983
984 next_use = XCNEWVEC (rtx, max_reg_num ());
985
986 /* Pass through each block from the end, recording the uses of each
987 register and establishing log links when def is encountered.
988 Note that we do not clear next_use array in order to save time,
989 so we have to test whether the use is in the same basic block as def.
990
991 There are a few cases below when we do not consider the definition or
992 usage -- these are taken from original flow.c did. Don't ask me why it is
993 done this way; I don't know and if it works, I don't want to know. */
994
995 FOR_EACH_BB (bb)
996 {
997 FOR_BB_INSNS_REVERSE (bb, insn)
998 {
999 if (!NONDEBUG_INSN_P (insn))
1000 continue;
1001
1002 /* Log links are created only once. */
1003 gcc_assert (!LOG_LINKS (insn));
1004
1005 for (def_vec = DF_INSN_DEFS (insn); *def_vec; def_vec++)
1006 {
1007 df_ref def = *def_vec;
1008 int regno = DF_REF_REGNO (def);
1009 rtx use_insn;
1010
1011 if (!next_use[regno])
1012 continue;
1013
1014 /* Do not consider if it is pre/post modification in MEM. */
1015 if (DF_REF_FLAGS (def) & DF_REF_PRE_POST_MODIFY)
1016 continue;
1017
1018 /* Do not make the log link for frame pointer. */
1019 if ((regno == FRAME_POINTER_REGNUM
1020 && (! reload_completed || frame_pointer_needed))
1021 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
1022 || (regno == HARD_FRAME_POINTER_REGNUM
1023 && (! reload_completed || frame_pointer_needed))
1024 #endif
1025 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
1026 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
1027 #endif
1028 )
1029 continue;
1030
1031 use_insn = next_use[regno];
1032 if (BLOCK_FOR_INSN (use_insn) == bb)
1033 {
1034 /* flow.c claimed:
1035
1036 We don't build a LOG_LINK for hard registers contained
1037 in ASM_OPERANDs. If these registers get replaced,
1038 we might wind up changing the semantics of the insn,
1039 even if reload can make what appear to be valid
1040 assignments later. */
1041 if (regno >= FIRST_PSEUDO_REGISTER
1042 || asm_noperands (PATTERN (use_insn)) < 0)
1043 {
1044 /* Don't add duplicate links between instructions. */
1045 struct insn_link *links;
1046 FOR_EACH_LOG_LINK (links, use_insn)
1047 if (insn == links->insn)
1048 break;
1049
1050 if (!links)
1051 LOG_LINKS (use_insn)
1052 = alloc_insn_link (insn, LOG_LINKS (use_insn));
1053 }
1054 }
1055 next_use[regno] = NULL_RTX;
1056 }
1057
1058 for (use_vec = DF_INSN_USES (insn); *use_vec; use_vec++)
1059 {
1060 df_ref use = *use_vec;
1061 int regno = DF_REF_REGNO (use);
1062
1063 /* Do not consider the usage of the stack pointer
1064 by function call. */
1065 if (DF_REF_FLAGS (use) & DF_REF_CALL_STACK_USAGE)
1066 continue;
1067
1068 next_use[regno] = insn;
1069 }
1070 }
1071 }
1072
1073 free (next_use);
1074 }
1075
1076 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1077 true if we found a LOG_LINK that proves that A feeds B. This only works
1078 if there are no instructions between A and B which could have a link
1079 depending on A, since in that case we would not record a link for B.
1080 We also check the implicit dependency created by a cc0 setter/user
1081 pair. */
1082
1083 static bool
insn_a_feeds_b(rtx a,rtx b)1084 insn_a_feeds_b (rtx a, rtx b)
1085 {
1086 struct insn_link *links;
1087 FOR_EACH_LOG_LINK (links, b)
1088 if (links->insn == a)
1089 return true;
1090 #ifdef HAVE_cc0
1091 if (sets_cc0_p (a))
1092 return true;
1093 #endif
1094 return false;
1095 }
1096
1097 /* Main entry point for combiner. F is the first insn of the function.
1098 NREGS is the first unused pseudo-reg number.
1099
1100 Return nonzero if the combiner has turned an indirect jump
1101 instruction into a direct jump. */
1102 static int
combine_instructions(rtx f,unsigned int nregs)1103 combine_instructions (rtx f, unsigned int nregs)
1104 {
1105 rtx insn, next;
1106 #ifdef HAVE_cc0
1107 rtx prev;
1108 #endif
1109 struct insn_link *links, *nextlinks;
1110 rtx first;
1111 basic_block last_bb;
1112
1113 int new_direct_jump_p = 0;
1114
1115 for (first = f; first && !INSN_P (first); )
1116 first = NEXT_INSN (first);
1117 if (!first)
1118 return 0;
1119
1120 combine_attempts = 0;
1121 combine_merges = 0;
1122 combine_extras = 0;
1123 combine_successes = 0;
1124
1125 rtl_hooks = combine_rtl_hooks;
1126
1127 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
1128
1129 init_recog_no_volatile ();
1130
1131 /* Allocate array for insn info. */
1132 max_uid_known = get_max_uid ();
1133 uid_log_links = XCNEWVEC (struct insn_link *, max_uid_known + 1);
1134 uid_insn_cost = XCNEWVEC (int, max_uid_known + 1);
1135 gcc_obstack_init (&insn_link_obstack);
1136
1137 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
1138
1139 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1140 problems when, for example, we have j <<= 1 in a loop. */
1141
1142 nonzero_sign_valid = 0;
1143 label_tick = label_tick_ebb_start = 1;
1144
1145 /* Scan all SETs and see if we can deduce anything about what
1146 bits are known to be zero for some registers and how many copies
1147 of the sign bit are known to exist for those registers.
1148
1149 Also set any known values so that we can use it while searching
1150 for what bits are known to be set. */
1151
1152 setup_incoming_promotions (first);
1153 /* Allow the entry block and the first block to fall into the same EBB.
1154 Conceptually the incoming promotions are assigned to the entry block. */
1155 last_bb = ENTRY_BLOCK_PTR;
1156
1157 create_log_links ();
1158 FOR_EACH_BB (this_basic_block)
1159 {
1160 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1161 last_call_luid = 0;
1162 mem_last_set = -1;
1163
1164 label_tick++;
1165 if (!single_pred_p (this_basic_block)
1166 || single_pred (this_basic_block) != last_bb)
1167 label_tick_ebb_start = label_tick;
1168 last_bb = this_basic_block;
1169
1170 FOR_BB_INSNS (this_basic_block, insn)
1171 if (INSN_P (insn) && BLOCK_FOR_INSN (insn))
1172 {
1173 #ifdef AUTO_INC_DEC
1174 rtx links;
1175 #endif
1176
1177 subst_low_luid = DF_INSN_LUID (insn);
1178 subst_insn = insn;
1179
1180 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
1181 insn);
1182 record_dead_and_set_regs (insn);
1183
1184 #ifdef AUTO_INC_DEC
1185 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
1186 if (REG_NOTE_KIND (links) == REG_INC)
1187 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
1188 insn);
1189 #endif
1190
1191 /* Record the current insn_rtx_cost of this instruction. */
1192 if (NONJUMP_INSN_P (insn))
1193 INSN_COST (insn) = insn_rtx_cost (PATTERN (insn),
1194 optimize_this_for_speed_p);
1195 if (dump_file)
1196 fprintf(dump_file, "insn_cost %d: %d\n",
1197 INSN_UID (insn), INSN_COST (insn));
1198 }
1199 }
1200
1201 nonzero_sign_valid = 1;
1202
1203 /* Now scan all the insns in forward order. */
1204 label_tick = label_tick_ebb_start = 1;
1205 init_reg_last ();
1206 setup_incoming_promotions (first);
1207 last_bb = ENTRY_BLOCK_PTR;
1208
1209 FOR_EACH_BB (this_basic_block)
1210 {
1211 rtx last_combined_insn = NULL_RTX;
1212 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1213 last_call_luid = 0;
1214 mem_last_set = -1;
1215
1216 label_tick++;
1217 if (!single_pred_p (this_basic_block)
1218 || single_pred (this_basic_block) != last_bb)
1219 label_tick_ebb_start = label_tick;
1220 last_bb = this_basic_block;
1221
1222 rtl_profile_for_bb (this_basic_block);
1223 for (insn = BB_HEAD (this_basic_block);
1224 insn != NEXT_INSN (BB_END (this_basic_block));
1225 insn = next ? next : NEXT_INSN (insn))
1226 {
1227 next = 0;
1228 if (NONDEBUG_INSN_P (insn))
1229 {
1230 while (last_combined_insn
1231 && INSN_DELETED_P (last_combined_insn))
1232 last_combined_insn = PREV_INSN (last_combined_insn);
1233 if (last_combined_insn == NULL_RTX
1234 || BARRIER_P (last_combined_insn)
1235 || BLOCK_FOR_INSN (last_combined_insn) != this_basic_block
1236 || DF_INSN_LUID (last_combined_insn) <= DF_INSN_LUID (insn))
1237 last_combined_insn = insn;
1238
1239 /* See if we know about function return values before this
1240 insn based upon SUBREG flags. */
1241 check_promoted_subreg (insn, PATTERN (insn));
1242
1243 /* See if we can find hardregs and subreg of pseudos in
1244 narrower modes. This could help turning TRUNCATEs
1245 into SUBREGs. */
1246 note_uses (&PATTERN (insn), record_truncated_values, NULL);
1247
1248 /* Try this insn with each insn it links back to. */
1249
1250 FOR_EACH_LOG_LINK (links, insn)
1251 if ((next = try_combine (insn, links->insn, NULL_RTX,
1252 NULL_RTX, &new_direct_jump_p,
1253 last_combined_insn)) != 0)
1254 goto retry;
1255
1256 /* Try each sequence of three linked insns ending with this one. */
1257
1258 FOR_EACH_LOG_LINK (links, insn)
1259 {
1260 rtx link = links->insn;
1261
1262 /* If the linked insn has been replaced by a note, then there
1263 is no point in pursuing this chain any further. */
1264 if (NOTE_P (link))
1265 continue;
1266
1267 FOR_EACH_LOG_LINK (nextlinks, link)
1268 if ((next = try_combine (insn, link, nextlinks->insn,
1269 NULL_RTX, &new_direct_jump_p,
1270 last_combined_insn)) != 0)
1271 goto retry;
1272 }
1273
1274 #ifdef HAVE_cc0
1275 /* Try to combine a jump insn that uses CC0
1276 with a preceding insn that sets CC0, and maybe with its
1277 logical predecessor as well.
1278 This is how we make decrement-and-branch insns.
1279 We need this special code because data flow connections
1280 via CC0 do not get entered in LOG_LINKS. */
1281
1282 if (JUMP_P (insn)
1283 && (prev = prev_nonnote_insn (insn)) != 0
1284 && NONJUMP_INSN_P (prev)
1285 && sets_cc0_p (PATTERN (prev)))
1286 {
1287 if ((next = try_combine (insn, prev, NULL_RTX, NULL_RTX,
1288 &new_direct_jump_p,
1289 last_combined_insn)) != 0)
1290 goto retry;
1291
1292 FOR_EACH_LOG_LINK (nextlinks, prev)
1293 if ((next = try_combine (insn, prev, nextlinks->insn,
1294 NULL_RTX, &new_direct_jump_p,
1295 last_combined_insn)) != 0)
1296 goto retry;
1297 }
1298
1299 /* Do the same for an insn that explicitly references CC0. */
1300 if (NONJUMP_INSN_P (insn)
1301 && (prev = prev_nonnote_insn (insn)) != 0
1302 && NONJUMP_INSN_P (prev)
1303 && sets_cc0_p (PATTERN (prev))
1304 && GET_CODE (PATTERN (insn)) == SET
1305 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
1306 {
1307 if ((next = try_combine (insn, prev, NULL_RTX, NULL_RTX,
1308 &new_direct_jump_p,
1309 last_combined_insn)) != 0)
1310 goto retry;
1311
1312 FOR_EACH_LOG_LINK (nextlinks, prev)
1313 if ((next = try_combine (insn, prev, nextlinks->insn,
1314 NULL_RTX, &new_direct_jump_p,
1315 last_combined_insn)) != 0)
1316 goto retry;
1317 }
1318
1319 /* Finally, see if any of the insns that this insn links to
1320 explicitly references CC0. If so, try this insn, that insn,
1321 and its predecessor if it sets CC0. */
1322 FOR_EACH_LOG_LINK (links, insn)
1323 if (NONJUMP_INSN_P (links->insn)
1324 && GET_CODE (PATTERN (links->insn)) == SET
1325 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (links->insn)))
1326 && (prev = prev_nonnote_insn (links->insn)) != 0
1327 && NONJUMP_INSN_P (prev)
1328 && sets_cc0_p (PATTERN (prev))
1329 && (next = try_combine (insn, links->insn,
1330 prev, NULL_RTX, &new_direct_jump_p,
1331 last_combined_insn)) != 0)
1332 goto retry;
1333 #endif
1334
1335 /* Try combining an insn with two different insns whose results it
1336 uses. */
1337 FOR_EACH_LOG_LINK (links, insn)
1338 for (nextlinks = links->next; nextlinks;
1339 nextlinks = nextlinks->next)
1340 if ((next = try_combine (insn, links->insn,
1341 nextlinks->insn, NULL_RTX,
1342 &new_direct_jump_p,
1343 last_combined_insn)) != 0)
1344 goto retry;
1345
1346 /* Try four-instruction combinations. */
1347 FOR_EACH_LOG_LINK (links, insn)
1348 {
1349 struct insn_link *next1;
1350 rtx link = links->insn;
1351
1352 /* If the linked insn has been replaced by a note, then there
1353 is no point in pursuing this chain any further. */
1354 if (NOTE_P (link))
1355 continue;
1356
1357 FOR_EACH_LOG_LINK (next1, link)
1358 {
1359 rtx link1 = next1->insn;
1360 if (NOTE_P (link1))
1361 continue;
1362 /* I0 -> I1 -> I2 -> I3. */
1363 FOR_EACH_LOG_LINK (nextlinks, link1)
1364 if ((next = try_combine (insn, link, link1,
1365 nextlinks->insn,
1366 &new_direct_jump_p,
1367 last_combined_insn)) != 0)
1368 goto retry;
1369 /* I0, I1 -> I2, I2 -> I3. */
1370 for (nextlinks = next1->next; nextlinks;
1371 nextlinks = nextlinks->next)
1372 if ((next = try_combine (insn, link, link1,
1373 nextlinks->insn,
1374 &new_direct_jump_p,
1375 last_combined_insn)) != 0)
1376 goto retry;
1377 }
1378
1379 for (next1 = links->next; next1; next1 = next1->next)
1380 {
1381 rtx link1 = next1->insn;
1382 if (NOTE_P (link1))
1383 continue;
1384 /* I0 -> I2; I1, I2 -> I3. */
1385 FOR_EACH_LOG_LINK (nextlinks, link)
1386 if ((next = try_combine (insn, link, link1,
1387 nextlinks->insn,
1388 &new_direct_jump_p,
1389 last_combined_insn)) != 0)
1390 goto retry;
1391 /* I0 -> I1; I1, I2 -> I3. */
1392 FOR_EACH_LOG_LINK (nextlinks, link1)
1393 if ((next = try_combine (insn, link, link1,
1394 nextlinks->insn,
1395 &new_direct_jump_p,
1396 last_combined_insn)) != 0)
1397 goto retry;
1398 }
1399 }
1400
1401 /* Try this insn with each REG_EQUAL note it links back to. */
1402 FOR_EACH_LOG_LINK (links, insn)
1403 {
1404 rtx set, note;
1405 rtx temp = links->insn;
1406 if ((set = single_set (temp)) != 0
1407 && (note = find_reg_equal_equiv_note (temp)) != 0
1408 && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
1409 /* Avoid using a register that may already been marked
1410 dead by an earlier instruction. */
1411 && ! unmentioned_reg_p (note, SET_SRC (set))
1412 && (GET_MODE (note) == VOIDmode
1413 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
1414 : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
1415 {
1416 /* Temporarily replace the set's source with the
1417 contents of the REG_EQUAL note. The insn will
1418 be deleted or recognized by try_combine. */
1419 rtx orig = SET_SRC (set);
1420 SET_SRC (set) = note;
1421 i2mod = temp;
1422 i2mod_old_rhs = copy_rtx (orig);
1423 i2mod_new_rhs = copy_rtx (note);
1424 next = try_combine (insn, i2mod, NULL_RTX, NULL_RTX,
1425 &new_direct_jump_p,
1426 last_combined_insn);
1427 i2mod = NULL_RTX;
1428 if (next)
1429 goto retry;
1430 SET_SRC (set) = orig;
1431 }
1432 }
1433
1434 if (!NOTE_P (insn))
1435 record_dead_and_set_regs (insn);
1436
1437 retry:
1438 ;
1439 }
1440 }
1441 }
1442
1443 default_rtl_profile ();
1444 clear_bb_flags ();
1445 new_direct_jump_p |= purge_all_dead_edges ();
1446 delete_noop_moves ();
1447
1448 /* Clean up. */
1449 obstack_free (&insn_link_obstack, NULL);
1450 free (uid_log_links);
1451 free (uid_insn_cost);
1452 VEC_free (reg_stat_type, heap, reg_stat);
1453
1454 {
1455 struct undo *undo, *next;
1456 for (undo = undobuf.frees; undo; undo = next)
1457 {
1458 next = undo->next;
1459 free (undo);
1460 }
1461 undobuf.frees = 0;
1462 }
1463
1464 total_attempts += combine_attempts;
1465 total_merges += combine_merges;
1466 total_extras += combine_extras;
1467 total_successes += combine_successes;
1468
1469 nonzero_sign_valid = 0;
1470 rtl_hooks = general_rtl_hooks;
1471
1472 /* Make recognizer allow volatile MEMs again. */
1473 init_recog ();
1474
1475 return new_direct_jump_p;
1476 }
1477
1478 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1479
1480 static void
init_reg_last(void)1481 init_reg_last (void)
1482 {
1483 unsigned int i;
1484 reg_stat_type *p;
1485
1486 FOR_EACH_VEC_ELT (reg_stat_type, reg_stat, i, p)
1487 memset (p, 0, offsetof (reg_stat_type, sign_bit_copies));
1488 }
1489
1490 /* Set up any promoted values for incoming argument registers. */
1491
1492 static void
setup_incoming_promotions(rtx first)1493 setup_incoming_promotions (rtx first)
1494 {
1495 tree arg;
1496 bool strictly_local = false;
1497
1498 for (arg = DECL_ARGUMENTS (current_function_decl); arg;
1499 arg = DECL_CHAIN (arg))
1500 {
1501 rtx x, reg = DECL_INCOMING_RTL (arg);
1502 int uns1, uns3;
1503 enum machine_mode mode1, mode2, mode3, mode4;
1504
1505 /* Only continue if the incoming argument is in a register. */
1506 if (!REG_P (reg))
1507 continue;
1508
1509 /* Determine, if possible, whether all call sites of the current
1510 function lie within the current compilation unit. (This does
1511 take into account the exporting of a function via taking its
1512 address, and so forth.) */
1513 strictly_local = cgraph_local_info (current_function_decl)->local;
1514
1515 /* The mode and signedness of the argument before any promotions happen
1516 (equal to the mode of the pseudo holding it at that stage). */
1517 mode1 = TYPE_MODE (TREE_TYPE (arg));
1518 uns1 = TYPE_UNSIGNED (TREE_TYPE (arg));
1519
1520 /* The mode and signedness of the argument after any source language and
1521 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1522 mode2 = TYPE_MODE (DECL_ARG_TYPE (arg));
1523 uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg));
1524
1525 /* The mode and signedness of the argument as it is actually passed,
1526 after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions. */
1527 mode3 = promote_function_mode (DECL_ARG_TYPE (arg), mode2, &uns3,
1528 TREE_TYPE (cfun->decl), 0);
1529
1530 /* The mode of the register in which the argument is being passed. */
1531 mode4 = GET_MODE (reg);
1532
1533 /* Eliminate sign extensions in the callee when:
1534 (a) A mode promotion has occurred; */
1535 if (mode1 == mode3)
1536 continue;
1537 /* (b) The mode of the register is the same as the mode of
1538 the argument as it is passed; */
1539 if (mode3 != mode4)
1540 continue;
1541 /* (c) There's no language level extension; */
1542 if (mode1 == mode2)
1543 ;
1544 /* (c.1) All callers are from the current compilation unit. If that's
1545 the case we don't have to rely on an ABI, we only have to know
1546 what we're generating right now, and we know that we will do the
1547 mode1 to mode2 promotion with the given sign. */
1548 else if (!strictly_local)
1549 continue;
1550 /* (c.2) The combination of the two promotions is useful. This is
1551 true when the signs match, or if the first promotion is unsigned.
1552 In the later case, (sign_extend (zero_extend x)) is the same as
1553 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1554 else if (uns1)
1555 uns3 = true;
1556 else if (uns3)
1557 continue;
1558
1559 /* Record that the value was promoted from mode1 to mode3,
1560 so that any sign extension at the head of the current
1561 function may be eliminated. */
1562 x = gen_rtx_CLOBBER (mode1, const0_rtx);
1563 x = gen_rtx_fmt_e ((uns3 ? ZERO_EXTEND : SIGN_EXTEND), mode3, x);
1564 record_value_for_reg (reg, first, x);
1565 }
1566 }
1567
1568 /* Called via note_stores. If X is a pseudo that is narrower than
1569 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1570
1571 If we are setting only a portion of X and we can't figure out what
1572 portion, assume all bits will be used since we don't know what will
1573 be happening.
1574
1575 Similarly, set how many bits of X are known to be copies of the sign bit
1576 at all locations in the function. This is the smallest number implied
1577 by any set of X. */
1578
1579 static void
set_nonzero_bits_and_sign_copies(rtx x,const_rtx set,void * data)1580 set_nonzero_bits_and_sign_copies (rtx x, const_rtx set, void *data)
1581 {
1582 rtx insn = (rtx) data;
1583 unsigned int num;
1584
1585 if (REG_P (x)
1586 && REGNO (x) >= FIRST_PSEUDO_REGISTER
1587 /* If this register is undefined at the start of the file, we can't
1588 say what its contents were. */
1589 && ! REGNO_REG_SET_P
1590 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x))
1591 && HWI_COMPUTABLE_MODE_P (GET_MODE (x)))
1592 {
1593 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
1594
1595 if (set == 0 || GET_CODE (set) == CLOBBER)
1596 {
1597 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1598 rsp->sign_bit_copies = 1;
1599 return;
1600 }
1601
1602 /* If this register is being initialized using itself, and the
1603 register is uninitialized in this basic block, and there are
1604 no LOG_LINKS which set the register, then part of the
1605 register is uninitialized. In that case we can't assume
1606 anything about the number of nonzero bits.
1607
1608 ??? We could do better if we checked this in
1609 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1610 could avoid making assumptions about the insn which initially
1611 sets the register, while still using the information in other
1612 insns. We would have to be careful to check every insn
1613 involved in the combination. */
1614
1615 if (insn
1616 && reg_referenced_p (x, PATTERN (insn))
1617 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn)),
1618 REGNO (x)))
1619 {
1620 struct insn_link *link;
1621
1622 FOR_EACH_LOG_LINK (link, insn)
1623 if (dead_or_set_p (link->insn, x))
1624 break;
1625 if (!link)
1626 {
1627 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1628 rsp->sign_bit_copies = 1;
1629 return;
1630 }
1631 }
1632
1633 /* If this is a complex assignment, see if we can convert it into a
1634 simple assignment. */
1635 set = expand_field_assignment (set);
1636
1637 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1638 set what we know about X. */
1639
1640 if (SET_DEST (set) == x
1641 || (paradoxical_subreg_p (SET_DEST (set))
1642 && SUBREG_REG (SET_DEST (set)) == x))
1643 {
1644 rtx src = SET_SRC (set);
1645
1646 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1647 /* If X is narrower than a word and SRC is a non-negative
1648 constant that would appear negative in the mode of X,
1649 sign-extend it for use in reg_stat[].nonzero_bits because some
1650 machines (maybe most) will actually do the sign-extension
1651 and this is the conservative approach.
1652
1653 ??? For 2.5, try to tighten up the MD files in this regard
1654 instead of this kludge. */
1655
1656 if (GET_MODE_PRECISION (GET_MODE (x)) < BITS_PER_WORD
1657 && CONST_INT_P (src)
1658 && INTVAL (src) > 0
1659 && val_signbit_known_set_p (GET_MODE (x), INTVAL (src)))
1660 src = GEN_INT (INTVAL (src) | ~GET_MODE_MASK (GET_MODE (x)));
1661 #endif
1662
1663 /* Don't call nonzero_bits if it cannot change anything. */
1664 if (rsp->nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1665 rsp->nonzero_bits |= nonzero_bits (src, nonzero_bits_mode);
1666 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1667 if (rsp->sign_bit_copies == 0
1668 || rsp->sign_bit_copies > num)
1669 rsp->sign_bit_copies = num;
1670 }
1671 else
1672 {
1673 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1674 rsp->sign_bit_copies = 1;
1675 }
1676 }
1677 }
1678
1679 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1680 optionally insns that were previously combined into I3 or that will be
1681 combined into the merger of INSN and I3. The order is PRED, PRED2,
1682 INSN, SUCC, SUCC2, I3.
1683
1684 Return 0 if the combination is not allowed for any reason.
1685
1686 If the combination is allowed, *PDEST will be set to the single
1687 destination of INSN and *PSRC to the single source, and this function
1688 will return 1. */
1689
1690 static int
can_combine_p(rtx insn,rtx i3,rtx pred ATTRIBUTE_UNUSED,rtx pred2 ATTRIBUTE_UNUSED,rtx succ,rtx succ2,rtx * pdest,rtx * psrc)1691 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED,
1692 rtx pred2 ATTRIBUTE_UNUSED, rtx succ, rtx succ2,
1693 rtx *pdest, rtx *psrc)
1694 {
1695 int i;
1696 const_rtx set = 0;
1697 rtx src, dest;
1698 rtx p;
1699 #ifdef AUTO_INC_DEC
1700 rtx link;
1701 #endif
1702 bool all_adjacent = true;
1703 int (*is_volatile_p) (const_rtx);
1704
1705 if (succ)
1706 {
1707 if (succ2)
1708 {
1709 if (next_active_insn (succ2) != i3)
1710 all_adjacent = false;
1711 if (next_active_insn (succ) != succ2)
1712 all_adjacent = false;
1713 }
1714 else if (next_active_insn (succ) != i3)
1715 all_adjacent = false;
1716 if (next_active_insn (insn) != succ)
1717 all_adjacent = false;
1718 }
1719 else if (next_active_insn (insn) != i3)
1720 all_adjacent = false;
1721
1722 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1723 or a PARALLEL consisting of such a SET and CLOBBERs.
1724
1725 If INSN has CLOBBER parallel parts, ignore them for our processing.
1726 By definition, these happen during the execution of the insn. When it
1727 is merged with another insn, all bets are off. If they are, in fact,
1728 needed and aren't also supplied in I3, they may be added by
1729 recog_for_combine. Otherwise, it won't match.
1730
1731 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1732 note.
1733
1734 Get the source and destination of INSN. If more than one, can't
1735 combine. */
1736
1737 if (GET_CODE (PATTERN (insn)) == SET)
1738 set = PATTERN (insn);
1739 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1740 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1741 {
1742 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1743 {
1744 rtx elt = XVECEXP (PATTERN (insn), 0, i);
1745
1746 switch (GET_CODE (elt))
1747 {
1748 /* This is important to combine floating point insns
1749 for the SH4 port. */
1750 case USE:
1751 /* Combining an isolated USE doesn't make sense.
1752 We depend here on combinable_i3pat to reject them. */
1753 /* The code below this loop only verifies that the inputs of
1754 the SET in INSN do not change. We call reg_set_between_p
1755 to verify that the REG in the USE does not change between
1756 I3 and INSN.
1757 If the USE in INSN was for a pseudo register, the matching
1758 insn pattern will likely match any register; combining this
1759 with any other USE would only be safe if we knew that the
1760 used registers have identical values, or if there was
1761 something to tell them apart, e.g. different modes. For
1762 now, we forgo such complicated tests and simply disallow
1763 combining of USES of pseudo registers with any other USE. */
1764 if (REG_P (XEXP (elt, 0))
1765 && GET_CODE (PATTERN (i3)) == PARALLEL)
1766 {
1767 rtx i3pat = PATTERN (i3);
1768 int i = XVECLEN (i3pat, 0) - 1;
1769 unsigned int regno = REGNO (XEXP (elt, 0));
1770
1771 do
1772 {
1773 rtx i3elt = XVECEXP (i3pat, 0, i);
1774
1775 if (GET_CODE (i3elt) == USE
1776 && REG_P (XEXP (i3elt, 0))
1777 && (REGNO (XEXP (i3elt, 0)) == regno
1778 ? reg_set_between_p (XEXP (elt, 0),
1779 PREV_INSN (insn), i3)
1780 : regno >= FIRST_PSEUDO_REGISTER))
1781 return 0;
1782 }
1783 while (--i >= 0);
1784 }
1785 break;
1786
1787 /* We can ignore CLOBBERs. */
1788 case CLOBBER:
1789 break;
1790
1791 case SET:
1792 /* Ignore SETs whose result isn't used but not those that
1793 have side-effects. */
1794 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1795 && insn_nothrow_p (insn)
1796 && !side_effects_p (elt))
1797 break;
1798
1799 /* If we have already found a SET, this is a second one and
1800 so we cannot combine with this insn. */
1801 if (set)
1802 return 0;
1803
1804 set = elt;
1805 break;
1806
1807 default:
1808 /* Anything else means we can't combine. */
1809 return 0;
1810 }
1811 }
1812
1813 if (set == 0
1814 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1815 so don't do anything with it. */
1816 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1817 return 0;
1818 }
1819 else
1820 return 0;
1821
1822 if (set == 0)
1823 return 0;
1824
1825 /* The simplification in expand_field_assignment may call back to
1826 get_last_value, so set safe guard here. */
1827 subst_low_luid = DF_INSN_LUID (insn);
1828
1829 set = expand_field_assignment (set);
1830 src = SET_SRC (set), dest = SET_DEST (set);
1831
1832 /* Don't eliminate a store in the stack pointer. */
1833 if (dest == stack_pointer_rtx
1834 /* Don't combine with an insn that sets a register to itself if it has
1835 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1836 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1837 /* Can't merge an ASM_OPERANDS. */
1838 || GET_CODE (src) == ASM_OPERANDS
1839 /* Can't merge a function call. */
1840 || GET_CODE (src) == CALL
1841 /* Don't eliminate a function call argument. */
1842 || (CALL_P (i3)
1843 && (find_reg_fusage (i3, USE, dest)
1844 || (REG_P (dest)
1845 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1846 && global_regs[REGNO (dest)])))
1847 /* Don't substitute into an incremented register. */
1848 || FIND_REG_INC_NOTE (i3, dest)
1849 || (succ && FIND_REG_INC_NOTE (succ, dest))
1850 || (succ2 && FIND_REG_INC_NOTE (succ2, dest))
1851 /* Don't substitute into a non-local goto, this confuses CFG. */
1852 || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1853 /* Make sure that DEST is not used after SUCC but before I3. */
1854 || (!all_adjacent
1855 && ((succ2
1856 && (reg_used_between_p (dest, succ2, i3)
1857 || reg_used_between_p (dest, succ, succ2)))
1858 || (!succ2 && succ && reg_used_between_p (dest, succ, i3))))
1859 /* Make sure that the value that is to be substituted for the register
1860 does not use any registers whose values alter in between. However,
1861 If the insns are adjacent, a use can't cross a set even though we
1862 think it might (this can happen for a sequence of insns each setting
1863 the same destination; last_set of that register might point to
1864 a NOTE). If INSN has a REG_EQUIV note, the register is always
1865 equivalent to the memory so the substitution is valid even if there
1866 are intervening stores. Also, don't move a volatile asm or
1867 UNSPEC_VOLATILE across any other insns. */
1868 || (! all_adjacent
1869 && (((!MEM_P (src)
1870 || ! find_reg_note (insn, REG_EQUIV, src))
1871 && use_crosses_set_p (src, DF_INSN_LUID (insn)))
1872 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1873 || GET_CODE (src) == UNSPEC_VOLATILE))
1874 /* Don't combine across a CALL_INSN, because that would possibly
1875 change whether the life span of some REGs crosses calls or not,
1876 and it is a pain to update that information.
1877 Exception: if source is a constant, moving it later can't hurt.
1878 Accept that as a special case. */
1879 || (DF_INSN_LUID (insn) < last_call_luid && ! CONSTANT_P (src)))
1880 return 0;
1881
1882 /* DEST must either be a REG or CC0. */
1883 if (REG_P (dest))
1884 {
1885 /* If register alignment is being enforced for multi-word items in all
1886 cases except for parameters, it is possible to have a register copy
1887 insn referencing a hard register that is not allowed to contain the
1888 mode being copied and which would not be valid as an operand of most
1889 insns. Eliminate this problem by not combining with such an insn.
1890
1891 Also, on some machines we don't want to extend the life of a hard
1892 register. */
1893
1894 if (REG_P (src)
1895 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1896 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1897 /* Don't extend the life of a hard register unless it is
1898 user variable (if we have few registers) or it can't
1899 fit into the desired register (meaning something special
1900 is going on).
1901 Also avoid substituting a return register into I3, because
1902 reload can't handle a conflict with constraints of other
1903 inputs. */
1904 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1905 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1906 return 0;
1907 }
1908 else if (GET_CODE (dest) != CC0)
1909 return 0;
1910
1911
1912 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1913 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1914 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1915 {
1916 /* Don't substitute for a register intended as a clobberable
1917 operand. */
1918 rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1919 if (rtx_equal_p (reg, dest))
1920 return 0;
1921
1922 /* If the clobber represents an earlyclobber operand, we must not
1923 substitute an expression containing the clobbered register.
1924 As we do not analyze the constraint strings here, we have to
1925 make the conservative assumption. However, if the register is
1926 a fixed hard reg, the clobber cannot represent any operand;
1927 we leave it up to the machine description to either accept or
1928 reject use-and-clobber patterns. */
1929 if (!REG_P (reg)
1930 || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1931 || !fixed_regs[REGNO (reg)])
1932 if (reg_overlap_mentioned_p (reg, src))
1933 return 0;
1934 }
1935
1936 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1937 or not), reject, unless nothing volatile comes between it and I3 */
1938
1939 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1940 {
1941 /* Make sure neither succ nor succ2 contains a volatile reference. */
1942 if (succ2 != 0 && volatile_refs_p (PATTERN (succ2)))
1943 return 0;
1944 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1945 return 0;
1946 /* We'll check insns between INSN and I3 below. */
1947 }
1948
1949 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1950 to be an explicit register variable, and was chosen for a reason. */
1951
1952 if (GET_CODE (src) == ASM_OPERANDS
1953 && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1954 return 0;
1955
1956 /* If INSN contains volatile references (specifically volatile MEMs),
1957 we cannot combine across any other volatile references.
1958 Even if INSN doesn't contain volatile references, any intervening
1959 volatile insn might affect machine state. */
1960
1961 is_volatile_p = volatile_refs_p (PATTERN (insn))
1962 ? volatile_refs_p
1963 : volatile_insn_p;
1964
1965 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1966 if (INSN_P (p) && p != succ && p != succ2 && is_volatile_p (PATTERN (p)))
1967 return 0;
1968
1969 /* If INSN contains an autoincrement or autodecrement, make sure that
1970 register is not used between there and I3, and not already used in
1971 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1972 Also insist that I3 not be a jump; if it were one
1973 and the incremented register were spilled, we would lose. */
1974
1975 #ifdef AUTO_INC_DEC
1976 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1977 if (REG_NOTE_KIND (link) == REG_INC
1978 && (JUMP_P (i3)
1979 || reg_used_between_p (XEXP (link, 0), insn, i3)
1980 || (pred != NULL_RTX
1981 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
1982 || (pred2 != NULL_RTX
1983 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred2)))
1984 || (succ != NULL_RTX
1985 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
1986 || (succ2 != NULL_RTX
1987 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ2)))
1988 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1989 return 0;
1990 #endif
1991
1992 #ifdef HAVE_cc0
1993 /* Don't combine an insn that follows a CC0-setting insn.
1994 An insn that uses CC0 must not be separated from the one that sets it.
1995 We do, however, allow I2 to follow a CC0-setting insn if that insn
1996 is passed as I1; in that case it will be deleted also.
1997 We also allow combining in this case if all the insns are adjacent
1998 because that would leave the two CC0 insns adjacent as well.
1999 It would be more logical to test whether CC0 occurs inside I1 or I2,
2000 but that would be much slower, and this ought to be equivalent. */
2001
2002 p = prev_nonnote_insn (insn);
2003 if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
2004 && ! all_adjacent)
2005 return 0;
2006 #endif
2007
2008 /* If we get here, we have passed all the tests and the combination is
2009 to be allowed. */
2010
2011 *pdest = dest;
2012 *psrc = src;
2013
2014 return 1;
2015 }
2016
2017 /* LOC is the location within I3 that contains its pattern or the component
2018 of a PARALLEL of the pattern. We validate that it is valid for combining.
2019
2020 One problem is if I3 modifies its output, as opposed to replacing it
2021 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2022 doing so would produce an insn that is not equivalent to the original insns.
2023
2024 Consider:
2025
2026 (set (reg:DI 101) (reg:DI 100))
2027 (set (subreg:SI (reg:DI 101) 0) <foo>)
2028
2029 This is NOT equivalent to:
2030
2031 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2032 (set (reg:DI 101) (reg:DI 100))])
2033
2034 Not only does this modify 100 (in which case it might still be valid
2035 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2036
2037 We can also run into a problem if I2 sets a register that I1
2038 uses and I1 gets directly substituted into I3 (not via I2). In that
2039 case, we would be getting the wrong value of I2DEST into I3, so we
2040 must reject the combination. This case occurs when I2 and I1 both
2041 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2042 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2043 of a SET must prevent combination from occurring. The same situation
2044 can occur for I0, in which case I0_NOT_IN_SRC is set.
2045
2046 Before doing the above check, we first try to expand a field assignment
2047 into a set of logical operations.
2048
2049 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2050 we place a register that is both set and used within I3. If more than one
2051 such register is detected, we fail.
2052
2053 Return 1 if the combination is valid, zero otherwise. */
2054
2055 static int
combinable_i3pat(rtx i3,rtx * loc,rtx i2dest,rtx i1dest,rtx i0dest,int i1_not_in_src,int i0_not_in_src,rtx * pi3dest_killed)2056 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest, rtx i0dest,
2057 int i1_not_in_src, int i0_not_in_src, rtx *pi3dest_killed)
2058 {
2059 rtx x = *loc;
2060
2061 if (GET_CODE (x) == SET)
2062 {
2063 rtx set = x ;
2064 rtx dest = SET_DEST (set);
2065 rtx src = SET_SRC (set);
2066 rtx inner_dest = dest;
2067 rtx subdest;
2068
2069 while (GET_CODE (inner_dest) == STRICT_LOW_PART
2070 || GET_CODE (inner_dest) == SUBREG
2071 || GET_CODE (inner_dest) == ZERO_EXTRACT)
2072 inner_dest = XEXP (inner_dest, 0);
2073
2074 /* Check for the case where I3 modifies its output, as discussed
2075 above. We don't want to prevent pseudos from being combined
2076 into the address of a MEM, so only prevent the combination if
2077 i1 or i2 set the same MEM. */
2078 if ((inner_dest != dest &&
2079 (!MEM_P (inner_dest)
2080 || rtx_equal_p (i2dest, inner_dest)
2081 || (i1dest && rtx_equal_p (i1dest, inner_dest))
2082 || (i0dest && rtx_equal_p (i0dest, inner_dest)))
2083 && (reg_overlap_mentioned_p (i2dest, inner_dest)
2084 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))
2085 || (i0dest && reg_overlap_mentioned_p (i0dest, inner_dest))))
2086
2087 /* This is the same test done in can_combine_p except we can't test
2088 all_adjacent; we don't have to, since this instruction will stay
2089 in place, thus we are not considering increasing the lifetime of
2090 INNER_DEST.
2091
2092 Also, if this insn sets a function argument, combining it with
2093 something that might need a spill could clobber a previous
2094 function argument; the all_adjacent test in can_combine_p also
2095 checks this; here, we do a more specific test for this case. */
2096
2097 || (REG_P (inner_dest)
2098 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
2099 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
2100 GET_MODE (inner_dest))))
2101 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src))
2102 || (i0_not_in_src && reg_overlap_mentioned_p (i0dest, src)))
2103 return 0;
2104
2105 /* If DEST is used in I3, it is being killed in this insn, so
2106 record that for later. We have to consider paradoxical
2107 subregs here, since they kill the whole register, but we
2108 ignore partial subregs, STRICT_LOW_PART, etc.
2109 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2110 STACK_POINTER_REGNUM, since these are always considered to be
2111 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2112 subdest = dest;
2113 if (GET_CODE (subdest) == SUBREG
2114 && (GET_MODE_SIZE (GET_MODE (subdest))
2115 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
2116 subdest = SUBREG_REG (subdest);
2117 if (pi3dest_killed
2118 && REG_P (subdest)
2119 && reg_referenced_p (subdest, PATTERN (i3))
2120 && REGNO (subdest) != FRAME_POINTER_REGNUM
2121 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
2122 && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
2123 #endif
2124 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
2125 && (REGNO (subdest) != ARG_POINTER_REGNUM
2126 || ! fixed_regs [REGNO (subdest)])
2127 #endif
2128 && REGNO (subdest) != STACK_POINTER_REGNUM)
2129 {
2130 if (*pi3dest_killed)
2131 return 0;
2132
2133 *pi3dest_killed = subdest;
2134 }
2135 }
2136
2137 else if (GET_CODE (x) == PARALLEL)
2138 {
2139 int i;
2140
2141 for (i = 0; i < XVECLEN (x, 0); i++)
2142 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest, i0dest,
2143 i1_not_in_src, i0_not_in_src, pi3dest_killed))
2144 return 0;
2145 }
2146
2147 return 1;
2148 }
2149
2150 /* Return 1 if X is an arithmetic expression that contains a multiplication
2151 and division. We don't count multiplications by powers of two here. */
2152
2153 static int
contains_muldiv(rtx x)2154 contains_muldiv (rtx x)
2155 {
2156 switch (GET_CODE (x))
2157 {
2158 case MOD: case DIV: case UMOD: case UDIV:
2159 return 1;
2160
2161 case MULT:
2162 return ! (CONST_INT_P (XEXP (x, 1))
2163 && exact_log2 (UINTVAL (XEXP (x, 1))) >= 0);
2164 default:
2165 if (BINARY_P (x))
2166 return contains_muldiv (XEXP (x, 0))
2167 || contains_muldiv (XEXP (x, 1));
2168
2169 if (UNARY_P (x))
2170 return contains_muldiv (XEXP (x, 0));
2171
2172 return 0;
2173 }
2174 }
2175
2176 /* Determine whether INSN can be used in a combination. Return nonzero if
2177 not. This is used in try_combine to detect early some cases where we
2178 can't perform combinations. */
2179
2180 static int
cant_combine_insn_p(rtx insn)2181 cant_combine_insn_p (rtx insn)
2182 {
2183 rtx set;
2184 rtx src, dest;
2185
2186 /* If this isn't really an insn, we can't do anything.
2187 This can occur when flow deletes an insn that it has merged into an
2188 auto-increment address. */
2189 if (! INSN_P (insn))
2190 return 1;
2191
2192 /* Never combine loads and stores involving hard regs that are likely
2193 to be spilled. The register allocator can usually handle such
2194 reg-reg moves by tying. If we allow the combiner to make
2195 substitutions of likely-spilled regs, reload might die.
2196 As an exception, we allow combinations involving fixed regs; these are
2197 not available to the register allocator so there's no risk involved. */
2198
2199 set = single_set (insn);
2200 if (! set)
2201 return 0;
2202 src = SET_SRC (set);
2203 dest = SET_DEST (set);
2204 if (GET_CODE (src) == SUBREG)
2205 src = SUBREG_REG (src);
2206 if (GET_CODE (dest) == SUBREG)
2207 dest = SUBREG_REG (dest);
2208 if (REG_P (src) && REG_P (dest)
2209 && ((HARD_REGISTER_P (src)
2210 && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (src))
2211 && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (src))))
2212 || (HARD_REGISTER_P (dest)
2213 && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (dest))
2214 && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest))))))
2215 return 1;
2216
2217 return 0;
2218 }
2219
2220 struct likely_spilled_retval_info
2221 {
2222 unsigned regno, nregs;
2223 unsigned mask;
2224 };
2225
2226 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2227 hard registers that are known to be written to / clobbered in full. */
2228 static void
likely_spilled_retval_1(rtx x,const_rtx set,void * data)2229 likely_spilled_retval_1 (rtx x, const_rtx set, void *data)
2230 {
2231 struct likely_spilled_retval_info *const info =
2232 (struct likely_spilled_retval_info *) data;
2233 unsigned regno, nregs;
2234 unsigned new_mask;
2235
2236 if (!REG_P (XEXP (set, 0)))
2237 return;
2238 regno = REGNO (x);
2239 if (regno >= info->regno + info->nregs)
2240 return;
2241 nregs = hard_regno_nregs[regno][GET_MODE (x)];
2242 if (regno + nregs <= info->regno)
2243 return;
2244 new_mask = (2U << (nregs - 1)) - 1;
2245 if (regno < info->regno)
2246 new_mask >>= info->regno - regno;
2247 else
2248 new_mask <<= regno - info->regno;
2249 info->mask &= ~new_mask;
2250 }
2251
2252 /* Return nonzero iff part of the return value is live during INSN, and
2253 it is likely spilled. This can happen when more than one insn is needed
2254 to copy the return value, e.g. when we consider to combine into the
2255 second copy insn for a complex value. */
2256
2257 static int
likely_spilled_retval_p(rtx insn)2258 likely_spilled_retval_p (rtx insn)
2259 {
2260 rtx use = BB_END (this_basic_block);
2261 rtx reg, p;
2262 unsigned regno, nregs;
2263 /* We assume here that no machine mode needs more than
2264 32 hard registers when the value overlaps with a register
2265 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2266 unsigned mask;
2267 struct likely_spilled_retval_info info;
2268
2269 if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
2270 return 0;
2271 reg = XEXP (PATTERN (use), 0);
2272 if (!REG_P (reg) || !targetm.calls.function_value_regno_p (REGNO (reg)))
2273 return 0;
2274 regno = REGNO (reg);
2275 nregs = hard_regno_nregs[regno][GET_MODE (reg)];
2276 if (nregs == 1)
2277 return 0;
2278 mask = (2U << (nregs - 1)) - 1;
2279
2280 /* Disregard parts of the return value that are set later. */
2281 info.regno = regno;
2282 info.nregs = nregs;
2283 info.mask = mask;
2284 for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
2285 if (INSN_P (p))
2286 note_stores (PATTERN (p), likely_spilled_retval_1, &info);
2287 mask = info.mask;
2288
2289 /* Check if any of the (probably) live return value registers is
2290 likely spilled. */
2291 nregs --;
2292 do
2293 {
2294 if ((mask & 1 << nregs)
2295 && targetm.class_likely_spilled_p (REGNO_REG_CLASS (regno + nregs)))
2296 return 1;
2297 } while (nregs--);
2298 return 0;
2299 }
2300
2301 /* Adjust INSN after we made a change to its destination.
2302
2303 Changing the destination can invalidate notes that say something about
2304 the results of the insn and a LOG_LINK pointing to the insn. */
2305
2306 static void
adjust_for_new_dest(rtx insn)2307 adjust_for_new_dest (rtx insn)
2308 {
2309 /* For notes, be conservative and simply remove them. */
2310 remove_reg_equal_equiv_notes (insn);
2311
2312 /* The new insn will have a destination that was previously the destination
2313 of an insn just above it. Call distribute_links to make a LOG_LINK from
2314 the next use of that destination. */
2315 distribute_links (alloc_insn_link (insn, NULL));
2316
2317 df_insn_rescan (insn);
2318 }
2319
2320 /* Return TRUE if combine can reuse reg X in mode MODE.
2321 ADDED_SETS is nonzero if the original set is still required. */
2322 static bool
can_change_dest_mode(rtx x,int added_sets,enum machine_mode mode)2323 can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode)
2324 {
2325 unsigned int regno;
2326
2327 if (!REG_P(x))
2328 return false;
2329
2330 regno = REGNO (x);
2331 /* Allow hard registers if the new mode is legal, and occupies no more
2332 registers than the old mode. */
2333 if (regno < FIRST_PSEUDO_REGISTER)
2334 return (HARD_REGNO_MODE_OK (regno, mode)
2335 && (hard_regno_nregs[regno][GET_MODE (x)]
2336 >= hard_regno_nregs[regno][mode]));
2337
2338 /* Or a pseudo that is only used once. */
2339 return (REG_N_SETS (regno) == 1 && !added_sets
2340 && !REG_USERVAR_P (x));
2341 }
2342
2343
2344 /* Check whether X, the destination of a set, refers to part of
2345 the register specified by REG. */
2346
2347 static bool
reg_subword_p(rtx x,rtx reg)2348 reg_subword_p (rtx x, rtx reg)
2349 {
2350 /* Check that reg is an integer mode register. */
2351 if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
2352 return false;
2353
2354 if (GET_CODE (x) == STRICT_LOW_PART
2355 || GET_CODE (x) == ZERO_EXTRACT)
2356 x = XEXP (x, 0);
2357
2358 return GET_CODE (x) == SUBREG
2359 && SUBREG_REG (x) == reg
2360 && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
2361 }
2362
2363 #ifdef AUTO_INC_DEC
2364 /* Replace auto-increment addressing modes with explicit operations to access
2365 the same addresses without modifying the corresponding registers. */
2366
2367 static rtx
cleanup_auto_inc_dec(rtx src,enum machine_mode mem_mode)2368 cleanup_auto_inc_dec (rtx src, enum machine_mode mem_mode)
2369 {
2370 rtx x = src;
2371 const RTX_CODE code = GET_CODE (x);
2372 int i;
2373 const char *fmt;
2374
2375 switch (code)
2376 {
2377 case REG:
2378 case CONST_INT:
2379 case CONST_DOUBLE:
2380 case CONST_FIXED:
2381 case CONST_VECTOR:
2382 case SYMBOL_REF:
2383 case CODE_LABEL:
2384 case PC:
2385 case CC0:
2386 case SCRATCH:
2387 /* SCRATCH must be shared because they represent distinct values. */
2388 return x;
2389 case CLOBBER:
2390 if (REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
2391 return x;
2392 break;
2393
2394 case CONST:
2395 if (shared_const_p (x))
2396 return x;
2397 break;
2398
2399 case MEM:
2400 mem_mode = GET_MODE (x);
2401 break;
2402
2403 case PRE_INC:
2404 case PRE_DEC:
2405 gcc_assert (mem_mode != VOIDmode && mem_mode != BLKmode);
2406 return gen_rtx_PLUS (GET_MODE (x),
2407 cleanup_auto_inc_dec (XEXP (x, 0), mem_mode),
2408 GEN_INT (code == PRE_INC
2409 ? GET_MODE_SIZE (mem_mode)
2410 : -GET_MODE_SIZE (mem_mode)));
2411
2412 case POST_INC:
2413 case POST_DEC:
2414 case PRE_MODIFY:
2415 case POST_MODIFY:
2416 return cleanup_auto_inc_dec (code == PRE_MODIFY
2417 ? XEXP (x, 1) : XEXP (x, 0),
2418 mem_mode);
2419
2420 default:
2421 break;
2422 }
2423
2424 /* Copy the various flags, fields, and other information. We assume
2425 that all fields need copying, and then clear the fields that should
2426 not be copied. That is the sensible default behavior, and forces
2427 us to explicitly document why we are *not* copying a flag. */
2428 x = shallow_copy_rtx (x);
2429
2430 /* We do not copy the USED flag, which is used as a mark bit during
2431 walks over the RTL. */
2432 RTX_FLAG (x, used) = 0;
2433
2434 /* We do not copy FRAME_RELATED for INSNs. */
2435 if (INSN_P (x))
2436 RTX_FLAG (x, frame_related) = 0;
2437
2438 fmt = GET_RTX_FORMAT (code);
2439 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2440 if (fmt[i] == 'e')
2441 XEXP (x, i) = cleanup_auto_inc_dec (XEXP (x, i), mem_mode);
2442 else if (fmt[i] == 'E' || fmt[i] == 'V')
2443 {
2444 int j;
2445 XVEC (x, i) = rtvec_alloc (XVECLEN (x, i));
2446 for (j = 0; j < XVECLEN (x, i); j++)
2447 XVECEXP (x, i, j)
2448 = cleanup_auto_inc_dec (XVECEXP (src, i, j), mem_mode);
2449 }
2450
2451 return x;
2452 }
2453 #endif
2454
2455 /* Auxiliary data structure for propagate_for_debug_stmt. */
2456
2457 struct rtx_subst_pair
2458 {
2459 rtx to;
2460 bool adjusted;
2461 };
2462
2463 /* DATA points to an rtx_subst_pair. Return the value that should be
2464 substituted. */
2465
2466 static rtx
propagate_for_debug_subst(rtx from,const_rtx old_rtx,void * data)2467 propagate_for_debug_subst (rtx from, const_rtx old_rtx, void *data)
2468 {
2469 struct rtx_subst_pair *pair = (struct rtx_subst_pair *)data;
2470
2471 if (!rtx_equal_p (from, old_rtx))
2472 return NULL_RTX;
2473 if (!pair->adjusted)
2474 {
2475 pair->adjusted = true;
2476 #ifdef AUTO_INC_DEC
2477 pair->to = cleanup_auto_inc_dec (pair->to, VOIDmode);
2478 #else
2479 pair->to = copy_rtx (pair->to);
2480 #endif
2481 pair->to = make_compound_operation (pair->to, SET);
2482 return pair->to;
2483 }
2484 return copy_rtx (pair->to);
2485 }
2486
2487 /* Replace all the occurrences of DEST with SRC in DEBUG_INSNs between INSN
2488 and LAST, not including INSN, but including LAST. Also stop at the end
2489 of THIS_BASIC_BLOCK. */
2490
2491 static void
propagate_for_debug(rtx insn,rtx last,rtx dest,rtx src)2492 propagate_for_debug (rtx insn, rtx last, rtx dest, rtx src)
2493 {
2494 rtx next, loc, end = NEXT_INSN (BB_END (this_basic_block));
2495
2496 struct rtx_subst_pair p;
2497 p.to = src;
2498 p.adjusted = false;
2499
2500 next = NEXT_INSN (insn);
2501 last = NEXT_INSN (last);
2502 while (next != last && next != end)
2503 {
2504 insn = next;
2505 next = NEXT_INSN (insn);
2506 if (DEBUG_INSN_P (insn))
2507 {
2508 loc = simplify_replace_fn_rtx (INSN_VAR_LOCATION_LOC (insn),
2509 dest, propagate_for_debug_subst, &p);
2510 if (loc == INSN_VAR_LOCATION_LOC (insn))
2511 continue;
2512 INSN_VAR_LOCATION_LOC (insn) = loc;
2513 df_insn_rescan (insn);
2514 }
2515 }
2516 }
2517
2518 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2519 Note that the INSN should be deleted *after* removing dead edges, so
2520 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2521 but not for a (set (pc) (label_ref FOO)). */
2522
2523 static void
update_cfg_for_uncondjump(rtx insn)2524 update_cfg_for_uncondjump (rtx insn)
2525 {
2526 basic_block bb = BLOCK_FOR_INSN (insn);
2527 gcc_assert (BB_END (bb) == insn);
2528
2529 purge_dead_edges (bb);
2530
2531 delete_insn (insn);
2532 if (EDGE_COUNT (bb->succs) == 1)
2533 {
2534 rtx insn;
2535
2536 single_succ_edge (bb)->flags |= EDGE_FALLTHRU;
2537
2538 /* Remove barriers from the footer if there are any. */
2539 for (insn = bb->il.rtl->footer; insn; insn = NEXT_INSN (insn))
2540 if (BARRIER_P (insn))
2541 {
2542 if (PREV_INSN (insn))
2543 NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
2544 else
2545 bb->il.rtl->footer = NEXT_INSN (insn);
2546 if (NEXT_INSN (insn))
2547 PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
2548 }
2549 else if (LABEL_P (insn))
2550 break;
2551 }
2552 }
2553
2554 /* Try to combine the insns I0, I1 and I2 into I3.
2555 Here I0, I1 and I2 appear earlier than I3.
2556 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2557 I3.
2558
2559 If we are combining more than two insns and the resulting insn is not
2560 recognized, try splitting it into two insns. If that happens, I2 and I3
2561 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2562 Otherwise, I0, I1 and I2 are pseudo-deleted.
2563
2564 Return 0 if the combination does not work. Then nothing is changed.
2565 If we did the combination, return the insn at which combine should
2566 resume scanning.
2567
2568 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2569 new direct jump instruction.
2570
2571 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2572 been I3 passed to an earlier try_combine within the same basic
2573 block. */
2574
2575 static rtx
try_combine(rtx i3,rtx i2,rtx i1,rtx i0,int * new_direct_jump_p,rtx last_combined_insn)2576 try_combine (rtx i3, rtx i2, rtx i1, rtx i0, int *new_direct_jump_p,
2577 rtx last_combined_insn)
2578 {
2579 /* New patterns for I3 and I2, respectively. */
2580 rtx newpat, newi2pat = 0;
2581 rtvec newpat_vec_with_clobbers = 0;
2582 int substed_i2 = 0, substed_i1 = 0, substed_i0 = 0;
2583 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2584 dead. */
2585 int added_sets_0, added_sets_1, added_sets_2;
2586 /* Total number of SETs to put into I3. */
2587 int total_sets;
2588 /* Nonzero if I2's or I1's body now appears in I3. */
2589 int i2_is_used = 0, i1_is_used = 0;
2590 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2591 int insn_code_number, i2_code_number = 0, other_code_number = 0;
2592 /* Contains I3 if the destination of I3 is used in its source, which means
2593 that the old life of I3 is being killed. If that usage is placed into
2594 I2 and not in I3, a REG_DEAD note must be made. */
2595 rtx i3dest_killed = 0;
2596 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2597 rtx i2dest = 0, i2src = 0, i1dest = 0, i1src = 0, i0dest = 0, i0src = 0;
2598 /* Copy of SET_SRC of I1 and I0, if needed. */
2599 rtx i1src_copy = 0, i0src_copy = 0, i0src_copy2 = 0;
2600 /* Set if I2DEST was reused as a scratch register. */
2601 bool i2scratch = false;
2602 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2603 rtx i0pat = 0, i1pat = 0, i2pat = 0;
2604 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2605 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
2606 int i0dest_in_i0src = 0, i1dest_in_i0src = 0, i2dest_in_i0src = 0;
2607 int i2dest_killed = 0, i1dest_killed = 0, i0dest_killed = 0;
2608 int i1_feeds_i2_n = 0, i0_feeds_i2_n = 0, i0_feeds_i1_n = 0;
2609 /* Notes that must be added to REG_NOTES in I3 and I2. */
2610 rtx new_i3_notes, new_i2_notes;
2611 /* Notes that we substituted I3 into I2 instead of the normal case. */
2612 int i3_subst_into_i2 = 0;
2613 /* Notes that I1, I2 or I3 is a MULT operation. */
2614 int have_mult = 0;
2615 int swap_i2i3 = 0;
2616 int changed_i3_dest = 0;
2617
2618 int maxreg;
2619 rtx temp;
2620 struct insn_link *link;
2621 rtx other_pat = 0;
2622 rtx new_other_notes;
2623 int i;
2624
2625 /* Only try four-insn combinations when there's high likelihood of
2626 success. Look for simple insns, such as loads of constants or
2627 binary operations involving a constant. */
2628 if (i0)
2629 {
2630 int i;
2631 int ngood = 0;
2632 int nshift = 0;
2633
2634 if (!flag_expensive_optimizations)
2635 return 0;
2636
2637 for (i = 0; i < 4; i++)
2638 {
2639 rtx insn = i == 0 ? i0 : i == 1 ? i1 : i == 2 ? i2 : i3;
2640 rtx set = single_set (insn);
2641 rtx src;
2642 if (!set)
2643 continue;
2644 src = SET_SRC (set);
2645 if (CONSTANT_P (src))
2646 {
2647 ngood += 2;
2648 break;
2649 }
2650 else if (BINARY_P (src) && CONSTANT_P (XEXP (src, 1)))
2651 ngood++;
2652 else if (GET_CODE (src) == ASHIFT || GET_CODE (src) == ASHIFTRT
2653 || GET_CODE (src) == LSHIFTRT)
2654 nshift++;
2655 }
2656 if (ngood < 2 && nshift < 2)
2657 return 0;
2658 }
2659
2660 /* Exit early if one of the insns involved can't be used for
2661 combinations. */
2662 if (cant_combine_insn_p (i3)
2663 || cant_combine_insn_p (i2)
2664 || (i1 && cant_combine_insn_p (i1))
2665 || (i0 && cant_combine_insn_p (i0))
2666 || likely_spilled_retval_p (i3))
2667 return 0;
2668
2669 combine_attempts++;
2670 undobuf.other_insn = 0;
2671
2672 /* Reset the hard register usage information. */
2673 CLEAR_HARD_REG_SET (newpat_used_regs);
2674
2675 if (dump_file && (dump_flags & TDF_DETAILS))
2676 {
2677 if (i0)
2678 fprintf (dump_file, "\nTrying %d, %d, %d -> %d:\n",
2679 INSN_UID (i0), INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2680 else if (i1)
2681 fprintf (dump_file, "\nTrying %d, %d -> %d:\n",
2682 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2683 else
2684 fprintf (dump_file, "\nTrying %d -> %d:\n",
2685 INSN_UID (i2), INSN_UID (i3));
2686 }
2687
2688 /* If multiple insns feed into one of I2 or I3, they can be in any
2689 order. To simplify the code below, reorder them in sequence. */
2690 if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i2))
2691 temp = i2, i2 = i0, i0 = temp;
2692 if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i1))
2693 temp = i1, i1 = i0, i0 = temp;
2694 if (i1 && DF_INSN_LUID (i1) > DF_INSN_LUID (i2))
2695 temp = i1, i1 = i2, i2 = temp;
2696
2697 added_links_insn = 0;
2698
2699 /* First check for one important special case that the code below will
2700 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2701 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2702 we may be able to replace that destination with the destination of I3.
2703 This occurs in the common code where we compute both a quotient and
2704 remainder into a structure, in which case we want to do the computation
2705 directly into the structure to avoid register-register copies.
2706
2707 Note that this case handles both multiple sets in I2 and also cases
2708 where I2 has a number of CLOBBERs inside the PARALLEL.
2709
2710 We make very conservative checks below and only try to handle the
2711 most common cases of this. For example, we only handle the case
2712 where I2 and I3 are adjacent to avoid making difficult register
2713 usage tests. */
2714
2715 if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
2716 && REG_P (SET_SRC (PATTERN (i3)))
2717 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
2718 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
2719 && GET_CODE (PATTERN (i2)) == PARALLEL
2720 && ! side_effects_p (SET_DEST (PATTERN (i3)))
2721 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2722 below would need to check what is inside (and reg_overlap_mentioned_p
2723 doesn't support those codes anyway). Don't allow those destinations;
2724 the resulting insn isn't likely to be recognized anyway. */
2725 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
2726 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
2727 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
2728 SET_DEST (PATTERN (i3)))
2729 && next_active_insn (i2) == i3)
2730 {
2731 rtx p2 = PATTERN (i2);
2732
2733 /* Make sure that the destination of I3,
2734 which we are going to substitute into one output of I2,
2735 is not used within another output of I2. We must avoid making this:
2736 (parallel [(set (mem (reg 69)) ...)
2737 (set (reg 69) ...)])
2738 which is not well-defined as to order of actions.
2739 (Besides, reload can't handle output reloads for this.)
2740
2741 The problem can also happen if the dest of I3 is a memory ref,
2742 if another dest in I2 is an indirect memory ref. */
2743 for (i = 0; i < XVECLEN (p2, 0); i++)
2744 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2745 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2746 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
2747 SET_DEST (XVECEXP (p2, 0, i))))
2748 break;
2749
2750 if (i == XVECLEN (p2, 0))
2751 for (i = 0; i < XVECLEN (p2, 0); i++)
2752 if (GET_CODE (XVECEXP (p2, 0, i)) == SET
2753 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
2754 {
2755 combine_merges++;
2756
2757 subst_insn = i3;
2758 subst_low_luid = DF_INSN_LUID (i2);
2759
2760 added_sets_2 = added_sets_1 = added_sets_0 = 0;
2761 i2src = SET_SRC (XVECEXP (p2, 0, i));
2762 i2dest = SET_DEST (XVECEXP (p2, 0, i));
2763 i2dest_killed = dead_or_set_p (i2, i2dest);
2764
2765 /* Replace the dest in I2 with our dest and make the resulting
2766 insn the new pattern for I3. Then skip to where we validate
2767 the pattern. Everything was set up above. */
2768 SUBST (SET_DEST (XVECEXP (p2, 0, i)), SET_DEST (PATTERN (i3)));
2769 newpat = p2;
2770 i3_subst_into_i2 = 1;
2771 goto validate_replacement;
2772 }
2773 }
2774
2775 /* If I2 is setting a pseudo to a constant and I3 is setting some
2776 sub-part of it to another constant, merge them by making a new
2777 constant. */
2778 if (i1 == 0
2779 && (temp = single_set (i2)) != 0
2780 && (CONST_INT_P (SET_SRC (temp))
2781 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
2782 && GET_CODE (PATTERN (i3)) == SET
2783 && (CONST_INT_P (SET_SRC (PATTERN (i3)))
2784 || GET_CODE (SET_SRC (PATTERN (i3))) == CONST_DOUBLE)
2785 && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp)))
2786 {
2787 rtx dest = SET_DEST (PATTERN (i3));
2788 int offset = -1;
2789 int width = 0;
2790
2791 if (GET_CODE (dest) == ZERO_EXTRACT)
2792 {
2793 if (CONST_INT_P (XEXP (dest, 1))
2794 && CONST_INT_P (XEXP (dest, 2)))
2795 {
2796 width = INTVAL (XEXP (dest, 1));
2797 offset = INTVAL (XEXP (dest, 2));
2798 dest = XEXP (dest, 0);
2799 if (BITS_BIG_ENDIAN)
2800 offset = GET_MODE_PRECISION (GET_MODE (dest)) - width - offset;
2801 }
2802 }
2803 else
2804 {
2805 if (GET_CODE (dest) == STRICT_LOW_PART)
2806 dest = XEXP (dest, 0);
2807 width = GET_MODE_PRECISION (GET_MODE (dest));
2808 offset = 0;
2809 }
2810
2811 if (offset >= 0)
2812 {
2813 /* If this is the low part, we're done. */
2814 if (subreg_lowpart_p (dest))
2815 ;
2816 /* Handle the case where inner is twice the size of outer. */
2817 else if (GET_MODE_PRECISION (GET_MODE (SET_DEST (temp)))
2818 == 2 * GET_MODE_PRECISION (GET_MODE (dest)))
2819 offset += GET_MODE_PRECISION (GET_MODE (dest));
2820 /* Otherwise give up for now. */
2821 else
2822 offset = -1;
2823 }
2824
2825 if (offset >= 0
2826 && (GET_MODE_PRECISION (GET_MODE (SET_DEST (temp)))
2827 <= HOST_BITS_PER_DOUBLE_INT))
2828 {
2829 double_int m, o, i;
2830 rtx inner = SET_SRC (PATTERN (i3));
2831 rtx outer = SET_SRC (temp);
2832
2833 o = rtx_to_double_int (outer);
2834 i = rtx_to_double_int (inner);
2835
2836 m = double_int_mask (width);
2837 i = double_int_and (i, m);
2838 m = double_int_lshift (m, offset, HOST_BITS_PER_DOUBLE_INT, false);
2839 i = double_int_lshift (i, offset, HOST_BITS_PER_DOUBLE_INT, false);
2840 o = double_int_ior (double_int_and_not (o, m), i);
2841
2842 combine_merges++;
2843 subst_insn = i3;
2844 subst_low_luid = DF_INSN_LUID (i2);
2845 added_sets_2 = added_sets_1 = added_sets_0 = 0;
2846 i2dest = SET_DEST (temp);
2847 i2dest_killed = dead_or_set_p (i2, i2dest);
2848
2849 /* Replace the source in I2 with the new constant and make the
2850 resulting insn the new pattern for I3. Then skip to where we
2851 validate the pattern. Everything was set up above. */
2852 SUBST (SET_SRC (temp),
2853 immed_double_int_const (o, GET_MODE (SET_DEST (temp))));
2854
2855 newpat = PATTERN (i2);
2856
2857 /* The dest of I3 has been replaced with the dest of I2. */
2858 changed_i3_dest = 1;
2859 goto validate_replacement;
2860 }
2861 }
2862
2863 #ifndef HAVE_cc0
2864 /* If we have no I1 and I2 looks like:
2865 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2866 (set Y OP)])
2867 make up a dummy I1 that is
2868 (set Y OP)
2869 and change I2 to be
2870 (set (reg:CC X) (compare:CC Y (const_int 0)))
2871
2872 (We can ignore any trailing CLOBBERs.)
2873
2874 This undoes a previous combination and allows us to match a branch-and-
2875 decrement insn. */
2876
2877 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
2878 && XVECLEN (PATTERN (i2), 0) >= 2
2879 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
2880 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2881 == MODE_CC)
2882 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2883 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2884 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
2885 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
2886 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2887 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
2888 {
2889 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
2890 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
2891 break;
2892
2893 if (i == 1)
2894 {
2895 /* We make I1 with the same INSN_UID as I2. This gives it
2896 the same DF_INSN_LUID for value tracking. Our fake I1 will
2897 never appear in the insn stream so giving it the same INSN_UID
2898 as I2 will not cause a problem. */
2899
2900 i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
2901 BLOCK_FOR_INSN (i2), XVECEXP (PATTERN (i2), 0, 1),
2902 INSN_LOCATOR (i2), -1, NULL_RTX);
2903
2904 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2905 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2906 SET_DEST (PATTERN (i1)));
2907 SUBST_LINK (LOG_LINKS (i2), alloc_insn_link (i1, LOG_LINKS (i2)));
2908 }
2909 }
2910 #endif
2911
2912 /* Verify that I2 and I1 are valid for combining. */
2913 if (! can_combine_p (i2, i3, i0, i1, NULL_RTX, NULL_RTX, &i2dest, &i2src)
2914 || (i1 && ! can_combine_p (i1, i3, i0, NULL_RTX, i2, NULL_RTX,
2915 &i1dest, &i1src))
2916 || (i0 && ! can_combine_p (i0, i3, NULL_RTX, NULL_RTX, i1, i2,
2917 &i0dest, &i0src)))
2918 {
2919 undo_all ();
2920 return 0;
2921 }
2922
2923 /* Record whether I2DEST is used in I2SRC and similarly for the other
2924 cases. Knowing this will help in register status updating below. */
2925 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2926 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2927 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2928 i0dest_in_i0src = i0 && reg_overlap_mentioned_p (i0dest, i0src);
2929 i1dest_in_i0src = i0 && reg_overlap_mentioned_p (i1dest, i0src);
2930 i2dest_in_i0src = i0 && reg_overlap_mentioned_p (i2dest, i0src);
2931 i2dest_killed = dead_or_set_p (i2, i2dest);
2932 i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2933 i0dest_killed = i0 && dead_or_set_p (i0, i0dest);
2934
2935 /* For the earlier insns, determine which of the subsequent ones they
2936 feed. */
2937 i1_feeds_i2_n = i1 && insn_a_feeds_b (i1, i2);
2938 i0_feeds_i1_n = i0 && insn_a_feeds_b (i0, i1);
2939 i0_feeds_i2_n = (i0 && (!i0_feeds_i1_n ? insn_a_feeds_b (i0, i2)
2940 : (!reg_overlap_mentioned_p (i1dest, i0dest)
2941 && reg_overlap_mentioned_p (i0dest, i2src))));
2942
2943 /* Ensure that I3's pattern can be the destination of combines. */
2944 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest, i0dest,
2945 i1 && i2dest_in_i1src && !i1_feeds_i2_n,
2946 i0 && ((i2dest_in_i0src && !i0_feeds_i2_n)
2947 || (i1dest_in_i0src && !i0_feeds_i1_n)),
2948 &i3dest_killed))
2949 {
2950 undo_all ();
2951 return 0;
2952 }
2953
2954 /* See if any of the insns is a MULT operation. Unless one is, we will
2955 reject a combination that is, since it must be slower. Be conservative
2956 here. */
2957 if (GET_CODE (i2src) == MULT
2958 || (i1 != 0 && GET_CODE (i1src) == MULT)
2959 || (i0 != 0 && GET_CODE (i0src) == MULT)
2960 || (GET_CODE (PATTERN (i3)) == SET
2961 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2962 have_mult = 1;
2963
2964 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2965 We used to do this EXCEPT in one case: I3 has a post-inc in an
2966 output operand. However, that exception can give rise to insns like
2967 mov r3,(r3)+
2968 which is a famous insn on the PDP-11 where the value of r3 used as the
2969 source was model-dependent. Avoid this sort of thing. */
2970
2971 #if 0
2972 if (!(GET_CODE (PATTERN (i3)) == SET
2973 && REG_P (SET_SRC (PATTERN (i3)))
2974 && MEM_P (SET_DEST (PATTERN (i3)))
2975 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2976 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2977 /* It's not the exception. */
2978 #endif
2979 #ifdef AUTO_INC_DEC
2980 {
2981 rtx link;
2982 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2983 if (REG_NOTE_KIND (link) == REG_INC
2984 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2985 || (i1 != 0
2986 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2987 {
2988 undo_all ();
2989 return 0;
2990 }
2991 }
2992 #endif
2993
2994 /* See if the SETs in I1 or I2 need to be kept around in the merged
2995 instruction: whenever the value set there is still needed past I3.
2996 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2997
2998 For the SET in I1, we have two cases: If I1 and I2 independently
2999 feed into I3, the set in I1 needs to be kept around if I1DEST dies
3000 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
3001 in I1 needs to be kept around unless I1DEST dies or is set in either
3002 I2 or I3. The same consideration applies to I0. */
3003
3004 added_sets_2 = !dead_or_set_p (i3, i2dest);
3005
3006 if (i1)
3007 added_sets_1 = !(dead_or_set_p (i3, i1dest)
3008 || (i1_feeds_i2_n && dead_or_set_p (i2, i1dest)));
3009 else
3010 added_sets_1 = 0;
3011
3012 if (i0)
3013 added_sets_0 = !(dead_or_set_p (i3, i0dest)
3014 || (i0_feeds_i2_n && dead_or_set_p (i2, i0dest))
3015 || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest)));
3016 else
3017 added_sets_0 = 0;
3018
3019 /* We are about to copy insns for the case where they need to be kept
3020 around. Check that they can be copied in the merged instruction. */
3021
3022 if (targetm.cannot_copy_insn_p
3023 && ((added_sets_2 && targetm.cannot_copy_insn_p (i2))
3024 || (i1 && added_sets_1 && targetm.cannot_copy_insn_p (i1))
3025 || (i0 && added_sets_0 && targetm.cannot_copy_insn_p (i0))))
3026 {
3027 undo_all ();
3028 return 0;
3029 }
3030
3031 /* If the set in I2 needs to be kept around, we must make a copy of
3032 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3033 PATTERN (I2), we are only substituting for the original I1DEST, not into
3034 an already-substituted copy. This also prevents making self-referential
3035 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3036 I2DEST. */
3037
3038 if (added_sets_2)
3039 {
3040 if (GET_CODE (PATTERN (i2)) == PARALLEL)
3041 i2pat = gen_rtx_SET (VOIDmode, i2dest, copy_rtx (i2src));
3042 else
3043 i2pat = copy_rtx (PATTERN (i2));
3044 }
3045
3046 if (added_sets_1)
3047 {
3048 if (GET_CODE (PATTERN (i1)) == PARALLEL)
3049 i1pat = gen_rtx_SET (VOIDmode, i1dest, copy_rtx (i1src));
3050 else
3051 i1pat = copy_rtx (PATTERN (i1));
3052 }
3053
3054 if (added_sets_0)
3055 {
3056 if (GET_CODE (PATTERN (i0)) == PARALLEL)
3057 i0pat = gen_rtx_SET (VOIDmode, i0dest, copy_rtx (i0src));
3058 else
3059 i0pat = copy_rtx (PATTERN (i0));
3060 }
3061
3062 combine_merges++;
3063
3064 /* Substitute in the latest insn for the regs set by the earlier ones. */
3065
3066 maxreg = max_reg_num ();
3067
3068 subst_insn = i3;
3069
3070 #ifndef HAVE_cc0
3071 /* Many machines that don't use CC0 have insns that can both perform an
3072 arithmetic operation and set the condition code. These operations will
3073 be represented as a PARALLEL with the first element of the vector
3074 being a COMPARE of an arithmetic operation with the constant zero.
3075 The second element of the vector will set some pseudo to the result
3076 of the same arithmetic operation. If we simplify the COMPARE, we won't
3077 match such a pattern and so will generate an extra insn. Here we test
3078 for this case, where both the comparison and the operation result are
3079 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3080 I2SRC. Later we will make the PARALLEL that contains I2. */
3081
3082 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
3083 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
3084 && CONST_INT_P (XEXP (SET_SRC (PATTERN (i3)), 1))
3085 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
3086 {
3087 rtx newpat_dest;
3088 rtx *cc_use_loc = NULL, cc_use_insn = NULL_RTX;
3089 rtx op0 = i2src, op1 = XEXP (SET_SRC (PATTERN (i3)), 1);
3090 enum machine_mode compare_mode, orig_compare_mode;
3091 enum rtx_code compare_code = UNKNOWN, orig_compare_code = UNKNOWN;
3092
3093 newpat = PATTERN (i3);
3094 newpat_dest = SET_DEST (newpat);
3095 compare_mode = orig_compare_mode = GET_MODE (newpat_dest);
3096
3097 if (undobuf.other_insn == 0
3098 && (cc_use_loc = find_single_use (SET_DEST (newpat), i3,
3099 &cc_use_insn)))
3100 {
3101 compare_code = orig_compare_code = GET_CODE (*cc_use_loc);
3102 compare_code = simplify_compare_const (compare_code,
3103 op0, &op1);
3104 #ifdef CANONICALIZE_COMPARISON
3105 CANONICALIZE_COMPARISON (compare_code, op0, op1);
3106 #endif
3107 }
3108
3109 /* Do the rest only if op1 is const0_rtx, which may be the
3110 result of simplification. */
3111 if (op1 == const0_rtx)
3112 {
3113 /* If a single use of the CC is found, prepare to modify it
3114 when SELECT_CC_MODE returns a new CC-class mode, or when
3115 the above simplify_compare_const() returned a new comparison
3116 operator. undobuf.other_insn is assigned the CC use insn
3117 when modifying it. */
3118 if (cc_use_loc)
3119 {
3120 #ifdef SELECT_CC_MODE
3121 enum machine_mode new_mode
3122 = SELECT_CC_MODE (compare_code, op0, op1);
3123 if (new_mode != orig_compare_mode
3124 && can_change_dest_mode (SET_DEST (newpat),
3125 added_sets_2, new_mode))
3126 {
3127 unsigned int regno = REGNO (newpat_dest);
3128 compare_mode = new_mode;
3129 if (regno < FIRST_PSEUDO_REGISTER)
3130 newpat_dest = gen_rtx_REG (compare_mode, regno);
3131 else
3132 {
3133 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
3134 newpat_dest = regno_reg_rtx[regno];
3135 }
3136 }
3137 #endif
3138 /* Cases for modifying the CC-using comparison. */
3139 if (compare_code != orig_compare_code
3140 /* ??? Do we need to verify the zero rtx? */
3141 && XEXP (*cc_use_loc, 1) == const0_rtx)
3142 {
3143 /* Replace cc_use_loc with entire new RTX. */
3144 SUBST (*cc_use_loc,
3145 gen_rtx_fmt_ee (compare_code, compare_mode,
3146 newpat_dest, const0_rtx));
3147 undobuf.other_insn = cc_use_insn;
3148 }
3149 else if (compare_mode != orig_compare_mode)
3150 {
3151 /* Just replace the CC reg with a new mode. */
3152 SUBST (XEXP (*cc_use_loc, 0), newpat_dest);
3153 undobuf.other_insn = cc_use_insn;
3154 }
3155 }
3156
3157 /* Now we modify the current newpat:
3158 First, SET_DEST(newpat) is updated if the CC mode has been
3159 altered. For targets without SELECT_CC_MODE, this should be
3160 optimized away. */
3161 if (compare_mode != orig_compare_mode)
3162 SUBST (SET_DEST (newpat), newpat_dest);
3163 /* This is always done to propagate i2src into newpat. */
3164 SUBST (SET_SRC (newpat),
3165 gen_rtx_COMPARE (compare_mode, op0, op1));
3166 /* Create new version of i2pat if needed; the below PARALLEL
3167 creation needs this to work correctly. */
3168 if (! rtx_equal_p (i2src, op0))
3169 i2pat = gen_rtx_SET (VOIDmode, i2dest, op0);
3170 i2_is_used = 1;
3171 }
3172 }
3173 #endif
3174
3175 if (i2_is_used == 0)
3176 {
3177 /* It is possible that the source of I2 or I1 may be performing
3178 an unneeded operation, such as a ZERO_EXTEND of something
3179 that is known to have the high part zero. Handle that case
3180 by letting subst look at the inner insns.
3181
3182 Another way to do this would be to have a function that tries
3183 to simplify a single insn instead of merging two or more
3184 insns. We don't do this because of the potential of infinite
3185 loops and because of the potential extra memory required.
3186 However, doing it the way we are is a bit of a kludge and
3187 doesn't catch all cases.
3188
3189 But only do this if -fexpensive-optimizations since it slows
3190 things down and doesn't usually win.
3191
3192 This is not done in the COMPARE case above because the
3193 unmodified I2PAT is used in the PARALLEL and so a pattern
3194 with a modified I2SRC would not match. */
3195
3196 if (flag_expensive_optimizations)
3197 {
3198 /* Pass pc_rtx so no substitutions are done, just
3199 simplifications. */
3200 if (i1)
3201 {
3202 subst_low_luid = DF_INSN_LUID (i1);
3203 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0, 0);
3204 }
3205
3206 subst_low_luid = DF_INSN_LUID (i2);
3207 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0, 0);
3208 }
3209
3210 n_occurrences = 0; /* `subst' counts here */
3211 subst_low_luid = DF_INSN_LUID (i2);
3212
3213 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3214 copy of I2SRC each time we substitute it, in order to avoid creating
3215 self-referential RTL when we will be substituting I1SRC for I1DEST
3216 later. Likewise if I0 feeds into I2, either directly or indirectly
3217 through I1, and I0DEST is in I0SRC. */
3218 newpat = subst (PATTERN (i3), i2dest, i2src, 0, 0,
3219 (i1_feeds_i2_n && i1dest_in_i1src)
3220 || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n))
3221 && i0dest_in_i0src));
3222 substed_i2 = 1;
3223
3224 /* Record whether I2's body now appears within I3's body. */
3225 i2_is_used = n_occurrences;
3226 }
3227
3228 /* If we already got a failure, don't try to do more. Otherwise, try to
3229 substitute I1 if we have it. */
3230
3231 if (i1 && GET_CODE (newpat) != CLOBBER)
3232 {
3233 /* Check that an autoincrement side-effect on I1 has not been lost.
3234 This happens if I1DEST is mentioned in I2 and dies there, and
3235 has disappeared from the new pattern. */
3236 if ((FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3237 && i1_feeds_i2_n
3238 && dead_or_set_p (i2, i1dest)
3239 && !reg_overlap_mentioned_p (i1dest, newpat))
3240 /* Before we can do this substitution, we must redo the test done
3241 above (see detailed comments there) that ensures I1DEST isn't
3242 mentioned in any SETs in NEWPAT that are field assignments. */
3243 || !combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX, NULL_RTX,
3244 0, 0, 0))
3245 {
3246 undo_all ();
3247 return 0;
3248 }
3249
3250 n_occurrences = 0;
3251 subst_low_luid = DF_INSN_LUID (i1);
3252
3253 /* If the following substitution will modify I1SRC, make a copy of it
3254 for the case where it is substituted for I1DEST in I2PAT later. */
3255 if (added_sets_2 && i1_feeds_i2_n)
3256 i1src_copy = copy_rtx (i1src);
3257
3258 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3259 copy of I1SRC each time we substitute it, in order to avoid creating
3260 self-referential RTL when we will be substituting I0SRC for I0DEST
3261 later. */
3262 newpat = subst (newpat, i1dest, i1src, 0, 0,
3263 i0_feeds_i1_n && i0dest_in_i0src);
3264 substed_i1 = 1;
3265
3266 /* Record whether I1's body now appears within I3's body. */
3267 i1_is_used = n_occurrences;
3268 }
3269
3270 /* Likewise for I0 if we have it. */
3271
3272 if (i0 && GET_CODE (newpat) != CLOBBER)
3273 {
3274 if ((FIND_REG_INC_NOTE (i0, NULL_RTX) != 0
3275 && ((i0_feeds_i2_n && dead_or_set_p (i2, i0dest))
3276 || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest)))
3277 && !reg_overlap_mentioned_p (i0dest, newpat))
3278 || !combinable_i3pat (NULL_RTX, &newpat, i0dest, NULL_RTX, NULL_RTX,
3279 0, 0, 0))
3280 {
3281 undo_all ();
3282 return 0;
3283 }
3284
3285 /* If the following substitution will modify I0SRC, make a copy of it
3286 for the case where it is substituted for I0DEST in I1PAT later. */
3287 if (added_sets_1 && i0_feeds_i1_n)
3288 i0src_copy = copy_rtx (i0src);
3289 /* And a copy for I0DEST in I2PAT substitution. */
3290 if (added_sets_2 && ((i0_feeds_i1_n && i1_feeds_i2_n)
3291 || (i0_feeds_i2_n)))
3292 i0src_copy2 = copy_rtx (i0src);
3293
3294 n_occurrences = 0;
3295 subst_low_luid = DF_INSN_LUID (i0);
3296 newpat = subst (newpat, i0dest, i0src, 0, 0, 0);
3297 substed_i0 = 1;
3298 }
3299
3300 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3301 to count all the ways that I2SRC and I1SRC can be used. */
3302 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
3303 && i2_is_used + added_sets_2 > 1)
3304 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3305 && (i1_is_used + added_sets_1 + (added_sets_2 && i1_feeds_i2_n)
3306 > 1))
3307 || (i0 != 0 && FIND_REG_INC_NOTE (i0, NULL_RTX) != 0
3308 && (n_occurrences + added_sets_0
3309 + (added_sets_1 && i0_feeds_i1_n)
3310 + (added_sets_2 && i0_feeds_i2_n)
3311 > 1))
3312 /* Fail if we tried to make a new register. */
3313 || max_reg_num () != maxreg
3314 /* Fail if we couldn't do something and have a CLOBBER. */
3315 || GET_CODE (newpat) == CLOBBER
3316 /* Fail if this new pattern is a MULT and we didn't have one before
3317 at the outer level. */
3318 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
3319 && ! have_mult))
3320 {
3321 undo_all ();
3322 return 0;
3323 }
3324
3325 /* If the actions of the earlier insns must be kept
3326 in addition to substituting them into the latest one,
3327 we must make a new PARALLEL for the latest insn
3328 to hold additional the SETs. */
3329
3330 if (added_sets_0 || added_sets_1 || added_sets_2)
3331 {
3332 int extra_sets = added_sets_0 + added_sets_1 + added_sets_2;
3333 combine_extras++;
3334
3335 if (GET_CODE (newpat) == PARALLEL)
3336 {
3337 rtvec old = XVEC (newpat, 0);
3338 total_sets = XVECLEN (newpat, 0) + extra_sets;
3339 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3340 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
3341 sizeof (old->elem[0]) * old->num_elem);
3342 }
3343 else
3344 {
3345 rtx old = newpat;
3346 total_sets = 1 + extra_sets;
3347 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3348 XVECEXP (newpat, 0, 0) = old;
3349 }
3350
3351 if (added_sets_0)
3352 XVECEXP (newpat, 0, --total_sets) = i0pat;
3353
3354 if (added_sets_1)
3355 {
3356 rtx t = i1pat;
3357 if (i0_feeds_i1_n)
3358 t = subst (t, i0dest, i0src_copy ? i0src_copy : i0src, 0, 0, 0);
3359
3360 XVECEXP (newpat, 0, --total_sets) = t;
3361 }
3362 if (added_sets_2)
3363 {
3364 rtx t = i2pat;
3365 if (i1_feeds_i2_n)
3366 t = subst (t, i1dest, i1src_copy ? i1src_copy : i1src, 0, 0,
3367 i0_feeds_i1_n && i0dest_in_i0src);
3368 if ((i0_feeds_i1_n && i1_feeds_i2_n) || i0_feeds_i2_n)
3369 t = subst (t, i0dest, i0src_copy2 ? i0src_copy2 : i0src, 0, 0, 0);
3370
3371 XVECEXP (newpat, 0, --total_sets) = t;
3372 }
3373 }
3374
3375 validate_replacement:
3376
3377 /* Note which hard regs this insn has as inputs. */
3378 mark_used_regs_combine (newpat);
3379
3380 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3381 consider splitting this pattern, we might need these clobbers. */
3382 if (i1 && GET_CODE (newpat) == PARALLEL
3383 && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
3384 {
3385 int len = XVECLEN (newpat, 0);
3386
3387 newpat_vec_with_clobbers = rtvec_alloc (len);
3388 for (i = 0; i < len; i++)
3389 RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
3390 }
3391
3392 /* Is the result of combination a valid instruction? */
3393 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3394
3395 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
3396 the second SET's destination is a register that is unused and isn't
3397 marked as an instruction that might trap in an EH region. In that case,
3398 we just need the first SET. This can occur when simplifying a divmod
3399 insn. We *must* test for this case here because the code below that
3400 splits two independent SETs doesn't handle this case correctly when it
3401 updates the register status.
3402
3403 It's pointless doing this if we originally had two sets, one from
3404 i3, and one from i2. Combining then splitting the parallel results
3405 in the original i2 again plus an invalid insn (which we delete).
3406 The net effect is only to move instructions around, which makes
3407 debug info less accurate.
3408
3409 Also check the case where the first SET's destination is unused.
3410 That would not cause incorrect code, but does cause an unneeded
3411 insn to remain. */
3412
3413 if (insn_code_number < 0
3414 && !(added_sets_2 && i1 == 0)
3415 && GET_CODE (newpat) == PARALLEL
3416 && XVECLEN (newpat, 0) == 2
3417 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3418 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3419 && asm_noperands (newpat) < 0)
3420 {
3421 rtx set0 = XVECEXP (newpat, 0, 0);
3422 rtx set1 = XVECEXP (newpat, 0, 1);
3423
3424 if (((REG_P (SET_DEST (set1))
3425 && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
3426 || (GET_CODE (SET_DEST (set1)) == SUBREG
3427 && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
3428 && insn_nothrow_p (i3)
3429 && !side_effects_p (SET_SRC (set1)))
3430 {
3431 newpat = set0;
3432 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3433 }
3434
3435 else if (((REG_P (SET_DEST (set0))
3436 && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
3437 || (GET_CODE (SET_DEST (set0)) == SUBREG
3438 && find_reg_note (i3, REG_UNUSED,
3439 SUBREG_REG (SET_DEST (set0)))))
3440 && insn_nothrow_p (i3)
3441 && !side_effects_p (SET_SRC (set0)))
3442 {
3443 newpat = set1;
3444 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3445
3446 if (insn_code_number >= 0)
3447 changed_i3_dest = 1;
3448 }
3449 }
3450
3451 /* If we were combining three insns and the result is a simple SET
3452 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3453 insns. There are two ways to do this. It can be split using a
3454 machine-specific method (like when you have an addition of a large
3455 constant) or by combine in the function find_split_point. */
3456
3457 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
3458 && asm_noperands (newpat) < 0)
3459 {
3460 rtx parallel, m_split, *split;
3461
3462 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3463 use I2DEST as a scratch register will help. In the latter case,
3464 convert I2DEST to the mode of the source of NEWPAT if we can. */
3465
3466 m_split = combine_split_insns (newpat, i3);
3467
3468 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3469 inputs of NEWPAT. */
3470
3471 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3472 possible to try that as a scratch reg. This would require adding
3473 more code to make it work though. */
3474
3475 if (m_split == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
3476 {
3477 enum machine_mode new_mode = GET_MODE (SET_DEST (newpat));
3478
3479 /* First try to split using the original register as a
3480 scratch register. */
3481 parallel = gen_rtx_PARALLEL (VOIDmode,
3482 gen_rtvec (2, newpat,
3483 gen_rtx_CLOBBER (VOIDmode,
3484 i2dest)));
3485 m_split = combine_split_insns (parallel, i3);
3486
3487 /* If that didn't work, try changing the mode of I2DEST if
3488 we can. */
3489 if (m_split == 0
3490 && new_mode != GET_MODE (i2dest)
3491 && new_mode != VOIDmode
3492 && can_change_dest_mode (i2dest, added_sets_2, new_mode))
3493 {
3494 enum machine_mode old_mode = GET_MODE (i2dest);
3495 rtx ni2dest;
3496
3497 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3498 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
3499 else
3500 {
3501 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode);
3502 ni2dest = regno_reg_rtx[REGNO (i2dest)];
3503 }
3504
3505 parallel = (gen_rtx_PARALLEL
3506 (VOIDmode,
3507 gen_rtvec (2, newpat,
3508 gen_rtx_CLOBBER (VOIDmode,
3509 ni2dest))));
3510 m_split = combine_split_insns (parallel, i3);
3511
3512 if (m_split == 0
3513 && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
3514 {
3515 struct undo *buf;
3516
3517 adjust_reg_mode (regno_reg_rtx[REGNO (i2dest)], old_mode);
3518 buf = undobuf.undos;
3519 undobuf.undos = buf->next;
3520 buf->next = undobuf.frees;
3521 undobuf.frees = buf;
3522 }
3523 }
3524
3525 i2scratch = m_split != 0;
3526 }
3527
3528 /* If recog_for_combine has discarded clobbers, try to use them
3529 again for the split. */
3530 if (m_split == 0 && newpat_vec_with_clobbers)
3531 {
3532 parallel = gen_rtx_PARALLEL (VOIDmode, newpat_vec_with_clobbers);
3533 m_split = combine_split_insns (parallel, i3);
3534 }
3535
3536 if (m_split && NEXT_INSN (m_split) == NULL_RTX)
3537 {
3538 m_split = PATTERN (m_split);
3539 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
3540 if (insn_code_number >= 0)
3541 newpat = m_split;
3542 }
3543 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
3544 && (next_nonnote_nondebug_insn (i2) == i3
3545 || ! use_crosses_set_p (PATTERN (m_split), DF_INSN_LUID (i2))))
3546 {
3547 rtx i2set, i3set;
3548 rtx newi3pat = PATTERN (NEXT_INSN (m_split));
3549 newi2pat = PATTERN (m_split);
3550
3551 i3set = single_set (NEXT_INSN (m_split));
3552 i2set = single_set (m_split);
3553
3554 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3555
3556 /* If I2 or I3 has multiple SETs, we won't know how to track
3557 register status, so don't use these insns. If I2's destination
3558 is used between I2 and I3, we also can't use these insns. */
3559
3560 if (i2_code_number >= 0 && i2set && i3set
3561 && (next_nonnote_nondebug_insn (i2) == i3
3562 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
3563 insn_code_number = recog_for_combine (&newi3pat, i3,
3564 &new_i3_notes);
3565 if (insn_code_number >= 0)
3566 newpat = newi3pat;
3567
3568 /* It is possible that both insns now set the destination of I3.
3569 If so, we must show an extra use of it. */
3570
3571 if (insn_code_number >= 0)
3572 {
3573 rtx new_i3_dest = SET_DEST (i3set);
3574 rtx new_i2_dest = SET_DEST (i2set);
3575
3576 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
3577 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
3578 || GET_CODE (new_i3_dest) == SUBREG)
3579 new_i3_dest = XEXP (new_i3_dest, 0);
3580
3581 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
3582 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
3583 || GET_CODE (new_i2_dest) == SUBREG)
3584 new_i2_dest = XEXP (new_i2_dest, 0);
3585
3586 if (REG_P (new_i3_dest)
3587 && REG_P (new_i2_dest)
3588 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
3589 INC_REG_N_SETS (REGNO (new_i2_dest), 1);
3590 }
3591 }
3592
3593 /* If we can split it and use I2DEST, go ahead and see if that
3594 helps things be recognized. Verify that none of the registers
3595 are set between I2 and I3. */
3596 if (insn_code_number < 0
3597 && (split = find_split_point (&newpat, i3, false)) != 0
3598 #ifdef HAVE_cc0
3599 && REG_P (i2dest)
3600 #endif
3601 /* We need I2DEST in the proper mode. If it is a hard register
3602 or the only use of a pseudo, we can change its mode.
3603 Make sure we don't change a hard register to have a mode that
3604 isn't valid for it, or change the number of registers. */
3605 && (GET_MODE (*split) == GET_MODE (i2dest)
3606 || GET_MODE (*split) == VOIDmode
3607 || can_change_dest_mode (i2dest, added_sets_2,
3608 GET_MODE (*split)))
3609 && (next_nonnote_nondebug_insn (i2) == i3
3610 || ! use_crosses_set_p (*split, DF_INSN_LUID (i2)))
3611 /* We can't overwrite I2DEST if its value is still used by
3612 NEWPAT. */
3613 && ! reg_referenced_p (i2dest, newpat))
3614 {
3615 rtx newdest = i2dest;
3616 enum rtx_code split_code = GET_CODE (*split);
3617 enum machine_mode split_mode = GET_MODE (*split);
3618 bool subst_done = false;
3619 newi2pat = NULL_RTX;
3620
3621 i2scratch = true;
3622
3623 /* *SPLIT may be part of I2SRC, so make sure we have the
3624 original expression around for later debug processing.
3625 We should not need I2SRC any more in other cases. */
3626 if (MAY_HAVE_DEBUG_INSNS)
3627 i2src = copy_rtx (i2src);
3628 else
3629 i2src = NULL;
3630
3631 /* Get NEWDEST as a register in the proper mode. We have already
3632 validated that we can do this. */
3633 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
3634 {
3635 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3636 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
3637 else
3638 {
3639 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode);
3640 newdest = regno_reg_rtx[REGNO (i2dest)];
3641 }
3642 }
3643
3644 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3645 an ASHIFT. This can occur if it was inside a PLUS and hence
3646 appeared to be a memory address. This is a kludge. */
3647 if (split_code == MULT
3648 && CONST_INT_P (XEXP (*split, 1))
3649 && INTVAL (XEXP (*split, 1)) > 0
3650 && (i = exact_log2 (UINTVAL (XEXP (*split, 1)))) >= 0)
3651 {
3652 SUBST (*split, gen_rtx_ASHIFT (split_mode,
3653 XEXP (*split, 0), GEN_INT (i)));
3654 /* Update split_code because we may not have a multiply
3655 anymore. */
3656 split_code = GET_CODE (*split);
3657 }
3658
3659 #ifdef INSN_SCHEDULING
3660 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3661 be written as a ZERO_EXTEND. */
3662 if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
3663 {
3664 #ifdef LOAD_EXTEND_OP
3665 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3666 what it really is. */
3667 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
3668 == SIGN_EXTEND)
3669 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
3670 SUBREG_REG (*split)));
3671 else
3672 #endif
3673 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
3674 SUBREG_REG (*split)));
3675 }
3676 #endif
3677
3678 /* Attempt to split binary operators using arithmetic identities. */
3679 if (BINARY_P (SET_SRC (newpat))
3680 && split_mode == GET_MODE (SET_SRC (newpat))
3681 && ! side_effects_p (SET_SRC (newpat)))
3682 {
3683 rtx setsrc = SET_SRC (newpat);
3684 enum machine_mode mode = GET_MODE (setsrc);
3685 enum rtx_code code = GET_CODE (setsrc);
3686 rtx src_op0 = XEXP (setsrc, 0);
3687 rtx src_op1 = XEXP (setsrc, 1);
3688
3689 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3690 if (rtx_equal_p (src_op0, src_op1))
3691 {
3692 newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0);
3693 SUBST (XEXP (setsrc, 0), newdest);
3694 SUBST (XEXP (setsrc, 1), newdest);
3695 subst_done = true;
3696 }
3697 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3698 else if ((code == PLUS || code == MULT)
3699 && GET_CODE (src_op0) == code
3700 && GET_CODE (XEXP (src_op0, 0)) == code
3701 && (INTEGRAL_MODE_P (mode)
3702 || (FLOAT_MODE_P (mode)
3703 && flag_unsafe_math_optimizations)))
3704 {
3705 rtx p = XEXP (XEXP (src_op0, 0), 0);
3706 rtx q = XEXP (XEXP (src_op0, 0), 1);
3707 rtx r = XEXP (src_op0, 1);
3708 rtx s = src_op1;
3709
3710 /* Split both "((X op Y) op X) op Y" and
3711 "((X op Y) op Y) op X" as "T op T" where T is
3712 "X op Y". */
3713 if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
3714 || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
3715 {
3716 newi2pat = gen_rtx_SET (VOIDmode, newdest,
3717 XEXP (src_op0, 0));
3718 SUBST (XEXP (setsrc, 0), newdest);
3719 SUBST (XEXP (setsrc, 1), newdest);
3720 subst_done = true;
3721 }
3722 /* Split "((X op X) op Y) op Y)" as "T op T" where
3723 T is "X op Y". */
3724 else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
3725 {
3726 rtx tmp = simplify_gen_binary (code, mode, p, r);
3727 newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp);
3728 SUBST (XEXP (setsrc, 0), newdest);
3729 SUBST (XEXP (setsrc, 1), newdest);
3730 subst_done = true;
3731 }
3732 }
3733 }
3734
3735 if (!subst_done)
3736 {
3737 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
3738 SUBST (*split, newdest);
3739 }
3740
3741 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3742
3743 /* recog_for_combine might have added CLOBBERs to newi2pat.
3744 Make sure NEWPAT does not depend on the clobbered regs. */
3745 if (GET_CODE (newi2pat) == PARALLEL)
3746 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3747 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3748 {
3749 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3750 if (reg_overlap_mentioned_p (reg, newpat))
3751 {
3752 undo_all ();
3753 return 0;
3754 }
3755 }
3756
3757 /* If the split point was a MULT and we didn't have one before,
3758 don't use one now. */
3759 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
3760 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3761 }
3762 }
3763
3764 /* Check for a case where we loaded from memory in a narrow mode and
3765 then sign extended it, but we need both registers. In that case,
3766 we have a PARALLEL with both loads from the same memory location.
3767 We can split this into a load from memory followed by a register-register
3768 copy. This saves at least one insn, more if register allocation can
3769 eliminate the copy.
3770
3771 We cannot do this if the destination of the first assignment is a
3772 condition code register or cc0. We eliminate this case by making sure
3773 the SET_DEST and SET_SRC have the same mode.
3774
3775 We cannot do this if the destination of the second assignment is
3776 a register that we have already assumed is zero-extended. Similarly
3777 for a SUBREG of such a register. */
3778
3779 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3780 && GET_CODE (newpat) == PARALLEL
3781 && XVECLEN (newpat, 0) == 2
3782 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3783 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
3784 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
3785 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
3786 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3787 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3788 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
3789 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3790 DF_INSN_LUID (i2))
3791 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3792 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3793 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
3794 (REG_P (temp)
3795 && VEC_index (reg_stat_type, reg_stat,
3796 REGNO (temp))->nonzero_bits != 0
3797 && GET_MODE_PRECISION (GET_MODE (temp)) < BITS_PER_WORD
3798 && GET_MODE_PRECISION (GET_MODE (temp)) < HOST_BITS_PER_INT
3799 && (VEC_index (reg_stat_type, reg_stat,
3800 REGNO (temp))->nonzero_bits
3801 != GET_MODE_MASK (word_mode))))
3802 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
3803 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
3804 (REG_P (temp)
3805 && VEC_index (reg_stat_type, reg_stat,
3806 REGNO (temp))->nonzero_bits != 0
3807 && GET_MODE_PRECISION (GET_MODE (temp)) < BITS_PER_WORD
3808 && GET_MODE_PRECISION (GET_MODE (temp)) < HOST_BITS_PER_INT
3809 && (VEC_index (reg_stat_type, reg_stat,
3810 REGNO (temp))->nonzero_bits
3811 != GET_MODE_MASK (word_mode)))))
3812 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3813 SET_SRC (XVECEXP (newpat, 0, 1)))
3814 && ! find_reg_note (i3, REG_UNUSED,
3815 SET_DEST (XVECEXP (newpat, 0, 0))))
3816 {
3817 rtx ni2dest;
3818
3819 newi2pat = XVECEXP (newpat, 0, 0);
3820 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
3821 newpat = XVECEXP (newpat, 0, 1);
3822 SUBST (SET_SRC (newpat),
3823 gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
3824 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3825
3826 if (i2_code_number >= 0)
3827 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3828
3829 if (insn_code_number >= 0)
3830 swap_i2i3 = 1;
3831 }
3832
3833 /* Similarly, check for a case where we have a PARALLEL of two independent
3834 SETs but we started with three insns. In this case, we can do the sets
3835 as two separate insns. This case occurs when some SET allows two
3836 other insns to combine, but the destination of that SET is still live. */
3837
3838 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3839 && GET_CODE (newpat) == PARALLEL
3840 && XVECLEN (newpat, 0) == 2
3841 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3842 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
3843 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
3844 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3845 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3846 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3847 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3848 XVECEXP (newpat, 0, 0))
3849 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
3850 XVECEXP (newpat, 0, 1))
3851 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
3852 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
3853 {
3854 /* Normally, it doesn't matter which of the two is done first,
3855 but the one that references cc0 can't be the second, and
3856 one which uses any regs/memory set in between i2 and i3 can't
3857 be first. */
3858 if (!use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3859 DF_INSN_LUID (i2))
3860 #ifdef HAVE_cc0
3861 && !reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0))
3862 #endif
3863 )
3864 {
3865 newi2pat = XVECEXP (newpat, 0, 1);
3866 newpat = XVECEXP (newpat, 0, 0);
3867 }
3868 else if (!use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 0)),
3869 DF_INSN_LUID (i2))
3870 #ifdef HAVE_cc0
3871 && !reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 1))
3872 #endif
3873 )
3874 {
3875 newi2pat = XVECEXP (newpat, 0, 0);
3876 newpat = XVECEXP (newpat, 0, 1);
3877 }
3878 else
3879 {
3880 undo_all ();
3881 return 0;
3882 }
3883
3884 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3885
3886 if (i2_code_number >= 0)
3887 {
3888 /* recog_for_combine might have added CLOBBERs to newi2pat.
3889 Make sure NEWPAT does not depend on the clobbered regs. */
3890 if (GET_CODE (newi2pat) == PARALLEL)
3891 {
3892 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3893 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3894 {
3895 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3896 if (reg_overlap_mentioned_p (reg, newpat))
3897 {
3898 undo_all ();
3899 return 0;
3900 }
3901 }
3902 }
3903
3904 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3905 }
3906 }
3907
3908 /* If it still isn't recognized, fail and change things back the way they
3909 were. */
3910 if ((insn_code_number < 0
3911 /* Is the result a reasonable ASM_OPERANDS? */
3912 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
3913 {
3914 undo_all ();
3915 return 0;
3916 }
3917
3918 /* If we had to change another insn, make sure it is valid also. */
3919 if (undobuf.other_insn)
3920 {
3921 CLEAR_HARD_REG_SET (newpat_used_regs);
3922
3923 other_pat = PATTERN (undobuf.other_insn);
3924 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
3925 &new_other_notes);
3926
3927 if (other_code_number < 0 && ! check_asm_operands (other_pat))
3928 {
3929 undo_all ();
3930 return 0;
3931 }
3932 }
3933
3934 #ifdef HAVE_cc0
3935 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3936 they are adjacent to each other or not. */
3937 {
3938 rtx p = prev_nonnote_insn (i3);
3939 if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
3940 && sets_cc0_p (newi2pat))
3941 {
3942 undo_all ();
3943 return 0;
3944 }
3945 }
3946 #endif
3947
3948 /* Only allow this combination if insn_rtx_costs reports that the
3949 replacement instructions are cheaper than the originals. */
3950 if (!combine_validate_cost (i0, i1, i2, i3, newpat, newi2pat, other_pat))
3951 {
3952 undo_all ();
3953 return 0;
3954 }
3955
3956 if (MAY_HAVE_DEBUG_INSNS)
3957 {
3958 struct undo *undo;
3959
3960 for (undo = undobuf.undos; undo; undo = undo->next)
3961 if (undo->kind == UNDO_MODE)
3962 {
3963 rtx reg = *undo->where.r;
3964 enum machine_mode new_mode = GET_MODE (reg);
3965 enum machine_mode old_mode = undo->old_contents.m;
3966
3967 /* Temporarily revert mode back. */
3968 adjust_reg_mode (reg, old_mode);
3969
3970 if (reg == i2dest && i2scratch)
3971 {
3972 /* If we used i2dest as a scratch register with a
3973 different mode, substitute it for the original
3974 i2src while its original mode is temporarily
3975 restored, and then clear i2scratch so that we don't
3976 do it again later. */
3977 propagate_for_debug (i2, last_combined_insn, reg, i2src);
3978 i2scratch = false;
3979 /* Put back the new mode. */
3980 adjust_reg_mode (reg, new_mode);
3981 }
3982 else
3983 {
3984 rtx tempreg = gen_raw_REG (old_mode, REGNO (reg));
3985 rtx first, last;
3986
3987 if (reg == i2dest)
3988 {
3989 first = i2;
3990 last = last_combined_insn;
3991 }
3992 else
3993 {
3994 first = i3;
3995 last = undobuf.other_insn;
3996 gcc_assert (last);
3997 if (DF_INSN_LUID (last)
3998 < DF_INSN_LUID (last_combined_insn))
3999 last = last_combined_insn;
4000 }
4001
4002 /* We're dealing with a reg that changed mode but not
4003 meaning, so we want to turn it into a subreg for
4004 the new mode. However, because of REG sharing and
4005 because its mode had already changed, we have to do
4006 it in two steps. First, replace any debug uses of
4007 reg, with its original mode temporarily restored,
4008 with this copy we have created; then, replace the
4009 copy with the SUBREG of the original shared reg,
4010 once again changed to the new mode. */
4011 propagate_for_debug (first, last, reg, tempreg);
4012 adjust_reg_mode (reg, new_mode);
4013 propagate_for_debug (first, last, tempreg,
4014 lowpart_subreg (old_mode, reg, new_mode));
4015 }
4016 }
4017 }
4018
4019 /* If we will be able to accept this, we have made a
4020 change to the destination of I3. This requires us to
4021 do a few adjustments. */
4022
4023 if (changed_i3_dest)
4024 {
4025 PATTERN (i3) = newpat;
4026 adjust_for_new_dest (i3);
4027 }
4028
4029 /* We now know that we can do this combination. Merge the insns and
4030 update the status of registers and LOG_LINKS. */
4031
4032 if (undobuf.other_insn)
4033 {
4034 rtx note, next;
4035
4036 PATTERN (undobuf.other_insn) = other_pat;
4037
4038 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
4039 are still valid. Then add any non-duplicate notes added by
4040 recog_for_combine. */
4041 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
4042 {
4043 next = XEXP (note, 1);
4044
4045 if (REG_NOTE_KIND (note) == REG_UNUSED
4046 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
4047 remove_note (undobuf.other_insn, note);
4048 }
4049
4050 distribute_notes (new_other_notes, undobuf.other_insn,
4051 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX,
4052 NULL_RTX);
4053 }
4054
4055 if (swap_i2i3)
4056 {
4057 rtx insn;
4058 struct insn_link *link;
4059 rtx ni2dest;
4060
4061 /* I3 now uses what used to be its destination and which is now
4062 I2's destination. This requires us to do a few adjustments. */
4063 PATTERN (i3) = newpat;
4064 adjust_for_new_dest (i3);
4065
4066 /* We need a LOG_LINK from I3 to I2. But we used to have one,
4067 so we still will.
4068
4069 However, some later insn might be using I2's dest and have
4070 a LOG_LINK pointing at I3. We must remove this link.
4071 The simplest way to remove the link is to point it at I1,
4072 which we know will be a NOTE. */
4073
4074 /* newi2pat is usually a SET here; however, recog_for_combine might
4075 have added some clobbers. */
4076 if (GET_CODE (newi2pat) == PARALLEL)
4077 ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
4078 else
4079 ni2dest = SET_DEST (newi2pat);
4080
4081 for (insn = NEXT_INSN (i3);
4082 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
4083 || insn != BB_HEAD (this_basic_block->next_bb));
4084 insn = NEXT_INSN (insn))
4085 {
4086 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
4087 {
4088 FOR_EACH_LOG_LINK (link, insn)
4089 if (link->insn == i3)
4090 link->insn = i1;
4091
4092 break;
4093 }
4094 }
4095 }
4096
4097 {
4098 rtx i3notes, i2notes, i1notes = 0, i0notes = 0;
4099 struct insn_link *i3links, *i2links, *i1links = 0, *i0links = 0;
4100 rtx midnotes = 0;
4101 int from_luid;
4102 /* Compute which registers we expect to eliminate. newi2pat may be setting
4103 either i3dest or i2dest, so we must check it. Also, i1dest may be the
4104 same as i3dest, in which case newi2pat may be setting i1dest. */
4105 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
4106 || i2dest_in_i2src || i2dest_in_i1src || i2dest_in_i0src
4107 || !i2dest_killed
4108 ? 0 : i2dest);
4109 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src || i1dest_in_i0src
4110 || (newi2pat && reg_set_p (i1dest, newi2pat))
4111 || !i1dest_killed
4112 ? 0 : i1dest);
4113 rtx elim_i0 = (i0 == 0 || i0dest_in_i0src
4114 || (newi2pat && reg_set_p (i0dest, newi2pat))
4115 || !i0dest_killed
4116 ? 0 : i0dest);
4117
4118 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4119 clear them. */
4120 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
4121 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
4122 if (i1)
4123 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
4124 if (i0)
4125 i0notes = REG_NOTES (i0), i0links = LOG_LINKS (i0);
4126
4127 /* Ensure that we do not have something that should not be shared but
4128 occurs multiple times in the new insns. Check this by first
4129 resetting all the `used' flags and then copying anything is shared. */
4130
4131 reset_used_flags (i3notes);
4132 reset_used_flags (i2notes);
4133 reset_used_flags (i1notes);
4134 reset_used_flags (i0notes);
4135 reset_used_flags (newpat);
4136 reset_used_flags (newi2pat);
4137 if (undobuf.other_insn)
4138 reset_used_flags (PATTERN (undobuf.other_insn));
4139
4140 i3notes = copy_rtx_if_shared (i3notes);
4141 i2notes = copy_rtx_if_shared (i2notes);
4142 i1notes = copy_rtx_if_shared (i1notes);
4143 i0notes = copy_rtx_if_shared (i0notes);
4144 newpat = copy_rtx_if_shared (newpat);
4145 newi2pat = copy_rtx_if_shared (newi2pat);
4146 if (undobuf.other_insn)
4147 reset_used_flags (PATTERN (undobuf.other_insn));
4148
4149 INSN_CODE (i3) = insn_code_number;
4150 PATTERN (i3) = newpat;
4151
4152 if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
4153 {
4154 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
4155
4156 reset_used_flags (call_usage);
4157 call_usage = copy_rtx (call_usage);
4158
4159 if (substed_i2)
4160 {
4161 /* I2SRC must still be meaningful at this point. Some splitting
4162 operations can invalidate I2SRC, but those operations do not
4163 apply to calls. */
4164 gcc_assert (i2src);
4165 replace_rtx (call_usage, i2dest, i2src);
4166 }
4167
4168 if (substed_i1)
4169 replace_rtx (call_usage, i1dest, i1src);
4170 if (substed_i0)
4171 replace_rtx (call_usage, i0dest, i0src);
4172
4173 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
4174 }
4175
4176 if (undobuf.other_insn)
4177 INSN_CODE (undobuf.other_insn) = other_code_number;
4178
4179 /* We had one special case above where I2 had more than one set and
4180 we replaced a destination of one of those sets with the destination
4181 of I3. In that case, we have to update LOG_LINKS of insns later
4182 in this basic block. Note that this (expensive) case is rare.
4183
4184 Also, in this case, we must pretend that all REG_NOTEs for I2
4185 actually came from I3, so that REG_UNUSED notes from I2 will be
4186 properly handled. */
4187
4188 if (i3_subst_into_i2)
4189 {
4190 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
4191 if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
4192 || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
4193 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
4194 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
4195 && ! find_reg_note (i2, REG_UNUSED,
4196 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
4197 for (temp = NEXT_INSN (i2);
4198 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
4199 || BB_HEAD (this_basic_block) != temp);
4200 temp = NEXT_INSN (temp))
4201 if (temp != i3 && INSN_P (temp))
4202 FOR_EACH_LOG_LINK (link, temp)
4203 if (link->insn == i2)
4204 link->insn = i3;
4205
4206 if (i3notes)
4207 {
4208 rtx link = i3notes;
4209 while (XEXP (link, 1))
4210 link = XEXP (link, 1);
4211 XEXP (link, 1) = i2notes;
4212 }
4213 else
4214 i3notes = i2notes;
4215 i2notes = 0;
4216 }
4217
4218 LOG_LINKS (i3) = NULL;
4219 REG_NOTES (i3) = 0;
4220 LOG_LINKS (i2) = NULL;
4221 REG_NOTES (i2) = 0;
4222
4223 if (newi2pat)
4224 {
4225 if (MAY_HAVE_DEBUG_INSNS && i2scratch)
4226 propagate_for_debug (i2, last_combined_insn, i2dest, i2src);
4227 INSN_CODE (i2) = i2_code_number;
4228 PATTERN (i2) = newi2pat;
4229 }
4230 else
4231 {
4232 if (MAY_HAVE_DEBUG_INSNS && i2src)
4233 propagate_for_debug (i2, last_combined_insn, i2dest, i2src);
4234 SET_INSN_DELETED (i2);
4235 }
4236
4237 if (i1)
4238 {
4239 LOG_LINKS (i1) = NULL;
4240 REG_NOTES (i1) = 0;
4241 if (MAY_HAVE_DEBUG_INSNS)
4242 propagate_for_debug (i1, last_combined_insn, i1dest, i1src);
4243 SET_INSN_DELETED (i1);
4244 }
4245
4246 if (i0)
4247 {
4248 LOG_LINKS (i0) = NULL;
4249 REG_NOTES (i0) = 0;
4250 if (MAY_HAVE_DEBUG_INSNS)
4251 propagate_for_debug (i0, last_combined_insn, i0dest, i0src);
4252 SET_INSN_DELETED (i0);
4253 }
4254
4255 /* Get death notes for everything that is now used in either I3 or
4256 I2 and used to die in a previous insn. If we built two new
4257 patterns, move from I1 to I2 then I2 to I3 so that we get the
4258 proper movement on registers that I2 modifies. */
4259
4260 if (i0)
4261 from_luid = DF_INSN_LUID (i0);
4262 else if (i1)
4263 from_luid = DF_INSN_LUID (i1);
4264 else
4265 from_luid = DF_INSN_LUID (i2);
4266 if (newi2pat)
4267 move_deaths (newi2pat, NULL_RTX, from_luid, i2, &midnotes);
4268 move_deaths (newpat, newi2pat, from_luid, i3, &midnotes);
4269
4270 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4271 if (i3notes)
4272 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
4273 elim_i2, elim_i1, elim_i0);
4274 if (i2notes)
4275 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
4276 elim_i2, elim_i1, elim_i0);
4277 if (i1notes)
4278 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
4279 elim_i2, elim_i1, elim_i0);
4280 if (i0notes)
4281 distribute_notes (i0notes, i0, i3, newi2pat ? i2 : NULL_RTX,
4282 elim_i2, elim_i1, elim_i0);
4283 if (midnotes)
4284 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4285 elim_i2, elim_i1, elim_i0);
4286
4287 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4288 know these are REG_UNUSED and want them to go to the desired insn,
4289 so we always pass it as i3. */
4290
4291 if (newi2pat && new_i2_notes)
4292 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX,
4293 NULL_RTX);
4294
4295 if (new_i3_notes)
4296 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX,
4297 NULL_RTX);
4298
4299 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4300 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4301 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4302 in that case, it might delete I2. Similarly for I2 and I1.
4303 Show an additional death due to the REG_DEAD note we make here. If
4304 we discard it in distribute_notes, we will decrement it again. */
4305
4306 if (i3dest_killed)
4307 {
4308 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
4309 distribute_notes (alloc_reg_note (REG_DEAD, i3dest_killed,
4310 NULL_RTX),
4311 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1, elim_i0);
4312 else
4313 distribute_notes (alloc_reg_note (REG_DEAD, i3dest_killed,
4314 NULL_RTX),
4315 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4316 elim_i2, elim_i1, elim_i0);
4317 }
4318
4319 if (i2dest_in_i2src)
4320 {
4321 rtx new_note = alloc_reg_note (REG_DEAD, i2dest, NULL_RTX);
4322 if (newi2pat && reg_set_p (i2dest, newi2pat))
4323 distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, NULL_RTX,
4324 NULL_RTX, NULL_RTX);
4325 else
4326 distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4327 NULL_RTX, NULL_RTX, NULL_RTX);
4328 }
4329
4330 if (i1dest_in_i1src)
4331 {
4332 rtx new_note = alloc_reg_note (REG_DEAD, i1dest, NULL_RTX);
4333 if (newi2pat && reg_set_p (i1dest, newi2pat))
4334 distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, NULL_RTX,
4335 NULL_RTX, NULL_RTX);
4336 else
4337 distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4338 NULL_RTX, NULL_RTX, NULL_RTX);
4339 }
4340
4341 if (i0dest_in_i0src)
4342 {
4343 rtx new_note = alloc_reg_note (REG_DEAD, i0dest, NULL_RTX);
4344 if (newi2pat && reg_set_p (i0dest, newi2pat))
4345 distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, NULL_RTX,
4346 NULL_RTX, NULL_RTX);
4347 else
4348 distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4349 NULL_RTX, NULL_RTX, NULL_RTX);
4350 }
4351
4352 distribute_links (i3links);
4353 distribute_links (i2links);
4354 distribute_links (i1links);
4355 distribute_links (i0links);
4356
4357 if (REG_P (i2dest))
4358 {
4359 struct insn_link *link;
4360 rtx i2_insn = 0, i2_val = 0, set;
4361
4362 /* The insn that used to set this register doesn't exist, and
4363 this life of the register may not exist either. See if one of
4364 I3's links points to an insn that sets I2DEST. If it does,
4365 that is now the last known value for I2DEST. If we don't update
4366 this and I2 set the register to a value that depended on its old
4367 contents, we will get confused. If this insn is used, thing
4368 will be set correctly in combine_instructions. */
4369 FOR_EACH_LOG_LINK (link, i3)
4370 if ((set = single_set (link->insn)) != 0
4371 && rtx_equal_p (i2dest, SET_DEST (set)))
4372 i2_insn = link->insn, i2_val = SET_SRC (set);
4373
4374 record_value_for_reg (i2dest, i2_insn, i2_val);
4375
4376 /* If the reg formerly set in I2 died only once and that was in I3,
4377 zero its use count so it won't make `reload' do any work. */
4378 if (! added_sets_2
4379 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
4380 && ! i2dest_in_i2src)
4381 INC_REG_N_SETS (REGNO (i2dest), -1);
4382 }
4383
4384 if (i1 && REG_P (i1dest))
4385 {
4386 struct insn_link *link;
4387 rtx i1_insn = 0, i1_val = 0, set;
4388
4389 FOR_EACH_LOG_LINK (link, i3)
4390 if ((set = single_set (link->insn)) != 0
4391 && rtx_equal_p (i1dest, SET_DEST (set)))
4392 i1_insn = link->insn, i1_val = SET_SRC (set);
4393
4394 record_value_for_reg (i1dest, i1_insn, i1_val);
4395
4396 if (! added_sets_1 && ! i1dest_in_i1src)
4397 INC_REG_N_SETS (REGNO (i1dest), -1);
4398 }
4399
4400 if (i0 && REG_P (i0dest))
4401 {
4402 struct insn_link *link;
4403 rtx i0_insn = 0, i0_val = 0, set;
4404
4405 FOR_EACH_LOG_LINK (link, i3)
4406 if ((set = single_set (link->insn)) != 0
4407 && rtx_equal_p (i0dest, SET_DEST (set)))
4408 i0_insn = link->insn, i0_val = SET_SRC (set);
4409
4410 record_value_for_reg (i0dest, i0_insn, i0_val);
4411
4412 if (! added_sets_0 && ! i0dest_in_i0src)
4413 INC_REG_N_SETS (REGNO (i0dest), -1);
4414 }
4415
4416 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4417 been made to this insn. The order of
4418 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
4419 can affect nonzero_bits of newpat */
4420 if (newi2pat)
4421 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
4422 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
4423 }
4424
4425 if (undobuf.other_insn != NULL_RTX)
4426 {
4427 if (dump_file)
4428 {
4429 fprintf (dump_file, "modifying other_insn ");
4430 dump_insn_slim (dump_file, undobuf.other_insn);
4431 }
4432 df_insn_rescan (undobuf.other_insn);
4433 }
4434
4435 if (i0 && !(NOTE_P(i0) && (NOTE_KIND (i0) == NOTE_INSN_DELETED)))
4436 {
4437 if (dump_file)
4438 {
4439 fprintf (dump_file, "modifying insn i1 ");
4440 dump_insn_slim (dump_file, i0);
4441 }
4442 df_insn_rescan (i0);
4443 }
4444
4445 if (i1 && !(NOTE_P(i1) && (NOTE_KIND (i1) == NOTE_INSN_DELETED)))
4446 {
4447 if (dump_file)
4448 {
4449 fprintf (dump_file, "modifying insn i1 ");
4450 dump_insn_slim (dump_file, i1);
4451 }
4452 df_insn_rescan (i1);
4453 }
4454
4455 if (i2 && !(NOTE_P(i2) && (NOTE_KIND (i2) == NOTE_INSN_DELETED)))
4456 {
4457 if (dump_file)
4458 {
4459 fprintf (dump_file, "modifying insn i2 ");
4460 dump_insn_slim (dump_file, i2);
4461 }
4462 df_insn_rescan (i2);
4463 }
4464
4465 if (i3 && !(NOTE_P(i3) && (NOTE_KIND (i3) == NOTE_INSN_DELETED)))
4466 {
4467 if (dump_file)
4468 {
4469 fprintf (dump_file, "modifying insn i3 ");
4470 dump_insn_slim (dump_file, i3);
4471 }
4472 df_insn_rescan (i3);
4473 }
4474
4475 /* Set new_direct_jump_p if a new return or simple jump instruction
4476 has been created. Adjust the CFG accordingly. */
4477
4478 if (returnjump_p (i3) || any_uncondjump_p (i3))
4479 {
4480 *new_direct_jump_p = 1;
4481 mark_jump_label (PATTERN (i3), i3, 0);
4482 update_cfg_for_uncondjump (i3);
4483 }
4484
4485 if (undobuf.other_insn != NULL_RTX
4486 && (returnjump_p (undobuf.other_insn)
4487 || any_uncondjump_p (undobuf.other_insn)))
4488 {
4489 *new_direct_jump_p = 1;
4490 update_cfg_for_uncondjump (undobuf.other_insn);
4491 }
4492
4493 /* A noop might also need cleaning up of CFG, if it comes from the
4494 simplification of a jump. */
4495 if (JUMP_P (i3)
4496 && GET_CODE (newpat) == SET
4497 && SET_SRC (newpat) == pc_rtx
4498 && SET_DEST (newpat) == pc_rtx)
4499 {
4500 *new_direct_jump_p = 1;
4501 update_cfg_for_uncondjump (i3);
4502 }
4503
4504 if (undobuf.other_insn != NULL_RTX
4505 && JUMP_P (undobuf.other_insn)
4506 && GET_CODE (PATTERN (undobuf.other_insn)) == SET
4507 && SET_SRC (PATTERN (undobuf.other_insn)) == pc_rtx
4508 && SET_DEST (PATTERN (undobuf.other_insn)) == pc_rtx)
4509 {
4510 *new_direct_jump_p = 1;
4511 update_cfg_for_uncondjump (undobuf.other_insn);
4512 }
4513
4514 combine_successes++;
4515 undo_commit ();
4516
4517 if (added_links_insn
4518 && (newi2pat == 0 || DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i2))
4519 && DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i3))
4520 return added_links_insn;
4521 else
4522 return newi2pat ? i2 : i3;
4523 }
4524
4525 /* Undo all the modifications recorded in undobuf. */
4526
4527 static void
undo_all(void)4528 undo_all (void)
4529 {
4530 struct undo *undo, *next;
4531
4532 for (undo = undobuf.undos; undo; undo = next)
4533 {
4534 next = undo->next;
4535 switch (undo->kind)
4536 {
4537 case UNDO_RTX:
4538 *undo->where.r = undo->old_contents.r;
4539 break;
4540 case UNDO_INT:
4541 *undo->where.i = undo->old_contents.i;
4542 break;
4543 case UNDO_MODE:
4544 adjust_reg_mode (*undo->where.r, undo->old_contents.m);
4545 break;
4546 case UNDO_LINKS:
4547 *undo->where.l = undo->old_contents.l;
4548 break;
4549 default:
4550 gcc_unreachable ();
4551 }
4552
4553 undo->next = undobuf.frees;
4554 undobuf.frees = undo;
4555 }
4556
4557 undobuf.undos = 0;
4558 }
4559
4560 /* We've committed to accepting the changes we made. Move all
4561 of the undos to the free list. */
4562
4563 static void
undo_commit(void)4564 undo_commit (void)
4565 {
4566 struct undo *undo, *next;
4567
4568 for (undo = undobuf.undos; undo; undo = next)
4569 {
4570 next = undo->next;
4571 undo->next = undobuf.frees;
4572 undobuf.frees = undo;
4573 }
4574 undobuf.undos = 0;
4575 }
4576
4577 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4578 where we have an arithmetic expression and return that point. LOC will
4579 be inside INSN.
4580
4581 try_combine will call this function to see if an insn can be split into
4582 two insns. */
4583
4584 static rtx *
find_split_point(rtx * loc,rtx insn,bool set_src)4585 find_split_point (rtx *loc, rtx insn, bool set_src)
4586 {
4587 rtx x = *loc;
4588 enum rtx_code code = GET_CODE (x);
4589 rtx *split;
4590 unsigned HOST_WIDE_INT len = 0;
4591 HOST_WIDE_INT pos = 0;
4592 int unsignedp = 0;
4593 rtx inner = NULL_RTX;
4594
4595 /* First special-case some codes. */
4596 switch (code)
4597 {
4598 case SUBREG:
4599 #ifdef INSN_SCHEDULING
4600 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4601 point. */
4602 if (MEM_P (SUBREG_REG (x)))
4603 return loc;
4604 #endif
4605 return find_split_point (&SUBREG_REG (x), insn, false);
4606
4607 case MEM:
4608 #ifdef HAVE_lo_sum
4609 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4610 using LO_SUM and HIGH. */
4611 if (GET_CODE (XEXP (x, 0)) == CONST
4612 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
4613 {
4614 enum machine_mode address_mode
4615 = targetm.addr_space.address_mode (MEM_ADDR_SPACE (x));
4616
4617 SUBST (XEXP (x, 0),
4618 gen_rtx_LO_SUM (address_mode,
4619 gen_rtx_HIGH (address_mode, XEXP (x, 0)),
4620 XEXP (x, 0)));
4621 return &XEXP (XEXP (x, 0), 0);
4622 }
4623 #endif
4624
4625 /* If we have a PLUS whose second operand is a constant and the
4626 address is not valid, perhaps will can split it up using
4627 the machine-specific way to split large constants. We use
4628 the first pseudo-reg (one of the virtual regs) as a placeholder;
4629 it will not remain in the result. */
4630 if (GET_CODE (XEXP (x, 0)) == PLUS
4631 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
4632 && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4633 MEM_ADDR_SPACE (x)))
4634 {
4635 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
4636 rtx seq = combine_split_insns (gen_rtx_SET (VOIDmode, reg,
4637 XEXP (x, 0)),
4638 subst_insn);
4639
4640 /* This should have produced two insns, each of which sets our
4641 placeholder. If the source of the second is a valid address,
4642 we can make put both sources together and make a split point
4643 in the middle. */
4644
4645 if (seq
4646 && NEXT_INSN (seq) != NULL_RTX
4647 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
4648 && NONJUMP_INSN_P (seq)
4649 && GET_CODE (PATTERN (seq)) == SET
4650 && SET_DEST (PATTERN (seq)) == reg
4651 && ! reg_mentioned_p (reg,
4652 SET_SRC (PATTERN (seq)))
4653 && NONJUMP_INSN_P (NEXT_INSN (seq))
4654 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
4655 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
4656 && memory_address_addr_space_p
4657 (GET_MODE (x), SET_SRC (PATTERN (NEXT_INSN (seq))),
4658 MEM_ADDR_SPACE (x)))
4659 {
4660 rtx src1 = SET_SRC (PATTERN (seq));
4661 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
4662
4663 /* Replace the placeholder in SRC2 with SRC1. If we can
4664 find where in SRC2 it was placed, that can become our
4665 split point and we can replace this address with SRC2.
4666 Just try two obvious places. */
4667
4668 src2 = replace_rtx (src2, reg, src1);
4669 split = 0;
4670 if (XEXP (src2, 0) == src1)
4671 split = &XEXP (src2, 0);
4672 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
4673 && XEXP (XEXP (src2, 0), 0) == src1)
4674 split = &XEXP (XEXP (src2, 0), 0);
4675
4676 if (split)
4677 {
4678 SUBST (XEXP (x, 0), src2);
4679 return split;
4680 }
4681 }
4682
4683 /* If that didn't work, perhaps the first operand is complex and
4684 needs to be computed separately, so make a split point there.
4685 This will occur on machines that just support REG + CONST
4686 and have a constant moved through some previous computation. */
4687
4688 else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
4689 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4690 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4691 return &XEXP (XEXP (x, 0), 0);
4692 }
4693
4694 /* If we have a PLUS whose first operand is complex, try computing it
4695 separately by making a split there. */
4696 if (GET_CODE (XEXP (x, 0)) == PLUS
4697 && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4698 MEM_ADDR_SPACE (x))
4699 && ! OBJECT_P (XEXP (XEXP (x, 0), 0))
4700 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4701 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4702 return &XEXP (XEXP (x, 0), 0);
4703 break;
4704
4705 case SET:
4706 #ifdef HAVE_cc0
4707 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4708 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4709 we need to put the operand into a register. So split at that
4710 point. */
4711
4712 if (SET_DEST (x) == cc0_rtx
4713 && GET_CODE (SET_SRC (x)) != COMPARE
4714 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
4715 && !OBJECT_P (SET_SRC (x))
4716 && ! (GET_CODE (SET_SRC (x)) == SUBREG
4717 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
4718 return &SET_SRC (x);
4719 #endif
4720
4721 /* See if we can split SET_SRC as it stands. */
4722 split = find_split_point (&SET_SRC (x), insn, true);
4723 if (split && split != &SET_SRC (x))
4724 return split;
4725
4726 /* See if we can split SET_DEST as it stands. */
4727 split = find_split_point (&SET_DEST (x), insn, false);
4728 if (split && split != &SET_DEST (x))
4729 return split;
4730
4731 /* See if this is a bitfield assignment with everything constant. If
4732 so, this is an IOR of an AND, so split it into that. */
4733 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
4734 && HWI_COMPUTABLE_MODE_P (GET_MODE (XEXP (SET_DEST (x), 0)))
4735 && CONST_INT_P (XEXP (SET_DEST (x), 1))
4736 && CONST_INT_P (XEXP (SET_DEST (x), 2))
4737 && CONST_INT_P (SET_SRC (x))
4738 && ((INTVAL (XEXP (SET_DEST (x), 1))
4739 + INTVAL (XEXP (SET_DEST (x), 2)))
4740 <= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x), 0))))
4741 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
4742 {
4743 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
4744 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
4745 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
4746 rtx dest = XEXP (SET_DEST (x), 0);
4747 enum machine_mode mode = GET_MODE (dest);
4748 unsigned HOST_WIDE_INT mask
4749 = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
4750 rtx or_mask;
4751
4752 if (BITS_BIG_ENDIAN)
4753 pos = GET_MODE_PRECISION (mode) - len - pos;
4754
4755 or_mask = gen_int_mode (src << pos, mode);
4756 if (src == mask)
4757 SUBST (SET_SRC (x),
4758 simplify_gen_binary (IOR, mode, dest, or_mask));
4759 else
4760 {
4761 rtx negmask = gen_int_mode (~(mask << pos), mode);
4762 SUBST (SET_SRC (x),
4763 simplify_gen_binary (IOR, mode,
4764 simplify_gen_binary (AND, mode,
4765 dest, negmask),
4766 or_mask));
4767 }
4768
4769 SUBST (SET_DEST (x), dest);
4770
4771 split = find_split_point (&SET_SRC (x), insn, true);
4772 if (split && split != &SET_SRC (x))
4773 return split;
4774 }
4775
4776 /* Otherwise, see if this is an operation that we can split into two.
4777 If so, try to split that. */
4778 code = GET_CODE (SET_SRC (x));
4779
4780 switch (code)
4781 {
4782 case AND:
4783 /* If we are AND'ing with a large constant that is only a single
4784 bit and the result is only being used in a context where we
4785 need to know if it is zero or nonzero, replace it with a bit
4786 extraction. This will avoid the large constant, which might
4787 have taken more than one insn to make. If the constant were
4788 not a valid argument to the AND but took only one insn to make,
4789 this is no worse, but if it took more than one insn, it will
4790 be better. */
4791
4792 if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4793 && REG_P (XEXP (SET_SRC (x), 0))
4794 && (pos = exact_log2 (UINTVAL (XEXP (SET_SRC (x), 1)))) >= 7
4795 && REG_P (SET_DEST (x))
4796 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
4797 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
4798 && XEXP (*split, 0) == SET_DEST (x)
4799 && XEXP (*split, 1) == const0_rtx)
4800 {
4801 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
4802 XEXP (SET_SRC (x), 0),
4803 pos, NULL_RTX, 1, 1, 0, 0);
4804 if (extraction != 0)
4805 {
4806 SUBST (SET_SRC (x), extraction);
4807 return find_split_point (loc, insn, false);
4808 }
4809 }
4810 break;
4811
4812 case NE:
4813 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4814 is known to be on, this can be converted into a NEG of a shift. */
4815 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
4816 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
4817 && 1 <= (pos = exact_log2
4818 (nonzero_bits (XEXP (SET_SRC (x), 0),
4819 GET_MODE (XEXP (SET_SRC (x), 0))))))
4820 {
4821 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
4822
4823 SUBST (SET_SRC (x),
4824 gen_rtx_NEG (mode,
4825 gen_rtx_LSHIFTRT (mode,
4826 XEXP (SET_SRC (x), 0),
4827 GEN_INT (pos))));
4828
4829 split = find_split_point (&SET_SRC (x), insn, true);
4830 if (split && split != &SET_SRC (x))
4831 return split;
4832 }
4833 break;
4834
4835 case SIGN_EXTEND:
4836 inner = XEXP (SET_SRC (x), 0);
4837
4838 /* We can't optimize if either mode is a partial integer
4839 mode as we don't know how many bits are significant
4840 in those modes. */
4841 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
4842 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
4843 break;
4844
4845 pos = 0;
4846 len = GET_MODE_PRECISION (GET_MODE (inner));
4847 unsignedp = 0;
4848 break;
4849
4850 case SIGN_EXTRACT:
4851 case ZERO_EXTRACT:
4852 if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4853 && CONST_INT_P (XEXP (SET_SRC (x), 2)))
4854 {
4855 inner = XEXP (SET_SRC (x), 0);
4856 len = INTVAL (XEXP (SET_SRC (x), 1));
4857 pos = INTVAL (XEXP (SET_SRC (x), 2));
4858
4859 if (BITS_BIG_ENDIAN)
4860 pos = GET_MODE_PRECISION (GET_MODE (inner)) - len - pos;
4861 unsignedp = (code == ZERO_EXTRACT);
4862 }
4863 break;
4864
4865 default:
4866 break;
4867 }
4868
4869 if (len && pos >= 0
4870 && pos + len <= GET_MODE_PRECISION (GET_MODE (inner)))
4871 {
4872 enum machine_mode mode = GET_MODE (SET_SRC (x));
4873
4874 /* For unsigned, we have a choice of a shift followed by an
4875 AND or two shifts. Use two shifts for field sizes where the
4876 constant might be too large. We assume here that we can
4877 always at least get 8-bit constants in an AND insn, which is
4878 true for every current RISC. */
4879
4880 if (unsignedp && len <= 8)
4881 {
4882 SUBST (SET_SRC (x),
4883 gen_rtx_AND (mode,
4884 gen_rtx_LSHIFTRT
4885 (mode, gen_lowpart (mode, inner),
4886 GEN_INT (pos)),
4887 GEN_INT (((unsigned HOST_WIDE_INT) 1 << len)
4888 - 1)));
4889
4890 split = find_split_point (&SET_SRC (x), insn, true);
4891 if (split && split != &SET_SRC (x))
4892 return split;
4893 }
4894 else
4895 {
4896 SUBST (SET_SRC (x),
4897 gen_rtx_fmt_ee
4898 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
4899 gen_rtx_ASHIFT (mode,
4900 gen_lowpart (mode, inner),
4901 GEN_INT (GET_MODE_PRECISION (mode)
4902 - len - pos)),
4903 GEN_INT (GET_MODE_PRECISION (mode) - len)));
4904
4905 split = find_split_point (&SET_SRC (x), insn, true);
4906 if (split && split != &SET_SRC (x))
4907 return split;
4908 }
4909 }
4910
4911 /* See if this is a simple operation with a constant as the second
4912 operand. It might be that this constant is out of range and hence
4913 could be used as a split point. */
4914 if (BINARY_P (SET_SRC (x))
4915 && CONSTANT_P (XEXP (SET_SRC (x), 1))
4916 && (OBJECT_P (XEXP (SET_SRC (x), 0))
4917 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
4918 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
4919 return &XEXP (SET_SRC (x), 1);
4920
4921 /* Finally, see if this is a simple operation with its first operand
4922 not in a register. The operation might require this operand in a
4923 register, so return it as a split point. We can always do this
4924 because if the first operand were another operation, we would have
4925 already found it as a split point. */
4926 if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
4927 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
4928 return &XEXP (SET_SRC (x), 0);
4929
4930 return 0;
4931
4932 case AND:
4933 case IOR:
4934 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4935 it is better to write this as (not (ior A B)) so we can split it.
4936 Similarly for IOR. */
4937 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
4938 {
4939 SUBST (*loc,
4940 gen_rtx_NOT (GET_MODE (x),
4941 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
4942 GET_MODE (x),
4943 XEXP (XEXP (x, 0), 0),
4944 XEXP (XEXP (x, 1), 0))));
4945 return find_split_point (loc, insn, set_src);
4946 }
4947
4948 /* Many RISC machines have a large set of logical insns. If the
4949 second operand is a NOT, put it first so we will try to split the
4950 other operand first. */
4951 if (GET_CODE (XEXP (x, 1)) == NOT)
4952 {
4953 rtx tem = XEXP (x, 0);
4954 SUBST (XEXP (x, 0), XEXP (x, 1));
4955 SUBST (XEXP (x, 1), tem);
4956 }
4957 break;
4958
4959 case PLUS:
4960 case MINUS:
4961 /* Canonicalization can produce (minus A (mult B C)), where C is a
4962 constant. It may be better to try splitting (plus (mult B -C) A)
4963 instead if this isn't a multiply by a power of two. */
4964 if (set_src && code == MINUS && GET_CODE (XEXP (x, 1)) == MULT
4965 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4966 && exact_log2 (INTVAL (XEXP (XEXP (x, 1), 1))) < 0)
4967 {
4968 enum machine_mode mode = GET_MODE (x);
4969 unsigned HOST_WIDE_INT this_int = INTVAL (XEXP (XEXP (x, 1), 1));
4970 HOST_WIDE_INT other_int = trunc_int_for_mode (-this_int, mode);
4971 SUBST (*loc, gen_rtx_PLUS (mode, gen_rtx_MULT (mode,
4972 XEXP (XEXP (x, 1), 0),
4973 GEN_INT (other_int)),
4974 XEXP (x, 0)));
4975 return find_split_point (loc, insn, set_src);
4976 }
4977
4978 /* Split at a multiply-accumulate instruction. However if this is
4979 the SET_SRC, we likely do not have such an instruction and it's
4980 worthless to try this split. */
4981 if (!set_src && GET_CODE (XEXP (x, 0)) == MULT)
4982 return loc;
4983
4984 default:
4985 break;
4986 }
4987
4988 /* Otherwise, select our actions depending on our rtx class. */
4989 switch (GET_RTX_CLASS (code))
4990 {
4991 case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
4992 case RTX_TERNARY:
4993 split = find_split_point (&XEXP (x, 2), insn, false);
4994 if (split)
4995 return split;
4996 /* ... fall through ... */
4997 case RTX_BIN_ARITH:
4998 case RTX_COMM_ARITH:
4999 case RTX_COMPARE:
5000 case RTX_COMM_COMPARE:
5001 split = find_split_point (&XEXP (x, 1), insn, false);
5002 if (split)
5003 return split;
5004 /* ... fall through ... */
5005 case RTX_UNARY:
5006 /* Some machines have (and (shift ...) ...) insns. If X is not
5007 an AND, but XEXP (X, 0) is, use it as our split point. */
5008 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
5009 return &XEXP (x, 0);
5010
5011 split = find_split_point (&XEXP (x, 0), insn, false);
5012 if (split)
5013 return split;
5014 return loc;
5015
5016 default:
5017 /* Otherwise, we don't have a split point. */
5018 return 0;
5019 }
5020 }
5021
5022 /* Throughout X, replace FROM with TO, and return the result.
5023 The result is TO if X is FROM;
5024 otherwise the result is X, but its contents may have been modified.
5025 If they were modified, a record was made in undobuf so that
5026 undo_all will (among other things) return X to its original state.
5027
5028 If the number of changes necessary is too much to record to undo,
5029 the excess changes are not made, so the result is invalid.
5030 The changes already made can still be undone.
5031 undobuf.num_undo is incremented for such changes, so by testing that
5032 the caller can tell whether the result is valid.
5033
5034 `n_occurrences' is incremented each time FROM is replaced.
5035
5036 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
5037
5038 IN_COND is nonzero if we are at the top level of a condition.
5039
5040 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
5041 by copying if `n_occurrences' is nonzero. */
5042
5043 static rtx
subst(rtx x,rtx from,rtx to,int in_dest,int in_cond,int unique_copy)5044 subst (rtx x, rtx from, rtx to, int in_dest, int in_cond, int unique_copy)
5045 {
5046 enum rtx_code code = GET_CODE (x);
5047 enum machine_mode op0_mode = VOIDmode;
5048 const char *fmt;
5049 int len, i;
5050 rtx new_rtx;
5051
5052 /* Two expressions are equal if they are identical copies of a shared
5053 RTX or if they are both registers with the same register number
5054 and mode. */
5055
5056 #define COMBINE_RTX_EQUAL_P(X,Y) \
5057 ((X) == (Y) \
5058 || (REG_P (X) && REG_P (Y) \
5059 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5060
5061 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
5062 {
5063 n_occurrences++;
5064 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
5065 }
5066
5067 /* If X and FROM are the same register but different modes, they
5068 will not have been seen as equal above. However, the log links code
5069 will make a LOG_LINKS entry for that case. If we do nothing, we
5070 will try to rerecognize our original insn and, when it succeeds,
5071 we will delete the feeding insn, which is incorrect.
5072
5073 So force this insn not to match in this (rare) case. */
5074 if (! in_dest && code == REG && REG_P (from)
5075 && reg_overlap_mentioned_p (x, from))
5076 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
5077
5078 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5079 of which may contain things that can be combined. */
5080 if (code != MEM && code != LO_SUM && OBJECT_P (x))
5081 return x;
5082
5083 /* It is possible to have a subexpression appear twice in the insn.
5084 Suppose that FROM is a register that appears within TO.
5085 Then, after that subexpression has been scanned once by `subst',
5086 the second time it is scanned, TO may be found. If we were
5087 to scan TO here, we would find FROM within it and create a
5088 self-referent rtl structure which is completely wrong. */
5089 if (COMBINE_RTX_EQUAL_P (x, to))
5090 return to;
5091
5092 /* Parallel asm_operands need special attention because all of the
5093 inputs are shared across the arms. Furthermore, unsharing the
5094 rtl results in recognition failures. Failure to handle this case
5095 specially can result in circular rtl.
5096
5097 Solve this by doing a normal pass across the first entry of the
5098 parallel, and only processing the SET_DESTs of the subsequent
5099 entries. Ug. */
5100
5101 if (code == PARALLEL
5102 && GET_CODE (XVECEXP (x, 0, 0)) == SET
5103 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
5104 {
5105 new_rtx = subst (XVECEXP (x, 0, 0), from, to, 0, 0, unique_copy);
5106
5107 /* If this substitution failed, this whole thing fails. */
5108 if (GET_CODE (new_rtx) == CLOBBER
5109 && XEXP (new_rtx, 0) == const0_rtx)
5110 return new_rtx;
5111
5112 SUBST (XVECEXP (x, 0, 0), new_rtx);
5113
5114 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
5115 {
5116 rtx dest = SET_DEST (XVECEXP (x, 0, i));
5117
5118 if (!REG_P (dest)
5119 && GET_CODE (dest) != CC0
5120 && GET_CODE (dest) != PC)
5121 {
5122 new_rtx = subst (dest, from, to, 0, 0, unique_copy);
5123
5124 /* If this substitution failed, this whole thing fails. */
5125 if (GET_CODE (new_rtx) == CLOBBER
5126 && XEXP (new_rtx, 0) == const0_rtx)
5127 return new_rtx;
5128
5129 SUBST (SET_DEST (XVECEXP (x, 0, i)), new_rtx);
5130 }
5131 }
5132 }
5133 else
5134 {
5135 len = GET_RTX_LENGTH (code);
5136 fmt = GET_RTX_FORMAT (code);
5137
5138 /* We don't need to process a SET_DEST that is a register, CC0,
5139 or PC, so set up to skip this common case. All other cases
5140 where we want to suppress replacing something inside a
5141 SET_SRC are handled via the IN_DEST operand. */
5142 if (code == SET
5143 && (REG_P (SET_DEST (x))
5144 || GET_CODE (SET_DEST (x)) == CC0
5145 || GET_CODE (SET_DEST (x)) == PC))
5146 fmt = "ie";
5147
5148 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5149 constant. */
5150 if (fmt[0] == 'e')
5151 op0_mode = GET_MODE (XEXP (x, 0));
5152
5153 for (i = 0; i < len; i++)
5154 {
5155 if (fmt[i] == 'E')
5156 {
5157 int j;
5158 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5159 {
5160 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
5161 {
5162 new_rtx = (unique_copy && n_occurrences
5163 ? copy_rtx (to) : to);
5164 n_occurrences++;
5165 }
5166 else
5167 {
5168 new_rtx = subst (XVECEXP (x, i, j), from, to, 0, 0,
5169 unique_copy);
5170
5171 /* If this substitution failed, this whole thing
5172 fails. */
5173 if (GET_CODE (new_rtx) == CLOBBER
5174 && XEXP (new_rtx, 0) == const0_rtx)
5175 return new_rtx;
5176 }
5177
5178 SUBST (XVECEXP (x, i, j), new_rtx);
5179 }
5180 }
5181 else if (fmt[i] == 'e')
5182 {
5183 /* If this is a register being set, ignore it. */
5184 new_rtx = XEXP (x, i);
5185 if (in_dest
5186 && i == 0
5187 && (((code == SUBREG || code == ZERO_EXTRACT)
5188 && REG_P (new_rtx))
5189 || code == STRICT_LOW_PART))
5190 ;
5191
5192 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
5193 {
5194 /* In general, don't install a subreg involving two
5195 modes not tieable. It can worsen register
5196 allocation, and can even make invalid reload
5197 insns, since the reg inside may need to be copied
5198 from in the outside mode, and that may be invalid
5199 if it is an fp reg copied in integer mode.
5200
5201 We allow two exceptions to this: It is valid if
5202 it is inside another SUBREG and the mode of that
5203 SUBREG and the mode of the inside of TO is
5204 tieable and it is valid if X is a SET that copies
5205 FROM to CC0. */
5206
5207 if (GET_CODE (to) == SUBREG
5208 && ! MODES_TIEABLE_P (GET_MODE (to),
5209 GET_MODE (SUBREG_REG (to)))
5210 && ! (code == SUBREG
5211 && MODES_TIEABLE_P (GET_MODE (x),
5212 GET_MODE (SUBREG_REG (to))))
5213 #ifdef HAVE_cc0
5214 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
5215 #endif
5216 )
5217 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5218
5219 #ifdef CANNOT_CHANGE_MODE_CLASS
5220 if (code == SUBREG
5221 && REG_P (to)
5222 && REGNO (to) < FIRST_PSEUDO_REGISTER
5223 && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
5224 GET_MODE (to),
5225 GET_MODE (x)))
5226 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5227 #endif
5228
5229 new_rtx = (unique_copy && n_occurrences ? copy_rtx (to) : to);
5230 n_occurrences++;
5231 }
5232 else
5233 /* If we are in a SET_DEST, suppress most cases unless we
5234 have gone inside a MEM, in which case we want to
5235 simplify the address. We assume here that things that
5236 are actually part of the destination have their inner
5237 parts in the first expression. This is true for SUBREG,
5238 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5239 things aside from REG and MEM that should appear in a
5240 SET_DEST. */
5241 new_rtx = subst (XEXP (x, i), from, to,
5242 (((in_dest
5243 && (code == SUBREG || code == STRICT_LOW_PART
5244 || code == ZERO_EXTRACT))
5245 || code == SET)
5246 && i == 0),
5247 code == IF_THEN_ELSE && i == 0,
5248 unique_copy);
5249
5250 /* If we found that we will have to reject this combination,
5251 indicate that by returning the CLOBBER ourselves, rather than
5252 an expression containing it. This will speed things up as
5253 well as prevent accidents where two CLOBBERs are considered
5254 to be equal, thus producing an incorrect simplification. */
5255
5256 if (GET_CODE (new_rtx) == CLOBBER && XEXP (new_rtx, 0) == const0_rtx)
5257 return new_rtx;
5258
5259 if (GET_CODE (x) == SUBREG
5260 && (CONST_INT_P (new_rtx)
5261 || GET_CODE (new_rtx) == CONST_DOUBLE))
5262 {
5263 enum machine_mode mode = GET_MODE (x);
5264
5265 x = simplify_subreg (GET_MODE (x), new_rtx,
5266 GET_MODE (SUBREG_REG (x)),
5267 SUBREG_BYTE (x));
5268 if (! x)
5269 x = gen_rtx_CLOBBER (mode, const0_rtx);
5270 }
5271 else if (CONST_INT_P (new_rtx)
5272 && GET_CODE (x) == ZERO_EXTEND)
5273 {
5274 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
5275 new_rtx, GET_MODE (XEXP (x, 0)));
5276 gcc_assert (x);
5277 }
5278 else
5279 SUBST (XEXP (x, i), new_rtx);
5280 }
5281 }
5282 }
5283
5284 /* Check if we are loading something from the constant pool via float
5285 extension; in this case we would undo compress_float_constant
5286 optimization and degenerate constant load to an immediate value. */
5287 if (GET_CODE (x) == FLOAT_EXTEND
5288 && MEM_P (XEXP (x, 0))
5289 && MEM_READONLY_P (XEXP (x, 0)))
5290 {
5291 rtx tmp = avoid_constant_pool_reference (x);
5292 if (x != tmp)
5293 return x;
5294 }
5295
5296 /* Try to simplify X. If the simplification changed the code, it is likely
5297 that further simplification will help, so loop, but limit the number
5298 of repetitions that will be performed. */
5299
5300 for (i = 0; i < 4; i++)
5301 {
5302 /* If X is sufficiently simple, don't bother trying to do anything
5303 with it. */
5304 if (code != CONST_INT && code != REG && code != CLOBBER)
5305 x = combine_simplify_rtx (x, op0_mode, in_dest, in_cond);
5306
5307 if (GET_CODE (x) == code)
5308 break;
5309
5310 code = GET_CODE (x);
5311
5312 /* We no longer know the original mode of operand 0 since we
5313 have changed the form of X) */
5314 op0_mode = VOIDmode;
5315 }
5316
5317 return x;
5318 }
5319
5320 /* Simplify X, a piece of RTL. We just operate on the expression at the
5321 outer level; call `subst' to simplify recursively. Return the new
5322 expression.
5323
5324 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5325 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5326 of a condition. */
5327
5328 static rtx
combine_simplify_rtx(rtx x,enum machine_mode op0_mode,int in_dest,int in_cond)5329 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest,
5330 int in_cond)
5331 {
5332 enum rtx_code code = GET_CODE (x);
5333 enum machine_mode mode = GET_MODE (x);
5334 rtx temp;
5335 int i;
5336
5337 /* If this is a commutative operation, put a constant last and a complex
5338 expression first. We don't need to do this for comparisons here. */
5339 if (COMMUTATIVE_ARITH_P (x)
5340 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
5341 {
5342 temp = XEXP (x, 0);
5343 SUBST (XEXP (x, 0), XEXP (x, 1));
5344 SUBST (XEXP (x, 1), temp);
5345 }
5346
5347 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5348 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5349 things. Check for cases where both arms are testing the same
5350 condition.
5351
5352 Don't do anything if all operands are very simple. */
5353
5354 if ((BINARY_P (x)
5355 && ((!OBJECT_P (XEXP (x, 0))
5356 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5357 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
5358 || (!OBJECT_P (XEXP (x, 1))
5359 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
5360 && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
5361 || (UNARY_P (x)
5362 && (!OBJECT_P (XEXP (x, 0))
5363 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5364 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
5365 {
5366 rtx cond, true_rtx, false_rtx;
5367
5368 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
5369 if (cond != 0
5370 /* If everything is a comparison, what we have is highly unlikely
5371 to be simpler, so don't use it. */
5372 && ! (COMPARISON_P (x)
5373 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
5374 {
5375 rtx cop1 = const0_rtx;
5376 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
5377
5378 if (cond_code == NE && COMPARISON_P (cond))
5379 return x;
5380
5381 /* Simplify the alternative arms; this may collapse the true and
5382 false arms to store-flag values. Be careful to use copy_rtx
5383 here since true_rtx or false_rtx might share RTL with x as a
5384 result of the if_then_else_cond call above. */
5385 true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0, 0);
5386 false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0, 0);
5387
5388 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5389 is unlikely to be simpler. */
5390 if (general_operand (true_rtx, VOIDmode)
5391 && general_operand (false_rtx, VOIDmode))
5392 {
5393 enum rtx_code reversed;
5394
5395 /* Restarting if we generate a store-flag expression will cause
5396 us to loop. Just drop through in this case. */
5397
5398 /* If the result values are STORE_FLAG_VALUE and zero, we can
5399 just make the comparison operation. */
5400 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
5401 x = simplify_gen_relational (cond_code, mode, VOIDmode,
5402 cond, cop1);
5403 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
5404 && ((reversed = reversed_comparison_code_parts
5405 (cond_code, cond, cop1, NULL))
5406 != UNKNOWN))
5407 x = simplify_gen_relational (reversed, mode, VOIDmode,
5408 cond, cop1);
5409
5410 /* Likewise, we can make the negate of a comparison operation
5411 if the result values are - STORE_FLAG_VALUE and zero. */
5412 else if (CONST_INT_P (true_rtx)
5413 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
5414 && false_rtx == const0_rtx)
5415 x = simplify_gen_unary (NEG, mode,
5416 simplify_gen_relational (cond_code,
5417 mode, VOIDmode,
5418 cond, cop1),
5419 mode);
5420 else if (CONST_INT_P (false_rtx)
5421 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
5422 && true_rtx == const0_rtx
5423 && ((reversed = reversed_comparison_code_parts
5424 (cond_code, cond, cop1, NULL))
5425 != UNKNOWN))
5426 x = simplify_gen_unary (NEG, mode,
5427 simplify_gen_relational (reversed,
5428 mode, VOIDmode,
5429 cond, cop1),
5430 mode);
5431 else
5432 return gen_rtx_IF_THEN_ELSE (mode,
5433 simplify_gen_relational (cond_code,
5434 mode,
5435 VOIDmode,
5436 cond,
5437 cop1),
5438 true_rtx, false_rtx);
5439
5440 code = GET_CODE (x);
5441 op0_mode = VOIDmode;
5442 }
5443 }
5444 }
5445
5446 /* Try to fold this expression in case we have constants that weren't
5447 present before. */
5448 temp = 0;
5449 switch (GET_RTX_CLASS (code))
5450 {
5451 case RTX_UNARY:
5452 if (op0_mode == VOIDmode)
5453 op0_mode = GET_MODE (XEXP (x, 0));
5454 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
5455 break;
5456 case RTX_COMPARE:
5457 case RTX_COMM_COMPARE:
5458 {
5459 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
5460 if (cmp_mode == VOIDmode)
5461 {
5462 cmp_mode = GET_MODE (XEXP (x, 1));
5463 if (cmp_mode == VOIDmode)
5464 cmp_mode = op0_mode;
5465 }
5466 temp = simplify_relational_operation (code, mode, cmp_mode,
5467 XEXP (x, 0), XEXP (x, 1));
5468 }
5469 break;
5470 case RTX_COMM_ARITH:
5471 case RTX_BIN_ARITH:
5472 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
5473 break;
5474 case RTX_BITFIELD_OPS:
5475 case RTX_TERNARY:
5476 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
5477 XEXP (x, 1), XEXP (x, 2));
5478 break;
5479 default:
5480 break;
5481 }
5482
5483 if (temp)
5484 {
5485 x = temp;
5486 code = GET_CODE (temp);
5487 op0_mode = VOIDmode;
5488 mode = GET_MODE (temp);
5489 }
5490
5491 /* First see if we can apply the inverse distributive law. */
5492 if (code == PLUS || code == MINUS
5493 || code == AND || code == IOR || code == XOR)
5494 {
5495 x = apply_distributive_law (x);
5496 code = GET_CODE (x);
5497 op0_mode = VOIDmode;
5498 }
5499
5500 /* If CODE is an associative operation not otherwise handled, see if we
5501 can associate some operands. This can win if they are constants or
5502 if they are logically related (i.e. (a & b) & a). */
5503 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
5504 || code == AND || code == IOR || code == XOR
5505 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
5506 && ((INTEGRAL_MODE_P (mode) && code != DIV)
5507 || (flag_associative_math && FLOAT_MODE_P (mode))))
5508 {
5509 if (GET_CODE (XEXP (x, 0)) == code)
5510 {
5511 rtx other = XEXP (XEXP (x, 0), 0);
5512 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
5513 rtx inner_op1 = XEXP (x, 1);
5514 rtx inner;
5515
5516 /* Make sure we pass the constant operand if any as the second
5517 one if this is a commutative operation. */
5518 if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
5519 {
5520 rtx tem = inner_op0;
5521 inner_op0 = inner_op1;
5522 inner_op1 = tem;
5523 }
5524 inner = simplify_binary_operation (code == MINUS ? PLUS
5525 : code == DIV ? MULT
5526 : code,
5527 mode, inner_op0, inner_op1);
5528
5529 /* For commutative operations, try the other pair if that one
5530 didn't simplify. */
5531 if (inner == 0 && COMMUTATIVE_ARITH_P (x))
5532 {
5533 other = XEXP (XEXP (x, 0), 1);
5534 inner = simplify_binary_operation (code, mode,
5535 XEXP (XEXP (x, 0), 0),
5536 XEXP (x, 1));
5537 }
5538
5539 if (inner)
5540 return simplify_gen_binary (code, mode, other, inner);
5541 }
5542 }
5543
5544 /* A little bit of algebraic simplification here. */
5545 switch (code)
5546 {
5547 case MEM:
5548 /* Ensure that our address has any ASHIFTs converted to MULT in case
5549 address-recognizing predicates are called later. */
5550 temp = make_compound_operation (XEXP (x, 0), MEM);
5551 SUBST (XEXP (x, 0), temp);
5552 break;
5553
5554 case SUBREG:
5555 if (op0_mode == VOIDmode)
5556 op0_mode = GET_MODE (SUBREG_REG (x));
5557
5558 /* See if this can be moved to simplify_subreg. */
5559 if (CONSTANT_P (SUBREG_REG (x))
5560 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
5561 /* Don't call gen_lowpart if the inner mode
5562 is VOIDmode and we cannot simplify it, as SUBREG without
5563 inner mode is invalid. */
5564 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
5565 || gen_lowpart_common (mode, SUBREG_REG (x))))
5566 return gen_lowpart (mode, SUBREG_REG (x));
5567
5568 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
5569 break;
5570 {
5571 rtx temp;
5572 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
5573 SUBREG_BYTE (x));
5574 if (temp)
5575 return temp;
5576 }
5577
5578 /* Don't change the mode of the MEM if that would change the meaning
5579 of the address. */
5580 if (MEM_P (SUBREG_REG (x))
5581 && (MEM_VOLATILE_P (SUBREG_REG (x))
5582 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
5583 return gen_rtx_CLOBBER (mode, const0_rtx);
5584
5585 /* Note that we cannot do any narrowing for non-constants since
5586 we might have been counting on using the fact that some bits were
5587 zero. We now do this in the SET. */
5588
5589 break;
5590
5591 case NEG:
5592 temp = expand_compound_operation (XEXP (x, 0));
5593
5594 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5595 replaced by (lshiftrt X C). This will convert
5596 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5597
5598 if (GET_CODE (temp) == ASHIFTRT
5599 && CONST_INT_P (XEXP (temp, 1))
5600 && INTVAL (XEXP (temp, 1)) == GET_MODE_PRECISION (mode) - 1)
5601 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
5602 INTVAL (XEXP (temp, 1)));
5603
5604 /* If X has only a single bit that might be nonzero, say, bit I, convert
5605 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5606 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5607 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5608 or a SUBREG of one since we'd be making the expression more
5609 complex if it was just a register. */
5610
5611 if (!REG_P (temp)
5612 && ! (GET_CODE (temp) == SUBREG
5613 && REG_P (SUBREG_REG (temp)))
5614 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
5615 {
5616 rtx temp1 = simplify_shift_const
5617 (NULL_RTX, ASHIFTRT, mode,
5618 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
5619 GET_MODE_PRECISION (mode) - 1 - i),
5620 GET_MODE_PRECISION (mode) - 1 - i);
5621
5622 /* If all we did was surround TEMP with the two shifts, we
5623 haven't improved anything, so don't use it. Otherwise,
5624 we are better off with TEMP1. */
5625 if (GET_CODE (temp1) != ASHIFTRT
5626 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
5627 || XEXP (XEXP (temp1, 0), 0) != temp)
5628 return temp1;
5629 }
5630 break;
5631
5632 case TRUNCATE:
5633 /* We can't handle truncation to a partial integer mode here
5634 because we don't know the real bitsize of the partial
5635 integer mode. */
5636 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
5637 break;
5638
5639 if (HWI_COMPUTABLE_MODE_P (mode))
5640 SUBST (XEXP (x, 0),
5641 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
5642 GET_MODE_MASK (mode), 0));
5643
5644 /* We can truncate a constant value and return it. */
5645 if (CONST_INT_P (XEXP (x, 0)))
5646 return gen_int_mode (INTVAL (XEXP (x, 0)), mode);
5647
5648 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5649 whose value is a comparison can be replaced with a subreg if
5650 STORE_FLAG_VALUE permits. */
5651 if (HWI_COMPUTABLE_MODE_P (mode)
5652 && (STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
5653 && (temp = get_last_value (XEXP (x, 0)))
5654 && COMPARISON_P (temp))
5655 return gen_lowpart (mode, XEXP (x, 0));
5656 break;
5657
5658 case CONST:
5659 /* (const (const X)) can become (const X). Do it this way rather than
5660 returning the inner CONST since CONST can be shared with a
5661 REG_EQUAL note. */
5662 if (GET_CODE (XEXP (x, 0)) == CONST)
5663 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
5664 break;
5665
5666 #ifdef HAVE_lo_sum
5667 case LO_SUM:
5668 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5669 can add in an offset. find_split_point will split this address up
5670 again if it doesn't match. */
5671 if (GET_CODE (XEXP (x, 0)) == HIGH
5672 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
5673 return XEXP (x, 1);
5674 break;
5675 #endif
5676
5677 case PLUS:
5678 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5679 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5680 bit-field and can be replaced by either a sign_extend or a
5681 sign_extract. The `and' may be a zero_extend and the two
5682 <c>, -<c> constants may be reversed. */
5683 if (GET_CODE (XEXP (x, 0)) == XOR
5684 && CONST_INT_P (XEXP (x, 1))
5685 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
5686 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
5687 && ((i = exact_log2 (UINTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
5688 || (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0)
5689 && HWI_COMPUTABLE_MODE_P (mode)
5690 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
5691 && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
5692 && (UINTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
5693 == ((unsigned HOST_WIDE_INT) 1 << (i + 1)) - 1))
5694 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
5695 && (GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
5696 == (unsigned int) i + 1))))
5697 return simplify_shift_const
5698 (NULL_RTX, ASHIFTRT, mode,
5699 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5700 XEXP (XEXP (XEXP (x, 0), 0), 0),
5701 GET_MODE_PRECISION (mode) - (i + 1)),
5702 GET_MODE_PRECISION (mode) - (i + 1));
5703
5704 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5705 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5706 the bitsize of the mode - 1. This allows simplification of
5707 "a = (b & 8) == 0;" */
5708 if (XEXP (x, 1) == constm1_rtx
5709 && !REG_P (XEXP (x, 0))
5710 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5711 && REG_P (SUBREG_REG (XEXP (x, 0))))
5712 && nonzero_bits (XEXP (x, 0), mode) == 1)
5713 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
5714 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5715 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
5716 GET_MODE_PRECISION (mode) - 1),
5717 GET_MODE_PRECISION (mode) - 1);
5718
5719 /* If we are adding two things that have no bits in common, convert
5720 the addition into an IOR. This will often be further simplified,
5721 for example in cases like ((a & 1) + (a & 2)), which can
5722 become a & 3. */
5723
5724 if (HWI_COMPUTABLE_MODE_P (mode)
5725 && (nonzero_bits (XEXP (x, 0), mode)
5726 & nonzero_bits (XEXP (x, 1), mode)) == 0)
5727 {
5728 /* Try to simplify the expression further. */
5729 rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
5730 temp = combine_simplify_rtx (tor, VOIDmode, in_dest, 0);
5731
5732 /* If we could, great. If not, do not go ahead with the IOR
5733 replacement, since PLUS appears in many special purpose
5734 address arithmetic instructions. */
5735 if (GET_CODE (temp) != CLOBBER
5736 && (GET_CODE (temp) != IOR
5737 || ((XEXP (temp, 0) != XEXP (x, 0)
5738 || XEXP (temp, 1) != XEXP (x, 1))
5739 && (XEXP (temp, 0) != XEXP (x, 1)
5740 || XEXP (temp, 1) != XEXP (x, 0)))))
5741 return temp;
5742 }
5743 break;
5744
5745 case MINUS:
5746 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5747 (and <foo> (const_int pow2-1)) */
5748 if (GET_CODE (XEXP (x, 1)) == AND
5749 && CONST_INT_P (XEXP (XEXP (x, 1), 1))
5750 && exact_log2 (-UINTVAL (XEXP (XEXP (x, 1), 1))) >= 0
5751 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
5752 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
5753 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
5754 break;
5755
5756 case MULT:
5757 /* If we have (mult (plus A B) C), apply the distributive law and then
5758 the inverse distributive law to see if things simplify. This
5759 occurs mostly in addresses, often when unrolling loops. */
5760
5761 if (GET_CODE (XEXP (x, 0)) == PLUS)
5762 {
5763 rtx result = distribute_and_simplify_rtx (x, 0);
5764 if (result)
5765 return result;
5766 }
5767
5768 /* Try simplify a*(b/c) as (a*b)/c. */
5769 if (FLOAT_MODE_P (mode) && flag_associative_math
5770 && GET_CODE (XEXP (x, 0)) == DIV)
5771 {
5772 rtx tem = simplify_binary_operation (MULT, mode,
5773 XEXP (XEXP (x, 0), 0),
5774 XEXP (x, 1));
5775 if (tem)
5776 return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
5777 }
5778 break;
5779
5780 case UDIV:
5781 /* If this is a divide by a power of two, treat it as a shift if
5782 its first operand is a shift. */
5783 if (CONST_INT_P (XEXP (x, 1))
5784 && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0
5785 && (GET_CODE (XEXP (x, 0)) == ASHIFT
5786 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
5787 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
5788 || GET_CODE (XEXP (x, 0)) == ROTATE
5789 || GET_CODE (XEXP (x, 0)) == ROTATERT))
5790 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
5791 break;
5792
5793 case EQ: case NE:
5794 case GT: case GTU: case GE: case GEU:
5795 case LT: case LTU: case LE: case LEU:
5796 case UNEQ: case LTGT:
5797 case UNGT: case UNGE:
5798 case UNLT: case UNLE:
5799 case UNORDERED: case ORDERED:
5800 /* If the first operand is a condition code, we can't do anything
5801 with it. */
5802 if (GET_CODE (XEXP (x, 0)) == COMPARE
5803 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
5804 && ! CC0_P (XEXP (x, 0))))
5805 {
5806 rtx op0 = XEXP (x, 0);
5807 rtx op1 = XEXP (x, 1);
5808 enum rtx_code new_code;
5809
5810 if (GET_CODE (op0) == COMPARE)
5811 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
5812
5813 /* Simplify our comparison, if possible. */
5814 new_code = simplify_comparison (code, &op0, &op1);
5815
5816 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5817 if only the low-order bit is possibly nonzero in X (such as when
5818 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5819 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5820 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5821 (plus X 1).
5822
5823 Remove any ZERO_EXTRACT we made when thinking this was a
5824 comparison. It may now be simpler to use, e.g., an AND. If a
5825 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5826 the call to make_compound_operation in the SET case.
5827
5828 Don't apply these optimizations if the caller would
5829 prefer a comparison rather than a value.
5830 E.g., for the condition in an IF_THEN_ELSE most targets need
5831 an explicit comparison. */
5832
5833 if (in_cond)
5834 ;
5835
5836 else if (STORE_FLAG_VALUE == 1
5837 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5838 && op1 == const0_rtx
5839 && mode == GET_MODE (op0)
5840 && nonzero_bits (op0, mode) == 1)
5841 return gen_lowpart (mode,
5842 expand_compound_operation (op0));
5843
5844 else if (STORE_FLAG_VALUE == 1
5845 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5846 && op1 == const0_rtx
5847 && mode == GET_MODE (op0)
5848 && (num_sign_bit_copies (op0, mode)
5849 == GET_MODE_PRECISION (mode)))
5850 {
5851 op0 = expand_compound_operation (op0);
5852 return simplify_gen_unary (NEG, mode,
5853 gen_lowpart (mode, op0),
5854 mode);
5855 }
5856
5857 else if (STORE_FLAG_VALUE == 1
5858 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5859 && op1 == const0_rtx
5860 && mode == GET_MODE (op0)
5861 && nonzero_bits (op0, mode) == 1)
5862 {
5863 op0 = expand_compound_operation (op0);
5864 return simplify_gen_binary (XOR, mode,
5865 gen_lowpart (mode, op0),
5866 const1_rtx);
5867 }
5868
5869 else if (STORE_FLAG_VALUE == 1
5870 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5871 && op1 == const0_rtx
5872 && mode == GET_MODE (op0)
5873 && (num_sign_bit_copies (op0, mode)
5874 == GET_MODE_PRECISION (mode)))
5875 {
5876 op0 = expand_compound_operation (op0);
5877 return plus_constant (gen_lowpart (mode, op0), 1);
5878 }
5879
5880 /* If STORE_FLAG_VALUE is -1, we have cases similar to
5881 those above. */
5882 if (in_cond)
5883 ;
5884
5885 else if (STORE_FLAG_VALUE == -1
5886 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5887 && op1 == const0_rtx
5888 && (num_sign_bit_copies (op0, mode)
5889 == GET_MODE_PRECISION (mode)))
5890 return gen_lowpart (mode,
5891 expand_compound_operation (op0));
5892
5893 else if (STORE_FLAG_VALUE == -1
5894 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5895 && op1 == const0_rtx
5896 && mode == GET_MODE (op0)
5897 && nonzero_bits (op0, mode) == 1)
5898 {
5899 op0 = expand_compound_operation (op0);
5900 return simplify_gen_unary (NEG, mode,
5901 gen_lowpart (mode, op0),
5902 mode);
5903 }
5904
5905 else if (STORE_FLAG_VALUE == -1
5906 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5907 && op1 == const0_rtx
5908 && mode == GET_MODE (op0)
5909 && (num_sign_bit_copies (op0, mode)
5910 == GET_MODE_PRECISION (mode)))
5911 {
5912 op0 = expand_compound_operation (op0);
5913 return simplify_gen_unary (NOT, mode,
5914 gen_lowpart (mode, op0),
5915 mode);
5916 }
5917
5918 /* If X is 0/1, (eq X 0) is X-1. */
5919 else if (STORE_FLAG_VALUE == -1
5920 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5921 && op1 == const0_rtx
5922 && mode == GET_MODE (op0)
5923 && nonzero_bits (op0, mode) == 1)
5924 {
5925 op0 = expand_compound_operation (op0);
5926 return plus_constant (gen_lowpart (mode, op0), -1);
5927 }
5928
5929 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5930 one bit that might be nonzero, we can convert (ne x 0) to
5931 (ashift x c) where C puts the bit in the sign bit. Remove any
5932 AND with STORE_FLAG_VALUE when we are done, since we are only
5933 going to test the sign bit. */
5934 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5935 && HWI_COMPUTABLE_MODE_P (mode)
5936 && val_signbit_p (mode, STORE_FLAG_VALUE)
5937 && op1 == const0_rtx
5938 && mode == GET_MODE (op0)
5939 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
5940 {
5941 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
5942 expand_compound_operation (op0),
5943 GET_MODE_PRECISION (mode) - 1 - i);
5944 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
5945 return XEXP (x, 0);
5946 else
5947 return x;
5948 }
5949
5950 /* If the code changed, return a whole new comparison. */
5951 if (new_code != code)
5952 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
5953
5954 /* Otherwise, keep this operation, but maybe change its operands.
5955 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
5956 SUBST (XEXP (x, 0), op0);
5957 SUBST (XEXP (x, 1), op1);
5958 }
5959 break;
5960
5961 case IF_THEN_ELSE:
5962 return simplify_if_then_else (x);
5963
5964 case ZERO_EXTRACT:
5965 case SIGN_EXTRACT:
5966 case ZERO_EXTEND:
5967 case SIGN_EXTEND:
5968 /* If we are processing SET_DEST, we are done. */
5969 if (in_dest)
5970 return x;
5971
5972 return expand_compound_operation (x);
5973
5974 case SET:
5975 return simplify_set (x);
5976
5977 case AND:
5978 case IOR:
5979 return simplify_logical (x);
5980
5981 case ASHIFT:
5982 case LSHIFTRT:
5983 case ASHIFTRT:
5984 case ROTATE:
5985 case ROTATERT:
5986 /* If this is a shift by a constant amount, simplify it. */
5987 if (CONST_INT_P (XEXP (x, 1)))
5988 return simplify_shift_const (x, code, mode, XEXP (x, 0),
5989 INTVAL (XEXP (x, 1)));
5990
5991 else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
5992 SUBST (XEXP (x, 1),
5993 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
5994 ((unsigned HOST_WIDE_INT) 1
5995 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
5996 - 1,
5997 0));
5998 break;
5999
6000 default:
6001 break;
6002 }
6003
6004 return x;
6005 }
6006
6007 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6008
6009 static rtx
simplify_if_then_else(rtx x)6010 simplify_if_then_else (rtx x)
6011 {
6012 enum machine_mode mode = GET_MODE (x);
6013 rtx cond = XEXP (x, 0);
6014 rtx true_rtx = XEXP (x, 1);
6015 rtx false_rtx = XEXP (x, 2);
6016 enum rtx_code true_code = GET_CODE (cond);
6017 int comparison_p = COMPARISON_P (cond);
6018 rtx temp;
6019 int i;
6020 enum rtx_code false_code;
6021 rtx reversed;
6022
6023 /* Simplify storing of the truth value. */
6024 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
6025 return simplify_gen_relational (true_code, mode, VOIDmode,
6026 XEXP (cond, 0), XEXP (cond, 1));
6027
6028 /* Also when the truth value has to be reversed. */
6029 if (comparison_p
6030 && true_rtx == const0_rtx && false_rtx == const_true_rtx
6031 && (reversed = reversed_comparison (cond, mode)))
6032 return reversed;
6033
6034 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6035 in it is being compared against certain values. Get the true and false
6036 comparisons and see if that says anything about the value of each arm. */
6037
6038 if (comparison_p
6039 && ((false_code = reversed_comparison_code (cond, NULL))
6040 != UNKNOWN)
6041 && REG_P (XEXP (cond, 0)))
6042 {
6043 HOST_WIDE_INT nzb;
6044 rtx from = XEXP (cond, 0);
6045 rtx true_val = XEXP (cond, 1);
6046 rtx false_val = true_val;
6047 int swapped = 0;
6048
6049 /* If FALSE_CODE is EQ, swap the codes and arms. */
6050
6051 if (false_code == EQ)
6052 {
6053 swapped = 1, true_code = EQ, false_code = NE;
6054 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
6055 }
6056
6057 /* If we are comparing against zero and the expression being tested has
6058 only a single bit that might be nonzero, that is its value when it is
6059 not equal to zero. Similarly if it is known to be -1 or 0. */
6060
6061 if (true_code == EQ && true_val == const0_rtx
6062 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
6063 {
6064 false_code = EQ;
6065 false_val = gen_int_mode (nzb, GET_MODE (from));
6066 }
6067 else if (true_code == EQ && true_val == const0_rtx
6068 && (num_sign_bit_copies (from, GET_MODE (from))
6069 == GET_MODE_PRECISION (GET_MODE (from))))
6070 {
6071 false_code = EQ;
6072 false_val = constm1_rtx;
6073 }
6074
6075 /* Now simplify an arm if we know the value of the register in the
6076 branch and it is used in the arm. Be careful due to the potential
6077 of locally-shared RTL. */
6078
6079 if (reg_mentioned_p (from, true_rtx))
6080 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
6081 from, true_val),
6082 pc_rtx, pc_rtx, 0, 0, 0);
6083 if (reg_mentioned_p (from, false_rtx))
6084 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
6085 from, false_val),
6086 pc_rtx, pc_rtx, 0, 0, 0);
6087
6088 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
6089 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
6090
6091 true_rtx = XEXP (x, 1);
6092 false_rtx = XEXP (x, 2);
6093 true_code = GET_CODE (cond);
6094 }
6095
6096 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6097 reversed, do so to avoid needing two sets of patterns for
6098 subtract-and-branch insns. Similarly if we have a constant in the true
6099 arm, the false arm is the same as the first operand of the comparison, or
6100 the false arm is more complicated than the true arm. */
6101
6102 if (comparison_p
6103 && reversed_comparison_code (cond, NULL) != UNKNOWN
6104 && (true_rtx == pc_rtx
6105 || (CONSTANT_P (true_rtx)
6106 && !CONST_INT_P (false_rtx) && false_rtx != pc_rtx)
6107 || true_rtx == const0_rtx
6108 || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
6109 || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
6110 && !OBJECT_P (false_rtx))
6111 || reg_mentioned_p (true_rtx, false_rtx)
6112 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
6113 {
6114 true_code = reversed_comparison_code (cond, NULL);
6115 SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
6116 SUBST (XEXP (x, 1), false_rtx);
6117 SUBST (XEXP (x, 2), true_rtx);
6118
6119 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
6120 cond = XEXP (x, 0);
6121
6122 /* It is possible that the conditional has been simplified out. */
6123 true_code = GET_CODE (cond);
6124 comparison_p = COMPARISON_P (cond);
6125 }
6126
6127 /* If the two arms are identical, we don't need the comparison. */
6128
6129 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
6130 return true_rtx;
6131
6132 /* Convert a == b ? b : a to "a". */
6133 if (true_code == EQ && ! side_effects_p (cond)
6134 && !HONOR_NANS (mode)
6135 && rtx_equal_p (XEXP (cond, 0), false_rtx)
6136 && rtx_equal_p (XEXP (cond, 1), true_rtx))
6137 return false_rtx;
6138 else if (true_code == NE && ! side_effects_p (cond)
6139 && !HONOR_NANS (mode)
6140 && rtx_equal_p (XEXP (cond, 0), true_rtx)
6141 && rtx_equal_p (XEXP (cond, 1), false_rtx))
6142 return true_rtx;
6143
6144 /* Look for cases where we have (abs x) or (neg (abs X)). */
6145
6146 if (GET_MODE_CLASS (mode) == MODE_INT
6147 && comparison_p
6148 && XEXP (cond, 1) == const0_rtx
6149 && GET_CODE (false_rtx) == NEG
6150 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
6151 && rtx_equal_p (true_rtx, XEXP (cond, 0))
6152 && ! side_effects_p (true_rtx))
6153 switch (true_code)
6154 {
6155 case GT:
6156 case GE:
6157 return simplify_gen_unary (ABS, mode, true_rtx, mode);
6158 case LT:
6159 case LE:
6160 return
6161 simplify_gen_unary (NEG, mode,
6162 simplify_gen_unary (ABS, mode, true_rtx, mode),
6163 mode);
6164 default:
6165 break;
6166 }
6167
6168 /* Look for MIN or MAX. */
6169
6170 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
6171 && comparison_p
6172 && rtx_equal_p (XEXP (cond, 0), true_rtx)
6173 && rtx_equal_p (XEXP (cond, 1), false_rtx)
6174 && ! side_effects_p (cond))
6175 switch (true_code)
6176 {
6177 case GE:
6178 case GT:
6179 return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
6180 case LE:
6181 case LT:
6182 return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
6183 case GEU:
6184 case GTU:
6185 return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
6186 case LEU:
6187 case LTU:
6188 return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
6189 default:
6190 break;
6191 }
6192
6193 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6194 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6195 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6196 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6197 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6198 neither 1 or -1, but it isn't worth checking for. */
6199
6200 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6201 && comparison_p
6202 && GET_MODE_CLASS (mode) == MODE_INT
6203 && ! side_effects_p (x))
6204 {
6205 rtx t = make_compound_operation (true_rtx, SET);
6206 rtx f = make_compound_operation (false_rtx, SET);
6207 rtx cond_op0 = XEXP (cond, 0);
6208 rtx cond_op1 = XEXP (cond, 1);
6209 enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
6210 enum machine_mode m = mode;
6211 rtx z = 0, c1 = NULL_RTX;
6212
6213 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
6214 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
6215 || GET_CODE (t) == ASHIFT
6216 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
6217 && rtx_equal_p (XEXP (t, 0), f))
6218 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
6219
6220 /* If an identity-zero op is commutative, check whether there
6221 would be a match if we swapped the operands. */
6222 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
6223 || GET_CODE (t) == XOR)
6224 && rtx_equal_p (XEXP (t, 1), f))
6225 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
6226 else if (GET_CODE (t) == SIGN_EXTEND
6227 && (GET_CODE (XEXP (t, 0)) == PLUS
6228 || GET_CODE (XEXP (t, 0)) == MINUS
6229 || GET_CODE (XEXP (t, 0)) == IOR
6230 || GET_CODE (XEXP (t, 0)) == XOR
6231 || GET_CODE (XEXP (t, 0)) == ASHIFT
6232 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6233 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6234 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6235 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6236 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6237 && (num_sign_bit_copies (f, GET_MODE (f))
6238 > (unsigned int)
6239 (GET_MODE_PRECISION (mode)
6240 - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t, 0), 0))))))
6241 {
6242 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6243 extend_op = SIGN_EXTEND;
6244 m = GET_MODE (XEXP (t, 0));
6245 }
6246 else if (GET_CODE (t) == SIGN_EXTEND
6247 && (GET_CODE (XEXP (t, 0)) == PLUS
6248 || GET_CODE (XEXP (t, 0)) == IOR
6249 || GET_CODE (XEXP (t, 0)) == XOR)
6250 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6251 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6252 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6253 && (num_sign_bit_copies (f, GET_MODE (f))
6254 > (unsigned int)
6255 (GET_MODE_PRECISION (mode)
6256 - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t, 0), 1))))))
6257 {
6258 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6259 extend_op = SIGN_EXTEND;
6260 m = GET_MODE (XEXP (t, 0));
6261 }
6262 else if (GET_CODE (t) == ZERO_EXTEND
6263 && (GET_CODE (XEXP (t, 0)) == PLUS
6264 || GET_CODE (XEXP (t, 0)) == MINUS
6265 || GET_CODE (XEXP (t, 0)) == IOR
6266 || GET_CODE (XEXP (t, 0)) == XOR
6267 || GET_CODE (XEXP (t, 0)) == ASHIFT
6268 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6269 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6270 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6271 && HWI_COMPUTABLE_MODE_P (mode)
6272 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6273 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6274 && ((nonzero_bits (f, GET_MODE (f))
6275 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
6276 == 0))
6277 {
6278 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6279 extend_op = ZERO_EXTEND;
6280 m = GET_MODE (XEXP (t, 0));
6281 }
6282 else if (GET_CODE (t) == ZERO_EXTEND
6283 && (GET_CODE (XEXP (t, 0)) == PLUS
6284 || GET_CODE (XEXP (t, 0)) == IOR
6285 || GET_CODE (XEXP (t, 0)) == XOR)
6286 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6287 && HWI_COMPUTABLE_MODE_P (mode)
6288 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6289 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6290 && ((nonzero_bits (f, GET_MODE (f))
6291 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
6292 == 0))
6293 {
6294 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6295 extend_op = ZERO_EXTEND;
6296 m = GET_MODE (XEXP (t, 0));
6297 }
6298
6299 if (z)
6300 {
6301 temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
6302 cond_op0, cond_op1),
6303 pc_rtx, pc_rtx, 0, 0, 0);
6304 temp = simplify_gen_binary (MULT, m, temp,
6305 simplify_gen_binary (MULT, m, c1,
6306 const_true_rtx));
6307 temp = subst (temp, pc_rtx, pc_rtx, 0, 0, 0);
6308 temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
6309
6310 if (extend_op != UNKNOWN)
6311 temp = simplify_gen_unary (extend_op, mode, temp, m);
6312
6313 return temp;
6314 }
6315 }
6316
6317 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6318 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6319 negation of a single bit, we can convert this operation to a shift. We
6320 can actually do this more generally, but it doesn't seem worth it. */
6321
6322 if (true_code == NE && XEXP (cond, 1) == const0_rtx
6323 && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
6324 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
6325 && (i = exact_log2 (UINTVAL (true_rtx))) >= 0)
6326 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
6327 == GET_MODE_PRECISION (mode))
6328 && (i = exact_log2 (-UINTVAL (true_rtx))) >= 0)))
6329 return
6330 simplify_shift_const (NULL_RTX, ASHIFT, mode,
6331 gen_lowpart (mode, XEXP (cond, 0)), i);
6332
6333 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
6334 if (true_code == NE && XEXP (cond, 1) == const0_rtx
6335 && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
6336 && GET_MODE (XEXP (cond, 0)) == mode
6337 && (UINTVAL (true_rtx) & GET_MODE_MASK (mode))
6338 == nonzero_bits (XEXP (cond, 0), mode)
6339 && (i = exact_log2 (UINTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
6340 return XEXP (cond, 0);
6341
6342 return x;
6343 }
6344
6345 /* Simplify X, a SET expression. Return the new expression. */
6346
6347 static rtx
simplify_set(rtx x)6348 simplify_set (rtx x)
6349 {
6350 rtx src = SET_SRC (x);
6351 rtx dest = SET_DEST (x);
6352 enum machine_mode mode
6353 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
6354 rtx other_insn;
6355 rtx *cc_use;
6356
6357 /* (set (pc) (return)) gets written as (return). */
6358 if (GET_CODE (dest) == PC && ANY_RETURN_P (src))
6359 return src;
6360
6361 /* Now that we know for sure which bits of SRC we are using, see if we can
6362 simplify the expression for the object knowing that we only need the
6363 low-order bits. */
6364
6365 if (GET_MODE_CLASS (mode) == MODE_INT && HWI_COMPUTABLE_MODE_P (mode))
6366 {
6367 src = force_to_mode (src, mode, ~(unsigned HOST_WIDE_INT) 0, 0);
6368 SUBST (SET_SRC (x), src);
6369 }
6370
6371 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6372 the comparison result and try to simplify it unless we already have used
6373 undobuf.other_insn. */
6374 if ((GET_MODE_CLASS (mode) == MODE_CC
6375 || GET_CODE (src) == COMPARE
6376 || CC0_P (dest))
6377 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
6378 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
6379 && COMPARISON_P (*cc_use)
6380 && rtx_equal_p (XEXP (*cc_use, 0), dest))
6381 {
6382 enum rtx_code old_code = GET_CODE (*cc_use);
6383 enum rtx_code new_code;
6384 rtx op0, op1, tmp;
6385 int other_changed = 0;
6386 rtx inner_compare = NULL_RTX;
6387 enum machine_mode compare_mode = GET_MODE (dest);
6388
6389 if (GET_CODE (src) == COMPARE)
6390 {
6391 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
6392 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
6393 {
6394 inner_compare = op0;
6395 op0 = XEXP (inner_compare, 0), op1 = XEXP (inner_compare, 1);
6396 }
6397 }
6398 else
6399 op0 = src, op1 = CONST0_RTX (GET_MODE (src));
6400
6401 tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
6402 op0, op1);
6403 if (!tmp)
6404 new_code = old_code;
6405 else if (!CONSTANT_P (tmp))
6406 {
6407 new_code = GET_CODE (tmp);
6408 op0 = XEXP (tmp, 0);
6409 op1 = XEXP (tmp, 1);
6410 }
6411 else
6412 {
6413 rtx pat = PATTERN (other_insn);
6414 undobuf.other_insn = other_insn;
6415 SUBST (*cc_use, tmp);
6416
6417 /* Attempt to simplify CC user. */
6418 if (GET_CODE (pat) == SET)
6419 {
6420 rtx new_rtx = simplify_rtx (SET_SRC (pat));
6421 if (new_rtx != NULL_RTX)
6422 SUBST (SET_SRC (pat), new_rtx);
6423 }
6424
6425 /* Convert X into a no-op move. */
6426 SUBST (SET_DEST (x), pc_rtx);
6427 SUBST (SET_SRC (x), pc_rtx);
6428 return x;
6429 }
6430
6431 /* Simplify our comparison, if possible. */
6432 new_code = simplify_comparison (new_code, &op0, &op1);
6433
6434 #ifdef SELECT_CC_MODE
6435 /* If this machine has CC modes other than CCmode, check to see if we
6436 need to use a different CC mode here. */
6437 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
6438 compare_mode = GET_MODE (op0);
6439 else if (inner_compare
6440 && GET_MODE_CLASS (GET_MODE (inner_compare)) == MODE_CC
6441 && new_code == old_code
6442 && op0 == XEXP (inner_compare, 0)
6443 && op1 == XEXP (inner_compare, 1))
6444 compare_mode = GET_MODE (inner_compare);
6445 else
6446 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
6447
6448 #ifndef HAVE_cc0
6449 /* If the mode changed, we have to change SET_DEST, the mode in the
6450 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6451 a hard register, just build new versions with the proper mode. If it
6452 is a pseudo, we lose unless it is only time we set the pseudo, in
6453 which case we can safely change its mode. */
6454 if (compare_mode != GET_MODE (dest))
6455 {
6456 if (can_change_dest_mode (dest, 0, compare_mode))
6457 {
6458 unsigned int regno = REGNO (dest);
6459 rtx new_dest;
6460
6461 if (regno < FIRST_PSEUDO_REGISTER)
6462 new_dest = gen_rtx_REG (compare_mode, regno);
6463 else
6464 {
6465 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
6466 new_dest = regno_reg_rtx[regno];
6467 }
6468
6469 SUBST (SET_DEST (x), new_dest);
6470 SUBST (XEXP (*cc_use, 0), new_dest);
6471 other_changed = 1;
6472
6473 dest = new_dest;
6474 }
6475 }
6476 #endif /* cc0 */
6477 #endif /* SELECT_CC_MODE */
6478
6479 /* If the code changed, we have to build a new comparison in
6480 undobuf.other_insn. */
6481 if (new_code != old_code)
6482 {
6483 int other_changed_previously = other_changed;
6484 unsigned HOST_WIDE_INT mask;
6485 rtx old_cc_use = *cc_use;
6486
6487 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
6488 dest, const0_rtx));
6489 other_changed = 1;
6490
6491 /* If the only change we made was to change an EQ into an NE or
6492 vice versa, OP0 has only one bit that might be nonzero, and OP1
6493 is zero, check if changing the user of the condition code will
6494 produce a valid insn. If it won't, we can keep the original code
6495 in that insn by surrounding our operation with an XOR. */
6496
6497 if (((old_code == NE && new_code == EQ)
6498 || (old_code == EQ && new_code == NE))
6499 && ! other_changed_previously && op1 == const0_rtx
6500 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0))
6501 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
6502 {
6503 rtx pat = PATTERN (other_insn), note = 0;
6504
6505 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
6506 && ! check_asm_operands (pat)))
6507 {
6508 *cc_use = old_cc_use;
6509 other_changed = 0;
6510
6511 op0 = simplify_gen_binary (XOR, GET_MODE (op0),
6512 op0, GEN_INT (mask));
6513 }
6514 }
6515 }
6516
6517 if (other_changed)
6518 undobuf.other_insn = other_insn;
6519
6520 /* Otherwise, if we didn't previously have a COMPARE in the
6521 correct mode, we need one. */
6522 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
6523 {
6524 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6525 src = SET_SRC (x);
6526 }
6527 else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
6528 {
6529 SUBST (SET_SRC (x), op0);
6530 src = SET_SRC (x);
6531 }
6532 /* Otherwise, update the COMPARE if needed. */
6533 else if (XEXP (src, 0) != op0 || XEXP (src, 1) != op1)
6534 {
6535 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6536 src = SET_SRC (x);
6537 }
6538 }
6539 else
6540 {
6541 /* Get SET_SRC in a form where we have placed back any
6542 compound expressions. Then do the checks below. */
6543 src = make_compound_operation (src, SET);
6544 SUBST (SET_SRC (x), src);
6545 }
6546
6547 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6548 and X being a REG or (subreg (reg)), we may be able to convert this to
6549 (set (subreg:m2 x) (op)).
6550
6551 We can always do this if M1 is narrower than M2 because that means that
6552 we only care about the low bits of the result.
6553
6554 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6555 perform a narrower operation than requested since the high-order bits will
6556 be undefined. On machine where it is defined, this transformation is safe
6557 as long as M1 and M2 have the same number of words. */
6558
6559 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6560 && !OBJECT_P (SUBREG_REG (src))
6561 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
6562 / UNITS_PER_WORD)
6563 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
6564 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
6565 #ifndef WORD_REGISTER_OPERATIONS
6566 && (GET_MODE_SIZE (GET_MODE (src))
6567 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
6568 #endif
6569 #ifdef CANNOT_CHANGE_MODE_CLASS
6570 && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
6571 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
6572 GET_MODE (SUBREG_REG (src)),
6573 GET_MODE (src)))
6574 #endif
6575 && (REG_P (dest)
6576 || (GET_CODE (dest) == SUBREG
6577 && REG_P (SUBREG_REG (dest)))))
6578 {
6579 SUBST (SET_DEST (x),
6580 gen_lowpart (GET_MODE (SUBREG_REG (src)),
6581 dest));
6582 SUBST (SET_SRC (x), SUBREG_REG (src));
6583
6584 src = SET_SRC (x), dest = SET_DEST (x);
6585 }
6586
6587 #ifdef HAVE_cc0
6588 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6589 in SRC. */
6590 if (dest == cc0_rtx
6591 && GET_CODE (src) == SUBREG
6592 && subreg_lowpart_p (src)
6593 && (GET_MODE_PRECISION (GET_MODE (src))
6594 < GET_MODE_PRECISION (GET_MODE (SUBREG_REG (src)))))
6595 {
6596 rtx inner = SUBREG_REG (src);
6597 enum machine_mode inner_mode = GET_MODE (inner);
6598
6599 /* Here we make sure that we don't have a sign bit on. */
6600 if (val_signbit_known_clear_p (GET_MODE (src),
6601 nonzero_bits (inner, inner_mode)))
6602 {
6603 SUBST (SET_SRC (x), inner);
6604 src = SET_SRC (x);
6605 }
6606 }
6607 #endif
6608
6609 #ifdef LOAD_EXTEND_OP
6610 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6611 would require a paradoxical subreg. Replace the subreg with a
6612 zero_extend to avoid the reload that would otherwise be required. */
6613
6614 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6615 && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src)))
6616 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
6617 && SUBREG_BYTE (src) == 0
6618 && paradoxical_subreg_p (src)
6619 && MEM_P (SUBREG_REG (src)))
6620 {
6621 SUBST (SET_SRC (x),
6622 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
6623 GET_MODE (src), SUBREG_REG (src)));
6624
6625 src = SET_SRC (x);
6626 }
6627 #endif
6628
6629 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6630 are comparing an item known to be 0 or -1 against 0, use a logical
6631 operation instead. Check for one of the arms being an IOR of the other
6632 arm with some value. We compute three terms to be IOR'ed together. In
6633 practice, at most two will be nonzero. Then we do the IOR's. */
6634
6635 if (GET_CODE (dest) != PC
6636 && GET_CODE (src) == IF_THEN_ELSE
6637 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
6638 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
6639 && XEXP (XEXP (src, 0), 1) == const0_rtx
6640 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
6641 #ifdef HAVE_conditional_move
6642 && ! can_conditionally_move_p (GET_MODE (src))
6643 #endif
6644 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
6645 GET_MODE (XEXP (XEXP (src, 0), 0)))
6646 == GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (src, 0), 0))))
6647 && ! side_effects_p (src))
6648 {
6649 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
6650 ? XEXP (src, 1) : XEXP (src, 2));
6651 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
6652 ? XEXP (src, 2) : XEXP (src, 1));
6653 rtx term1 = const0_rtx, term2, term3;
6654
6655 if (GET_CODE (true_rtx) == IOR
6656 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
6657 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
6658 else if (GET_CODE (true_rtx) == IOR
6659 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
6660 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
6661 else if (GET_CODE (false_rtx) == IOR
6662 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
6663 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
6664 else if (GET_CODE (false_rtx) == IOR
6665 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
6666 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
6667
6668 term2 = simplify_gen_binary (AND, GET_MODE (src),
6669 XEXP (XEXP (src, 0), 0), true_rtx);
6670 term3 = simplify_gen_binary (AND, GET_MODE (src),
6671 simplify_gen_unary (NOT, GET_MODE (src),
6672 XEXP (XEXP (src, 0), 0),
6673 GET_MODE (src)),
6674 false_rtx);
6675
6676 SUBST (SET_SRC (x),
6677 simplify_gen_binary (IOR, GET_MODE (src),
6678 simplify_gen_binary (IOR, GET_MODE (src),
6679 term1, term2),
6680 term3));
6681
6682 src = SET_SRC (x);
6683 }
6684
6685 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6686 whole thing fail. */
6687 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
6688 return src;
6689 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
6690 return dest;
6691 else
6692 /* Convert this into a field assignment operation, if possible. */
6693 return make_field_assignment (x);
6694 }
6695
6696 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6697 result. */
6698
6699 static rtx
simplify_logical(rtx x)6700 simplify_logical (rtx x)
6701 {
6702 enum machine_mode mode = GET_MODE (x);
6703 rtx op0 = XEXP (x, 0);
6704 rtx op1 = XEXP (x, 1);
6705
6706 switch (GET_CODE (x))
6707 {
6708 case AND:
6709 /* We can call simplify_and_const_int only if we don't lose
6710 any (sign) bits when converting INTVAL (op1) to
6711 "unsigned HOST_WIDE_INT". */
6712 if (CONST_INT_P (op1)
6713 && (HWI_COMPUTABLE_MODE_P (mode)
6714 || INTVAL (op1) > 0))
6715 {
6716 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
6717 if (GET_CODE (x) != AND)
6718 return x;
6719
6720 op0 = XEXP (x, 0);
6721 op1 = XEXP (x, 1);
6722 }
6723
6724 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6725 apply the distributive law and then the inverse distributive
6726 law to see if things simplify. */
6727 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
6728 {
6729 rtx result = distribute_and_simplify_rtx (x, 0);
6730 if (result)
6731 return result;
6732 }
6733 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
6734 {
6735 rtx result = distribute_and_simplify_rtx (x, 1);
6736 if (result)
6737 return result;
6738 }
6739 break;
6740
6741 case IOR:
6742 /* If we have (ior (and A B) C), apply the distributive law and then
6743 the inverse distributive law to see if things simplify. */
6744
6745 if (GET_CODE (op0) == AND)
6746 {
6747 rtx result = distribute_and_simplify_rtx (x, 0);
6748 if (result)
6749 return result;
6750 }
6751
6752 if (GET_CODE (op1) == AND)
6753 {
6754 rtx result = distribute_and_simplify_rtx (x, 1);
6755 if (result)
6756 return result;
6757 }
6758 break;
6759
6760 default:
6761 gcc_unreachable ();
6762 }
6763
6764 return x;
6765 }
6766
6767 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6768 operations" because they can be replaced with two more basic operations.
6769 ZERO_EXTEND is also considered "compound" because it can be replaced with
6770 an AND operation, which is simpler, though only one operation.
6771
6772 The function expand_compound_operation is called with an rtx expression
6773 and will convert it to the appropriate shifts and AND operations,
6774 simplifying at each stage.
6775
6776 The function make_compound_operation is called to convert an expression
6777 consisting of shifts and ANDs into the equivalent compound expression.
6778 It is the inverse of this function, loosely speaking. */
6779
6780 static rtx
expand_compound_operation(rtx x)6781 expand_compound_operation (rtx x)
6782 {
6783 unsigned HOST_WIDE_INT pos = 0, len;
6784 int unsignedp = 0;
6785 unsigned int modewidth;
6786 rtx tem;
6787
6788 switch (GET_CODE (x))
6789 {
6790 case ZERO_EXTEND:
6791 unsignedp = 1;
6792 case SIGN_EXTEND:
6793 /* We can't necessarily use a const_int for a multiword mode;
6794 it depends on implicitly extending the value.
6795 Since we don't know the right way to extend it,
6796 we can't tell whether the implicit way is right.
6797
6798 Even for a mode that is no wider than a const_int,
6799 we can't win, because we need to sign extend one of its bits through
6800 the rest of it, and we don't know which bit. */
6801 if (CONST_INT_P (XEXP (x, 0)))
6802 return x;
6803
6804 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6805 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6806 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6807 reloaded. If not for that, MEM's would very rarely be safe.
6808
6809 Reject MODEs bigger than a word, because we might not be able
6810 to reference a two-register group starting with an arbitrary register
6811 (and currently gen_lowpart might crash for a SUBREG). */
6812
6813 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
6814 return x;
6815
6816 /* Reject MODEs that aren't scalar integers because turning vector
6817 or complex modes into shifts causes problems. */
6818
6819 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6820 return x;
6821
6822 len = GET_MODE_PRECISION (GET_MODE (XEXP (x, 0)));
6823 /* If the inner object has VOIDmode (the only way this can happen
6824 is if it is an ASM_OPERANDS), we can't do anything since we don't
6825 know how much masking to do. */
6826 if (len == 0)
6827 return x;
6828
6829 break;
6830
6831 case ZERO_EXTRACT:
6832 unsignedp = 1;
6833
6834 /* ... fall through ... */
6835
6836 case SIGN_EXTRACT:
6837 /* If the operand is a CLOBBER, just return it. */
6838 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
6839 return XEXP (x, 0);
6840
6841 if (!CONST_INT_P (XEXP (x, 1))
6842 || !CONST_INT_P (XEXP (x, 2))
6843 || GET_MODE (XEXP (x, 0)) == VOIDmode)
6844 return x;
6845
6846 /* Reject MODEs that aren't scalar integers because turning vector
6847 or complex modes into shifts causes problems. */
6848
6849 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6850 return x;
6851
6852 len = INTVAL (XEXP (x, 1));
6853 pos = INTVAL (XEXP (x, 2));
6854
6855 /* This should stay within the object being extracted, fail otherwise. */
6856 if (len + pos > GET_MODE_PRECISION (GET_MODE (XEXP (x, 0))))
6857 return x;
6858
6859 if (BITS_BIG_ENDIAN)
6860 pos = GET_MODE_PRECISION (GET_MODE (XEXP (x, 0))) - len - pos;
6861
6862 break;
6863
6864 default:
6865 return x;
6866 }
6867 /* Convert sign extension to zero extension, if we know that the high
6868 bit is not set, as this is easier to optimize. It will be converted
6869 back to cheaper alternative in make_extraction. */
6870 if (GET_CODE (x) == SIGN_EXTEND
6871 && (HWI_COMPUTABLE_MODE_P (GET_MODE (x))
6872 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6873 & ~(((unsigned HOST_WIDE_INT)
6874 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
6875 >> 1))
6876 == 0)))
6877 {
6878 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
6879 rtx temp2 = expand_compound_operation (temp);
6880
6881 /* Make sure this is a profitable operation. */
6882 if (set_src_cost (x, optimize_this_for_speed_p)
6883 > set_src_cost (temp2, optimize_this_for_speed_p))
6884 return temp2;
6885 else if (set_src_cost (x, optimize_this_for_speed_p)
6886 > set_src_cost (temp, optimize_this_for_speed_p))
6887 return temp;
6888 else
6889 return x;
6890 }
6891
6892 /* We can optimize some special cases of ZERO_EXTEND. */
6893 if (GET_CODE (x) == ZERO_EXTEND)
6894 {
6895 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6896 know that the last value didn't have any inappropriate bits
6897 set. */
6898 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6899 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6900 && HWI_COMPUTABLE_MODE_P (GET_MODE (x))
6901 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
6902 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6903 return XEXP (XEXP (x, 0), 0);
6904
6905 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6906 if (GET_CODE (XEXP (x, 0)) == SUBREG
6907 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6908 && subreg_lowpart_p (XEXP (x, 0))
6909 && HWI_COMPUTABLE_MODE_P (GET_MODE (x))
6910 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
6911 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6912 return SUBREG_REG (XEXP (x, 0));
6913
6914 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6915 is a comparison and STORE_FLAG_VALUE permits. This is like
6916 the first case, but it works even when GET_MODE (x) is larger
6917 than HOST_WIDE_INT. */
6918 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6919 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6920 && COMPARISON_P (XEXP (XEXP (x, 0), 0))
6921 && (GET_MODE_PRECISION (GET_MODE (XEXP (x, 0)))
6922 <= HOST_BITS_PER_WIDE_INT)
6923 && (STORE_FLAG_VALUE & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6924 return XEXP (XEXP (x, 0), 0);
6925
6926 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6927 if (GET_CODE (XEXP (x, 0)) == SUBREG
6928 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6929 && subreg_lowpart_p (XEXP (x, 0))
6930 && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
6931 && (GET_MODE_PRECISION (GET_MODE (XEXP (x, 0)))
6932 <= HOST_BITS_PER_WIDE_INT)
6933 && (STORE_FLAG_VALUE & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6934 return SUBREG_REG (XEXP (x, 0));
6935
6936 }
6937
6938 /* If we reach here, we want to return a pair of shifts. The inner
6939 shift is a left shift of BITSIZE - POS - LEN bits. The outer
6940 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
6941 logical depending on the value of UNSIGNEDP.
6942
6943 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6944 converted into an AND of a shift.
6945
6946 We must check for the case where the left shift would have a negative
6947 count. This can happen in a case like (x >> 31) & 255 on machines
6948 that can't shift by a constant. On those machines, we would first
6949 combine the shift with the AND to produce a variable-position
6950 extraction. Then the constant of 31 would be substituted in
6951 to produce such a position. */
6952
6953 modewidth = GET_MODE_PRECISION (GET_MODE (x));
6954 if (modewidth >= pos + len)
6955 {
6956 enum machine_mode mode = GET_MODE (x);
6957 tem = gen_lowpart (mode, XEXP (x, 0));
6958 if (!tem || GET_CODE (tem) == CLOBBER)
6959 return x;
6960 tem = simplify_shift_const (NULL_RTX, ASHIFT, mode,
6961 tem, modewidth - pos - len);
6962 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
6963 mode, tem, modewidth - len);
6964 }
6965 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
6966 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
6967 simplify_shift_const (NULL_RTX, LSHIFTRT,
6968 GET_MODE (x),
6969 XEXP (x, 0), pos),
6970 ((unsigned HOST_WIDE_INT) 1 << len) - 1);
6971 else
6972 /* Any other cases we can't handle. */
6973 return x;
6974
6975 /* If we couldn't do this for some reason, return the original
6976 expression. */
6977 if (GET_CODE (tem) == CLOBBER)
6978 return x;
6979
6980 return tem;
6981 }
6982
6983 /* X is a SET which contains an assignment of one object into
6984 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6985 or certain SUBREGS). If possible, convert it into a series of
6986 logical operations.
6987
6988 We half-heartedly support variable positions, but do not at all
6989 support variable lengths. */
6990
6991 static const_rtx
expand_field_assignment(const_rtx x)6992 expand_field_assignment (const_rtx x)
6993 {
6994 rtx inner;
6995 rtx pos; /* Always counts from low bit. */
6996 int len;
6997 rtx mask, cleared, masked;
6998 enum machine_mode compute_mode;
6999
7000 /* Loop until we find something we can't simplify. */
7001 while (1)
7002 {
7003 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
7004 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
7005 {
7006 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
7007 len = GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x), 0)));
7008 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
7009 }
7010 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
7011 && CONST_INT_P (XEXP (SET_DEST (x), 1)))
7012 {
7013 inner = XEXP (SET_DEST (x), 0);
7014 len = INTVAL (XEXP (SET_DEST (x), 1));
7015 pos = XEXP (SET_DEST (x), 2);
7016
7017 /* A constant position should stay within the width of INNER. */
7018 if (CONST_INT_P (pos)
7019 && INTVAL (pos) + len > GET_MODE_PRECISION (GET_MODE (inner)))
7020 break;
7021
7022 if (BITS_BIG_ENDIAN)
7023 {
7024 if (CONST_INT_P (pos))
7025 pos = GEN_INT (GET_MODE_PRECISION (GET_MODE (inner)) - len
7026 - INTVAL (pos));
7027 else if (GET_CODE (pos) == MINUS
7028 && CONST_INT_P (XEXP (pos, 1))
7029 && (INTVAL (XEXP (pos, 1))
7030 == GET_MODE_PRECISION (GET_MODE (inner)) - len))
7031 /* If position is ADJUST - X, new position is X. */
7032 pos = XEXP (pos, 0);
7033 else
7034 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
7035 GEN_INT (GET_MODE_PRECISION (
7036 GET_MODE (inner))
7037 - len),
7038 pos);
7039 }
7040 }
7041
7042 /* A SUBREG between two modes that occupy the same numbers of words
7043 can be done by moving the SUBREG to the source. */
7044 else if (GET_CODE (SET_DEST (x)) == SUBREG
7045 /* We need SUBREGs to compute nonzero_bits properly. */
7046 && nonzero_sign_valid
7047 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
7048 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
7049 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
7050 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
7051 {
7052 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
7053 gen_lowpart
7054 (GET_MODE (SUBREG_REG (SET_DEST (x))),
7055 SET_SRC (x)));
7056 continue;
7057 }
7058 else
7059 break;
7060
7061 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
7062 inner = SUBREG_REG (inner);
7063
7064 compute_mode = GET_MODE (inner);
7065
7066 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7067 if (! SCALAR_INT_MODE_P (compute_mode))
7068 {
7069 enum machine_mode imode;
7070
7071 /* Don't do anything for vector or complex integral types. */
7072 if (! FLOAT_MODE_P (compute_mode))
7073 break;
7074
7075 /* Try to find an integral mode to pun with. */
7076 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
7077 if (imode == BLKmode)
7078 break;
7079
7080 compute_mode = imode;
7081 inner = gen_lowpart (imode, inner);
7082 }
7083
7084 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7085 if (len >= HOST_BITS_PER_WIDE_INT)
7086 break;
7087
7088 /* Now compute the equivalent expression. Make a copy of INNER
7089 for the SET_DEST in case it is a MEM into which we will substitute;
7090 we don't want shared RTL in that case. */
7091 mask = GEN_INT (((unsigned HOST_WIDE_INT) 1 << len) - 1);
7092 cleared = simplify_gen_binary (AND, compute_mode,
7093 simplify_gen_unary (NOT, compute_mode,
7094 simplify_gen_binary (ASHIFT,
7095 compute_mode,
7096 mask, pos),
7097 compute_mode),
7098 inner);
7099 masked = simplify_gen_binary (ASHIFT, compute_mode,
7100 simplify_gen_binary (
7101 AND, compute_mode,
7102 gen_lowpart (compute_mode, SET_SRC (x)),
7103 mask),
7104 pos);
7105
7106 x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
7107 simplify_gen_binary (IOR, compute_mode,
7108 cleared, masked));
7109 }
7110
7111 return x;
7112 }
7113
7114 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7115 it is an RTX that represents a variable starting position; otherwise,
7116 POS is the (constant) starting bit position (counted from the LSB).
7117
7118 UNSIGNEDP is nonzero for an unsigned reference and zero for a
7119 signed reference.
7120
7121 IN_DEST is nonzero if this is a reference in the destination of a
7122 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7123 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7124 be used.
7125
7126 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7127 ZERO_EXTRACT should be built even for bits starting at bit 0.
7128
7129 MODE is the desired mode of the result (if IN_DEST == 0).
7130
7131 The result is an RTX for the extraction or NULL_RTX if the target
7132 can't handle it. */
7133
7134 static rtx
make_extraction(enum machine_mode mode,rtx inner,HOST_WIDE_INT pos,rtx pos_rtx,unsigned HOST_WIDE_INT len,int unsignedp,int in_dest,int in_compare)7135 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
7136 rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
7137 int in_dest, int in_compare)
7138 {
7139 /* This mode describes the size of the storage area
7140 to fetch the overall value from. Within that, we
7141 ignore the POS lowest bits, etc. */
7142 enum machine_mode is_mode = GET_MODE (inner);
7143 enum machine_mode inner_mode;
7144 enum machine_mode wanted_inner_mode;
7145 enum machine_mode wanted_inner_reg_mode = word_mode;
7146 enum machine_mode pos_mode = word_mode;
7147 enum machine_mode extraction_mode = word_mode;
7148 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
7149 rtx new_rtx = 0;
7150 rtx orig_pos_rtx = pos_rtx;
7151 HOST_WIDE_INT orig_pos;
7152
7153 if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
7154 {
7155 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7156 consider just the QI as the memory to extract from.
7157 The subreg adds or removes high bits; its mode is
7158 irrelevant to the meaning of this extraction,
7159 since POS and LEN count from the lsb. */
7160 if (MEM_P (SUBREG_REG (inner)))
7161 is_mode = GET_MODE (SUBREG_REG (inner));
7162 inner = SUBREG_REG (inner);
7163 }
7164 else if (GET_CODE (inner) == ASHIFT
7165 && CONST_INT_P (XEXP (inner, 1))
7166 && pos_rtx == 0 && pos == 0
7167 && len > UINTVAL (XEXP (inner, 1)))
7168 {
7169 /* We're extracting the least significant bits of an rtx
7170 (ashift X (const_int C)), where LEN > C. Extract the
7171 least significant (LEN - C) bits of X, giving an rtx
7172 whose mode is MODE, then shift it left C times. */
7173 new_rtx = make_extraction (mode, XEXP (inner, 0),
7174 0, 0, len - INTVAL (XEXP (inner, 1)),
7175 unsignedp, in_dest, in_compare);
7176 if (new_rtx != 0)
7177 return gen_rtx_ASHIFT (mode, new_rtx, XEXP (inner, 1));
7178 }
7179
7180 inner_mode = GET_MODE (inner);
7181
7182 if (pos_rtx && CONST_INT_P (pos_rtx))
7183 pos = INTVAL (pos_rtx), pos_rtx = 0;
7184
7185 /* See if this can be done without an extraction. We never can if the
7186 width of the field is not the same as that of some integer mode. For
7187 registers, we can only avoid the extraction if the position is at the
7188 low-order bit and this is either not in the destination or we have the
7189 appropriate STRICT_LOW_PART operation available.
7190
7191 For MEM, we can avoid an extract if the field starts on an appropriate
7192 boundary and we can change the mode of the memory reference. */
7193
7194 if (tmode != BLKmode
7195 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
7196 && !MEM_P (inner)
7197 && (inner_mode == tmode
7198 || !REG_P (inner)
7199 || TRULY_NOOP_TRUNCATION_MODES_P (tmode, inner_mode)
7200 || reg_truncated_to_mode (tmode, inner))
7201 && (! in_dest
7202 || (REG_P (inner)
7203 && have_insn_for (STRICT_LOW_PART, tmode))))
7204 || (MEM_P (inner) && pos_rtx == 0
7205 && (pos
7206 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
7207 : BITS_PER_UNIT)) == 0
7208 /* We can't do this if we are widening INNER_MODE (it
7209 may not be aligned, for one thing). */
7210 && GET_MODE_PRECISION (inner_mode) >= GET_MODE_PRECISION (tmode)
7211 && (inner_mode == tmode
7212 || (! mode_dependent_address_p (XEXP (inner, 0))
7213 && ! MEM_VOLATILE_P (inner))))))
7214 {
7215 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7216 field. If the original and current mode are the same, we need not
7217 adjust the offset. Otherwise, we do if bytes big endian.
7218
7219 If INNER is not a MEM, get a piece consisting of just the field
7220 of interest (in this case POS % BITS_PER_WORD must be 0). */
7221
7222 if (MEM_P (inner))
7223 {
7224 HOST_WIDE_INT offset;
7225
7226 /* POS counts from lsb, but make OFFSET count in memory order. */
7227 if (BYTES_BIG_ENDIAN)
7228 offset = (GET_MODE_PRECISION (is_mode) - len - pos) / BITS_PER_UNIT;
7229 else
7230 offset = pos / BITS_PER_UNIT;
7231
7232 new_rtx = adjust_address_nv (inner, tmode, offset);
7233 }
7234 else if (REG_P (inner))
7235 {
7236 if (tmode != inner_mode)
7237 {
7238 /* We can't call gen_lowpart in a DEST since we
7239 always want a SUBREG (see below) and it would sometimes
7240 return a new hard register. */
7241 if (pos || in_dest)
7242 {
7243 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
7244
7245 if (WORDS_BIG_ENDIAN
7246 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
7247 final_word = ((GET_MODE_SIZE (inner_mode)
7248 - GET_MODE_SIZE (tmode))
7249 / UNITS_PER_WORD) - final_word;
7250
7251 final_word *= UNITS_PER_WORD;
7252 if (BYTES_BIG_ENDIAN &&
7253 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
7254 final_word += (GET_MODE_SIZE (inner_mode)
7255 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
7256
7257 /* Avoid creating invalid subregs, for example when
7258 simplifying (x>>32)&255. */
7259 if (!validate_subreg (tmode, inner_mode, inner, final_word))
7260 return NULL_RTX;
7261
7262 new_rtx = gen_rtx_SUBREG (tmode, inner, final_word);
7263 }
7264 else
7265 new_rtx = gen_lowpart (tmode, inner);
7266 }
7267 else
7268 new_rtx = inner;
7269 }
7270 else
7271 new_rtx = force_to_mode (inner, tmode,
7272 len >= HOST_BITS_PER_WIDE_INT
7273 ? ~(unsigned HOST_WIDE_INT) 0
7274 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7275 0);
7276
7277 /* If this extraction is going into the destination of a SET,
7278 make a STRICT_LOW_PART unless we made a MEM. */
7279
7280 if (in_dest)
7281 return (MEM_P (new_rtx) ? new_rtx
7282 : (GET_CODE (new_rtx) != SUBREG
7283 ? gen_rtx_CLOBBER (tmode, const0_rtx)
7284 : gen_rtx_STRICT_LOW_PART (VOIDmode, new_rtx)));
7285
7286 if (mode == tmode)
7287 return new_rtx;
7288
7289 if (CONST_INT_P (new_rtx)
7290 || GET_CODE (new_rtx) == CONST_DOUBLE)
7291 return simplify_unary_operation (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7292 mode, new_rtx, tmode);
7293
7294 /* If we know that no extraneous bits are set, and that the high
7295 bit is not set, convert the extraction to the cheaper of
7296 sign and zero extension, that are equivalent in these cases. */
7297 if (flag_expensive_optimizations
7298 && (HWI_COMPUTABLE_MODE_P (tmode)
7299 && ((nonzero_bits (new_rtx, tmode)
7300 & ~(((unsigned HOST_WIDE_INT)GET_MODE_MASK (tmode)) >> 1))
7301 == 0)))
7302 {
7303 rtx temp = gen_rtx_ZERO_EXTEND (mode, new_rtx);
7304 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new_rtx);
7305
7306 /* Prefer ZERO_EXTENSION, since it gives more information to
7307 backends. */
7308 if (set_src_cost (temp, optimize_this_for_speed_p)
7309 <= set_src_cost (temp1, optimize_this_for_speed_p))
7310 return temp;
7311 return temp1;
7312 }
7313
7314 /* Otherwise, sign- or zero-extend unless we already are in the
7315 proper mode. */
7316
7317 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7318 mode, new_rtx));
7319 }
7320
7321 /* Unless this is a COMPARE or we have a funny memory reference,
7322 don't do anything with zero-extending field extracts starting at
7323 the low-order bit since they are simple AND operations. */
7324 if (pos_rtx == 0 && pos == 0 && ! in_dest
7325 && ! in_compare && unsignedp)
7326 return 0;
7327
7328 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7329 if the position is not a constant and the length is not 1. In all
7330 other cases, we would only be going outside our object in cases when
7331 an original shift would have been undefined. */
7332 if (MEM_P (inner)
7333 && ((pos_rtx == 0 && pos + len > GET_MODE_PRECISION (is_mode))
7334 || (pos_rtx != 0 && len != 1)))
7335 return 0;
7336
7337 /* Get the mode to use should INNER not be a MEM, the mode for the position,
7338 and the mode for the result. */
7339 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
7340 {
7341 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
7342 pos_mode = mode_for_extraction (EP_insv, 2);
7343 extraction_mode = mode_for_extraction (EP_insv, 3);
7344 }
7345
7346 if (! in_dest && unsignedp
7347 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
7348 {
7349 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
7350 pos_mode = mode_for_extraction (EP_extzv, 3);
7351 extraction_mode = mode_for_extraction (EP_extzv, 0);
7352 }
7353
7354 if (! in_dest && ! unsignedp
7355 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
7356 {
7357 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
7358 pos_mode = mode_for_extraction (EP_extv, 3);
7359 extraction_mode = mode_for_extraction (EP_extv, 0);
7360 }
7361
7362 /* Never narrow an object, since that might not be safe. */
7363
7364 if (mode != VOIDmode
7365 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
7366 extraction_mode = mode;
7367
7368 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
7369 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
7370 pos_mode = GET_MODE (pos_rtx);
7371
7372 /* If this is not from memory, the desired mode is the preferred mode
7373 for an extraction pattern's first input operand, or word_mode if there
7374 is none. */
7375 if (!MEM_P (inner))
7376 wanted_inner_mode = wanted_inner_reg_mode;
7377 else
7378 {
7379 /* Be careful not to go beyond the extracted object and maintain the
7380 natural alignment of the memory. */
7381 wanted_inner_mode = smallest_mode_for_size (len, MODE_INT);
7382 while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
7383 > GET_MODE_BITSIZE (wanted_inner_mode))
7384 {
7385 wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode);
7386 gcc_assert (wanted_inner_mode != VOIDmode);
7387 }
7388
7389 /* If we have to change the mode of memory and cannot, the desired mode
7390 is EXTRACTION_MODE. */
7391 if (inner_mode != wanted_inner_mode
7392 && (mode_dependent_address_p (XEXP (inner, 0))
7393 || MEM_VOLATILE_P (inner)
7394 || pos_rtx))
7395 wanted_inner_mode = extraction_mode;
7396 }
7397
7398 orig_pos = pos;
7399
7400 if (BITS_BIG_ENDIAN)
7401 {
7402 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7403 BITS_BIG_ENDIAN style. If position is constant, compute new
7404 position. Otherwise, build subtraction.
7405 Note that POS is relative to the mode of the original argument.
7406 If it's a MEM we need to recompute POS relative to that.
7407 However, if we're extracting from (or inserting into) a register,
7408 we want to recompute POS relative to wanted_inner_mode. */
7409 int width = (MEM_P (inner)
7410 ? GET_MODE_BITSIZE (is_mode)
7411 : GET_MODE_BITSIZE (wanted_inner_mode));
7412
7413 if (pos_rtx == 0)
7414 pos = width - len - pos;
7415 else
7416 pos_rtx
7417 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
7418 /* POS may be less than 0 now, but we check for that below.
7419 Note that it can only be less than 0 if !MEM_P (inner). */
7420 }
7421
7422 /* If INNER has a wider mode, and this is a constant extraction, try to
7423 make it smaller and adjust the byte to point to the byte containing
7424 the value. */
7425 if (wanted_inner_mode != VOIDmode
7426 && inner_mode != wanted_inner_mode
7427 && ! pos_rtx
7428 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
7429 && MEM_P (inner)
7430 && ! mode_dependent_address_p (XEXP (inner, 0))
7431 && ! MEM_VOLATILE_P (inner))
7432 {
7433 int offset = 0;
7434
7435 /* The computations below will be correct if the machine is big
7436 endian in both bits and bytes or little endian in bits and bytes.
7437 If it is mixed, we must adjust. */
7438
7439 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7440 adjust OFFSET to compensate. */
7441 if (BYTES_BIG_ENDIAN
7442 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
7443 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
7444
7445 /* We can now move to the desired byte. */
7446 offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
7447 * GET_MODE_SIZE (wanted_inner_mode);
7448 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
7449
7450 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
7451 && is_mode != wanted_inner_mode)
7452 offset = (GET_MODE_SIZE (is_mode)
7453 - GET_MODE_SIZE (wanted_inner_mode) - offset);
7454
7455 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
7456 }
7457
7458 /* If INNER is not memory, get it into the proper mode. If we are changing
7459 its mode, POS must be a constant and smaller than the size of the new
7460 mode. */
7461 else if (!MEM_P (inner))
7462 {
7463 /* On the LHS, don't create paradoxical subregs implicitely truncating
7464 the register unless TRULY_NOOP_TRUNCATION. */
7465 if (in_dest
7466 && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (inner),
7467 wanted_inner_mode))
7468 return NULL_RTX;
7469
7470 if (GET_MODE (inner) != wanted_inner_mode
7471 && (pos_rtx != 0
7472 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
7473 return NULL_RTX;
7474
7475 if (orig_pos < 0)
7476 return NULL_RTX;
7477
7478 inner = force_to_mode (inner, wanted_inner_mode,
7479 pos_rtx
7480 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
7481 ? ~(unsigned HOST_WIDE_INT) 0
7482 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
7483 << orig_pos),
7484 0);
7485 }
7486
7487 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7488 have to zero extend. Otherwise, we can just use a SUBREG. */
7489 if (pos_rtx != 0
7490 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
7491 {
7492 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
7493
7494 /* If we know that no extraneous bits are set, and that the high
7495 bit is not set, convert extraction to cheaper one - either
7496 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7497 cases. */
7498 if (flag_expensive_optimizations
7499 && (HWI_COMPUTABLE_MODE_P (GET_MODE (pos_rtx))
7500 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
7501 & ~(((unsigned HOST_WIDE_INT)
7502 GET_MODE_MASK (GET_MODE (pos_rtx)))
7503 >> 1))
7504 == 0)))
7505 {
7506 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
7507
7508 /* Prefer ZERO_EXTENSION, since it gives more information to
7509 backends. */
7510 if (set_src_cost (temp1, optimize_this_for_speed_p)
7511 < set_src_cost (temp, optimize_this_for_speed_p))
7512 temp = temp1;
7513 }
7514 pos_rtx = temp;
7515 }
7516 else if (pos_rtx != 0
7517 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
7518 pos_rtx = gen_lowpart (pos_mode, pos_rtx);
7519
7520 /* Make POS_RTX unless we already have it and it is correct. If we don't
7521 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7522 be a CONST_INT. */
7523 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
7524 pos_rtx = orig_pos_rtx;
7525
7526 else if (pos_rtx == 0)
7527 pos_rtx = GEN_INT (pos);
7528
7529 /* Make the required operation. See if we can use existing rtx. */
7530 new_rtx = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
7531 extraction_mode, inner, GEN_INT (len), pos_rtx);
7532 if (! in_dest)
7533 new_rtx = gen_lowpart (mode, new_rtx);
7534
7535 return new_rtx;
7536 }
7537
7538 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7539 with any other operations in X. Return X without that shift if so. */
7540
7541 static rtx
extract_left_shift(rtx x,int count)7542 extract_left_shift (rtx x, int count)
7543 {
7544 enum rtx_code code = GET_CODE (x);
7545 enum machine_mode mode = GET_MODE (x);
7546 rtx tem;
7547
7548 switch (code)
7549 {
7550 case ASHIFT:
7551 /* This is the shift itself. If it is wide enough, we will return
7552 either the value being shifted if the shift count is equal to
7553 COUNT or a shift for the difference. */
7554 if (CONST_INT_P (XEXP (x, 1))
7555 && INTVAL (XEXP (x, 1)) >= count)
7556 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
7557 INTVAL (XEXP (x, 1)) - count);
7558 break;
7559
7560 case NEG: case NOT:
7561 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7562 return simplify_gen_unary (code, mode, tem, mode);
7563
7564 break;
7565
7566 case PLUS: case IOR: case XOR: case AND:
7567 /* If we can safely shift this constant and we find the inner shift,
7568 make a new operation. */
7569 if (CONST_INT_P (XEXP (x, 1))
7570 && (UINTVAL (XEXP (x, 1))
7571 & ((((unsigned HOST_WIDE_INT) 1 << count)) - 1)) == 0
7572 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7573 return simplify_gen_binary (code, mode, tem,
7574 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
7575
7576 break;
7577
7578 default:
7579 break;
7580 }
7581
7582 return 0;
7583 }
7584
7585 /* Look at the expression rooted at X. Look for expressions
7586 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7587 Form these expressions.
7588
7589 Return the new rtx, usually just X.
7590
7591 Also, for machines like the VAX that don't have logical shift insns,
7592 try to convert logical to arithmetic shift operations in cases where
7593 they are equivalent. This undoes the canonicalizations to logical
7594 shifts done elsewhere.
7595
7596 We try, as much as possible, to re-use rtl expressions to save memory.
7597
7598 IN_CODE says what kind of expression we are processing. Normally, it is
7599 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
7600 being kludges), it is MEM. When processing the arguments of a comparison
7601 or a COMPARE against zero, it is COMPARE. */
7602
7603 static rtx
make_compound_operation(rtx x,enum rtx_code in_code)7604 make_compound_operation (rtx x, enum rtx_code in_code)
7605 {
7606 enum rtx_code code = GET_CODE (x);
7607 enum machine_mode mode = GET_MODE (x);
7608 int mode_width = GET_MODE_PRECISION (mode);
7609 rtx rhs, lhs;
7610 enum rtx_code next_code;
7611 int i, j;
7612 rtx new_rtx = 0;
7613 rtx tem;
7614 const char *fmt;
7615
7616 /* Select the code to be used in recursive calls. Once we are inside an
7617 address, we stay there. If we have a comparison, set to COMPARE,
7618 but once inside, go back to our default of SET. */
7619
7620 next_code = (code == MEM ? MEM
7621 : ((code == PLUS || code == MINUS)
7622 && SCALAR_INT_MODE_P (mode)) ? MEM
7623 : ((code == COMPARE || COMPARISON_P (x))
7624 && XEXP (x, 1) == const0_rtx) ? COMPARE
7625 : in_code == COMPARE ? SET : in_code);
7626
7627 /* Process depending on the code of this operation. If NEW is set
7628 nonzero, it will be returned. */
7629
7630 switch (code)
7631 {
7632 case ASHIFT:
7633 /* Convert shifts by constants into multiplications if inside
7634 an address. */
7635 if (in_code == MEM && CONST_INT_P (XEXP (x, 1))
7636 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7637 && INTVAL (XEXP (x, 1)) >= 0
7638 && SCALAR_INT_MODE_P (mode))
7639 {
7640 HOST_WIDE_INT count = INTVAL (XEXP (x, 1));
7641 HOST_WIDE_INT multval = (HOST_WIDE_INT) 1 << count;
7642
7643 new_rtx = make_compound_operation (XEXP (x, 0), next_code);
7644 if (GET_CODE (new_rtx) == NEG)
7645 {
7646 new_rtx = XEXP (new_rtx, 0);
7647 multval = -multval;
7648 }
7649 multval = trunc_int_for_mode (multval, mode);
7650 new_rtx = gen_rtx_MULT (mode, new_rtx, GEN_INT (multval));
7651 }
7652 break;
7653
7654 case PLUS:
7655 lhs = XEXP (x, 0);
7656 rhs = XEXP (x, 1);
7657 lhs = make_compound_operation (lhs, next_code);
7658 rhs = make_compound_operation (rhs, next_code);
7659 if (GET_CODE (lhs) == MULT && GET_CODE (XEXP (lhs, 0)) == NEG
7660 && SCALAR_INT_MODE_P (mode))
7661 {
7662 tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (lhs, 0), 0),
7663 XEXP (lhs, 1));
7664 new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem);
7665 }
7666 else if (GET_CODE (lhs) == MULT
7667 && (CONST_INT_P (XEXP (lhs, 1)) && INTVAL (XEXP (lhs, 1)) < 0))
7668 {
7669 tem = simplify_gen_binary (MULT, mode, XEXP (lhs, 0),
7670 simplify_gen_unary (NEG, mode,
7671 XEXP (lhs, 1),
7672 mode));
7673 new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem);
7674 }
7675 else
7676 {
7677 SUBST (XEXP (x, 0), lhs);
7678 SUBST (XEXP (x, 1), rhs);
7679 goto maybe_swap;
7680 }
7681 x = gen_lowpart (mode, new_rtx);
7682 goto maybe_swap;
7683
7684 case MINUS:
7685 lhs = XEXP (x, 0);
7686 rhs = XEXP (x, 1);
7687 lhs = make_compound_operation (lhs, next_code);
7688 rhs = make_compound_operation (rhs, next_code);
7689 if (GET_CODE (rhs) == MULT && GET_CODE (XEXP (rhs, 0)) == NEG
7690 && SCALAR_INT_MODE_P (mode))
7691 {
7692 tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (rhs, 0), 0),
7693 XEXP (rhs, 1));
7694 new_rtx = simplify_gen_binary (PLUS, mode, tem, lhs);
7695 }
7696 else if (GET_CODE (rhs) == MULT
7697 && (CONST_INT_P (XEXP (rhs, 1)) && INTVAL (XEXP (rhs, 1)) < 0))
7698 {
7699 tem = simplify_gen_binary (MULT, mode, XEXP (rhs, 0),
7700 simplify_gen_unary (NEG, mode,
7701 XEXP (rhs, 1),
7702 mode));
7703 new_rtx = simplify_gen_binary (PLUS, mode, tem, lhs);
7704 }
7705 else
7706 {
7707 SUBST (XEXP (x, 0), lhs);
7708 SUBST (XEXP (x, 1), rhs);
7709 return x;
7710 }
7711 return gen_lowpart (mode, new_rtx);
7712
7713 case AND:
7714 /* If the second operand is not a constant, we can't do anything
7715 with it. */
7716 if (!CONST_INT_P (XEXP (x, 1)))
7717 break;
7718
7719 /* If the constant is a power of two minus one and the first operand
7720 is a logical right shift, make an extraction. */
7721 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7722 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7723 {
7724 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7725 new_rtx = make_extraction (mode, new_rtx, 0, XEXP (XEXP (x, 0), 1), i, 1,
7726 0, in_code == COMPARE);
7727 }
7728
7729 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7730 else if (GET_CODE (XEXP (x, 0)) == SUBREG
7731 && subreg_lowpart_p (XEXP (x, 0))
7732 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
7733 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7734 {
7735 new_rtx = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
7736 next_code);
7737 new_rtx = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new_rtx, 0,
7738 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
7739 0, in_code == COMPARE);
7740 }
7741 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7742 else if ((GET_CODE (XEXP (x, 0)) == XOR
7743 || GET_CODE (XEXP (x, 0)) == IOR)
7744 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
7745 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
7746 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7747 {
7748 /* Apply the distributive law, and then try to make extractions. */
7749 new_rtx = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
7750 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
7751 XEXP (x, 1)),
7752 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
7753 XEXP (x, 1)));
7754 new_rtx = make_compound_operation (new_rtx, in_code);
7755 }
7756
7757 /* If we are have (and (rotate X C) M) and C is larger than the number
7758 of bits in M, this is an extraction. */
7759
7760 else if (GET_CODE (XEXP (x, 0)) == ROTATE
7761 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7762 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0
7763 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
7764 {
7765 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7766 new_rtx = make_extraction (mode, new_rtx,
7767 (GET_MODE_PRECISION (mode)
7768 - INTVAL (XEXP (XEXP (x, 0), 1))),
7769 NULL_RTX, i, 1, 0, in_code == COMPARE);
7770 }
7771
7772 /* On machines without logical shifts, if the operand of the AND is
7773 a logical shift and our mask turns off all the propagated sign
7774 bits, we can replace the logical shift with an arithmetic shift. */
7775 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7776 && !have_insn_for (LSHIFTRT, mode)
7777 && have_insn_for (ASHIFTRT, mode)
7778 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7779 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7780 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7781 && mode_width <= HOST_BITS_PER_WIDE_INT)
7782 {
7783 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
7784
7785 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
7786 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
7787 SUBST (XEXP (x, 0),
7788 gen_rtx_ASHIFTRT (mode,
7789 make_compound_operation
7790 (XEXP (XEXP (x, 0), 0), next_code),
7791 XEXP (XEXP (x, 0), 1)));
7792 }
7793
7794 /* If the constant is one less than a power of two, this might be
7795 representable by an extraction even if no shift is present.
7796 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7797 we are in a COMPARE. */
7798 else if ((i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7799 new_rtx = make_extraction (mode,
7800 make_compound_operation (XEXP (x, 0),
7801 next_code),
7802 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
7803
7804 /* If we are in a comparison and this is an AND with a power of two,
7805 convert this into the appropriate bit extract. */
7806 else if (in_code == COMPARE
7807 && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0)
7808 new_rtx = make_extraction (mode,
7809 make_compound_operation (XEXP (x, 0),
7810 next_code),
7811 i, NULL_RTX, 1, 1, 0, 1);
7812
7813 break;
7814
7815 case LSHIFTRT:
7816 /* If the sign bit is known to be zero, replace this with an
7817 arithmetic shift. */
7818 if (have_insn_for (ASHIFTRT, mode)
7819 && ! have_insn_for (LSHIFTRT, mode)
7820 && mode_width <= HOST_BITS_PER_WIDE_INT
7821 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
7822 {
7823 new_rtx = gen_rtx_ASHIFTRT (mode,
7824 make_compound_operation (XEXP (x, 0),
7825 next_code),
7826 XEXP (x, 1));
7827 break;
7828 }
7829
7830 /* ... fall through ... */
7831
7832 case ASHIFTRT:
7833 lhs = XEXP (x, 0);
7834 rhs = XEXP (x, 1);
7835
7836 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7837 this is a SIGN_EXTRACT. */
7838 if (CONST_INT_P (rhs)
7839 && GET_CODE (lhs) == ASHIFT
7840 && CONST_INT_P (XEXP (lhs, 1))
7841 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1))
7842 && INTVAL (XEXP (lhs, 1)) >= 0
7843 && INTVAL (rhs) < mode_width)
7844 {
7845 new_rtx = make_compound_operation (XEXP (lhs, 0), next_code);
7846 new_rtx = make_extraction (mode, new_rtx,
7847 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
7848 NULL_RTX, mode_width - INTVAL (rhs),
7849 code == LSHIFTRT, 0, in_code == COMPARE);
7850 break;
7851 }
7852
7853 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7854 If so, try to merge the shifts into a SIGN_EXTEND. We could
7855 also do this for some cases of SIGN_EXTRACT, but it doesn't
7856 seem worth the effort; the case checked for occurs on Alpha. */
7857
7858 if (!OBJECT_P (lhs)
7859 && ! (GET_CODE (lhs) == SUBREG
7860 && (OBJECT_P (SUBREG_REG (lhs))))
7861 && CONST_INT_P (rhs)
7862 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
7863 && INTVAL (rhs) < mode_width
7864 && (new_rtx = extract_left_shift (lhs, INTVAL (rhs))) != 0)
7865 new_rtx = make_extraction (mode, make_compound_operation (new_rtx, next_code),
7866 0, NULL_RTX, mode_width - INTVAL (rhs),
7867 code == LSHIFTRT, 0, in_code == COMPARE);
7868
7869 break;
7870
7871 case SUBREG:
7872 /* Call ourselves recursively on the inner expression. If we are
7873 narrowing the object and it has a different RTL code from
7874 what it originally did, do this SUBREG as a force_to_mode. */
7875 {
7876 rtx inner = SUBREG_REG (x), simplified;
7877
7878 tem = make_compound_operation (inner, in_code);
7879
7880 simplified
7881 = simplify_subreg (mode, tem, GET_MODE (inner), SUBREG_BYTE (x));
7882 if (simplified)
7883 tem = simplified;
7884
7885 if (GET_CODE (tem) != GET_CODE (inner)
7886 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (inner))
7887 && subreg_lowpart_p (x))
7888 {
7889 rtx newer
7890 = force_to_mode (tem, mode, ~(unsigned HOST_WIDE_INT) 0, 0);
7891
7892 /* If we have something other than a SUBREG, we might have
7893 done an expansion, so rerun ourselves. */
7894 if (GET_CODE (newer) != SUBREG)
7895 newer = make_compound_operation (newer, in_code);
7896
7897 /* force_to_mode can expand compounds. If it just re-expanded the
7898 compound, use gen_lowpart to convert to the desired mode. */
7899 if (rtx_equal_p (newer, x)
7900 /* Likewise if it re-expanded the compound only partially.
7901 This happens for SUBREG of ZERO_EXTRACT if they extract
7902 the same number of bits. */
7903 || (GET_CODE (newer) == SUBREG
7904 && (GET_CODE (SUBREG_REG (newer)) == LSHIFTRT
7905 || GET_CODE (SUBREG_REG (newer)) == ASHIFTRT)
7906 && GET_CODE (inner) == AND
7907 && rtx_equal_p (SUBREG_REG (newer), XEXP (inner, 0))))
7908 return gen_lowpart (GET_MODE (x), tem);
7909
7910 return newer;
7911 }
7912
7913 if (simplified)
7914 return tem;
7915 }
7916 break;
7917
7918 default:
7919 break;
7920 }
7921
7922 if (new_rtx)
7923 {
7924 x = gen_lowpart (mode, new_rtx);
7925 code = GET_CODE (x);
7926 }
7927
7928 /* Now recursively process each operand of this operation. We need to
7929 handle ZERO_EXTEND specially so that we don't lose track of the
7930 inner mode. */
7931 if (GET_CODE (x) == ZERO_EXTEND)
7932 {
7933 new_rtx = make_compound_operation (XEXP (x, 0), next_code);
7934 tem = simplify_const_unary_operation (ZERO_EXTEND, GET_MODE (x),
7935 new_rtx, GET_MODE (XEXP (x, 0)));
7936 if (tem)
7937 return tem;
7938 SUBST (XEXP (x, 0), new_rtx);
7939 return x;
7940 }
7941
7942 fmt = GET_RTX_FORMAT (code);
7943 for (i = 0; i < GET_RTX_LENGTH (code); i++)
7944 if (fmt[i] == 'e')
7945 {
7946 new_rtx = make_compound_operation (XEXP (x, i), next_code);
7947 SUBST (XEXP (x, i), new_rtx);
7948 }
7949 else if (fmt[i] == 'E')
7950 for (j = 0; j < XVECLEN (x, i); j++)
7951 {
7952 new_rtx = make_compound_operation (XVECEXP (x, i, j), next_code);
7953 SUBST (XVECEXP (x, i, j), new_rtx);
7954 }
7955
7956 maybe_swap:
7957 /* If this is a commutative operation, the changes to the operands
7958 may have made it noncanonical. */
7959 if (COMMUTATIVE_ARITH_P (x)
7960 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
7961 {
7962 tem = XEXP (x, 0);
7963 SUBST (XEXP (x, 0), XEXP (x, 1));
7964 SUBST (XEXP (x, 1), tem);
7965 }
7966
7967 return x;
7968 }
7969
7970 /* Given M see if it is a value that would select a field of bits
7971 within an item, but not the entire word. Return -1 if not.
7972 Otherwise, return the starting position of the field, where 0 is the
7973 low-order bit.
7974
7975 *PLEN is set to the length of the field. */
7976
7977 static int
get_pos_from_mask(unsigned HOST_WIDE_INT m,unsigned HOST_WIDE_INT * plen)7978 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
7979 {
7980 /* Get the bit number of the first 1 bit from the right, -1 if none. */
7981 int pos = m ? ctz_hwi (m) : -1;
7982 int len = 0;
7983
7984 if (pos >= 0)
7985 /* Now shift off the low-order zero bits and see if we have a
7986 power of two minus 1. */
7987 len = exact_log2 ((m >> pos) + 1);
7988
7989 if (len <= 0)
7990 pos = -1;
7991
7992 *plen = len;
7993 return pos;
7994 }
7995
7996 /* If X refers to a register that equals REG in value, replace these
7997 references with REG. */
7998 static rtx
canon_reg_for_combine(rtx x,rtx reg)7999 canon_reg_for_combine (rtx x, rtx reg)
8000 {
8001 rtx op0, op1, op2;
8002 const char *fmt;
8003 int i;
8004 bool copied;
8005
8006 enum rtx_code code = GET_CODE (x);
8007 switch (GET_RTX_CLASS (code))
8008 {
8009 case RTX_UNARY:
8010 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
8011 if (op0 != XEXP (x, 0))
8012 return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
8013 GET_MODE (reg));
8014 break;
8015
8016 case RTX_BIN_ARITH:
8017 case RTX_COMM_ARITH:
8018 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
8019 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
8020 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
8021 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
8022 break;
8023
8024 case RTX_COMPARE:
8025 case RTX_COMM_COMPARE:
8026 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
8027 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
8028 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
8029 return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
8030 GET_MODE (op0), op0, op1);
8031 break;
8032
8033 case RTX_TERNARY:
8034 case RTX_BITFIELD_OPS:
8035 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
8036 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
8037 op2 = canon_reg_for_combine (XEXP (x, 2), reg);
8038 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
8039 return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
8040 GET_MODE (op0), op0, op1, op2);
8041
8042 case RTX_OBJ:
8043 if (REG_P (x))
8044 {
8045 if (rtx_equal_p (get_last_value (reg), x)
8046 || rtx_equal_p (reg, get_last_value (x)))
8047 return reg;
8048 else
8049 break;
8050 }
8051
8052 /* fall through */
8053
8054 default:
8055 fmt = GET_RTX_FORMAT (code);
8056 copied = false;
8057 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8058 if (fmt[i] == 'e')
8059 {
8060 rtx op = canon_reg_for_combine (XEXP (x, i), reg);
8061 if (op != XEXP (x, i))
8062 {
8063 if (!copied)
8064 {
8065 copied = true;
8066 x = copy_rtx (x);
8067 }
8068 XEXP (x, i) = op;
8069 }
8070 }
8071 else if (fmt[i] == 'E')
8072 {
8073 int j;
8074 for (j = 0; j < XVECLEN (x, i); j++)
8075 {
8076 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
8077 if (op != XVECEXP (x, i, j))
8078 {
8079 if (!copied)
8080 {
8081 copied = true;
8082 x = copy_rtx (x);
8083 }
8084 XVECEXP (x, i, j) = op;
8085 }
8086 }
8087 }
8088
8089 break;
8090 }
8091
8092 return x;
8093 }
8094
8095 /* Return X converted to MODE. If the value is already truncated to
8096 MODE we can just return a subreg even though in the general case we
8097 would need an explicit truncation. */
8098
8099 static rtx
gen_lowpart_or_truncate(enum machine_mode mode,rtx x)8100 gen_lowpart_or_truncate (enum machine_mode mode, rtx x)
8101 {
8102 if (!CONST_INT_P (x)
8103 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))
8104 && !TRULY_NOOP_TRUNCATION_MODES_P (mode, GET_MODE (x))
8105 && !(REG_P (x) && reg_truncated_to_mode (mode, x)))
8106 {
8107 /* Bit-cast X into an integer mode. */
8108 if (!SCALAR_INT_MODE_P (GET_MODE (x)))
8109 x = gen_lowpart (int_mode_for_mode (GET_MODE (x)), x);
8110 x = simplify_gen_unary (TRUNCATE, int_mode_for_mode (mode),
8111 x, GET_MODE (x));
8112 }
8113
8114 return gen_lowpart (mode, x);
8115 }
8116
8117 /* See if X can be simplified knowing that we will only refer to it in
8118 MODE and will only refer to those bits that are nonzero in MASK.
8119 If other bits are being computed or if masking operations are done
8120 that select a superset of the bits in MASK, they can sometimes be
8121 ignored.
8122
8123 Return a possibly simplified expression, but always convert X to
8124 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8125
8126 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8127 are all off in X. This is used when X will be complemented, by either
8128 NOT, NEG, or XOR. */
8129
8130 static rtx
force_to_mode(rtx x,enum machine_mode mode,unsigned HOST_WIDE_INT mask,int just_select)8131 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
8132 int just_select)
8133 {
8134 enum rtx_code code = GET_CODE (x);
8135 int next_select = just_select || code == XOR || code == NOT || code == NEG;
8136 enum machine_mode op_mode;
8137 unsigned HOST_WIDE_INT fuller_mask, nonzero;
8138 rtx op0, op1, temp;
8139
8140 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8141 code below will do the wrong thing since the mode of such an
8142 expression is VOIDmode.
8143
8144 Also do nothing if X is a CLOBBER; this can happen if X was
8145 the return value from a call to gen_lowpart. */
8146 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
8147 return x;
8148
8149 /* We want to perform the operation is its present mode unless we know
8150 that the operation is valid in MODE, in which case we do the operation
8151 in MODE. */
8152 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
8153 && have_insn_for (code, mode))
8154 ? mode : GET_MODE (x));
8155
8156 /* It is not valid to do a right-shift in a narrower mode
8157 than the one it came in with. */
8158 if ((code == LSHIFTRT || code == ASHIFTRT)
8159 && GET_MODE_PRECISION (mode) < GET_MODE_PRECISION (GET_MODE (x)))
8160 op_mode = GET_MODE (x);
8161
8162 /* Truncate MASK to fit OP_MODE. */
8163 if (op_mode)
8164 mask &= GET_MODE_MASK (op_mode);
8165
8166 /* When we have an arithmetic operation, or a shift whose count we
8167 do not know, we need to assume that all bits up to the highest-order
8168 bit in MASK will be needed. This is how we form such a mask. */
8169 if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
8170 fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
8171 else
8172 fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
8173 - 1);
8174
8175 /* Determine what bits of X are guaranteed to be (non)zero. */
8176 nonzero = nonzero_bits (x, mode);
8177
8178 /* If none of the bits in X are needed, return a zero. */
8179 if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x))
8180 x = const0_rtx;
8181
8182 /* If X is a CONST_INT, return a new one. Do this here since the
8183 test below will fail. */
8184 if (CONST_INT_P (x))
8185 {
8186 if (SCALAR_INT_MODE_P (mode))
8187 return gen_int_mode (INTVAL (x) & mask, mode);
8188 else
8189 {
8190 x = GEN_INT (INTVAL (x) & mask);
8191 return gen_lowpart_common (mode, x);
8192 }
8193 }
8194
8195 /* If X is narrower than MODE and we want all the bits in X's mode, just
8196 get X in the proper mode. */
8197 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
8198 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
8199 return gen_lowpart (mode, x);
8200
8201 /* We can ignore the effect of a SUBREG if it narrows the mode or
8202 if the constant masks to zero all the bits the mode doesn't have. */
8203 if (GET_CODE (x) == SUBREG
8204 && subreg_lowpart_p (x)
8205 && ((GET_MODE_SIZE (GET_MODE (x))
8206 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8207 || (0 == (mask
8208 & GET_MODE_MASK (GET_MODE (x))
8209 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
8210 return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
8211
8212 /* The arithmetic simplifications here only work for scalar integer modes. */
8213 if (!SCALAR_INT_MODE_P (mode) || !SCALAR_INT_MODE_P (GET_MODE (x)))
8214 return gen_lowpart_or_truncate (mode, x);
8215
8216 switch (code)
8217 {
8218 case CLOBBER:
8219 /* If X is a (clobber (const_int)), return it since we know we are
8220 generating something that won't match. */
8221 return x;
8222
8223 case SIGN_EXTEND:
8224 case ZERO_EXTEND:
8225 case ZERO_EXTRACT:
8226 case SIGN_EXTRACT:
8227 x = expand_compound_operation (x);
8228 if (GET_CODE (x) != code)
8229 return force_to_mode (x, mode, mask, next_select);
8230 break;
8231
8232 case TRUNCATE:
8233 /* Similarly for a truncate. */
8234 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8235
8236 case AND:
8237 /* If this is an AND with a constant, convert it into an AND
8238 whose constant is the AND of that constant with MASK. If it
8239 remains an AND of MASK, delete it since it is redundant. */
8240
8241 if (CONST_INT_P (XEXP (x, 1)))
8242 {
8243 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
8244 mask & INTVAL (XEXP (x, 1)));
8245
8246 /* If X is still an AND, see if it is an AND with a mask that
8247 is just some low-order bits. If so, and it is MASK, we don't
8248 need it. */
8249
8250 if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8251 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
8252 == mask))
8253 x = XEXP (x, 0);
8254
8255 /* If it remains an AND, try making another AND with the bits
8256 in the mode mask that aren't in MASK turned on. If the
8257 constant in the AND is wide enough, this might make a
8258 cheaper constant. */
8259
8260 if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8261 && GET_MODE_MASK (GET_MODE (x)) != mask
8262 && HWI_COMPUTABLE_MODE_P (GET_MODE (x)))
8263 {
8264 unsigned HOST_WIDE_INT cval
8265 = UINTVAL (XEXP (x, 1))
8266 | (GET_MODE_MASK (GET_MODE (x)) & ~mask);
8267 int width = GET_MODE_PRECISION (GET_MODE (x));
8268 rtx y;
8269
8270 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
8271 number, sign extend it. */
8272 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
8273 && (cval & ((unsigned HOST_WIDE_INT) 1 << (width - 1))) != 0)
8274 cval |= (unsigned HOST_WIDE_INT) -1 << width;
8275
8276 y = simplify_gen_binary (AND, GET_MODE (x),
8277 XEXP (x, 0), GEN_INT (cval));
8278 if (set_src_cost (y, optimize_this_for_speed_p)
8279 < set_src_cost (x, optimize_this_for_speed_p))
8280 x = y;
8281 }
8282
8283 break;
8284 }
8285
8286 goto binop;
8287
8288 case PLUS:
8289 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8290 low-order bits (as in an alignment operation) and FOO is already
8291 aligned to that boundary, mask C1 to that boundary as well.
8292 This may eliminate that PLUS and, later, the AND. */
8293
8294 {
8295 unsigned int width = GET_MODE_PRECISION (mode);
8296 unsigned HOST_WIDE_INT smask = mask;
8297
8298 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8299 number, sign extend it. */
8300
8301 if (width < HOST_BITS_PER_WIDE_INT
8302 && (smask & ((unsigned HOST_WIDE_INT) 1 << (width - 1))) != 0)
8303 smask |= (unsigned HOST_WIDE_INT) (-1) << width;
8304
8305 if (CONST_INT_P (XEXP (x, 1))
8306 && exact_log2 (- smask) >= 0
8307 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
8308 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
8309 return force_to_mode (plus_constant (XEXP (x, 0),
8310 (INTVAL (XEXP (x, 1)) & smask)),
8311 mode, smask, next_select);
8312 }
8313
8314 /* ... fall through ... */
8315
8316 case MULT:
8317 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8318 most significant bit in MASK since carries from those bits will
8319 affect the bits we are interested in. */
8320 mask = fuller_mask;
8321 goto binop;
8322
8323 case MINUS:
8324 /* If X is (minus C Y) where C's least set bit is larger than any bit
8325 in the mask, then we may replace with (neg Y). */
8326 if (CONST_INT_P (XEXP (x, 0))
8327 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
8328 & -INTVAL (XEXP (x, 0))))
8329 > mask))
8330 {
8331 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
8332 GET_MODE (x));
8333 return force_to_mode (x, mode, mask, next_select);
8334 }
8335
8336 /* Similarly, if C contains every bit in the fuller_mask, then we may
8337 replace with (not Y). */
8338 if (CONST_INT_P (XEXP (x, 0))
8339 && ((UINTVAL (XEXP (x, 0)) | fuller_mask) == UINTVAL (XEXP (x, 0))))
8340 {
8341 x = simplify_gen_unary (NOT, GET_MODE (x),
8342 XEXP (x, 1), GET_MODE (x));
8343 return force_to_mode (x, mode, mask, next_select);
8344 }
8345
8346 mask = fuller_mask;
8347 goto binop;
8348
8349 case IOR:
8350 case XOR:
8351 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8352 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8353 operation which may be a bitfield extraction. Ensure that the
8354 constant we form is not wider than the mode of X. */
8355
8356 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8357 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8358 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8359 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
8360 && CONST_INT_P (XEXP (x, 1))
8361 && ((INTVAL (XEXP (XEXP (x, 0), 1))
8362 + floor_log2 (INTVAL (XEXP (x, 1))))
8363 < GET_MODE_PRECISION (GET_MODE (x)))
8364 && (UINTVAL (XEXP (x, 1))
8365 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
8366 {
8367 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
8368 << INTVAL (XEXP (XEXP (x, 0), 1)));
8369 temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
8370 XEXP (XEXP (x, 0), 0), temp);
8371 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
8372 XEXP (XEXP (x, 0), 1));
8373 return force_to_mode (x, mode, mask, next_select);
8374 }
8375
8376 binop:
8377 /* For most binary operations, just propagate into the operation and
8378 change the mode if we have an operation of that mode. */
8379
8380 op0 = force_to_mode (XEXP (x, 0), mode, mask, next_select);
8381 op1 = force_to_mode (XEXP (x, 1), mode, mask, next_select);
8382
8383 /* If we ended up truncating both operands, truncate the result of the
8384 operation instead. */
8385 if (GET_CODE (op0) == TRUNCATE
8386 && GET_CODE (op1) == TRUNCATE)
8387 {
8388 op0 = XEXP (op0, 0);
8389 op1 = XEXP (op1, 0);
8390 }
8391
8392 op0 = gen_lowpart_or_truncate (op_mode, op0);
8393 op1 = gen_lowpart_or_truncate (op_mode, op1);
8394
8395 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
8396 x = simplify_gen_binary (code, op_mode, op0, op1);
8397 break;
8398
8399 case ASHIFT:
8400 /* For left shifts, do the same, but just for the first operand.
8401 However, we cannot do anything with shifts where we cannot
8402 guarantee that the counts are smaller than the size of the mode
8403 because such a count will have a different meaning in a
8404 wider mode. */
8405
8406 if (! (CONST_INT_P (XEXP (x, 1))
8407 && INTVAL (XEXP (x, 1)) >= 0
8408 && INTVAL (XEXP (x, 1)) < GET_MODE_PRECISION (mode))
8409 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
8410 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
8411 < (unsigned HOST_WIDE_INT) GET_MODE_PRECISION (mode))))
8412 break;
8413
8414 /* If the shift count is a constant and we can do arithmetic in
8415 the mode of the shift, refine which bits we need. Otherwise, use the
8416 conservative form of the mask. */
8417 if (CONST_INT_P (XEXP (x, 1))
8418 && INTVAL (XEXP (x, 1)) >= 0
8419 && INTVAL (XEXP (x, 1)) < GET_MODE_PRECISION (op_mode)
8420 && HWI_COMPUTABLE_MODE_P (op_mode))
8421 mask >>= INTVAL (XEXP (x, 1));
8422 else
8423 mask = fuller_mask;
8424
8425 op0 = gen_lowpart_or_truncate (op_mode,
8426 force_to_mode (XEXP (x, 0), op_mode,
8427 mask, next_select));
8428
8429 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
8430 x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
8431 break;
8432
8433 case LSHIFTRT:
8434 /* Here we can only do something if the shift count is a constant,
8435 this shift constant is valid for the host, and we can do arithmetic
8436 in OP_MODE. */
8437
8438 if (CONST_INT_P (XEXP (x, 1))
8439 && INTVAL (XEXP (x, 1)) >= 0
8440 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
8441 && HWI_COMPUTABLE_MODE_P (op_mode))
8442 {
8443 rtx inner = XEXP (x, 0);
8444 unsigned HOST_WIDE_INT inner_mask;
8445
8446 /* Select the mask of the bits we need for the shift operand. */
8447 inner_mask = mask << INTVAL (XEXP (x, 1));
8448
8449 /* We can only change the mode of the shift if we can do arithmetic
8450 in the mode of the shift and INNER_MASK is no wider than the
8451 width of X's mode. */
8452 if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
8453 op_mode = GET_MODE (x);
8454
8455 inner = force_to_mode (inner, op_mode, inner_mask, next_select);
8456
8457 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
8458 x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
8459 }
8460
8461 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8462 shift and AND produces only copies of the sign bit (C2 is one less
8463 than a power of two), we can do this with just a shift. */
8464
8465 if (GET_CODE (x) == LSHIFTRT
8466 && CONST_INT_P (XEXP (x, 1))
8467 /* The shift puts one of the sign bit copies in the least significant
8468 bit. */
8469 && ((INTVAL (XEXP (x, 1))
8470 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
8471 >= GET_MODE_PRECISION (GET_MODE (x)))
8472 && exact_log2 (mask + 1) >= 0
8473 /* Number of bits left after the shift must be more than the mask
8474 needs. */
8475 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
8476 <= GET_MODE_PRECISION (GET_MODE (x)))
8477 /* Must be more sign bit copies than the mask needs. */
8478 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
8479 >= exact_log2 (mask + 1)))
8480 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
8481 GEN_INT (GET_MODE_PRECISION (GET_MODE (x))
8482 - exact_log2 (mask + 1)));
8483
8484 goto shiftrt;
8485
8486 case ASHIFTRT:
8487 /* If we are just looking for the sign bit, we don't need this shift at
8488 all, even if it has a variable count. */
8489 if (val_signbit_p (GET_MODE (x), mask))
8490 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8491
8492 /* If this is a shift by a constant, get a mask that contains those bits
8493 that are not copies of the sign bit. We then have two cases: If
8494 MASK only includes those bits, this can be a logical shift, which may
8495 allow simplifications. If MASK is a single-bit field not within
8496 those bits, we are requesting a copy of the sign bit and hence can
8497 shift the sign bit to the appropriate location. */
8498
8499 if (CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) >= 0
8500 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8501 {
8502 int i;
8503
8504 /* If the considered data is wider than HOST_WIDE_INT, we can't
8505 represent a mask for all its bits in a single scalar.
8506 But we only care about the lower bits, so calculate these. */
8507
8508 if (GET_MODE_PRECISION (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
8509 {
8510 nonzero = ~(unsigned HOST_WIDE_INT) 0;
8511
8512 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8513 is the number of bits a full-width mask would have set.
8514 We need only shift if these are fewer than nonzero can
8515 hold. If not, we must keep all bits set in nonzero. */
8516
8517 if (GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8518 < HOST_BITS_PER_WIDE_INT)
8519 nonzero >>= INTVAL (XEXP (x, 1))
8520 + HOST_BITS_PER_WIDE_INT
8521 - GET_MODE_PRECISION (GET_MODE (x)) ;
8522 }
8523 else
8524 {
8525 nonzero = GET_MODE_MASK (GET_MODE (x));
8526 nonzero >>= INTVAL (XEXP (x, 1));
8527 }
8528
8529 if ((mask & ~nonzero) == 0)
8530 {
8531 x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x),
8532 XEXP (x, 0), INTVAL (XEXP (x, 1)));
8533 if (GET_CODE (x) != ASHIFTRT)
8534 return force_to_mode (x, mode, mask, next_select);
8535 }
8536
8537 else if ((i = exact_log2 (mask)) >= 0)
8538 {
8539 x = simplify_shift_const
8540 (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
8541 GET_MODE_PRECISION (GET_MODE (x)) - 1 - i);
8542
8543 if (GET_CODE (x) != ASHIFTRT)
8544 return force_to_mode (x, mode, mask, next_select);
8545 }
8546 }
8547
8548 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8549 even if the shift count isn't a constant. */
8550 if (mask == 1)
8551 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
8552 XEXP (x, 0), XEXP (x, 1));
8553
8554 shiftrt:
8555
8556 /* If this is a zero- or sign-extension operation that just affects bits
8557 we don't care about, remove it. Be sure the call above returned
8558 something that is still a shift. */
8559
8560 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
8561 && CONST_INT_P (XEXP (x, 1))
8562 && INTVAL (XEXP (x, 1)) >= 0
8563 && (INTVAL (XEXP (x, 1))
8564 <= GET_MODE_PRECISION (GET_MODE (x)) - (floor_log2 (mask) + 1))
8565 && GET_CODE (XEXP (x, 0)) == ASHIFT
8566 && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
8567 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
8568 next_select);
8569
8570 break;
8571
8572 case ROTATE:
8573 case ROTATERT:
8574 /* If the shift count is constant and we can do computations
8575 in the mode of X, compute where the bits we care about are.
8576 Otherwise, we can't do anything. Don't change the mode of
8577 the shift or propagate MODE into the shift, though. */
8578 if (CONST_INT_P (XEXP (x, 1))
8579 && INTVAL (XEXP (x, 1)) >= 0)
8580 {
8581 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
8582 GET_MODE (x), GEN_INT (mask),
8583 XEXP (x, 1));
8584 if (temp && CONST_INT_P (temp))
8585 SUBST (XEXP (x, 0),
8586 force_to_mode (XEXP (x, 0), GET_MODE (x),
8587 INTVAL (temp), next_select));
8588 }
8589 break;
8590
8591 case NEG:
8592 /* If we just want the low-order bit, the NEG isn't needed since it
8593 won't change the low-order bit. */
8594 if (mask == 1)
8595 return force_to_mode (XEXP (x, 0), mode, mask, just_select);
8596
8597 /* We need any bits less significant than the most significant bit in
8598 MASK since carries from those bits will affect the bits we are
8599 interested in. */
8600 mask = fuller_mask;
8601 goto unop;
8602
8603 case NOT:
8604 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8605 same as the XOR case above. Ensure that the constant we form is not
8606 wider than the mode of X. */
8607
8608 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8609 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8610 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8611 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
8612 < GET_MODE_PRECISION (GET_MODE (x)))
8613 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
8614 {
8615 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
8616 GET_MODE (x));
8617 temp = simplify_gen_binary (XOR, GET_MODE (x),
8618 XEXP (XEXP (x, 0), 0), temp);
8619 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
8620 temp, XEXP (XEXP (x, 0), 1));
8621
8622 return force_to_mode (x, mode, mask, next_select);
8623 }
8624
8625 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8626 use the full mask inside the NOT. */
8627 mask = fuller_mask;
8628
8629 unop:
8630 op0 = gen_lowpart_or_truncate (op_mode,
8631 force_to_mode (XEXP (x, 0), mode, mask,
8632 next_select));
8633 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
8634 x = simplify_gen_unary (code, op_mode, op0, op_mode);
8635 break;
8636
8637 case NE:
8638 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8639 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8640 which is equal to STORE_FLAG_VALUE. */
8641 if ((mask & ~STORE_FLAG_VALUE) == 0
8642 && XEXP (x, 1) == const0_rtx
8643 && GET_MODE (XEXP (x, 0)) == mode
8644 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
8645 && (nonzero_bits (XEXP (x, 0), mode)
8646 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
8647 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8648
8649 break;
8650
8651 case IF_THEN_ELSE:
8652 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8653 written in a narrower mode. We play it safe and do not do so. */
8654
8655 SUBST (XEXP (x, 1),
8656 gen_lowpart_or_truncate (GET_MODE (x),
8657 force_to_mode (XEXP (x, 1), mode,
8658 mask, next_select)));
8659 SUBST (XEXP (x, 2),
8660 gen_lowpart_or_truncate (GET_MODE (x),
8661 force_to_mode (XEXP (x, 2), mode,
8662 mask, next_select)));
8663 break;
8664
8665 default:
8666 break;
8667 }
8668
8669 /* Ensure we return a value of the proper mode. */
8670 return gen_lowpart_or_truncate (mode, x);
8671 }
8672
8673 /* Return nonzero if X is an expression that has one of two values depending on
8674 whether some other value is zero or nonzero. In that case, we return the
8675 value that is being tested, *PTRUE is set to the value if the rtx being
8676 returned has a nonzero value, and *PFALSE is set to the other alternative.
8677
8678 If we return zero, we set *PTRUE and *PFALSE to X. */
8679
8680 static rtx
if_then_else_cond(rtx x,rtx * ptrue,rtx * pfalse)8681 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
8682 {
8683 enum machine_mode mode = GET_MODE (x);
8684 enum rtx_code code = GET_CODE (x);
8685 rtx cond0, cond1, true0, true1, false0, false1;
8686 unsigned HOST_WIDE_INT nz;
8687
8688 /* If we are comparing a value against zero, we are done. */
8689 if ((code == NE || code == EQ)
8690 && XEXP (x, 1) == const0_rtx)
8691 {
8692 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
8693 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
8694 return XEXP (x, 0);
8695 }
8696
8697 /* If this is a unary operation whose operand has one of two values, apply
8698 our opcode to compute those values. */
8699 else if (UNARY_P (x)
8700 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
8701 {
8702 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
8703 *pfalse = simplify_gen_unary (code, mode, false0,
8704 GET_MODE (XEXP (x, 0)));
8705 return cond0;
8706 }
8707
8708 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8709 make can't possibly match and would suppress other optimizations. */
8710 else if (code == COMPARE)
8711 ;
8712
8713 /* If this is a binary operation, see if either side has only one of two
8714 values. If either one does or if both do and they are conditional on
8715 the same value, compute the new true and false values. */
8716 else if (BINARY_P (x))
8717 {
8718 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
8719 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
8720
8721 if ((cond0 != 0 || cond1 != 0)
8722 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
8723 {
8724 /* If if_then_else_cond returned zero, then true/false are the
8725 same rtl. We must copy one of them to prevent invalid rtl
8726 sharing. */
8727 if (cond0 == 0)
8728 true0 = copy_rtx (true0);
8729 else if (cond1 == 0)
8730 true1 = copy_rtx (true1);
8731
8732 if (COMPARISON_P (x))
8733 {
8734 *ptrue = simplify_gen_relational (code, mode, VOIDmode,
8735 true0, true1);
8736 *pfalse = simplify_gen_relational (code, mode, VOIDmode,
8737 false0, false1);
8738 }
8739 else
8740 {
8741 *ptrue = simplify_gen_binary (code, mode, true0, true1);
8742 *pfalse = simplify_gen_binary (code, mode, false0, false1);
8743 }
8744
8745 return cond0 ? cond0 : cond1;
8746 }
8747
8748 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8749 operands is zero when the other is nonzero, and vice-versa,
8750 and STORE_FLAG_VALUE is 1 or -1. */
8751
8752 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8753 && (code == PLUS || code == IOR || code == XOR || code == MINUS
8754 || code == UMAX)
8755 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8756 {
8757 rtx op0 = XEXP (XEXP (x, 0), 1);
8758 rtx op1 = XEXP (XEXP (x, 1), 1);
8759
8760 cond0 = XEXP (XEXP (x, 0), 0);
8761 cond1 = XEXP (XEXP (x, 1), 0);
8762
8763 if (COMPARISON_P (cond0)
8764 && COMPARISON_P (cond1)
8765 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8766 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8767 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8768 || ((swap_condition (GET_CODE (cond0))
8769 == reversed_comparison_code (cond1, NULL))
8770 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8771 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8772 && ! side_effects_p (x))
8773 {
8774 *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
8775 *pfalse = simplify_gen_binary (MULT, mode,
8776 (code == MINUS
8777 ? simplify_gen_unary (NEG, mode,
8778 op1, mode)
8779 : op1),
8780 const_true_rtx);
8781 return cond0;
8782 }
8783 }
8784
8785 /* Similarly for MULT, AND and UMIN, except that for these the result
8786 is always zero. */
8787 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8788 && (code == MULT || code == AND || code == UMIN)
8789 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8790 {
8791 cond0 = XEXP (XEXP (x, 0), 0);
8792 cond1 = XEXP (XEXP (x, 1), 0);
8793
8794 if (COMPARISON_P (cond0)
8795 && COMPARISON_P (cond1)
8796 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8797 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8798 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8799 || ((swap_condition (GET_CODE (cond0))
8800 == reversed_comparison_code (cond1, NULL))
8801 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8802 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8803 && ! side_effects_p (x))
8804 {
8805 *ptrue = *pfalse = const0_rtx;
8806 return cond0;
8807 }
8808 }
8809 }
8810
8811 else if (code == IF_THEN_ELSE)
8812 {
8813 /* If we have IF_THEN_ELSE already, extract the condition and
8814 canonicalize it if it is NE or EQ. */
8815 cond0 = XEXP (x, 0);
8816 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
8817 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
8818 return XEXP (cond0, 0);
8819 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
8820 {
8821 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
8822 return XEXP (cond0, 0);
8823 }
8824 else
8825 return cond0;
8826 }
8827
8828 /* If X is a SUBREG, we can narrow both the true and false values
8829 if the inner expression, if there is a condition. */
8830 else if (code == SUBREG
8831 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
8832 &true0, &false0)))
8833 {
8834 true0 = simplify_gen_subreg (mode, true0,
8835 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8836 false0 = simplify_gen_subreg (mode, false0,
8837 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8838 if (true0 && false0)
8839 {
8840 *ptrue = true0;
8841 *pfalse = false0;
8842 return cond0;
8843 }
8844 }
8845
8846 /* If X is a constant, this isn't special and will cause confusions
8847 if we treat it as such. Likewise if it is equivalent to a constant. */
8848 else if (CONSTANT_P (x)
8849 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
8850 ;
8851
8852 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
8853 will be least confusing to the rest of the compiler. */
8854 else if (mode == BImode)
8855 {
8856 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
8857 return x;
8858 }
8859
8860 /* If X is known to be either 0 or -1, those are the true and
8861 false values when testing X. */
8862 else if (x == constm1_rtx || x == const0_rtx
8863 || (mode != VOIDmode
8864 && num_sign_bit_copies (x, mode) == GET_MODE_PRECISION (mode)))
8865 {
8866 *ptrue = constm1_rtx, *pfalse = const0_rtx;
8867 return x;
8868 }
8869
8870 /* Likewise for 0 or a single bit. */
8871 else if (HWI_COMPUTABLE_MODE_P (mode)
8872 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
8873 {
8874 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
8875 return x;
8876 }
8877
8878 /* Otherwise fail; show no condition with true and false values the same. */
8879 *ptrue = *pfalse = x;
8880 return 0;
8881 }
8882
8883 /* Return the value of expression X given the fact that condition COND
8884 is known to be true when applied to REG as its first operand and VAL
8885 as its second. X is known to not be shared and so can be modified in
8886 place.
8887
8888 We only handle the simplest cases, and specifically those cases that
8889 arise with IF_THEN_ELSE expressions. */
8890
8891 static rtx
known_cond(rtx x,enum rtx_code cond,rtx reg,rtx val)8892 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
8893 {
8894 enum rtx_code code = GET_CODE (x);
8895 rtx temp;
8896 const char *fmt;
8897 int i, j;
8898
8899 if (side_effects_p (x))
8900 return x;
8901
8902 /* If either operand of the condition is a floating point value,
8903 then we have to avoid collapsing an EQ comparison. */
8904 if (cond == EQ
8905 && rtx_equal_p (x, reg)
8906 && ! FLOAT_MODE_P (GET_MODE (x))
8907 && ! FLOAT_MODE_P (GET_MODE (val)))
8908 return val;
8909
8910 if (cond == UNEQ && rtx_equal_p (x, reg))
8911 return val;
8912
8913 /* If X is (abs REG) and we know something about REG's relationship
8914 with zero, we may be able to simplify this. */
8915
8916 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
8917 switch (cond)
8918 {
8919 case GE: case GT: case EQ:
8920 return XEXP (x, 0);
8921 case LT: case LE:
8922 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
8923 XEXP (x, 0),
8924 GET_MODE (XEXP (x, 0)));
8925 default:
8926 break;
8927 }
8928
8929 /* The only other cases we handle are MIN, MAX, and comparisons if the
8930 operands are the same as REG and VAL. */
8931
8932 else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
8933 {
8934 if (rtx_equal_p (XEXP (x, 0), val))
8935 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
8936
8937 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
8938 {
8939 if (COMPARISON_P (x))
8940 {
8941 if (comparison_dominates_p (cond, code))
8942 return const_true_rtx;
8943
8944 code = reversed_comparison_code (x, NULL);
8945 if (code != UNKNOWN
8946 && comparison_dominates_p (cond, code))
8947 return const0_rtx;
8948 else
8949 return x;
8950 }
8951 else if (code == SMAX || code == SMIN
8952 || code == UMIN || code == UMAX)
8953 {
8954 int unsignedp = (code == UMIN || code == UMAX);
8955
8956 /* Do not reverse the condition when it is NE or EQ.
8957 This is because we cannot conclude anything about
8958 the value of 'SMAX (x, y)' when x is not equal to y,
8959 but we can when x equals y. */
8960 if ((code == SMAX || code == UMAX)
8961 && ! (cond == EQ || cond == NE))
8962 cond = reverse_condition (cond);
8963
8964 switch (cond)
8965 {
8966 case GE: case GT:
8967 return unsignedp ? x : XEXP (x, 1);
8968 case LE: case LT:
8969 return unsignedp ? x : XEXP (x, 0);
8970 case GEU: case GTU:
8971 return unsignedp ? XEXP (x, 1) : x;
8972 case LEU: case LTU:
8973 return unsignedp ? XEXP (x, 0) : x;
8974 default:
8975 break;
8976 }
8977 }
8978 }
8979 }
8980 else if (code == SUBREG)
8981 {
8982 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
8983 rtx new_rtx, r = known_cond (SUBREG_REG (x), cond, reg, val);
8984
8985 if (SUBREG_REG (x) != r)
8986 {
8987 /* We must simplify subreg here, before we lose track of the
8988 original inner_mode. */
8989 new_rtx = simplify_subreg (GET_MODE (x), r,
8990 inner_mode, SUBREG_BYTE (x));
8991 if (new_rtx)
8992 return new_rtx;
8993 else
8994 SUBST (SUBREG_REG (x), r);
8995 }
8996
8997 return x;
8998 }
8999 /* We don't have to handle SIGN_EXTEND here, because even in the
9000 case of replacing something with a modeless CONST_INT, a
9001 CONST_INT is already (supposed to be) a valid sign extension for
9002 its narrower mode, which implies it's already properly
9003 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9004 story is different. */
9005 else if (code == ZERO_EXTEND)
9006 {
9007 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
9008 rtx new_rtx, r = known_cond (XEXP (x, 0), cond, reg, val);
9009
9010 if (XEXP (x, 0) != r)
9011 {
9012 /* We must simplify the zero_extend here, before we lose
9013 track of the original inner_mode. */
9014 new_rtx = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
9015 r, inner_mode);
9016 if (new_rtx)
9017 return new_rtx;
9018 else
9019 SUBST (XEXP (x, 0), r);
9020 }
9021
9022 return x;
9023 }
9024
9025 fmt = GET_RTX_FORMAT (code);
9026 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9027 {
9028 if (fmt[i] == 'e')
9029 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
9030 else if (fmt[i] == 'E')
9031 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9032 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
9033 cond, reg, val));
9034 }
9035
9036 return x;
9037 }
9038
9039 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9040 assignment as a field assignment. */
9041
9042 static int
rtx_equal_for_field_assignment_p(rtx x,rtx y)9043 rtx_equal_for_field_assignment_p (rtx x, rtx y)
9044 {
9045 if (x == y || rtx_equal_p (x, y))
9046 return 1;
9047
9048 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
9049 return 0;
9050
9051 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9052 Note that all SUBREGs of MEM are paradoxical; otherwise they
9053 would have been rewritten. */
9054 if (MEM_P (x) && GET_CODE (y) == SUBREG
9055 && MEM_P (SUBREG_REG (y))
9056 && rtx_equal_p (SUBREG_REG (y),
9057 gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
9058 return 1;
9059
9060 if (MEM_P (y) && GET_CODE (x) == SUBREG
9061 && MEM_P (SUBREG_REG (x))
9062 && rtx_equal_p (SUBREG_REG (x),
9063 gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
9064 return 1;
9065
9066 /* We used to see if get_last_value of X and Y were the same but that's
9067 not correct. In one direction, we'll cause the assignment to have
9068 the wrong destination and in the case, we'll import a register into this
9069 insn that might have already have been dead. So fail if none of the
9070 above cases are true. */
9071 return 0;
9072 }
9073
9074 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9075 Return that assignment if so.
9076
9077 We only handle the most common cases. */
9078
9079 static rtx
make_field_assignment(rtx x)9080 make_field_assignment (rtx x)
9081 {
9082 rtx dest = SET_DEST (x);
9083 rtx src = SET_SRC (x);
9084 rtx assign;
9085 rtx rhs, lhs;
9086 HOST_WIDE_INT c1;
9087 HOST_WIDE_INT pos;
9088 unsigned HOST_WIDE_INT len;
9089 rtx other;
9090 enum machine_mode mode;
9091
9092 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9093 a clear of a one-bit field. We will have changed it to
9094 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9095 for a SUBREG. */
9096
9097 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
9098 && CONST_INT_P (XEXP (XEXP (src, 0), 0))
9099 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
9100 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
9101 {
9102 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
9103 1, 1, 1, 0);
9104 if (assign != 0)
9105 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
9106 return x;
9107 }
9108
9109 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
9110 && subreg_lowpart_p (XEXP (src, 0))
9111 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
9112 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
9113 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
9114 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src, 0)), 0))
9115 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
9116 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
9117 {
9118 assign = make_extraction (VOIDmode, dest, 0,
9119 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
9120 1, 1, 1, 0);
9121 if (assign != 0)
9122 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
9123 return x;
9124 }
9125
9126 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9127 one-bit field. */
9128 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
9129 && XEXP (XEXP (src, 0), 0) == const1_rtx
9130 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
9131 {
9132 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
9133 1, 1, 1, 0);
9134 if (assign != 0)
9135 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
9136 return x;
9137 }
9138
9139 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9140 SRC is an AND with all bits of that field set, then we can discard
9141 the AND. */
9142 if (GET_CODE (dest) == ZERO_EXTRACT
9143 && CONST_INT_P (XEXP (dest, 1))
9144 && GET_CODE (src) == AND
9145 && CONST_INT_P (XEXP (src, 1)))
9146 {
9147 HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
9148 unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
9149 unsigned HOST_WIDE_INT ze_mask;
9150
9151 if (width >= HOST_BITS_PER_WIDE_INT)
9152 ze_mask = -1;
9153 else
9154 ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
9155
9156 /* Complete overlap. We can remove the source AND. */
9157 if ((and_mask & ze_mask) == ze_mask)
9158 return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
9159
9160 /* Partial overlap. We can reduce the source AND. */
9161 if ((and_mask & ze_mask) != and_mask)
9162 {
9163 mode = GET_MODE (src);
9164 src = gen_rtx_AND (mode, XEXP (src, 0),
9165 gen_int_mode (and_mask & ze_mask, mode));
9166 return gen_rtx_SET (VOIDmode, dest, src);
9167 }
9168 }
9169
9170 /* The other case we handle is assignments into a constant-position
9171 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9172 a mask that has all one bits except for a group of zero bits and
9173 OTHER is known to have zeros where C1 has ones, this is such an
9174 assignment. Compute the position and length from C1. Shift OTHER
9175 to the appropriate position, force it to the required mode, and
9176 make the extraction. Check for the AND in both operands. */
9177
9178 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
9179 return x;
9180
9181 rhs = expand_compound_operation (XEXP (src, 0));
9182 lhs = expand_compound_operation (XEXP (src, 1));
9183
9184 if (GET_CODE (rhs) == AND
9185 && CONST_INT_P (XEXP (rhs, 1))
9186 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
9187 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
9188 else if (GET_CODE (lhs) == AND
9189 && CONST_INT_P (XEXP (lhs, 1))
9190 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
9191 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
9192 else
9193 return x;
9194
9195 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
9196 if (pos < 0 || pos + len > GET_MODE_PRECISION (GET_MODE (dest))
9197 || GET_MODE_PRECISION (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
9198 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
9199 return x;
9200
9201 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
9202 if (assign == 0)
9203 return x;
9204
9205 /* The mode to use for the source is the mode of the assignment, or of
9206 what is inside a possible STRICT_LOW_PART. */
9207 mode = (GET_CODE (assign) == STRICT_LOW_PART
9208 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
9209
9210 /* Shift OTHER right POS places and make it the source, restricting it
9211 to the proper length and mode. */
9212
9213 src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
9214 GET_MODE (src),
9215 other, pos),
9216 dest);
9217 src = force_to_mode (src, mode,
9218 GET_MODE_PRECISION (mode) >= HOST_BITS_PER_WIDE_INT
9219 ? ~(unsigned HOST_WIDE_INT) 0
9220 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
9221 0);
9222
9223 /* If SRC is masked by an AND that does not make a difference in
9224 the value being stored, strip it. */
9225 if (GET_CODE (assign) == ZERO_EXTRACT
9226 && CONST_INT_P (XEXP (assign, 1))
9227 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
9228 && GET_CODE (src) == AND
9229 && CONST_INT_P (XEXP (src, 1))
9230 && UINTVAL (XEXP (src, 1))
9231 == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1)
9232 src = XEXP (src, 0);
9233
9234 return gen_rtx_SET (VOIDmode, assign, src);
9235 }
9236
9237 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9238 if so. */
9239
9240 static rtx
apply_distributive_law(rtx x)9241 apply_distributive_law (rtx x)
9242 {
9243 enum rtx_code code = GET_CODE (x);
9244 enum rtx_code inner_code;
9245 rtx lhs, rhs, other;
9246 rtx tem;
9247
9248 /* Distributivity is not true for floating point as it can change the
9249 value. So we don't do it unless -funsafe-math-optimizations. */
9250 if (FLOAT_MODE_P (GET_MODE (x))
9251 && ! flag_unsafe_math_optimizations)
9252 return x;
9253
9254 /* The outer operation can only be one of the following: */
9255 if (code != IOR && code != AND && code != XOR
9256 && code != PLUS && code != MINUS)
9257 return x;
9258
9259 lhs = XEXP (x, 0);
9260 rhs = XEXP (x, 1);
9261
9262 /* If either operand is a primitive we can't do anything, so get out
9263 fast. */
9264 if (OBJECT_P (lhs) || OBJECT_P (rhs))
9265 return x;
9266
9267 lhs = expand_compound_operation (lhs);
9268 rhs = expand_compound_operation (rhs);
9269 inner_code = GET_CODE (lhs);
9270 if (inner_code != GET_CODE (rhs))
9271 return x;
9272
9273 /* See if the inner and outer operations distribute. */
9274 switch (inner_code)
9275 {
9276 case LSHIFTRT:
9277 case ASHIFTRT:
9278 case AND:
9279 case IOR:
9280 /* These all distribute except over PLUS. */
9281 if (code == PLUS || code == MINUS)
9282 return x;
9283 break;
9284
9285 case MULT:
9286 if (code != PLUS && code != MINUS)
9287 return x;
9288 break;
9289
9290 case ASHIFT:
9291 /* This is also a multiply, so it distributes over everything. */
9292 break;
9293
9294 case SUBREG:
9295 /* Non-paradoxical SUBREGs distributes over all operations,
9296 provided the inner modes and byte offsets are the same, this
9297 is an extraction of a low-order part, we don't convert an fp
9298 operation to int or vice versa, this is not a vector mode,
9299 and we would not be converting a single-word operation into a
9300 multi-word operation. The latter test is not required, but
9301 it prevents generating unneeded multi-word operations. Some
9302 of the previous tests are redundant given the latter test,
9303 but are retained because they are required for correctness.
9304
9305 We produce the result slightly differently in this case. */
9306
9307 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
9308 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
9309 || ! subreg_lowpart_p (lhs)
9310 || (GET_MODE_CLASS (GET_MODE (lhs))
9311 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
9312 || paradoxical_subreg_p (lhs)
9313 || VECTOR_MODE_P (GET_MODE (lhs))
9314 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD
9315 /* Result might need to be truncated. Don't change mode if
9316 explicit truncation is needed. */
9317 || !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (x),
9318 GET_MODE (SUBREG_REG (lhs))))
9319 return x;
9320
9321 tem = simplify_gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
9322 SUBREG_REG (lhs), SUBREG_REG (rhs));
9323 return gen_lowpart (GET_MODE (x), tem);
9324
9325 default:
9326 return x;
9327 }
9328
9329 /* Set LHS and RHS to the inner operands (A and B in the example
9330 above) and set OTHER to the common operand (C in the example).
9331 There is only one way to do this unless the inner operation is
9332 commutative. */
9333 if (COMMUTATIVE_ARITH_P (lhs)
9334 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
9335 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
9336 else if (COMMUTATIVE_ARITH_P (lhs)
9337 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
9338 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
9339 else if (COMMUTATIVE_ARITH_P (lhs)
9340 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
9341 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
9342 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
9343 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
9344 else
9345 return x;
9346
9347 /* Form the new inner operation, seeing if it simplifies first. */
9348 tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
9349
9350 /* There is one exception to the general way of distributing:
9351 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9352 if (code == XOR && inner_code == IOR)
9353 {
9354 inner_code = AND;
9355 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
9356 }
9357
9358 /* We may be able to continuing distributing the result, so call
9359 ourselves recursively on the inner operation before forming the
9360 outer operation, which we return. */
9361 return simplify_gen_binary (inner_code, GET_MODE (x),
9362 apply_distributive_law (tem), other);
9363 }
9364
9365 /* See if X is of the form (* (+ A B) C), and if so convert to
9366 (+ (* A C) (* B C)) and try to simplify.
9367
9368 Most of the time, this results in no change. However, if some of
9369 the operands are the same or inverses of each other, simplifications
9370 will result.
9371
9372 For example, (and (ior A B) (not B)) can occur as the result of
9373 expanding a bit field assignment. When we apply the distributive
9374 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9375 which then simplifies to (and (A (not B))).
9376
9377 Note that no checks happen on the validity of applying the inverse
9378 distributive law. This is pointless since we can do it in the
9379 few places where this routine is called.
9380
9381 N is the index of the term that is decomposed (the arithmetic operation,
9382 i.e. (+ A B) in the first example above). !N is the index of the term that
9383 is distributed, i.e. of C in the first example above. */
9384 static rtx
distribute_and_simplify_rtx(rtx x,int n)9385 distribute_and_simplify_rtx (rtx x, int n)
9386 {
9387 enum machine_mode mode;
9388 enum rtx_code outer_code, inner_code;
9389 rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
9390
9391 /* Distributivity is not true for floating point as it can change the
9392 value. So we don't do it unless -funsafe-math-optimizations. */
9393 if (FLOAT_MODE_P (GET_MODE (x))
9394 && ! flag_unsafe_math_optimizations)
9395 return NULL_RTX;
9396
9397 decomposed = XEXP (x, n);
9398 if (!ARITHMETIC_P (decomposed))
9399 return NULL_RTX;
9400
9401 mode = GET_MODE (x);
9402 outer_code = GET_CODE (x);
9403 distributed = XEXP (x, !n);
9404
9405 inner_code = GET_CODE (decomposed);
9406 inner_op0 = XEXP (decomposed, 0);
9407 inner_op1 = XEXP (decomposed, 1);
9408
9409 /* Special case (and (xor B C) (not A)), which is equivalent to
9410 (xor (ior A B) (ior A C)) */
9411 if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
9412 {
9413 distributed = XEXP (distributed, 0);
9414 outer_code = IOR;
9415 }
9416
9417 if (n == 0)
9418 {
9419 /* Distribute the second term. */
9420 new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
9421 new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
9422 }
9423 else
9424 {
9425 /* Distribute the first term. */
9426 new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
9427 new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
9428 }
9429
9430 tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
9431 new_op0, new_op1));
9432 if (GET_CODE (tmp) != outer_code
9433 && (set_src_cost (tmp, optimize_this_for_speed_p)
9434 < set_src_cost (x, optimize_this_for_speed_p)))
9435 return tmp;
9436
9437 return NULL_RTX;
9438 }
9439
9440 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9441 in MODE. Return an equivalent form, if different from (and VAROP
9442 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9443
9444 static rtx
simplify_and_const_int_1(enum machine_mode mode,rtx varop,unsigned HOST_WIDE_INT constop)9445 simplify_and_const_int_1 (enum machine_mode mode, rtx varop,
9446 unsigned HOST_WIDE_INT constop)
9447 {
9448 unsigned HOST_WIDE_INT nonzero;
9449 unsigned HOST_WIDE_INT orig_constop;
9450 rtx orig_varop;
9451 int i;
9452
9453 orig_varop = varop;
9454 orig_constop = constop;
9455 if (GET_CODE (varop) == CLOBBER)
9456 return NULL_RTX;
9457
9458 /* Simplify VAROP knowing that we will be only looking at some of the
9459 bits in it.
9460
9461 Note by passing in CONSTOP, we guarantee that the bits not set in
9462 CONSTOP are not significant and will never be examined. We must
9463 ensure that is the case by explicitly masking out those bits
9464 before returning. */
9465 varop = force_to_mode (varop, mode, constop, 0);
9466
9467 /* If VAROP is a CLOBBER, we will fail so return it. */
9468 if (GET_CODE (varop) == CLOBBER)
9469 return varop;
9470
9471 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9472 to VAROP and return the new constant. */
9473 if (CONST_INT_P (varop))
9474 return gen_int_mode (INTVAL (varop) & constop, mode);
9475
9476 /* See what bits may be nonzero in VAROP. Unlike the general case of
9477 a call to nonzero_bits, here we don't care about bits outside
9478 MODE. */
9479
9480 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
9481
9482 /* Turn off all bits in the constant that are known to already be zero.
9483 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9484 which is tested below. */
9485
9486 constop &= nonzero;
9487
9488 /* If we don't have any bits left, return zero. */
9489 if (constop == 0)
9490 return const0_rtx;
9491
9492 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9493 a power of two, we can replace this with an ASHIFT. */
9494 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
9495 && (i = exact_log2 (constop)) >= 0)
9496 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
9497
9498 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9499 or XOR, then try to apply the distributive law. This may eliminate
9500 operations if either branch can be simplified because of the AND.
9501 It may also make some cases more complex, but those cases probably
9502 won't match a pattern either with or without this. */
9503
9504 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
9505 return
9506 gen_lowpart
9507 (mode,
9508 apply_distributive_law
9509 (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
9510 simplify_and_const_int (NULL_RTX,
9511 GET_MODE (varop),
9512 XEXP (varop, 0),
9513 constop),
9514 simplify_and_const_int (NULL_RTX,
9515 GET_MODE (varop),
9516 XEXP (varop, 1),
9517 constop))));
9518
9519 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9520 the AND and see if one of the operands simplifies to zero. If so, we
9521 may eliminate it. */
9522
9523 if (GET_CODE (varop) == PLUS
9524 && exact_log2 (constop + 1) >= 0)
9525 {
9526 rtx o0, o1;
9527
9528 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
9529 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
9530 if (o0 == const0_rtx)
9531 return o1;
9532 if (o1 == const0_rtx)
9533 return o0;
9534 }
9535
9536 /* Make a SUBREG if necessary. If we can't make it, fail. */
9537 varop = gen_lowpart (mode, varop);
9538 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
9539 return NULL_RTX;
9540
9541 /* If we are only masking insignificant bits, return VAROP. */
9542 if (constop == nonzero)
9543 return varop;
9544
9545 if (varop == orig_varop && constop == orig_constop)
9546 return NULL_RTX;
9547
9548 /* Otherwise, return an AND. */
9549 return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode));
9550 }
9551
9552
9553 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9554 in MODE.
9555
9556 Return an equivalent form, if different from X. Otherwise, return X. If
9557 X is zero, we are to always construct the equivalent form. */
9558
9559 static rtx
simplify_and_const_int(rtx x,enum machine_mode mode,rtx varop,unsigned HOST_WIDE_INT constop)9560 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
9561 unsigned HOST_WIDE_INT constop)
9562 {
9563 rtx tem = simplify_and_const_int_1 (mode, varop, constop);
9564 if (tem)
9565 return tem;
9566
9567 if (!x)
9568 x = simplify_gen_binary (AND, GET_MODE (varop), varop,
9569 gen_int_mode (constop, mode));
9570 if (GET_MODE (x) != mode)
9571 x = gen_lowpart (mode, x);
9572 return x;
9573 }
9574
9575 /* Given a REG, X, compute which bits in X can be nonzero.
9576 We don't care about bits outside of those defined in MODE.
9577
9578 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9579 a shift, AND, or zero_extract, we can do better. */
9580
9581 static rtx
reg_nonzero_bits_for_combine(const_rtx x,enum machine_mode mode,const_rtx known_x ATTRIBUTE_UNUSED,enum machine_mode known_mode ATTRIBUTE_UNUSED,unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,unsigned HOST_WIDE_INT * nonzero)9582 reg_nonzero_bits_for_combine (const_rtx x, enum machine_mode mode,
9583 const_rtx known_x ATTRIBUTE_UNUSED,
9584 enum machine_mode known_mode ATTRIBUTE_UNUSED,
9585 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
9586 unsigned HOST_WIDE_INT *nonzero)
9587 {
9588 rtx tem;
9589 reg_stat_type *rsp;
9590
9591 /* If X is a register whose nonzero bits value is current, use it.
9592 Otherwise, if X is a register whose value we can find, use that
9593 value. Otherwise, use the previously-computed global nonzero bits
9594 for this register. */
9595
9596 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
9597 if (rsp->last_set_value != 0
9598 && (rsp->last_set_mode == mode
9599 || (GET_MODE_CLASS (rsp->last_set_mode) == MODE_INT
9600 && GET_MODE_CLASS (mode) == MODE_INT))
9601 && ((rsp->last_set_label >= label_tick_ebb_start
9602 && rsp->last_set_label < label_tick)
9603 || (rsp->last_set_label == label_tick
9604 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9605 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9606 && REG_N_SETS (REGNO (x)) == 1
9607 && !REGNO_REG_SET_P
9608 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
9609 {
9610 *nonzero &= rsp->last_set_nonzero_bits;
9611 return NULL;
9612 }
9613
9614 tem = get_last_value (x);
9615
9616 if (tem)
9617 {
9618 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9619 /* If X is narrower than MODE and TEM is a non-negative
9620 constant that would appear negative in the mode of X,
9621 sign-extend it for use in reg_nonzero_bits because some
9622 machines (maybe most) will actually do the sign-extension
9623 and this is the conservative approach.
9624
9625 ??? For 2.5, try to tighten up the MD files in this regard
9626 instead of this kludge. */
9627
9628 if (GET_MODE_PRECISION (GET_MODE (x)) < GET_MODE_PRECISION (mode)
9629 && CONST_INT_P (tem)
9630 && INTVAL (tem) > 0
9631 && val_signbit_known_set_p (GET_MODE (x), INTVAL (tem)))
9632 tem = GEN_INT (INTVAL (tem) | ~GET_MODE_MASK (GET_MODE (x)));
9633 #endif
9634 return tem;
9635 }
9636 else if (nonzero_sign_valid && rsp->nonzero_bits)
9637 {
9638 unsigned HOST_WIDE_INT mask = rsp->nonzero_bits;
9639
9640 if (GET_MODE_PRECISION (GET_MODE (x)) < GET_MODE_PRECISION (mode))
9641 /* We don't know anything about the upper bits. */
9642 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
9643 *nonzero &= mask;
9644 }
9645
9646 return NULL;
9647 }
9648
9649 /* Return the number of bits at the high-order end of X that are known to
9650 be equal to the sign bit. X will be used in mode MODE; if MODE is
9651 VOIDmode, X will be used in its own mode. The returned value will always
9652 be between 1 and the number of bits in MODE. */
9653
9654 static rtx
reg_num_sign_bit_copies_for_combine(const_rtx x,enum machine_mode mode,const_rtx known_x ATTRIBUTE_UNUSED,enum machine_mode known_mode ATTRIBUTE_UNUSED,unsigned int known_ret ATTRIBUTE_UNUSED,unsigned int * result)9655 reg_num_sign_bit_copies_for_combine (const_rtx x, enum machine_mode mode,
9656 const_rtx known_x ATTRIBUTE_UNUSED,
9657 enum machine_mode known_mode
9658 ATTRIBUTE_UNUSED,
9659 unsigned int known_ret ATTRIBUTE_UNUSED,
9660 unsigned int *result)
9661 {
9662 rtx tem;
9663 reg_stat_type *rsp;
9664
9665 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
9666 if (rsp->last_set_value != 0
9667 && rsp->last_set_mode == mode
9668 && ((rsp->last_set_label >= label_tick_ebb_start
9669 && rsp->last_set_label < label_tick)
9670 || (rsp->last_set_label == label_tick
9671 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9672 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9673 && REG_N_SETS (REGNO (x)) == 1
9674 && !REGNO_REG_SET_P
9675 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
9676 {
9677 *result = rsp->last_set_sign_bit_copies;
9678 return NULL;
9679 }
9680
9681 tem = get_last_value (x);
9682 if (tem != 0)
9683 return tem;
9684
9685 if (nonzero_sign_valid && rsp->sign_bit_copies != 0
9686 && GET_MODE_PRECISION (GET_MODE (x)) == GET_MODE_PRECISION (mode))
9687 *result = rsp->sign_bit_copies;
9688
9689 return NULL;
9690 }
9691
9692 /* Return the number of "extended" bits there are in X, when interpreted
9693 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9694 unsigned quantities, this is the number of high-order zero bits.
9695 For signed quantities, this is the number of copies of the sign bit
9696 minus 1. In both case, this function returns the number of "spare"
9697 bits. For example, if two quantities for which this function returns
9698 at least 1 are added, the addition is known not to overflow.
9699
9700 This function will always return 0 unless called during combine, which
9701 implies that it must be called from a define_split. */
9702
9703 unsigned int
extended_count(const_rtx x,enum machine_mode mode,int unsignedp)9704 extended_count (const_rtx x, enum machine_mode mode, int unsignedp)
9705 {
9706 if (nonzero_sign_valid == 0)
9707 return 0;
9708
9709 return (unsignedp
9710 ? (HWI_COMPUTABLE_MODE_P (mode)
9711 ? (unsigned int) (GET_MODE_PRECISION (mode) - 1
9712 - floor_log2 (nonzero_bits (x, mode)))
9713 : 0)
9714 : num_sign_bit_copies (x, mode) - 1);
9715 }
9716
9717 /* This function is called from `simplify_shift_const' to merge two
9718 outer operations. Specifically, we have already found that we need
9719 to perform operation *POP0 with constant *PCONST0 at the outermost
9720 position. We would now like to also perform OP1 with constant CONST1
9721 (with *POP0 being done last).
9722
9723 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9724 the resulting operation. *PCOMP_P is set to 1 if we would need to
9725 complement the innermost operand, otherwise it is unchanged.
9726
9727 MODE is the mode in which the operation will be done. No bits outside
9728 the width of this mode matter. It is assumed that the width of this mode
9729 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9730
9731 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
9732 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9733 result is simply *PCONST0.
9734
9735 If the resulting operation cannot be expressed as one operation, we
9736 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9737
9738 static int
merge_outer_ops(enum rtx_code * pop0,HOST_WIDE_INT * pconst0,enum rtx_code op1,HOST_WIDE_INT const1,enum machine_mode mode,int * pcomp_p)9739 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
9740 {
9741 enum rtx_code op0 = *pop0;
9742 HOST_WIDE_INT const0 = *pconst0;
9743
9744 const0 &= GET_MODE_MASK (mode);
9745 const1 &= GET_MODE_MASK (mode);
9746
9747 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9748 if (op0 == AND)
9749 const1 &= const0;
9750
9751 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
9752 if OP0 is SET. */
9753
9754 if (op1 == UNKNOWN || op0 == SET)
9755 return 1;
9756
9757 else if (op0 == UNKNOWN)
9758 op0 = op1, const0 = const1;
9759
9760 else if (op0 == op1)
9761 {
9762 switch (op0)
9763 {
9764 case AND:
9765 const0 &= const1;
9766 break;
9767 case IOR:
9768 const0 |= const1;
9769 break;
9770 case XOR:
9771 const0 ^= const1;
9772 break;
9773 case PLUS:
9774 const0 += const1;
9775 break;
9776 case NEG:
9777 op0 = UNKNOWN;
9778 break;
9779 default:
9780 break;
9781 }
9782 }
9783
9784 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9785 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
9786 return 0;
9787
9788 /* If the two constants aren't the same, we can't do anything. The
9789 remaining six cases can all be done. */
9790 else if (const0 != const1)
9791 return 0;
9792
9793 else
9794 switch (op0)
9795 {
9796 case IOR:
9797 if (op1 == AND)
9798 /* (a & b) | b == b */
9799 op0 = SET;
9800 else /* op1 == XOR */
9801 /* (a ^ b) | b == a | b */
9802 {;}
9803 break;
9804
9805 case XOR:
9806 if (op1 == AND)
9807 /* (a & b) ^ b == (~a) & b */
9808 op0 = AND, *pcomp_p = 1;
9809 else /* op1 == IOR */
9810 /* (a | b) ^ b == a & ~b */
9811 op0 = AND, const0 = ~const0;
9812 break;
9813
9814 case AND:
9815 if (op1 == IOR)
9816 /* (a | b) & b == b */
9817 op0 = SET;
9818 else /* op1 == XOR */
9819 /* (a ^ b) & b) == (~a) & b */
9820 *pcomp_p = 1;
9821 break;
9822 default:
9823 break;
9824 }
9825
9826 /* Check for NO-OP cases. */
9827 const0 &= GET_MODE_MASK (mode);
9828 if (const0 == 0
9829 && (op0 == IOR || op0 == XOR || op0 == PLUS))
9830 op0 = UNKNOWN;
9831 else if (const0 == 0 && op0 == AND)
9832 op0 = SET;
9833 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
9834 && op0 == AND)
9835 op0 = UNKNOWN;
9836
9837 *pop0 = op0;
9838
9839 /* ??? Slightly redundant with the above mask, but not entirely.
9840 Moving this above means we'd have to sign-extend the mode mask
9841 for the final test. */
9842 if (op0 != UNKNOWN && op0 != NEG)
9843 *pconst0 = trunc_int_for_mode (const0, mode);
9844
9845 return 1;
9846 }
9847
9848 /* A helper to simplify_shift_const_1 to determine the mode we can perform
9849 the shift in. The original shift operation CODE is performed on OP in
9850 ORIG_MODE. Return the wider mode MODE if we can perform the operation
9851 in that mode. Return ORIG_MODE otherwise. We can also assume that the
9852 result of the shift is subject to operation OUTER_CODE with operand
9853 OUTER_CONST. */
9854
9855 static enum machine_mode
try_widen_shift_mode(enum rtx_code code,rtx op,int count,enum machine_mode orig_mode,enum machine_mode mode,enum rtx_code outer_code,HOST_WIDE_INT outer_const)9856 try_widen_shift_mode (enum rtx_code code, rtx op, int count,
9857 enum machine_mode orig_mode, enum machine_mode mode,
9858 enum rtx_code outer_code, HOST_WIDE_INT outer_const)
9859 {
9860 if (orig_mode == mode)
9861 return mode;
9862 gcc_assert (GET_MODE_PRECISION (mode) > GET_MODE_PRECISION (orig_mode));
9863
9864 /* In general we can't perform in wider mode for right shift and rotate. */
9865 switch (code)
9866 {
9867 case ASHIFTRT:
9868 /* We can still widen if the bits brought in from the left are identical
9869 to the sign bit of ORIG_MODE. */
9870 if (num_sign_bit_copies (op, mode)
9871 > (unsigned) (GET_MODE_PRECISION (mode)
9872 - GET_MODE_PRECISION (orig_mode)))
9873 return mode;
9874 return orig_mode;
9875
9876 case LSHIFTRT:
9877 /* Similarly here but with zero bits. */
9878 if (HWI_COMPUTABLE_MODE_P (mode)
9879 && (nonzero_bits (op, mode) & ~GET_MODE_MASK (orig_mode)) == 0)
9880 return mode;
9881
9882 /* We can also widen if the bits brought in will be masked off. This
9883 operation is performed in ORIG_MODE. */
9884 if (outer_code == AND)
9885 {
9886 int care_bits = low_bitmask_len (orig_mode, outer_const);
9887
9888 if (care_bits >= 0
9889 && GET_MODE_PRECISION (orig_mode) - care_bits >= count)
9890 return mode;
9891 }
9892 /* fall through */
9893
9894 case ROTATE:
9895 return orig_mode;
9896
9897 case ROTATERT:
9898 gcc_unreachable ();
9899
9900 default:
9901 return mode;
9902 }
9903 }
9904
9905 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
9906 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
9907 if we cannot simplify it. Otherwise, return a simplified value.
9908
9909 The shift is normally computed in the widest mode we find in VAROP, as
9910 long as it isn't a different number of words than RESULT_MODE. Exceptions
9911 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9912
9913 static rtx
simplify_shift_const_1(enum rtx_code code,enum machine_mode result_mode,rtx varop,int orig_count)9914 simplify_shift_const_1 (enum rtx_code code, enum machine_mode result_mode,
9915 rtx varop, int orig_count)
9916 {
9917 enum rtx_code orig_code = code;
9918 rtx orig_varop = varop;
9919 int count;
9920 enum machine_mode mode = result_mode;
9921 enum machine_mode shift_mode, tmode;
9922 unsigned int mode_words
9923 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
9924 /* We form (outer_op (code varop count) (outer_const)). */
9925 enum rtx_code outer_op = UNKNOWN;
9926 HOST_WIDE_INT outer_const = 0;
9927 int complement_p = 0;
9928 rtx new_rtx, x;
9929
9930 /* Make sure and truncate the "natural" shift on the way in. We don't
9931 want to do this inside the loop as it makes it more difficult to
9932 combine shifts. */
9933 if (SHIFT_COUNT_TRUNCATED)
9934 orig_count &= GET_MODE_BITSIZE (mode) - 1;
9935
9936 /* If we were given an invalid count, don't do anything except exactly
9937 what was requested. */
9938
9939 if (orig_count < 0 || orig_count >= (int) GET_MODE_PRECISION (mode))
9940 return NULL_RTX;
9941
9942 count = orig_count;
9943
9944 /* Unless one of the branches of the `if' in this loop does a `continue',
9945 we will `break' the loop after the `if'. */
9946
9947 while (count != 0)
9948 {
9949 /* If we have an operand of (clobber (const_int 0)), fail. */
9950 if (GET_CODE (varop) == CLOBBER)
9951 return NULL_RTX;
9952
9953 /* Convert ROTATERT to ROTATE. */
9954 if (code == ROTATERT)
9955 {
9956 unsigned int bitsize = GET_MODE_PRECISION (result_mode);
9957 code = ROTATE;
9958 if (VECTOR_MODE_P (result_mode))
9959 count = bitsize / GET_MODE_NUNITS (result_mode) - count;
9960 else
9961 count = bitsize - count;
9962 }
9963
9964 shift_mode = try_widen_shift_mode (code, varop, count, result_mode,
9965 mode, outer_op, outer_const);
9966
9967 /* Handle cases where the count is greater than the size of the mode
9968 minus 1. For ASHIFT, use the size minus one as the count (this can
9969 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9970 take the count modulo the size. For other shifts, the result is
9971 zero.
9972
9973 Since these shifts are being produced by the compiler by combining
9974 multiple operations, each of which are defined, we know what the
9975 result is supposed to be. */
9976
9977 if (count > (GET_MODE_PRECISION (shift_mode) - 1))
9978 {
9979 if (code == ASHIFTRT)
9980 count = GET_MODE_PRECISION (shift_mode) - 1;
9981 else if (code == ROTATE || code == ROTATERT)
9982 count %= GET_MODE_PRECISION (shift_mode);
9983 else
9984 {
9985 /* We can't simply return zero because there may be an
9986 outer op. */
9987 varop = const0_rtx;
9988 count = 0;
9989 break;
9990 }
9991 }
9992
9993 /* If we discovered we had to complement VAROP, leave. Making a NOT
9994 here would cause an infinite loop. */
9995 if (complement_p)
9996 break;
9997
9998 /* An arithmetic right shift of a quantity known to be -1 or 0
9999 is a no-op. */
10000 if (code == ASHIFTRT
10001 && (num_sign_bit_copies (varop, shift_mode)
10002 == GET_MODE_PRECISION (shift_mode)))
10003 {
10004 count = 0;
10005 break;
10006 }
10007
10008 /* If we are doing an arithmetic right shift and discarding all but
10009 the sign bit copies, this is equivalent to doing a shift by the
10010 bitsize minus one. Convert it into that shift because it will often
10011 allow other simplifications. */
10012
10013 if (code == ASHIFTRT
10014 && (count + num_sign_bit_copies (varop, shift_mode)
10015 >= GET_MODE_PRECISION (shift_mode)))
10016 count = GET_MODE_PRECISION (shift_mode) - 1;
10017
10018 /* We simplify the tests below and elsewhere by converting
10019 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10020 `make_compound_operation' will convert it to an ASHIFTRT for
10021 those machines (such as VAX) that don't have an LSHIFTRT. */
10022 if (code == ASHIFTRT
10023 && val_signbit_known_clear_p (shift_mode,
10024 nonzero_bits (varop, shift_mode)))
10025 code = LSHIFTRT;
10026
10027 if (((code == LSHIFTRT
10028 && HWI_COMPUTABLE_MODE_P (shift_mode)
10029 && !(nonzero_bits (varop, shift_mode) >> count))
10030 || (code == ASHIFT
10031 && HWI_COMPUTABLE_MODE_P (shift_mode)
10032 && !((nonzero_bits (varop, shift_mode) << count)
10033 & GET_MODE_MASK (shift_mode))))
10034 && !side_effects_p (varop))
10035 varop = const0_rtx;
10036
10037 switch (GET_CODE (varop))
10038 {
10039 case SIGN_EXTEND:
10040 case ZERO_EXTEND:
10041 case SIGN_EXTRACT:
10042 case ZERO_EXTRACT:
10043 new_rtx = expand_compound_operation (varop);
10044 if (new_rtx != varop)
10045 {
10046 varop = new_rtx;
10047 continue;
10048 }
10049 break;
10050
10051 case MEM:
10052 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10053 minus the width of a smaller mode, we can do this with a
10054 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10055 if ((code == ASHIFTRT || code == LSHIFTRT)
10056 && ! mode_dependent_address_p (XEXP (varop, 0))
10057 && ! MEM_VOLATILE_P (varop)
10058 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
10059 MODE_INT, 1)) != BLKmode)
10060 {
10061 new_rtx = adjust_address_nv (varop, tmode,
10062 BYTES_BIG_ENDIAN ? 0
10063 : count / BITS_PER_UNIT);
10064
10065 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
10066 : ZERO_EXTEND, mode, new_rtx);
10067 count = 0;
10068 continue;
10069 }
10070 break;
10071
10072 case SUBREG:
10073 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10074 the same number of words as what we've seen so far. Then store
10075 the widest mode in MODE. */
10076 if (subreg_lowpart_p (varop)
10077 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
10078 > GET_MODE_SIZE (GET_MODE (varop)))
10079 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
10080 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
10081 == mode_words
10082 && GET_MODE_CLASS (GET_MODE (varop)) == MODE_INT
10083 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (varop))) == MODE_INT)
10084 {
10085 varop = SUBREG_REG (varop);
10086 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
10087 mode = GET_MODE (varop);
10088 continue;
10089 }
10090 break;
10091
10092 case MULT:
10093 /* Some machines use MULT instead of ASHIFT because MULT
10094 is cheaper. But it is still better on those machines to
10095 merge two shifts into one. */
10096 if (CONST_INT_P (XEXP (varop, 1))
10097 && exact_log2 (UINTVAL (XEXP (varop, 1))) >= 0)
10098 {
10099 varop
10100 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
10101 XEXP (varop, 0),
10102 GEN_INT (exact_log2 (
10103 UINTVAL (XEXP (varop, 1)))));
10104 continue;
10105 }
10106 break;
10107
10108 case UDIV:
10109 /* Similar, for when divides are cheaper. */
10110 if (CONST_INT_P (XEXP (varop, 1))
10111 && exact_log2 (UINTVAL (XEXP (varop, 1))) >= 0)
10112 {
10113 varop
10114 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
10115 XEXP (varop, 0),
10116 GEN_INT (exact_log2 (
10117 UINTVAL (XEXP (varop, 1)))));
10118 continue;
10119 }
10120 break;
10121
10122 case ASHIFTRT:
10123 /* If we are extracting just the sign bit of an arithmetic
10124 right shift, that shift is not needed. However, the sign
10125 bit of a wider mode may be different from what would be
10126 interpreted as the sign bit in a narrower mode, so, if
10127 the result is narrower, don't discard the shift. */
10128 if (code == LSHIFTRT
10129 && count == (GET_MODE_BITSIZE (result_mode) - 1)
10130 && (GET_MODE_BITSIZE (result_mode)
10131 >= GET_MODE_BITSIZE (GET_MODE (varop))))
10132 {
10133 varop = XEXP (varop, 0);
10134 continue;
10135 }
10136
10137 /* ... fall through ... */
10138
10139 case LSHIFTRT:
10140 case ASHIFT:
10141 case ROTATE:
10142 /* Here we have two nested shifts. The result is usually the
10143 AND of a new shift with a mask. We compute the result below. */
10144 if (CONST_INT_P (XEXP (varop, 1))
10145 && INTVAL (XEXP (varop, 1)) >= 0
10146 && INTVAL (XEXP (varop, 1)) < GET_MODE_PRECISION (GET_MODE (varop))
10147 && HWI_COMPUTABLE_MODE_P (result_mode)
10148 && HWI_COMPUTABLE_MODE_P (mode)
10149 && !VECTOR_MODE_P (result_mode))
10150 {
10151 enum rtx_code first_code = GET_CODE (varop);
10152 unsigned int first_count = INTVAL (XEXP (varop, 1));
10153 unsigned HOST_WIDE_INT mask;
10154 rtx mask_rtx;
10155
10156 /* We have one common special case. We can't do any merging if
10157 the inner code is an ASHIFTRT of a smaller mode. However, if
10158 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10159 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10160 we can convert it to
10161 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10162 This simplifies certain SIGN_EXTEND operations. */
10163 if (code == ASHIFT && first_code == ASHIFTRT
10164 && count == (GET_MODE_PRECISION (result_mode)
10165 - GET_MODE_PRECISION (GET_MODE (varop))))
10166 {
10167 /* C3 has the low-order C1 bits zero. */
10168
10169 mask = GET_MODE_MASK (mode)
10170 & ~(((unsigned HOST_WIDE_INT) 1 << first_count) - 1);
10171
10172 varop = simplify_and_const_int (NULL_RTX, result_mode,
10173 XEXP (varop, 0), mask);
10174 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
10175 varop, count);
10176 count = first_count;
10177 code = ASHIFTRT;
10178 continue;
10179 }
10180
10181 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10182 than C1 high-order bits equal to the sign bit, we can convert
10183 this to either an ASHIFT or an ASHIFTRT depending on the
10184 two counts.
10185
10186 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10187
10188 if (code == ASHIFTRT && first_code == ASHIFT
10189 && GET_MODE (varop) == shift_mode
10190 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
10191 > first_count))
10192 {
10193 varop = XEXP (varop, 0);
10194 count -= first_count;
10195 if (count < 0)
10196 {
10197 count = -count;
10198 code = ASHIFT;
10199 }
10200
10201 continue;
10202 }
10203
10204 /* There are some cases we can't do. If CODE is ASHIFTRT,
10205 we can only do this if FIRST_CODE is also ASHIFTRT.
10206
10207 We can't do the case when CODE is ROTATE and FIRST_CODE is
10208 ASHIFTRT.
10209
10210 If the mode of this shift is not the mode of the outer shift,
10211 we can't do this if either shift is a right shift or ROTATE.
10212
10213 Finally, we can't do any of these if the mode is too wide
10214 unless the codes are the same.
10215
10216 Handle the case where the shift codes are the same
10217 first. */
10218
10219 if (code == first_code)
10220 {
10221 if (GET_MODE (varop) != result_mode
10222 && (code == ASHIFTRT || code == LSHIFTRT
10223 || code == ROTATE))
10224 break;
10225
10226 count += first_count;
10227 varop = XEXP (varop, 0);
10228 continue;
10229 }
10230
10231 if (code == ASHIFTRT
10232 || (code == ROTATE && first_code == ASHIFTRT)
10233 || GET_MODE_PRECISION (mode) > HOST_BITS_PER_WIDE_INT
10234 || (GET_MODE (varop) != result_mode
10235 && (first_code == ASHIFTRT || first_code == LSHIFTRT
10236 || first_code == ROTATE
10237 || code == ROTATE)))
10238 break;
10239
10240 /* To compute the mask to apply after the shift, shift the
10241 nonzero bits of the inner shift the same way the
10242 outer shift will. */
10243
10244 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
10245
10246 mask_rtx
10247 = simplify_const_binary_operation (code, result_mode, mask_rtx,
10248 GEN_INT (count));
10249
10250 /* Give up if we can't compute an outer operation to use. */
10251 if (mask_rtx == 0
10252 || !CONST_INT_P (mask_rtx)
10253 || ! merge_outer_ops (&outer_op, &outer_const, AND,
10254 INTVAL (mask_rtx),
10255 result_mode, &complement_p))
10256 break;
10257
10258 /* If the shifts are in the same direction, we add the
10259 counts. Otherwise, we subtract them. */
10260 if ((code == ASHIFTRT || code == LSHIFTRT)
10261 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
10262 count += first_count;
10263 else
10264 count -= first_count;
10265
10266 /* If COUNT is positive, the new shift is usually CODE,
10267 except for the two exceptions below, in which case it is
10268 FIRST_CODE. If the count is negative, FIRST_CODE should
10269 always be used */
10270 if (count > 0
10271 && ((first_code == ROTATE && code == ASHIFT)
10272 || (first_code == ASHIFTRT && code == LSHIFTRT)))
10273 code = first_code;
10274 else if (count < 0)
10275 code = first_code, count = -count;
10276
10277 varop = XEXP (varop, 0);
10278 continue;
10279 }
10280
10281 /* If we have (A << B << C) for any shift, we can convert this to
10282 (A << C << B). This wins if A is a constant. Only try this if
10283 B is not a constant. */
10284
10285 else if (GET_CODE (varop) == code
10286 && CONST_INT_P (XEXP (varop, 0))
10287 && !CONST_INT_P (XEXP (varop, 1)))
10288 {
10289 rtx new_rtx = simplify_const_binary_operation (code, mode,
10290 XEXP (varop, 0),
10291 GEN_INT (count));
10292 varop = gen_rtx_fmt_ee (code, mode, new_rtx, XEXP (varop, 1));
10293 count = 0;
10294 continue;
10295 }
10296 break;
10297
10298 case NOT:
10299 if (VECTOR_MODE_P (mode))
10300 break;
10301
10302 /* Make this fit the case below. */
10303 varop = gen_rtx_XOR (mode, XEXP (varop, 0), constm1_rtx);
10304 continue;
10305
10306 case IOR:
10307 case AND:
10308 case XOR:
10309 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10310 with C the size of VAROP - 1 and the shift is logical if
10311 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10312 we have an (le X 0) operation. If we have an arithmetic shift
10313 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10314 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10315
10316 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
10317 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
10318 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
10319 && (code == LSHIFTRT || code == ASHIFTRT)
10320 && count == (GET_MODE_PRECISION (GET_MODE (varop)) - 1)
10321 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
10322 {
10323 count = 0;
10324 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
10325 const0_rtx);
10326
10327 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
10328 varop = gen_rtx_NEG (GET_MODE (varop), varop);
10329
10330 continue;
10331 }
10332
10333 /* If we have (shift (logical)), move the logical to the outside
10334 to allow it to possibly combine with another logical and the
10335 shift to combine with another shift. This also canonicalizes to
10336 what a ZERO_EXTRACT looks like. Also, some machines have
10337 (and (shift)) insns. */
10338
10339 if (CONST_INT_P (XEXP (varop, 1))
10340 /* We can't do this if we have (ashiftrt (xor)) and the
10341 constant has its sign bit set in shift_mode. */
10342 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
10343 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
10344 shift_mode))
10345 && (new_rtx = simplify_const_binary_operation (code, result_mode,
10346 XEXP (varop, 1),
10347 GEN_INT (count))) != 0
10348 && CONST_INT_P (new_rtx)
10349 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
10350 INTVAL (new_rtx), result_mode, &complement_p))
10351 {
10352 varop = XEXP (varop, 0);
10353 continue;
10354 }
10355
10356 /* If we can't do that, try to simplify the shift in each arm of the
10357 logical expression, make a new logical expression, and apply
10358 the inverse distributive law. This also can't be done
10359 for some (ashiftrt (xor)). */
10360 if (CONST_INT_P (XEXP (varop, 1))
10361 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
10362 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
10363 shift_mode)))
10364 {
10365 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
10366 XEXP (varop, 0), count);
10367 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
10368 XEXP (varop, 1), count);
10369
10370 varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
10371 lhs, rhs);
10372 varop = apply_distributive_law (varop);
10373
10374 count = 0;
10375 continue;
10376 }
10377 break;
10378
10379 case EQ:
10380 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10381 says that the sign bit can be tested, FOO has mode MODE, C is
10382 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10383 that may be nonzero. */
10384 if (code == LSHIFTRT
10385 && XEXP (varop, 1) == const0_rtx
10386 && GET_MODE (XEXP (varop, 0)) == result_mode
10387 && count == (GET_MODE_PRECISION (result_mode) - 1)
10388 && HWI_COMPUTABLE_MODE_P (result_mode)
10389 && STORE_FLAG_VALUE == -1
10390 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
10391 && merge_outer_ops (&outer_op, &outer_const, XOR, 1, result_mode,
10392 &complement_p))
10393 {
10394 varop = XEXP (varop, 0);
10395 count = 0;
10396 continue;
10397 }
10398 break;
10399
10400 case NEG:
10401 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10402 than the number of bits in the mode is equivalent to A. */
10403 if (code == LSHIFTRT
10404 && count == (GET_MODE_PRECISION (result_mode) - 1)
10405 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
10406 {
10407 varop = XEXP (varop, 0);
10408 count = 0;
10409 continue;
10410 }
10411
10412 /* NEG commutes with ASHIFT since it is multiplication. Move the
10413 NEG outside to allow shifts to combine. */
10414 if (code == ASHIFT
10415 && merge_outer_ops (&outer_op, &outer_const, NEG, 0, result_mode,
10416 &complement_p))
10417 {
10418 varop = XEXP (varop, 0);
10419 continue;
10420 }
10421 break;
10422
10423 case PLUS:
10424 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10425 is one less than the number of bits in the mode is
10426 equivalent to (xor A 1). */
10427 if (code == LSHIFTRT
10428 && count == (GET_MODE_PRECISION (result_mode) - 1)
10429 && XEXP (varop, 1) == constm1_rtx
10430 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
10431 && merge_outer_ops (&outer_op, &outer_const, XOR, 1, result_mode,
10432 &complement_p))
10433 {
10434 count = 0;
10435 varop = XEXP (varop, 0);
10436 continue;
10437 }
10438
10439 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10440 that might be nonzero in BAR are those being shifted out and those
10441 bits are known zero in FOO, we can replace the PLUS with FOO.
10442 Similarly in the other operand order. This code occurs when
10443 we are computing the size of a variable-size array. */
10444
10445 if ((code == ASHIFTRT || code == LSHIFTRT)
10446 && count < HOST_BITS_PER_WIDE_INT
10447 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
10448 && (nonzero_bits (XEXP (varop, 1), result_mode)
10449 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
10450 {
10451 varop = XEXP (varop, 0);
10452 continue;
10453 }
10454 else if ((code == ASHIFTRT || code == LSHIFTRT)
10455 && count < HOST_BITS_PER_WIDE_INT
10456 && HWI_COMPUTABLE_MODE_P (result_mode)
10457 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
10458 >> count)
10459 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
10460 & nonzero_bits (XEXP (varop, 1),
10461 result_mode)))
10462 {
10463 varop = XEXP (varop, 1);
10464 continue;
10465 }
10466
10467 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10468 if (code == ASHIFT
10469 && CONST_INT_P (XEXP (varop, 1))
10470 && (new_rtx = simplify_const_binary_operation (ASHIFT, result_mode,
10471 XEXP (varop, 1),
10472 GEN_INT (count))) != 0
10473 && CONST_INT_P (new_rtx)
10474 && merge_outer_ops (&outer_op, &outer_const, PLUS,
10475 INTVAL (new_rtx), result_mode, &complement_p))
10476 {
10477 varop = XEXP (varop, 0);
10478 continue;
10479 }
10480
10481 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10482 signbit', and attempt to change the PLUS to an XOR and move it to
10483 the outer operation as is done above in the AND/IOR/XOR case
10484 leg for shift(logical). See details in logical handling above
10485 for reasoning in doing so. */
10486 if (code == LSHIFTRT
10487 && CONST_INT_P (XEXP (varop, 1))
10488 && mode_signbit_p (result_mode, XEXP (varop, 1))
10489 && (new_rtx = simplify_const_binary_operation (code, result_mode,
10490 XEXP (varop, 1),
10491 GEN_INT (count))) != 0
10492 && CONST_INT_P (new_rtx)
10493 && merge_outer_ops (&outer_op, &outer_const, XOR,
10494 INTVAL (new_rtx), result_mode, &complement_p))
10495 {
10496 varop = XEXP (varop, 0);
10497 continue;
10498 }
10499
10500 break;
10501
10502 case MINUS:
10503 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10504 with C the size of VAROP - 1 and the shift is logical if
10505 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10506 we have a (gt X 0) operation. If the shift is arithmetic with
10507 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10508 we have a (neg (gt X 0)) operation. */
10509
10510 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
10511 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
10512 && count == (GET_MODE_PRECISION (GET_MODE (varop)) - 1)
10513 && (code == LSHIFTRT || code == ASHIFTRT)
10514 && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
10515 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
10516 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
10517 {
10518 count = 0;
10519 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
10520 const0_rtx);
10521
10522 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
10523 varop = gen_rtx_NEG (GET_MODE (varop), varop);
10524
10525 continue;
10526 }
10527 break;
10528
10529 case TRUNCATE:
10530 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10531 if the truncate does not affect the value. */
10532 if (code == LSHIFTRT
10533 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
10534 && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
10535 && (INTVAL (XEXP (XEXP (varop, 0), 1))
10536 >= (GET_MODE_PRECISION (GET_MODE (XEXP (varop, 0)))
10537 - GET_MODE_PRECISION (GET_MODE (varop)))))
10538 {
10539 rtx varop_inner = XEXP (varop, 0);
10540
10541 varop_inner
10542 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
10543 XEXP (varop_inner, 0),
10544 GEN_INT
10545 (count + INTVAL (XEXP (varop_inner, 1))));
10546 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
10547 count = 0;
10548 continue;
10549 }
10550 break;
10551
10552 default:
10553 break;
10554 }
10555
10556 break;
10557 }
10558
10559 shift_mode = try_widen_shift_mode (code, varop, count, result_mode, mode,
10560 outer_op, outer_const);
10561
10562 /* We have now finished analyzing the shift. The result should be
10563 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
10564 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10565 to the result of the shift. OUTER_CONST is the relevant constant,
10566 but we must turn off all bits turned off in the shift. */
10567
10568 if (outer_op == UNKNOWN
10569 && orig_code == code && orig_count == count
10570 && varop == orig_varop
10571 && shift_mode == GET_MODE (varop))
10572 return NULL_RTX;
10573
10574 /* Make a SUBREG if necessary. If we can't make it, fail. */
10575 varop = gen_lowpart (shift_mode, varop);
10576 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
10577 return NULL_RTX;
10578
10579 /* If we have an outer operation and we just made a shift, it is
10580 possible that we could have simplified the shift were it not
10581 for the outer operation. So try to do the simplification
10582 recursively. */
10583
10584 if (outer_op != UNKNOWN)
10585 x = simplify_shift_const_1 (code, shift_mode, varop, count);
10586 else
10587 x = NULL_RTX;
10588
10589 if (x == NULL_RTX)
10590 x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count));
10591
10592 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10593 turn off all the bits that the shift would have turned off. */
10594 if (orig_code == LSHIFTRT && result_mode != shift_mode)
10595 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
10596 GET_MODE_MASK (result_mode) >> orig_count);
10597
10598 /* Do the remainder of the processing in RESULT_MODE. */
10599 x = gen_lowpart_or_truncate (result_mode, x);
10600
10601 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10602 operation. */
10603 if (complement_p)
10604 x = simplify_gen_unary (NOT, result_mode, x, result_mode);
10605
10606 if (outer_op != UNKNOWN)
10607 {
10608 if (GET_RTX_CLASS (outer_op) != RTX_UNARY
10609 && GET_MODE_PRECISION (result_mode) < HOST_BITS_PER_WIDE_INT)
10610 outer_const = trunc_int_for_mode (outer_const, result_mode);
10611
10612 if (outer_op == AND)
10613 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
10614 else if (outer_op == SET)
10615 {
10616 /* This means that we have determined that the result is
10617 equivalent to a constant. This should be rare. */
10618 if (!side_effects_p (x))
10619 x = GEN_INT (outer_const);
10620 }
10621 else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
10622 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
10623 else
10624 x = simplify_gen_binary (outer_op, result_mode, x,
10625 GEN_INT (outer_const));
10626 }
10627
10628 return x;
10629 }
10630
10631 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10632 The result of the shift is RESULT_MODE. If we cannot simplify it,
10633 return X or, if it is NULL, synthesize the expression with
10634 simplify_gen_binary. Otherwise, return a simplified value.
10635
10636 The shift is normally computed in the widest mode we find in VAROP, as
10637 long as it isn't a different number of words than RESULT_MODE. Exceptions
10638 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10639
10640 static rtx
simplify_shift_const(rtx x,enum rtx_code code,enum machine_mode result_mode,rtx varop,int count)10641 simplify_shift_const (rtx x, enum rtx_code code, enum machine_mode result_mode,
10642 rtx varop, int count)
10643 {
10644 rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
10645 if (tem)
10646 return tem;
10647
10648 if (!x)
10649 x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count));
10650 if (GET_MODE (x) != result_mode)
10651 x = gen_lowpart (result_mode, x);
10652 return x;
10653 }
10654
10655
10656 /* Like recog, but we receive the address of a pointer to a new pattern.
10657 We try to match the rtx that the pointer points to.
10658 If that fails, we may try to modify or replace the pattern,
10659 storing the replacement into the same pointer object.
10660
10661 Modifications include deletion or addition of CLOBBERs.
10662
10663 PNOTES is a pointer to a location where any REG_UNUSED notes added for
10664 the CLOBBERs are placed.
10665
10666 The value is the final insn code from the pattern ultimately matched,
10667 or -1. */
10668
10669 static int
recog_for_combine(rtx * pnewpat,rtx insn,rtx * pnotes)10670 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
10671 {
10672 rtx pat = *pnewpat;
10673 int insn_code_number;
10674 int num_clobbers_to_add = 0;
10675 int i;
10676 rtx notes = 0;
10677 rtx old_notes, old_pat;
10678
10679 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10680 we use to indicate that something didn't match. If we find such a
10681 thing, force rejection. */
10682 if (GET_CODE (pat) == PARALLEL)
10683 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
10684 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
10685 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
10686 return -1;
10687
10688 old_pat = PATTERN (insn);
10689 old_notes = REG_NOTES (insn);
10690 PATTERN (insn) = pat;
10691 REG_NOTES (insn) = 0;
10692
10693 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10694 if (dump_file && (dump_flags & TDF_DETAILS))
10695 {
10696 if (insn_code_number < 0)
10697 fputs ("Failed to match this instruction:\n", dump_file);
10698 else
10699 fputs ("Successfully matched this instruction:\n", dump_file);
10700 print_rtl_single (dump_file, pat);
10701 }
10702
10703 /* If it isn't, there is the possibility that we previously had an insn
10704 that clobbered some register as a side effect, but the combined
10705 insn doesn't need to do that. So try once more without the clobbers
10706 unless this represents an ASM insn. */
10707
10708 if (insn_code_number < 0 && ! check_asm_operands (pat)
10709 && GET_CODE (pat) == PARALLEL)
10710 {
10711 int pos;
10712
10713 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
10714 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
10715 {
10716 if (i != pos)
10717 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
10718 pos++;
10719 }
10720
10721 SUBST_INT (XVECLEN (pat, 0), pos);
10722
10723 if (pos == 1)
10724 pat = XVECEXP (pat, 0, 0);
10725
10726 PATTERN (insn) = pat;
10727 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10728 if (dump_file && (dump_flags & TDF_DETAILS))
10729 {
10730 if (insn_code_number < 0)
10731 fputs ("Failed to match this instruction:\n", dump_file);
10732 else
10733 fputs ("Successfully matched this instruction:\n", dump_file);
10734 print_rtl_single (dump_file, pat);
10735 }
10736 }
10737 PATTERN (insn) = old_pat;
10738 REG_NOTES (insn) = old_notes;
10739
10740 /* Recognize all noop sets, these will be killed by followup pass. */
10741 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
10742 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
10743
10744 /* If we had any clobbers to add, make a new pattern than contains
10745 them. Then check to make sure that all of them are dead. */
10746 if (num_clobbers_to_add)
10747 {
10748 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
10749 rtvec_alloc (GET_CODE (pat) == PARALLEL
10750 ? (XVECLEN (pat, 0)
10751 + num_clobbers_to_add)
10752 : num_clobbers_to_add + 1));
10753
10754 if (GET_CODE (pat) == PARALLEL)
10755 for (i = 0; i < XVECLEN (pat, 0); i++)
10756 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
10757 else
10758 XVECEXP (newpat, 0, 0) = pat;
10759
10760 add_clobbers (newpat, insn_code_number);
10761
10762 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
10763 i < XVECLEN (newpat, 0); i++)
10764 {
10765 if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
10766 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
10767 return -1;
10768 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) != SCRATCH)
10769 {
10770 gcc_assert (REG_P (XEXP (XVECEXP (newpat, 0, i), 0)));
10771 notes = alloc_reg_note (REG_UNUSED,
10772 XEXP (XVECEXP (newpat, 0, i), 0), notes);
10773 }
10774 }
10775 pat = newpat;
10776 }
10777
10778 *pnewpat = pat;
10779 *pnotes = notes;
10780
10781 return insn_code_number;
10782 }
10783
10784 /* Like gen_lowpart_general but for use by combine. In combine it
10785 is not possible to create any new pseudoregs. However, it is
10786 safe to create invalid memory addresses, because combine will
10787 try to recognize them and all they will do is make the combine
10788 attempt fail.
10789
10790 If for some reason this cannot do its job, an rtx
10791 (clobber (const_int 0)) is returned.
10792 An insn containing that will not be recognized. */
10793
10794 static rtx
gen_lowpart_for_combine(enum machine_mode omode,rtx x)10795 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
10796 {
10797 enum machine_mode imode = GET_MODE (x);
10798 unsigned int osize = GET_MODE_SIZE (omode);
10799 unsigned int isize = GET_MODE_SIZE (imode);
10800 rtx result;
10801
10802 if (omode == imode)
10803 return x;
10804
10805 /* We can only support MODE being wider than a word if X is a
10806 constant integer or has a mode the same size. */
10807 if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
10808 && ! ((imode == VOIDmode
10809 && (CONST_INT_P (x)
10810 || GET_CODE (x) == CONST_DOUBLE))
10811 || isize == osize))
10812 goto fail;
10813
10814 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10815 won't know what to do. So we will strip off the SUBREG here and
10816 process normally. */
10817 if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
10818 {
10819 x = SUBREG_REG (x);
10820
10821 /* For use in case we fall down into the address adjustments
10822 further below, we need to adjust the known mode and size of
10823 x; imode and isize, since we just adjusted x. */
10824 imode = GET_MODE (x);
10825
10826 if (imode == omode)
10827 return x;
10828
10829 isize = GET_MODE_SIZE (imode);
10830 }
10831
10832 result = gen_lowpart_common (omode, x);
10833
10834 if (result)
10835 return result;
10836
10837 if (MEM_P (x))
10838 {
10839 int offset = 0;
10840
10841 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10842 address. */
10843 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
10844 goto fail;
10845
10846 /* If we want to refer to something bigger than the original memref,
10847 generate a paradoxical subreg instead. That will force a reload
10848 of the original memref X. */
10849 if (isize < osize)
10850 return gen_rtx_SUBREG (omode, x, 0);
10851
10852 if (WORDS_BIG_ENDIAN)
10853 offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
10854
10855 /* Adjust the address so that the address-after-the-data is
10856 unchanged. */
10857 if (BYTES_BIG_ENDIAN)
10858 offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
10859
10860 return adjust_address_nv (x, omode, offset);
10861 }
10862
10863 /* If X is a comparison operator, rewrite it in a new mode. This
10864 probably won't match, but may allow further simplifications. */
10865 else if (COMPARISON_P (x))
10866 return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
10867
10868 /* If we couldn't simplify X any other way, just enclose it in a
10869 SUBREG. Normally, this SUBREG won't match, but some patterns may
10870 include an explicit SUBREG or we may simplify it further in combine. */
10871 else
10872 {
10873 int offset = 0;
10874 rtx res;
10875
10876 offset = subreg_lowpart_offset (omode, imode);
10877 if (imode == VOIDmode)
10878 {
10879 imode = int_mode_for_mode (omode);
10880 x = gen_lowpart_common (imode, x);
10881 if (x == NULL)
10882 goto fail;
10883 }
10884 res = simplify_gen_subreg (omode, x, imode, offset);
10885 if (res)
10886 return res;
10887 }
10888
10889 fail:
10890 return gen_rtx_CLOBBER (omode, const0_rtx);
10891 }
10892
10893 /* Try to simplify a comparison between OP0 and a constant OP1,
10894 where CODE is the comparison code that will be tested, into a
10895 (CODE OP0 const0_rtx) form.
10896
10897 The result is a possibly different comparison code to use.
10898 *POP1 may be updated. */
10899
10900 static enum rtx_code
simplify_compare_const(enum rtx_code code,rtx op0,rtx * pop1)10901 simplify_compare_const (enum rtx_code code, rtx op0, rtx *pop1)
10902 {
10903 enum machine_mode mode = GET_MODE (op0);
10904 unsigned int mode_width = GET_MODE_PRECISION (mode);
10905 HOST_WIDE_INT const_op = INTVAL (*pop1);
10906
10907 /* Get the constant we are comparing against and turn off all bits
10908 not on in our mode. */
10909 if (mode != VOIDmode)
10910 const_op = trunc_int_for_mode (const_op, mode);
10911
10912 /* If we are comparing against a constant power of two and the value
10913 being compared can only have that single bit nonzero (e.g., it was
10914 `and'ed with that bit), we can replace this with a comparison
10915 with zero. */
10916 if (const_op
10917 && (code == EQ || code == NE || code == GE || code == GEU
10918 || code == LT || code == LTU)
10919 && mode_width <= HOST_BITS_PER_WIDE_INT
10920 && exact_log2 (const_op) >= 0
10921 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
10922 {
10923 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10924 const_op = 0;
10925 }
10926
10927 /* Similarly, if we are comparing a value known to be either -1 or
10928 0 with -1, change it to the opposite comparison against zero. */
10929 if (const_op == -1
10930 && (code == EQ || code == NE || code == GT || code == LE
10931 || code == GEU || code == LTU)
10932 && num_sign_bit_copies (op0, mode) == mode_width)
10933 {
10934 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10935 const_op = 0;
10936 }
10937
10938 /* Do some canonicalizations based on the comparison code. We prefer
10939 comparisons against zero and then prefer equality comparisons.
10940 If we can reduce the size of a constant, we will do that too. */
10941 switch (code)
10942 {
10943 case LT:
10944 /* < C is equivalent to <= (C - 1) */
10945 if (const_op > 0)
10946 {
10947 const_op -= 1;
10948 code = LE;
10949 /* ... fall through to LE case below. */
10950 }
10951 else
10952 break;
10953
10954 case LE:
10955 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10956 if (const_op < 0)
10957 {
10958 const_op += 1;
10959 code = LT;
10960 }
10961
10962 /* If we are doing a <= 0 comparison on a value known to have
10963 a zero sign bit, we can replace this with == 0. */
10964 else if (const_op == 0
10965 && mode_width <= HOST_BITS_PER_WIDE_INT
10966 && (nonzero_bits (op0, mode)
10967 & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10968 == 0)
10969 code = EQ;
10970 break;
10971
10972 case GE:
10973 /* >= C is equivalent to > (C - 1). */
10974 if (const_op > 0)
10975 {
10976 const_op -= 1;
10977 code = GT;
10978 /* ... fall through to GT below. */
10979 }
10980 else
10981 break;
10982
10983 case GT:
10984 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10985 if (const_op < 0)
10986 {
10987 const_op += 1;
10988 code = GE;
10989 }
10990
10991 /* If we are doing a > 0 comparison on a value known to have
10992 a zero sign bit, we can replace this with != 0. */
10993 else if (const_op == 0
10994 && mode_width <= HOST_BITS_PER_WIDE_INT
10995 && (nonzero_bits (op0, mode)
10996 & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10997 == 0)
10998 code = NE;
10999 break;
11000
11001 case LTU:
11002 /* < C is equivalent to <= (C - 1). */
11003 if (const_op > 0)
11004 {
11005 const_op -= 1;
11006 code = LEU;
11007 /* ... fall through ... */
11008 }
11009 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11010 else if (mode_width <= HOST_BITS_PER_WIDE_INT
11011 && (unsigned HOST_WIDE_INT) const_op
11012 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1))
11013 {
11014 const_op = 0;
11015 code = GE;
11016 break;
11017 }
11018 else
11019 break;
11020
11021 case LEU:
11022 /* unsigned <= 0 is equivalent to == 0 */
11023 if (const_op == 0)
11024 code = EQ;
11025 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11026 else if (mode_width <= HOST_BITS_PER_WIDE_INT
11027 && (unsigned HOST_WIDE_INT) const_op
11028 == ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
11029 {
11030 const_op = 0;
11031 code = GE;
11032 }
11033 break;
11034
11035 case GEU:
11036 /* >= C is equivalent to > (C - 1). */
11037 if (const_op > 1)
11038 {
11039 const_op -= 1;
11040 code = GTU;
11041 /* ... fall through ... */
11042 }
11043
11044 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11045 else if (mode_width <= HOST_BITS_PER_WIDE_INT
11046 && (unsigned HOST_WIDE_INT) const_op
11047 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1))
11048 {
11049 const_op = 0;
11050 code = LT;
11051 break;
11052 }
11053 else
11054 break;
11055
11056 case GTU:
11057 /* unsigned > 0 is equivalent to != 0 */
11058 if (const_op == 0)
11059 code = NE;
11060 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11061 else if (mode_width <= HOST_BITS_PER_WIDE_INT
11062 && (unsigned HOST_WIDE_INT) const_op
11063 == ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
11064 {
11065 const_op = 0;
11066 code = LT;
11067 }
11068 break;
11069
11070 default:
11071 break;
11072 }
11073
11074 *pop1 = GEN_INT (const_op);
11075 return code;
11076 }
11077
11078 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11079 comparison code that will be tested.
11080
11081 The result is a possibly different comparison code to use. *POP0 and
11082 *POP1 may be updated.
11083
11084 It is possible that we might detect that a comparison is either always
11085 true or always false. However, we do not perform general constant
11086 folding in combine, so this knowledge isn't useful. Such tautologies
11087 should have been detected earlier. Hence we ignore all such cases. */
11088
11089 static enum rtx_code
simplify_comparison(enum rtx_code code,rtx * pop0,rtx * pop1)11090 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
11091 {
11092 rtx op0 = *pop0;
11093 rtx op1 = *pop1;
11094 rtx tem, tem1;
11095 int i;
11096 enum machine_mode mode, tmode;
11097
11098 /* Try a few ways of applying the same transformation to both operands. */
11099 while (1)
11100 {
11101 #ifndef WORD_REGISTER_OPERATIONS
11102 /* The test below this one won't handle SIGN_EXTENDs on these machines,
11103 so check specially. */
11104 if (code != GTU && code != GEU && code != LTU && code != LEU
11105 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
11106 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11107 && GET_CODE (XEXP (op1, 0)) == ASHIFT
11108 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
11109 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
11110 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
11111 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
11112 && CONST_INT_P (XEXP (op0, 1))
11113 && XEXP (op0, 1) == XEXP (op1, 1)
11114 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
11115 && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
11116 && (INTVAL (XEXP (op0, 1))
11117 == (GET_MODE_PRECISION (GET_MODE (op0))
11118 - (GET_MODE_PRECISION
11119 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
11120 {
11121 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
11122 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
11123 }
11124 #endif
11125
11126 /* If both operands are the same constant shift, see if we can ignore the
11127 shift. We can if the shift is a rotate or if the bits shifted out of
11128 this shift are known to be zero for both inputs and if the type of
11129 comparison is compatible with the shift. */
11130 if (GET_CODE (op0) == GET_CODE (op1)
11131 && HWI_COMPUTABLE_MODE_P (GET_MODE(op0))
11132 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
11133 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
11134 && (code != GT && code != LT && code != GE && code != LE))
11135 || (GET_CODE (op0) == ASHIFTRT
11136 && (code != GTU && code != LTU
11137 && code != GEU && code != LEU)))
11138 && CONST_INT_P (XEXP (op0, 1))
11139 && INTVAL (XEXP (op0, 1)) >= 0
11140 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11141 && XEXP (op0, 1) == XEXP (op1, 1))
11142 {
11143 enum machine_mode mode = GET_MODE (op0);
11144 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
11145 int shift_count = INTVAL (XEXP (op0, 1));
11146
11147 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
11148 mask &= (mask >> shift_count) << shift_count;
11149 else if (GET_CODE (op0) == ASHIFT)
11150 mask = (mask & (mask << shift_count)) >> shift_count;
11151
11152 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
11153 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
11154 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
11155 else
11156 break;
11157 }
11158
11159 /* If both operands are AND's of a paradoxical SUBREG by constant, the
11160 SUBREGs are of the same mode, and, in both cases, the AND would
11161 be redundant if the comparison was done in the narrower mode,
11162 do the comparison in the narrower mode (e.g., we are AND'ing with 1
11163 and the operand's possibly nonzero bits are 0xffffff01; in that case
11164 if we only care about QImode, we don't need the AND). This case
11165 occurs if the output mode of an scc insn is not SImode and
11166 STORE_FLAG_VALUE == 1 (e.g., the 386).
11167
11168 Similarly, check for a case where the AND's are ZERO_EXTEND
11169 operations from some narrower mode even though a SUBREG is not
11170 present. */
11171
11172 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
11173 && CONST_INT_P (XEXP (op0, 1))
11174 && CONST_INT_P (XEXP (op1, 1)))
11175 {
11176 rtx inner_op0 = XEXP (op0, 0);
11177 rtx inner_op1 = XEXP (op1, 0);
11178 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
11179 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
11180 int changed = 0;
11181
11182 if (paradoxical_subreg_p (inner_op0)
11183 && GET_CODE (inner_op1) == SUBREG
11184 && (GET_MODE (SUBREG_REG (inner_op0))
11185 == GET_MODE (SUBREG_REG (inner_op1)))
11186 && (GET_MODE_PRECISION (GET_MODE (SUBREG_REG (inner_op0)))
11187 <= HOST_BITS_PER_WIDE_INT)
11188 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
11189 GET_MODE (SUBREG_REG (inner_op0)))))
11190 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
11191 GET_MODE (SUBREG_REG (inner_op1))))))
11192 {
11193 op0 = SUBREG_REG (inner_op0);
11194 op1 = SUBREG_REG (inner_op1);
11195
11196 /* The resulting comparison is always unsigned since we masked
11197 off the original sign bit. */
11198 code = unsigned_condition (code);
11199
11200 changed = 1;
11201 }
11202
11203 else if (c0 == c1)
11204 for (tmode = GET_CLASS_NARROWEST_MODE
11205 (GET_MODE_CLASS (GET_MODE (op0)));
11206 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
11207 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
11208 {
11209 op0 = gen_lowpart (tmode, inner_op0);
11210 op1 = gen_lowpart (tmode, inner_op1);
11211 code = unsigned_condition (code);
11212 changed = 1;
11213 break;
11214 }
11215
11216 if (! changed)
11217 break;
11218 }
11219
11220 /* If both operands are NOT, we can strip off the outer operation
11221 and adjust the comparison code for swapped operands; similarly for
11222 NEG, except that this must be an equality comparison. */
11223 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
11224 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
11225 && (code == EQ || code == NE)))
11226 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
11227
11228 else
11229 break;
11230 }
11231
11232 /* If the first operand is a constant, swap the operands and adjust the
11233 comparison code appropriately, but don't do this if the second operand
11234 is already a constant integer. */
11235 if (swap_commutative_operands_p (op0, op1))
11236 {
11237 tem = op0, op0 = op1, op1 = tem;
11238 code = swap_condition (code);
11239 }
11240
11241 /* We now enter a loop during which we will try to simplify the comparison.
11242 For the most part, we only are concerned with comparisons with zero,
11243 but some things may really be comparisons with zero but not start
11244 out looking that way. */
11245
11246 while (CONST_INT_P (op1))
11247 {
11248 enum machine_mode mode = GET_MODE (op0);
11249 unsigned int mode_width = GET_MODE_PRECISION (mode);
11250 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
11251 int equality_comparison_p;
11252 int sign_bit_comparison_p;
11253 int unsigned_comparison_p;
11254 HOST_WIDE_INT const_op;
11255
11256 /* We only want to handle integral modes. This catches VOIDmode,
11257 CCmode, and the floating-point modes. An exception is that we
11258 can handle VOIDmode if OP0 is a COMPARE or a comparison
11259 operation. */
11260
11261 if (GET_MODE_CLASS (mode) != MODE_INT
11262 && ! (mode == VOIDmode
11263 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
11264 break;
11265
11266 /* Try to simplify the compare to constant, possibly changing the
11267 comparison op, and/or changing op1 to zero. */
11268 code = simplify_compare_const (code, op0, &op1);
11269 const_op = INTVAL (op1);
11270
11271 /* Compute some predicates to simplify code below. */
11272
11273 equality_comparison_p = (code == EQ || code == NE);
11274 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
11275 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
11276 || code == GEU);
11277
11278 /* If this is a sign bit comparison and we can do arithmetic in
11279 MODE, say that we will only be needing the sign bit of OP0. */
11280 if (sign_bit_comparison_p && HWI_COMPUTABLE_MODE_P (mode))
11281 op0 = force_to_mode (op0, mode,
11282 (unsigned HOST_WIDE_INT) 1
11283 << (GET_MODE_PRECISION (mode) - 1),
11284 0);
11285
11286 /* Now try cases based on the opcode of OP0. If none of the cases
11287 does a "continue", we exit this loop immediately after the
11288 switch. */
11289
11290 switch (GET_CODE (op0))
11291 {
11292 case ZERO_EXTRACT:
11293 /* If we are extracting a single bit from a variable position in
11294 a constant that has only a single bit set and are comparing it
11295 with zero, we can convert this into an equality comparison
11296 between the position and the location of the single bit. */
11297 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11298 have already reduced the shift count modulo the word size. */
11299 if (!SHIFT_COUNT_TRUNCATED
11300 && CONST_INT_P (XEXP (op0, 0))
11301 && XEXP (op0, 1) == const1_rtx
11302 && equality_comparison_p && const_op == 0
11303 && (i = exact_log2 (UINTVAL (XEXP (op0, 0)))) >= 0)
11304 {
11305 if (BITS_BIG_ENDIAN)
11306 {
11307 enum machine_mode new_mode
11308 = mode_for_extraction (EP_extzv, 1);
11309 if (new_mode == MAX_MACHINE_MODE)
11310 i = BITS_PER_WORD - 1 - i;
11311 else
11312 {
11313 mode = new_mode;
11314 i = (GET_MODE_PRECISION (mode) - 1 - i);
11315 }
11316 }
11317
11318 op0 = XEXP (op0, 2);
11319 op1 = GEN_INT (i);
11320 const_op = i;
11321
11322 /* Result is nonzero iff shift count is equal to I. */
11323 code = reverse_condition (code);
11324 continue;
11325 }
11326
11327 /* ... fall through ... */
11328
11329 case SIGN_EXTRACT:
11330 tem = expand_compound_operation (op0);
11331 if (tem != op0)
11332 {
11333 op0 = tem;
11334 continue;
11335 }
11336 break;
11337
11338 case NOT:
11339 /* If testing for equality, we can take the NOT of the constant. */
11340 if (equality_comparison_p
11341 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
11342 {
11343 op0 = XEXP (op0, 0);
11344 op1 = tem;
11345 continue;
11346 }
11347
11348 /* If just looking at the sign bit, reverse the sense of the
11349 comparison. */
11350 if (sign_bit_comparison_p)
11351 {
11352 op0 = XEXP (op0, 0);
11353 code = (code == GE ? LT : GE);
11354 continue;
11355 }
11356 break;
11357
11358 case NEG:
11359 /* If testing for equality, we can take the NEG of the constant. */
11360 if (equality_comparison_p
11361 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
11362 {
11363 op0 = XEXP (op0, 0);
11364 op1 = tem;
11365 continue;
11366 }
11367
11368 /* The remaining cases only apply to comparisons with zero. */
11369 if (const_op != 0)
11370 break;
11371
11372 /* When X is ABS or is known positive,
11373 (neg X) is < 0 if and only if X != 0. */
11374
11375 if (sign_bit_comparison_p
11376 && (GET_CODE (XEXP (op0, 0)) == ABS
11377 || (mode_width <= HOST_BITS_PER_WIDE_INT
11378 && (nonzero_bits (XEXP (op0, 0), mode)
11379 & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11380 == 0)))
11381 {
11382 op0 = XEXP (op0, 0);
11383 code = (code == LT ? NE : EQ);
11384 continue;
11385 }
11386
11387 /* If we have NEG of something whose two high-order bits are the
11388 same, we know that "(-a) < 0" is equivalent to "a > 0". */
11389 if (num_sign_bit_copies (op0, mode) >= 2)
11390 {
11391 op0 = XEXP (op0, 0);
11392 code = swap_condition (code);
11393 continue;
11394 }
11395 break;
11396
11397 case ROTATE:
11398 /* If we are testing equality and our count is a constant, we
11399 can perform the inverse operation on our RHS. */
11400 if (equality_comparison_p && CONST_INT_P (XEXP (op0, 1))
11401 && (tem = simplify_binary_operation (ROTATERT, mode,
11402 op1, XEXP (op0, 1))) != 0)
11403 {
11404 op0 = XEXP (op0, 0);
11405 op1 = tem;
11406 continue;
11407 }
11408
11409 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11410 a particular bit. Convert it to an AND of a constant of that
11411 bit. This will be converted into a ZERO_EXTRACT. */
11412 if (const_op == 0 && sign_bit_comparison_p
11413 && CONST_INT_P (XEXP (op0, 1))
11414 && mode_width <= HOST_BITS_PER_WIDE_INT)
11415 {
11416 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11417 ((unsigned HOST_WIDE_INT) 1
11418 << (mode_width - 1
11419 - INTVAL (XEXP (op0, 1)))));
11420 code = (code == LT ? NE : EQ);
11421 continue;
11422 }
11423
11424 /* Fall through. */
11425
11426 case ABS:
11427 /* ABS is ignorable inside an equality comparison with zero. */
11428 if (const_op == 0 && equality_comparison_p)
11429 {
11430 op0 = XEXP (op0, 0);
11431 continue;
11432 }
11433 break;
11434
11435 case SIGN_EXTEND:
11436 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11437 (compare FOO CONST) if CONST fits in FOO's mode and we
11438 are either testing inequality or have an unsigned
11439 comparison with ZERO_EXTEND or a signed comparison with
11440 SIGN_EXTEND. But don't do it if we don't have a compare
11441 insn of the given mode, since we'd have to revert it
11442 later on, and then we wouldn't know whether to sign- or
11443 zero-extend. */
11444 mode = GET_MODE (XEXP (op0, 0));
11445 if (GET_MODE_CLASS (mode) == MODE_INT
11446 && ! unsigned_comparison_p
11447 && HWI_COMPUTABLE_MODE_P (mode)
11448 && trunc_int_for_mode (const_op, mode) == const_op
11449 && have_insn_for (COMPARE, mode))
11450 {
11451 op0 = XEXP (op0, 0);
11452 continue;
11453 }
11454 break;
11455
11456 case SUBREG:
11457 /* Check for the case where we are comparing A - C1 with C2, that is
11458
11459 (subreg:MODE (plus (A) (-C1))) op (C2)
11460
11461 with C1 a constant, and try to lift the SUBREG, i.e. to do the
11462 comparison in the wider mode. One of the following two conditions
11463 must be true in order for this to be valid:
11464
11465 1. The mode extension results in the same bit pattern being added
11466 on both sides and the comparison is equality or unsigned. As
11467 C2 has been truncated to fit in MODE, the pattern can only be
11468 all 0s or all 1s.
11469
11470 2. The mode extension results in the sign bit being copied on
11471 each side.
11472
11473 The difficulty here is that we have predicates for A but not for
11474 (A - C1) so we need to check that C1 is within proper bounds so
11475 as to perturbate A as little as possible. */
11476
11477 if (mode_width <= HOST_BITS_PER_WIDE_INT
11478 && subreg_lowpart_p (op0)
11479 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0))) > mode_width
11480 && GET_CODE (SUBREG_REG (op0)) == PLUS
11481 && CONST_INT_P (XEXP (SUBREG_REG (op0), 1)))
11482 {
11483 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
11484 rtx a = XEXP (SUBREG_REG (op0), 0);
11485 HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
11486
11487 if ((c1 > 0
11488 && (unsigned HOST_WIDE_INT) c1
11489 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
11490 && (equality_comparison_p || unsigned_comparison_p)
11491 /* (A - C1) zero-extends if it is positive and sign-extends
11492 if it is negative, C2 both zero- and sign-extends. */
11493 && ((0 == (nonzero_bits (a, inner_mode)
11494 & ~GET_MODE_MASK (mode))
11495 && const_op >= 0)
11496 /* (A - C1) sign-extends if it is positive and 1-extends
11497 if it is negative, C2 both sign- and 1-extends. */
11498 || (num_sign_bit_copies (a, inner_mode)
11499 > (unsigned int) (GET_MODE_PRECISION (inner_mode)
11500 - mode_width)
11501 && const_op < 0)))
11502 || ((unsigned HOST_WIDE_INT) c1
11503 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
11504 /* (A - C1) always sign-extends, like C2. */
11505 && num_sign_bit_copies (a, inner_mode)
11506 > (unsigned int) (GET_MODE_PRECISION (inner_mode)
11507 - (mode_width - 1))))
11508 {
11509 op0 = SUBREG_REG (op0);
11510 continue;
11511 }
11512 }
11513
11514 /* If the inner mode is narrower and we are extracting the low part,
11515 we can treat the SUBREG as if it were a ZERO_EXTEND. */
11516 if (subreg_lowpart_p (op0)
11517 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0))) < mode_width)
11518 /* Fall through */ ;
11519 else
11520 break;
11521
11522 /* ... fall through ... */
11523
11524 case ZERO_EXTEND:
11525 mode = GET_MODE (XEXP (op0, 0));
11526 if (GET_MODE_CLASS (mode) == MODE_INT
11527 && (unsigned_comparison_p || equality_comparison_p)
11528 && HWI_COMPUTABLE_MODE_P (mode)
11529 && (unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (mode)
11530 && const_op >= 0
11531 && have_insn_for (COMPARE, mode))
11532 {
11533 op0 = XEXP (op0, 0);
11534 continue;
11535 }
11536 break;
11537
11538 case PLUS:
11539 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
11540 this for equality comparisons due to pathological cases involving
11541 overflows. */
11542 if (equality_comparison_p
11543 && 0 != (tem = simplify_binary_operation (MINUS, mode,
11544 op1, XEXP (op0, 1))))
11545 {
11546 op0 = XEXP (op0, 0);
11547 op1 = tem;
11548 continue;
11549 }
11550
11551 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
11552 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
11553 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
11554 {
11555 op0 = XEXP (XEXP (op0, 0), 0);
11556 code = (code == LT ? EQ : NE);
11557 continue;
11558 }
11559 break;
11560
11561 case MINUS:
11562 /* We used to optimize signed comparisons against zero, but that
11563 was incorrect. Unsigned comparisons against zero (GTU, LEU)
11564 arrive here as equality comparisons, or (GEU, LTU) are
11565 optimized away. No need to special-case them. */
11566
11567 /* (eq (minus A B) C) -> (eq A (plus B C)) or
11568 (eq B (minus A C)), whichever simplifies. We can only do
11569 this for equality comparisons due to pathological cases involving
11570 overflows. */
11571 if (equality_comparison_p
11572 && 0 != (tem = simplify_binary_operation (PLUS, mode,
11573 XEXP (op0, 1), op1)))
11574 {
11575 op0 = XEXP (op0, 0);
11576 op1 = tem;
11577 continue;
11578 }
11579
11580 if (equality_comparison_p
11581 && 0 != (tem = simplify_binary_operation (MINUS, mode,
11582 XEXP (op0, 0), op1)))
11583 {
11584 op0 = XEXP (op0, 1);
11585 op1 = tem;
11586 continue;
11587 }
11588
11589 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11590 of bits in X minus 1, is one iff X > 0. */
11591 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
11592 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11593 && UINTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
11594 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11595 {
11596 op0 = XEXP (op0, 1);
11597 code = (code == GE ? LE : GT);
11598 continue;
11599 }
11600 break;
11601
11602 case XOR:
11603 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
11604 if C is zero or B is a constant. */
11605 if (equality_comparison_p
11606 && 0 != (tem = simplify_binary_operation (XOR, mode,
11607 XEXP (op0, 1), op1)))
11608 {
11609 op0 = XEXP (op0, 0);
11610 op1 = tem;
11611 continue;
11612 }
11613 break;
11614
11615 case EQ: case NE:
11616 case UNEQ: case LTGT:
11617 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
11618 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
11619 case UNORDERED: case ORDERED:
11620 /* We can't do anything if OP0 is a condition code value, rather
11621 than an actual data value. */
11622 if (const_op != 0
11623 || CC0_P (XEXP (op0, 0))
11624 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
11625 break;
11626
11627 /* Get the two operands being compared. */
11628 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
11629 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
11630 else
11631 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
11632
11633 /* Check for the cases where we simply want the result of the
11634 earlier test or the opposite of that result. */
11635 if (code == NE || code == EQ
11636 || (val_signbit_known_set_p (GET_MODE (op0), STORE_FLAG_VALUE)
11637 && (code == LT || code == GE)))
11638 {
11639 enum rtx_code new_code;
11640 if (code == LT || code == NE)
11641 new_code = GET_CODE (op0);
11642 else
11643 new_code = reversed_comparison_code (op0, NULL);
11644
11645 if (new_code != UNKNOWN)
11646 {
11647 code = new_code;
11648 op0 = tem;
11649 op1 = tem1;
11650 continue;
11651 }
11652 }
11653 break;
11654
11655 case IOR:
11656 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11657 iff X <= 0. */
11658 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
11659 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
11660 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11661 {
11662 op0 = XEXP (op0, 1);
11663 code = (code == GE ? GT : LE);
11664 continue;
11665 }
11666 break;
11667
11668 case AND:
11669 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
11670 will be converted to a ZERO_EXTRACT later. */
11671 if (const_op == 0 && equality_comparison_p
11672 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11673 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
11674 {
11675 op0 = gen_rtx_LSHIFTRT (mode, XEXP (op0, 1),
11676 XEXP (XEXP (op0, 0), 1));
11677 op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1);
11678 continue;
11679 }
11680
11681 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11682 zero and X is a comparison and C1 and C2 describe only bits set
11683 in STORE_FLAG_VALUE, we can compare with X. */
11684 if (const_op == 0 && equality_comparison_p
11685 && mode_width <= HOST_BITS_PER_WIDE_INT
11686 && CONST_INT_P (XEXP (op0, 1))
11687 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
11688 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11689 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
11690 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
11691 {
11692 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11693 << INTVAL (XEXP (XEXP (op0, 0), 1)));
11694 if ((~STORE_FLAG_VALUE & mask) == 0
11695 && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
11696 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
11697 && COMPARISON_P (tem))))
11698 {
11699 op0 = XEXP (XEXP (op0, 0), 0);
11700 continue;
11701 }
11702 }
11703
11704 /* If we are doing an equality comparison of an AND of a bit equal
11705 to the sign bit, replace this with a LT or GE comparison of
11706 the underlying value. */
11707 if (equality_comparison_p
11708 && const_op == 0
11709 && CONST_INT_P (XEXP (op0, 1))
11710 && mode_width <= HOST_BITS_PER_WIDE_INT
11711 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11712 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11713 {
11714 op0 = XEXP (op0, 0);
11715 code = (code == EQ ? GE : LT);
11716 continue;
11717 }
11718
11719 /* If this AND operation is really a ZERO_EXTEND from a narrower
11720 mode, the constant fits within that mode, and this is either an
11721 equality or unsigned comparison, try to do this comparison in
11722 the narrower mode.
11723
11724 Note that in:
11725
11726 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
11727 -> (ne:DI (reg:SI 4) (const_int 0))
11728
11729 unless TRULY_NOOP_TRUNCATION allows it or the register is
11730 known to hold a value of the required mode the
11731 transformation is invalid. */
11732 if ((equality_comparison_p || unsigned_comparison_p)
11733 && CONST_INT_P (XEXP (op0, 1))
11734 && (i = exact_log2 ((UINTVAL (XEXP (op0, 1))
11735 & GET_MODE_MASK (mode))
11736 + 1)) >= 0
11737 && const_op >> i == 0
11738 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode
11739 && (TRULY_NOOP_TRUNCATION_MODES_P (tmode, GET_MODE (op0))
11740 || (REG_P (XEXP (op0, 0))
11741 && reg_truncated_to_mode (tmode, XEXP (op0, 0)))))
11742 {
11743 op0 = gen_lowpart (tmode, XEXP (op0, 0));
11744 continue;
11745 }
11746
11747 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11748 fits in both M1 and M2 and the SUBREG is either paradoxical
11749 or represents the low part, permute the SUBREG and the AND
11750 and try again. */
11751 if (GET_CODE (XEXP (op0, 0)) == SUBREG)
11752 {
11753 unsigned HOST_WIDE_INT c1;
11754 tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
11755 /* Require an integral mode, to avoid creating something like
11756 (AND:SF ...). */
11757 if (SCALAR_INT_MODE_P (tmode)
11758 /* It is unsafe to commute the AND into the SUBREG if the
11759 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11760 not defined. As originally written the upper bits
11761 have a defined value due to the AND operation.
11762 However, if we commute the AND inside the SUBREG then
11763 they no longer have defined values and the meaning of
11764 the code has been changed. */
11765 && (0
11766 #ifdef WORD_REGISTER_OPERATIONS
11767 || (mode_width > GET_MODE_PRECISION (tmode)
11768 && mode_width <= BITS_PER_WORD)
11769 #endif
11770 || (mode_width <= GET_MODE_PRECISION (tmode)
11771 && subreg_lowpart_p (XEXP (op0, 0))))
11772 && CONST_INT_P (XEXP (op0, 1))
11773 && mode_width <= HOST_BITS_PER_WIDE_INT
11774 && HWI_COMPUTABLE_MODE_P (tmode)
11775 && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
11776 && (c1 & ~GET_MODE_MASK (tmode)) == 0
11777 && c1 != mask
11778 && c1 != GET_MODE_MASK (tmode))
11779 {
11780 op0 = simplify_gen_binary (AND, tmode,
11781 SUBREG_REG (XEXP (op0, 0)),
11782 gen_int_mode (c1, tmode));
11783 op0 = gen_lowpart (mode, op0);
11784 continue;
11785 }
11786 }
11787
11788 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
11789 if (const_op == 0 && equality_comparison_p
11790 && XEXP (op0, 1) == const1_rtx
11791 && GET_CODE (XEXP (op0, 0)) == NOT)
11792 {
11793 op0 = simplify_and_const_int (NULL_RTX, mode,
11794 XEXP (XEXP (op0, 0), 0), 1);
11795 code = (code == NE ? EQ : NE);
11796 continue;
11797 }
11798
11799 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11800 (eq (and (lshiftrt X) 1) 0).
11801 Also handle the case where (not X) is expressed using xor. */
11802 if (const_op == 0 && equality_comparison_p
11803 && XEXP (op0, 1) == const1_rtx
11804 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
11805 {
11806 rtx shift_op = XEXP (XEXP (op0, 0), 0);
11807 rtx shift_count = XEXP (XEXP (op0, 0), 1);
11808
11809 if (GET_CODE (shift_op) == NOT
11810 || (GET_CODE (shift_op) == XOR
11811 && CONST_INT_P (XEXP (shift_op, 1))
11812 && CONST_INT_P (shift_count)
11813 && HWI_COMPUTABLE_MODE_P (mode)
11814 && (UINTVAL (XEXP (shift_op, 1))
11815 == (unsigned HOST_WIDE_INT) 1
11816 << INTVAL (shift_count))))
11817 {
11818 op0
11819 = gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count);
11820 op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1);
11821 code = (code == NE ? EQ : NE);
11822 continue;
11823 }
11824 }
11825 break;
11826
11827 case ASHIFT:
11828 /* If we have (compare (ashift FOO N) (const_int C)) and
11829 the high order N bits of FOO (N+1 if an inequality comparison)
11830 are known to be zero, we can do this by comparing FOO with C
11831 shifted right N bits so long as the low-order N bits of C are
11832 zero. */
11833 if (CONST_INT_P (XEXP (op0, 1))
11834 && INTVAL (XEXP (op0, 1)) >= 0
11835 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
11836 < HOST_BITS_PER_WIDE_INT)
11837 && (((unsigned HOST_WIDE_INT) const_op
11838 & (((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1)))
11839 - 1)) == 0)
11840 && mode_width <= HOST_BITS_PER_WIDE_INT
11841 && (nonzero_bits (XEXP (op0, 0), mode)
11842 & ~(mask >> (INTVAL (XEXP (op0, 1))
11843 + ! equality_comparison_p))) == 0)
11844 {
11845 /* We must perform a logical shift, not an arithmetic one,
11846 as we want the top N bits of C to be zero. */
11847 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
11848
11849 temp >>= INTVAL (XEXP (op0, 1));
11850 op1 = gen_int_mode (temp, mode);
11851 op0 = XEXP (op0, 0);
11852 continue;
11853 }
11854
11855 /* If we are doing a sign bit comparison, it means we are testing
11856 a particular bit. Convert it to the appropriate AND. */
11857 if (sign_bit_comparison_p && CONST_INT_P (XEXP (op0, 1))
11858 && mode_width <= HOST_BITS_PER_WIDE_INT)
11859 {
11860 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11861 ((unsigned HOST_WIDE_INT) 1
11862 << (mode_width - 1
11863 - INTVAL (XEXP (op0, 1)))));
11864 code = (code == LT ? NE : EQ);
11865 continue;
11866 }
11867
11868 /* If this an equality comparison with zero and we are shifting
11869 the low bit to the sign bit, we can convert this to an AND of the
11870 low-order bit. */
11871 if (const_op == 0 && equality_comparison_p
11872 && CONST_INT_P (XEXP (op0, 1))
11873 && UINTVAL (XEXP (op0, 1)) == mode_width - 1)
11874 {
11875 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), 1);
11876 continue;
11877 }
11878 break;
11879
11880 case ASHIFTRT:
11881 /* If this is an equality comparison with zero, we can do this
11882 as a logical shift, which might be much simpler. */
11883 if (equality_comparison_p && const_op == 0
11884 && CONST_INT_P (XEXP (op0, 1)))
11885 {
11886 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
11887 XEXP (op0, 0),
11888 INTVAL (XEXP (op0, 1)));
11889 continue;
11890 }
11891
11892 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11893 do the comparison in a narrower mode. */
11894 if (! unsigned_comparison_p
11895 && CONST_INT_P (XEXP (op0, 1))
11896 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11897 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
11898 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11899 MODE_INT, 1)) != BLKmode
11900 && (((unsigned HOST_WIDE_INT) const_op
11901 + (GET_MODE_MASK (tmode) >> 1) + 1)
11902 <= GET_MODE_MASK (tmode)))
11903 {
11904 op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
11905 continue;
11906 }
11907
11908 /* Likewise if OP0 is a PLUS of a sign extension with a
11909 constant, which is usually represented with the PLUS
11910 between the shifts. */
11911 if (! unsigned_comparison_p
11912 && CONST_INT_P (XEXP (op0, 1))
11913 && GET_CODE (XEXP (op0, 0)) == PLUS
11914 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11915 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
11916 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
11917 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11918 MODE_INT, 1)) != BLKmode
11919 && (((unsigned HOST_WIDE_INT) const_op
11920 + (GET_MODE_MASK (tmode) >> 1) + 1)
11921 <= GET_MODE_MASK (tmode)))
11922 {
11923 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
11924 rtx add_const = XEXP (XEXP (op0, 0), 1);
11925 rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
11926 add_const, XEXP (op0, 1));
11927
11928 op0 = simplify_gen_binary (PLUS, tmode,
11929 gen_lowpart (tmode, inner),
11930 new_const);
11931 continue;
11932 }
11933
11934 /* ... fall through ... */
11935 case LSHIFTRT:
11936 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11937 the low order N bits of FOO are known to be zero, we can do this
11938 by comparing FOO with C shifted left N bits so long as no
11939 overflow occurs. Even if the low order N bits of FOO aren't known
11940 to be zero, if the comparison is >= or < we can use the same
11941 optimization and for > or <= by setting all the low
11942 order N bits in the comparison constant. */
11943 if (CONST_INT_P (XEXP (op0, 1))
11944 && INTVAL (XEXP (op0, 1)) > 0
11945 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11946 && mode_width <= HOST_BITS_PER_WIDE_INT
11947 && (((unsigned HOST_WIDE_INT) const_op
11948 + (GET_CODE (op0) != LSHIFTRT
11949 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
11950 + 1)
11951 : 0))
11952 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
11953 {
11954 unsigned HOST_WIDE_INT low_bits
11955 = (nonzero_bits (XEXP (op0, 0), mode)
11956 & (((unsigned HOST_WIDE_INT) 1
11957 << INTVAL (XEXP (op0, 1))) - 1));
11958 if (low_bits == 0 || !equality_comparison_p)
11959 {
11960 /* If the shift was logical, then we must make the condition
11961 unsigned. */
11962 if (GET_CODE (op0) == LSHIFTRT)
11963 code = unsigned_condition (code);
11964
11965 const_op <<= INTVAL (XEXP (op0, 1));
11966 if (low_bits != 0
11967 && (code == GT || code == GTU
11968 || code == LE || code == LEU))
11969 const_op
11970 |= (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1);
11971 op1 = GEN_INT (const_op);
11972 op0 = XEXP (op0, 0);
11973 continue;
11974 }
11975 }
11976
11977 /* If we are using this shift to extract just the sign bit, we
11978 can replace this with an LT or GE comparison. */
11979 if (const_op == 0
11980 && (equality_comparison_p || sign_bit_comparison_p)
11981 && CONST_INT_P (XEXP (op0, 1))
11982 && UINTVAL (XEXP (op0, 1)) == mode_width - 1)
11983 {
11984 op0 = XEXP (op0, 0);
11985 code = (code == NE || code == GT ? LT : GE);
11986 continue;
11987 }
11988 break;
11989
11990 default:
11991 break;
11992 }
11993
11994 break;
11995 }
11996
11997 /* Now make any compound operations involved in this comparison. Then,
11998 check for an outmost SUBREG on OP0 that is not doing anything or is
11999 paradoxical. The latter transformation must only be performed when
12000 it is known that the "extra" bits will be the same in op0 and op1 or
12001 that they don't matter. There are three cases to consider:
12002
12003 1. SUBREG_REG (op0) is a register. In this case the bits are don't
12004 care bits and we can assume they have any convenient value. So
12005 making the transformation is safe.
12006
12007 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
12008 In this case the upper bits of op0 are undefined. We should not make
12009 the simplification in that case as we do not know the contents of
12010 those bits.
12011
12012 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
12013 UNKNOWN. In that case we know those bits are zeros or ones. We must
12014 also be sure that they are the same as the upper bits of op1.
12015
12016 We can never remove a SUBREG for a non-equality comparison because
12017 the sign bit is in a different place in the underlying object. */
12018
12019 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
12020 op1 = make_compound_operation (op1, SET);
12021
12022 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
12023 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
12024 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
12025 && (code == NE || code == EQ))
12026 {
12027 if (paradoxical_subreg_p (op0))
12028 {
12029 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
12030 implemented. */
12031 if (REG_P (SUBREG_REG (op0)))
12032 {
12033 op0 = SUBREG_REG (op0);
12034 op1 = gen_lowpart (GET_MODE (op0), op1);
12035 }
12036 }
12037 else if ((GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0)))
12038 <= HOST_BITS_PER_WIDE_INT)
12039 && (nonzero_bits (SUBREG_REG (op0),
12040 GET_MODE (SUBREG_REG (op0)))
12041 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
12042 {
12043 tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
12044
12045 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
12046 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
12047 op0 = SUBREG_REG (op0), op1 = tem;
12048 }
12049 }
12050
12051 /* We now do the opposite procedure: Some machines don't have compare
12052 insns in all modes. If OP0's mode is an integer mode smaller than a
12053 word and we can't do a compare in that mode, see if there is a larger
12054 mode for which we can do the compare. There are a number of cases in
12055 which we can use the wider mode. */
12056
12057 mode = GET_MODE (op0);
12058 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
12059 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
12060 && ! have_insn_for (COMPARE, mode))
12061 for (tmode = GET_MODE_WIDER_MODE (mode);
12062 (tmode != VOIDmode && HWI_COMPUTABLE_MODE_P (tmode));
12063 tmode = GET_MODE_WIDER_MODE (tmode))
12064 if (have_insn_for (COMPARE, tmode))
12065 {
12066 int zero_extended;
12067
12068 /* If this is a test for negative, we can make an explicit
12069 test of the sign bit. Test this first so we can use
12070 a paradoxical subreg to extend OP0. */
12071
12072 if (op1 == const0_rtx && (code == LT || code == GE)
12073 && HWI_COMPUTABLE_MODE_P (mode))
12074 {
12075 op0 = simplify_gen_binary (AND, tmode,
12076 gen_lowpart (tmode, op0),
12077 GEN_INT ((unsigned HOST_WIDE_INT) 1
12078 << (GET_MODE_BITSIZE (mode)
12079 - 1)));
12080 code = (code == LT) ? NE : EQ;
12081 break;
12082 }
12083
12084 /* If the only nonzero bits in OP0 and OP1 are those in the
12085 narrower mode and this is an equality or unsigned comparison,
12086 we can use the wider mode. Similarly for sign-extended
12087 values, in which case it is true for all comparisons. */
12088 zero_extended = ((code == EQ || code == NE
12089 || code == GEU || code == GTU
12090 || code == LEU || code == LTU)
12091 && (nonzero_bits (op0, tmode)
12092 & ~GET_MODE_MASK (mode)) == 0
12093 && ((CONST_INT_P (op1)
12094 || (nonzero_bits (op1, tmode)
12095 & ~GET_MODE_MASK (mode)) == 0)));
12096
12097 if (zero_extended
12098 || ((num_sign_bit_copies (op0, tmode)
12099 > (unsigned int) (GET_MODE_PRECISION (tmode)
12100 - GET_MODE_PRECISION (mode)))
12101 && (num_sign_bit_copies (op1, tmode)
12102 > (unsigned int) (GET_MODE_PRECISION (tmode)
12103 - GET_MODE_PRECISION (mode)))))
12104 {
12105 /* If OP0 is an AND and we don't have an AND in MODE either,
12106 make a new AND in the proper mode. */
12107 if (GET_CODE (op0) == AND
12108 && !have_insn_for (AND, mode))
12109 op0 = simplify_gen_binary (AND, tmode,
12110 gen_lowpart (tmode,
12111 XEXP (op0, 0)),
12112 gen_lowpart (tmode,
12113 XEXP (op0, 1)));
12114 else
12115 {
12116 if (zero_extended)
12117 {
12118 op0 = simplify_gen_unary (ZERO_EXTEND, tmode, op0, mode);
12119 op1 = simplify_gen_unary (ZERO_EXTEND, tmode, op1, mode);
12120 }
12121 else
12122 {
12123 op0 = simplify_gen_unary (SIGN_EXTEND, tmode, op0, mode);
12124 op1 = simplify_gen_unary (SIGN_EXTEND, tmode, op1, mode);
12125 }
12126 break;
12127 }
12128 }
12129 }
12130
12131 #ifdef CANONICALIZE_COMPARISON
12132 /* If this machine only supports a subset of valid comparisons, see if we
12133 can convert an unsupported one into a supported one. */
12134 CANONICALIZE_COMPARISON (code, op0, op1);
12135 #endif
12136
12137 *pop0 = op0;
12138 *pop1 = op1;
12139
12140 return code;
12141 }
12142
12143 /* Utility function for record_value_for_reg. Count number of
12144 rtxs in X. */
12145 static int
count_rtxs(rtx x)12146 count_rtxs (rtx x)
12147 {
12148 enum rtx_code code = GET_CODE (x);
12149 const char *fmt;
12150 int i, j, ret = 1;
12151
12152 if (GET_RTX_CLASS (code) == '2'
12153 || GET_RTX_CLASS (code) == 'c')
12154 {
12155 rtx x0 = XEXP (x, 0);
12156 rtx x1 = XEXP (x, 1);
12157
12158 if (x0 == x1)
12159 return 1 + 2 * count_rtxs (x0);
12160
12161 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
12162 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
12163 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12164 return 2 + 2 * count_rtxs (x0)
12165 + count_rtxs (x == XEXP (x1, 0)
12166 ? XEXP (x1, 1) : XEXP (x1, 0));
12167
12168 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
12169 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
12170 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12171 return 2 + 2 * count_rtxs (x1)
12172 + count_rtxs (x == XEXP (x0, 0)
12173 ? XEXP (x0, 1) : XEXP (x0, 0));
12174 }
12175
12176 fmt = GET_RTX_FORMAT (code);
12177 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12178 if (fmt[i] == 'e')
12179 ret += count_rtxs (XEXP (x, i));
12180 else if (fmt[i] == 'E')
12181 for (j = 0; j < XVECLEN (x, i); j++)
12182 ret += count_rtxs (XVECEXP (x, i, j));
12183
12184 return ret;
12185 }
12186
12187 /* Utility function for following routine. Called when X is part of a value
12188 being stored into last_set_value. Sets last_set_table_tick
12189 for each register mentioned. Similar to mention_regs in cse.c */
12190
12191 static void
update_table_tick(rtx x)12192 update_table_tick (rtx x)
12193 {
12194 enum rtx_code code = GET_CODE (x);
12195 const char *fmt = GET_RTX_FORMAT (code);
12196 int i, j;
12197
12198 if (code == REG)
12199 {
12200 unsigned int regno = REGNO (x);
12201 unsigned int endregno = END_REGNO (x);
12202 unsigned int r;
12203
12204 for (r = regno; r < endregno; r++)
12205 {
12206 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, r);
12207 rsp->last_set_table_tick = label_tick;
12208 }
12209
12210 return;
12211 }
12212
12213 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12214 if (fmt[i] == 'e')
12215 {
12216 /* Check for identical subexpressions. If x contains
12217 identical subexpression we only have to traverse one of
12218 them. */
12219 if (i == 0 && ARITHMETIC_P (x))
12220 {
12221 /* Note that at this point x1 has already been
12222 processed. */
12223 rtx x0 = XEXP (x, 0);
12224 rtx x1 = XEXP (x, 1);
12225
12226 /* If x0 and x1 are identical then there is no need to
12227 process x0. */
12228 if (x0 == x1)
12229 break;
12230
12231 /* If x0 is identical to a subexpression of x1 then while
12232 processing x1, x0 has already been processed. Thus we
12233 are done with x. */
12234 if (ARITHMETIC_P (x1)
12235 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12236 break;
12237
12238 /* If x1 is identical to a subexpression of x0 then we
12239 still have to process the rest of x0. */
12240 if (ARITHMETIC_P (x0)
12241 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12242 {
12243 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
12244 break;
12245 }
12246 }
12247
12248 update_table_tick (XEXP (x, i));
12249 }
12250 else if (fmt[i] == 'E')
12251 for (j = 0; j < XVECLEN (x, i); j++)
12252 update_table_tick (XVECEXP (x, i, j));
12253 }
12254
12255 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12256 are saying that the register is clobbered and we no longer know its
12257 value. If INSN is zero, don't update reg_stat[].last_set; this is
12258 only permitted with VALUE also zero and is used to invalidate the
12259 register. */
12260
12261 static void
record_value_for_reg(rtx reg,rtx insn,rtx value)12262 record_value_for_reg (rtx reg, rtx insn, rtx value)
12263 {
12264 unsigned int regno = REGNO (reg);
12265 unsigned int endregno = END_REGNO (reg);
12266 unsigned int i;
12267 reg_stat_type *rsp;
12268
12269 /* If VALUE contains REG and we have a previous value for REG, substitute
12270 the previous value. */
12271 if (value && insn && reg_overlap_mentioned_p (reg, value))
12272 {
12273 rtx tem;
12274
12275 /* Set things up so get_last_value is allowed to see anything set up to
12276 our insn. */
12277 subst_low_luid = DF_INSN_LUID (insn);
12278 tem = get_last_value (reg);
12279
12280 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12281 it isn't going to be useful and will take a lot of time to process,
12282 so just use the CLOBBER. */
12283
12284 if (tem)
12285 {
12286 if (ARITHMETIC_P (tem)
12287 && GET_CODE (XEXP (tem, 0)) == CLOBBER
12288 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
12289 tem = XEXP (tem, 0);
12290 else if (count_occurrences (value, reg, 1) >= 2)
12291 {
12292 /* If there are two or more occurrences of REG in VALUE,
12293 prevent the value from growing too much. */
12294 if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
12295 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
12296 }
12297
12298 value = replace_rtx (copy_rtx (value), reg, tem);
12299 }
12300 }
12301
12302 /* For each register modified, show we don't know its value, that
12303 we don't know about its bitwise content, that its value has been
12304 updated, and that we don't know the location of the death of the
12305 register. */
12306 for (i = regno; i < endregno; i++)
12307 {
12308 rsp = VEC_index (reg_stat_type, reg_stat, i);
12309
12310 if (insn)
12311 rsp->last_set = insn;
12312
12313 rsp->last_set_value = 0;
12314 rsp->last_set_mode = VOIDmode;
12315 rsp->last_set_nonzero_bits = 0;
12316 rsp->last_set_sign_bit_copies = 0;
12317 rsp->last_death = 0;
12318 rsp->truncated_to_mode = VOIDmode;
12319 }
12320
12321 /* Mark registers that are being referenced in this value. */
12322 if (value)
12323 update_table_tick (value);
12324
12325 /* Now update the status of each register being set.
12326 If someone is using this register in this block, set this register
12327 to invalid since we will get confused between the two lives in this
12328 basic block. This makes using this register always invalid. In cse, we
12329 scan the table to invalidate all entries using this register, but this
12330 is too much work for us. */
12331
12332 for (i = regno; i < endregno; i++)
12333 {
12334 rsp = VEC_index (reg_stat_type, reg_stat, i);
12335 rsp->last_set_label = label_tick;
12336 if (!insn
12337 || (value && rsp->last_set_table_tick >= label_tick_ebb_start))
12338 rsp->last_set_invalid = 1;
12339 else
12340 rsp->last_set_invalid = 0;
12341 }
12342
12343 /* The value being assigned might refer to X (like in "x++;"). In that
12344 case, we must replace it with (clobber (const_int 0)) to prevent
12345 infinite loops. */
12346 rsp = VEC_index (reg_stat_type, reg_stat, regno);
12347 if (value && !get_last_value_validate (&value, insn, label_tick, 0))
12348 {
12349 value = copy_rtx (value);
12350 if (!get_last_value_validate (&value, insn, label_tick, 1))
12351 value = 0;
12352 }
12353
12354 /* For the main register being modified, update the value, the mode, the
12355 nonzero bits, and the number of sign bit copies. */
12356
12357 rsp->last_set_value = value;
12358
12359 if (value)
12360 {
12361 enum machine_mode mode = GET_MODE (reg);
12362 subst_low_luid = DF_INSN_LUID (insn);
12363 rsp->last_set_mode = mode;
12364 if (GET_MODE_CLASS (mode) == MODE_INT
12365 && HWI_COMPUTABLE_MODE_P (mode))
12366 mode = nonzero_bits_mode;
12367 rsp->last_set_nonzero_bits = nonzero_bits (value, mode);
12368 rsp->last_set_sign_bit_copies
12369 = num_sign_bit_copies (value, GET_MODE (reg));
12370 }
12371 }
12372
12373 /* Called via note_stores from record_dead_and_set_regs to handle one
12374 SET or CLOBBER in an insn. DATA is the instruction in which the
12375 set is occurring. */
12376
12377 static void
record_dead_and_set_regs_1(rtx dest,const_rtx setter,void * data)12378 record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data)
12379 {
12380 rtx record_dead_insn = (rtx) data;
12381
12382 if (GET_CODE (dest) == SUBREG)
12383 dest = SUBREG_REG (dest);
12384
12385 if (!record_dead_insn)
12386 {
12387 if (REG_P (dest))
12388 record_value_for_reg (dest, NULL_RTX, NULL_RTX);
12389 return;
12390 }
12391
12392 if (REG_P (dest))
12393 {
12394 /* If we are setting the whole register, we know its value. Otherwise
12395 show that we don't know the value. We can handle SUBREG in
12396 some cases. */
12397 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
12398 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
12399 else if (GET_CODE (setter) == SET
12400 && GET_CODE (SET_DEST (setter)) == SUBREG
12401 && SUBREG_REG (SET_DEST (setter)) == dest
12402 && GET_MODE_PRECISION (GET_MODE (dest)) <= BITS_PER_WORD
12403 && subreg_lowpart_p (SET_DEST (setter)))
12404 record_value_for_reg (dest, record_dead_insn,
12405 gen_lowpart (GET_MODE (dest),
12406 SET_SRC (setter)));
12407 else
12408 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
12409 }
12410 else if (MEM_P (dest)
12411 /* Ignore pushes, they clobber nothing. */
12412 && ! push_operand (dest, GET_MODE (dest)))
12413 mem_last_set = DF_INSN_LUID (record_dead_insn);
12414 }
12415
12416 /* Update the records of when each REG was most recently set or killed
12417 for the things done by INSN. This is the last thing done in processing
12418 INSN in the combiner loop.
12419
12420 We update reg_stat[], in particular fields last_set, last_set_value,
12421 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12422 last_death, and also the similar information mem_last_set (which insn
12423 most recently modified memory) and last_call_luid (which insn was the
12424 most recent subroutine call). */
12425
12426 static void
record_dead_and_set_regs(rtx insn)12427 record_dead_and_set_regs (rtx insn)
12428 {
12429 rtx link;
12430 unsigned int i;
12431
12432 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
12433 {
12434 if (REG_NOTE_KIND (link) == REG_DEAD
12435 && REG_P (XEXP (link, 0)))
12436 {
12437 unsigned int regno = REGNO (XEXP (link, 0));
12438 unsigned int endregno = END_REGNO (XEXP (link, 0));
12439
12440 for (i = regno; i < endregno; i++)
12441 {
12442 reg_stat_type *rsp;
12443
12444 rsp = VEC_index (reg_stat_type, reg_stat, i);
12445 rsp->last_death = insn;
12446 }
12447 }
12448 else if (REG_NOTE_KIND (link) == REG_INC)
12449 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
12450 }
12451
12452 if (CALL_P (insn))
12453 {
12454 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
12455 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
12456 {
12457 reg_stat_type *rsp;
12458
12459 rsp = VEC_index (reg_stat_type, reg_stat, i);
12460 rsp->last_set_invalid = 1;
12461 rsp->last_set = insn;
12462 rsp->last_set_value = 0;
12463 rsp->last_set_mode = VOIDmode;
12464 rsp->last_set_nonzero_bits = 0;
12465 rsp->last_set_sign_bit_copies = 0;
12466 rsp->last_death = 0;
12467 rsp->truncated_to_mode = VOIDmode;
12468 }
12469
12470 last_call_luid = mem_last_set = DF_INSN_LUID (insn);
12471
12472 /* We can't combine into a call pattern. Remember, though, that
12473 the return value register is set at this LUID. We could
12474 still replace a register with the return value from the
12475 wrong subroutine call! */
12476 note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX);
12477 }
12478 else
12479 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
12480 }
12481
12482 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12483 register present in the SUBREG, so for each such SUBREG go back and
12484 adjust nonzero and sign bit information of the registers that are
12485 known to have some zero/sign bits set.
12486
12487 This is needed because when combine blows the SUBREGs away, the
12488 information on zero/sign bits is lost and further combines can be
12489 missed because of that. */
12490
12491 static void
record_promoted_value(rtx insn,rtx subreg)12492 record_promoted_value (rtx insn, rtx subreg)
12493 {
12494 struct insn_link *links;
12495 rtx set;
12496 unsigned int regno = REGNO (SUBREG_REG (subreg));
12497 enum machine_mode mode = GET_MODE (subreg);
12498
12499 if (GET_MODE_PRECISION (mode) > HOST_BITS_PER_WIDE_INT)
12500 return;
12501
12502 for (links = LOG_LINKS (insn); links;)
12503 {
12504 reg_stat_type *rsp;
12505
12506 insn = links->insn;
12507 set = single_set (insn);
12508
12509 if (! set || !REG_P (SET_DEST (set))
12510 || REGNO (SET_DEST (set)) != regno
12511 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
12512 {
12513 links = links->next;
12514 continue;
12515 }
12516
12517 rsp = VEC_index (reg_stat_type, reg_stat, regno);
12518 if (rsp->last_set == insn)
12519 {
12520 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
12521 rsp->last_set_nonzero_bits &= GET_MODE_MASK (mode);
12522 }
12523
12524 if (REG_P (SET_SRC (set)))
12525 {
12526 regno = REGNO (SET_SRC (set));
12527 links = LOG_LINKS (insn);
12528 }
12529 else
12530 break;
12531 }
12532 }
12533
12534 /* Check if X, a register, is known to contain a value already
12535 truncated to MODE. In this case we can use a subreg to refer to
12536 the truncated value even though in the generic case we would need
12537 an explicit truncation. */
12538
12539 static bool
reg_truncated_to_mode(enum machine_mode mode,const_rtx x)12540 reg_truncated_to_mode (enum machine_mode mode, const_rtx x)
12541 {
12542 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
12543 enum machine_mode truncated = rsp->truncated_to_mode;
12544
12545 if (truncated == 0
12546 || rsp->truncation_label < label_tick_ebb_start)
12547 return false;
12548 if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode))
12549 return true;
12550 if (TRULY_NOOP_TRUNCATION_MODES_P (mode, truncated))
12551 return true;
12552 return false;
12553 }
12554
12555 /* Callback for for_each_rtx. If *P is a hard reg or a subreg record the mode
12556 that the register is accessed in. For non-TRULY_NOOP_TRUNCATION targets we
12557 might be able to turn a truncate into a subreg using this information.
12558 Return -1 if traversing *P is complete or 0 otherwise. */
12559
12560 static int
record_truncated_value(rtx * p,void * data ATTRIBUTE_UNUSED)12561 record_truncated_value (rtx *p, void *data ATTRIBUTE_UNUSED)
12562 {
12563 rtx x = *p;
12564 enum machine_mode truncated_mode;
12565 reg_stat_type *rsp;
12566
12567 if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
12568 {
12569 enum machine_mode original_mode = GET_MODE (SUBREG_REG (x));
12570 truncated_mode = GET_MODE (x);
12571
12572 if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode))
12573 return -1;
12574
12575 if (TRULY_NOOP_TRUNCATION_MODES_P (truncated_mode, original_mode))
12576 return -1;
12577
12578 x = SUBREG_REG (x);
12579 }
12580 /* ??? For hard-regs we now record everything. We might be able to
12581 optimize this using last_set_mode. */
12582 else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
12583 truncated_mode = GET_MODE (x);
12584 else
12585 return 0;
12586
12587 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
12588 if (rsp->truncated_to_mode == 0
12589 || rsp->truncation_label < label_tick_ebb_start
12590 || (GET_MODE_SIZE (truncated_mode)
12591 < GET_MODE_SIZE (rsp->truncated_to_mode)))
12592 {
12593 rsp->truncated_to_mode = truncated_mode;
12594 rsp->truncation_label = label_tick;
12595 }
12596
12597 return -1;
12598 }
12599
12600 /* Callback for note_uses. Find hardregs and subregs of pseudos and
12601 the modes they are used in. This can help truning TRUNCATEs into
12602 SUBREGs. */
12603
12604 static void
record_truncated_values(rtx * x,void * data ATTRIBUTE_UNUSED)12605 record_truncated_values (rtx *x, void *data ATTRIBUTE_UNUSED)
12606 {
12607 for_each_rtx (x, record_truncated_value, NULL);
12608 }
12609
12610 /* Scan X for promoted SUBREGs. For each one found,
12611 note what it implies to the registers used in it. */
12612
12613 static void
check_promoted_subreg(rtx insn,rtx x)12614 check_promoted_subreg (rtx insn, rtx x)
12615 {
12616 if (GET_CODE (x) == SUBREG
12617 && SUBREG_PROMOTED_VAR_P (x)
12618 && REG_P (SUBREG_REG (x)))
12619 record_promoted_value (insn, x);
12620 else
12621 {
12622 const char *format = GET_RTX_FORMAT (GET_CODE (x));
12623 int i, j;
12624
12625 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
12626 switch (format[i])
12627 {
12628 case 'e':
12629 check_promoted_subreg (insn, XEXP (x, i));
12630 break;
12631 case 'V':
12632 case 'E':
12633 if (XVEC (x, i) != 0)
12634 for (j = 0; j < XVECLEN (x, i); j++)
12635 check_promoted_subreg (insn, XVECEXP (x, i, j));
12636 break;
12637 }
12638 }
12639 }
12640
12641 /* Verify that all the registers and memory references mentioned in *LOC are
12642 still valid. *LOC was part of a value set in INSN when label_tick was
12643 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
12644 the invalid references with (clobber (const_int 0)) and return 1. This
12645 replacement is useful because we often can get useful information about
12646 the form of a value (e.g., if it was produced by a shift that always
12647 produces -1 or 0) even though we don't know exactly what registers it
12648 was produced from. */
12649
12650 static int
get_last_value_validate(rtx * loc,rtx insn,int tick,int replace)12651 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
12652 {
12653 rtx x = *loc;
12654 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
12655 int len = GET_RTX_LENGTH (GET_CODE (x));
12656 int i, j;
12657
12658 if (REG_P (x))
12659 {
12660 unsigned int regno = REGNO (x);
12661 unsigned int endregno = END_REGNO (x);
12662 unsigned int j;
12663
12664 for (j = regno; j < endregno; j++)
12665 {
12666 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, j);
12667 if (rsp->last_set_invalid
12668 /* If this is a pseudo-register that was only set once and not
12669 live at the beginning of the function, it is always valid. */
12670 || (! (regno >= FIRST_PSEUDO_REGISTER
12671 && REG_N_SETS (regno) == 1
12672 && (!REGNO_REG_SET_P
12673 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno)))
12674 && rsp->last_set_label > tick))
12675 {
12676 if (replace)
12677 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12678 return replace;
12679 }
12680 }
12681
12682 return 1;
12683 }
12684 /* If this is a memory reference, make sure that there were no stores after
12685 it that might have clobbered the value. We don't have alias info, so we
12686 assume any store invalidates it. Moreover, we only have local UIDs, so
12687 we also assume that there were stores in the intervening basic blocks. */
12688 else if (MEM_P (x) && !MEM_READONLY_P (x)
12689 && (tick != label_tick || DF_INSN_LUID (insn) <= mem_last_set))
12690 {
12691 if (replace)
12692 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12693 return replace;
12694 }
12695
12696 for (i = 0; i < len; i++)
12697 {
12698 if (fmt[i] == 'e')
12699 {
12700 /* Check for identical subexpressions. If x contains
12701 identical subexpression we only have to traverse one of
12702 them. */
12703 if (i == 1 && ARITHMETIC_P (x))
12704 {
12705 /* Note that at this point x0 has already been checked
12706 and found valid. */
12707 rtx x0 = XEXP (x, 0);
12708 rtx x1 = XEXP (x, 1);
12709
12710 /* If x0 and x1 are identical then x is also valid. */
12711 if (x0 == x1)
12712 return 1;
12713
12714 /* If x1 is identical to a subexpression of x0 then
12715 while checking x0, x1 has already been checked. Thus
12716 it is valid and so as x. */
12717 if (ARITHMETIC_P (x0)
12718 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12719 return 1;
12720
12721 /* If x0 is identical to a subexpression of x1 then x is
12722 valid iff the rest of x1 is valid. */
12723 if (ARITHMETIC_P (x1)
12724 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12725 return
12726 get_last_value_validate (&XEXP (x1,
12727 x0 == XEXP (x1, 0) ? 1 : 0),
12728 insn, tick, replace);
12729 }
12730
12731 if (get_last_value_validate (&XEXP (x, i), insn, tick,
12732 replace) == 0)
12733 return 0;
12734 }
12735 else if (fmt[i] == 'E')
12736 for (j = 0; j < XVECLEN (x, i); j++)
12737 if (get_last_value_validate (&XVECEXP (x, i, j),
12738 insn, tick, replace) == 0)
12739 return 0;
12740 }
12741
12742 /* If we haven't found a reason for it to be invalid, it is valid. */
12743 return 1;
12744 }
12745
12746 /* Get the last value assigned to X, if known. Some registers
12747 in the value may be replaced with (clobber (const_int 0)) if their value
12748 is known longer known reliably. */
12749
12750 static rtx
get_last_value(const_rtx x)12751 get_last_value (const_rtx x)
12752 {
12753 unsigned int regno;
12754 rtx value;
12755 reg_stat_type *rsp;
12756
12757 /* If this is a non-paradoxical SUBREG, get the value of its operand and
12758 then convert it to the desired mode. If this is a paradoxical SUBREG,
12759 we cannot predict what values the "extra" bits might have. */
12760 if (GET_CODE (x) == SUBREG
12761 && subreg_lowpart_p (x)
12762 && !paradoxical_subreg_p (x)
12763 && (value = get_last_value (SUBREG_REG (x))) != 0)
12764 return gen_lowpart (GET_MODE (x), value);
12765
12766 if (!REG_P (x))
12767 return 0;
12768
12769 regno = REGNO (x);
12770 rsp = VEC_index (reg_stat_type, reg_stat, regno);
12771 value = rsp->last_set_value;
12772
12773 /* If we don't have a value, or if it isn't for this basic block and
12774 it's either a hard register, set more than once, or it's a live
12775 at the beginning of the function, return 0.
12776
12777 Because if it's not live at the beginning of the function then the reg
12778 is always set before being used (is never used without being set).
12779 And, if it's set only once, and it's always set before use, then all
12780 uses must have the same last value, even if it's not from this basic
12781 block. */
12782
12783 if (value == 0
12784 || (rsp->last_set_label < label_tick_ebb_start
12785 && (regno < FIRST_PSEUDO_REGISTER
12786 || REG_N_SETS (regno) != 1
12787 || REGNO_REG_SET_P
12788 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno))))
12789 return 0;
12790
12791 /* If the value was set in a later insn than the ones we are processing,
12792 we can't use it even if the register was only set once. */
12793 if (rsp->last_set_label == label_tick
12794 && DF_INSN_LUID (rsp->last_set) >= subst_low_luid)
12795 return 0;
12796
12797 /* If the value has all its registers valid, return it. */
12798 if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 0))
12799 return value;
12800
12801 /* Otherwise, make a copy and replace any invalid register with
12802 (clobber (const_int 0)). If that fails for some reason, return 0. */
12803
12804 value = copy_rtx (value);
12805 if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 1))
12806 return value;
12807
12808 return 0;
12809 }
12810
12811 /* Return nonzero if expression X refers to a REG or to memory
12812 that is set in an instruction more recent than FROM_LUID. */
12813
12814 static int
use_crosses_set_p(const_rtx x,int from_luid)12815 use_crosses_set_p (const_rtx x, int from_luid)
12816 {
12817 const char *fmt;
12818 int i;
12819 enum rtx_code code = GET_CODE (x);
12820
12821 if (code == REG)
12822 {
12823 unsigned int regno = REGNO (x);
12824 unsigned endreg = END_REGNO (x);
12825
12826 #ifdef PUSH_ROUNDING
12827 /* Don't allow uses of the stack pointer to be moved,
12828 because we don't know whether the move crosses a push insn. */
12829 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
12830 return 1;
12831 #endif
12832 for (; regno < endreg; regno++)
12833 {
12834 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
12835 if (rsp->last_set
12836 && rsp->last_set_label == label_tick
12837 && DF_INSN_LUID (rsp->last_set) > from_luid)
12838 return 1;
12839 }
12840 return 0;
12841 }
12842
12843 if (code == MEM && mem_last_set > from_luid)
12844 return 1;
12845
12846 fmt = GET_RTX_FORMAT (code);
12847
12848 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12849 {
12850 if (fmt[i] == 'E')
12851 {
12852 int j;
12853 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12854 if (use_crosses_set_p (XVECEXP (x, i, j), from_luid))
12855 return 1;
12856 }
12857 else if (fmt[i] == 'e'
12858 && use_crosses_set_p (XEXP (x, i), from_luid))
12859 return 1;
12860 }
12861 return 0;
12862 }
12863
12864 /* Define three variables used for communication between the following
12865 routines. */
12866
12867 static unsigned int reg_dead_regno, reg_dead_endregno;
12868 static int reg_dead_flag;
12869
12870 /* Function called via note_stores from reg_dead_at_p.
12871
12872 If DEST is within [reg_dead_regno, reg_dead_endregno), set
12873 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
12874
12875 static void
reg_dead_at_p_1(rtx dest,const_rtx x,void * data ATTRIBUTE_UNUSED)12876 reg_dead_at_p_1 (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
12877 {
12878 unsigned int regno, endregno;
12879
12880 if (!REG_P (dest))
12881 return;
12882
12883 regno = REGNO (dest);
12884 endregno = END_REGNO (dest);
12885 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
12886 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
12887 }
12888
12889 /* Return nonzero if REG is known to be dead at INSN.
12890
12891 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
12892 referencing REG, it is dead. If we hit a SET referencing REG, it is
12893 live. Otherwise, see if it is live or dead at the start of the basic
12894 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
12895 must be assumed to be always live. */
12896
12897 static int
reg_dead_at_p(rtx reg,rtx insn)12898 reg_dead_at_p (rtx reg, rtx insn)
12899 {
12900 basic_block block;
12901 unsigned int i;
12902
12903 /* Set variables for reg_dead_at_p_1. */
12904 reg_dead_regno = REGNO (reg);
12905 reg_dead_endregno = END_REGNO (reg);
12906
12907 reg_dead_flag = 0;
12908
12909 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
12910 we allow the machine description to decide whether use-and-clobber
12911 patterns are OK. */
12912 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
12913 {
12914 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12915 if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
12916 return 0;
12917 }
12918
12919 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
12920 beginning of basic block. */
12921 block = BLOCK_FOR_INSN (insn);
12922 for (;;)
12923 {
12924 if (INSN_P (insn))
12925 {
12926 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
12927 if (reg_dead_flag)
12928 return reg_dead_flag == 1 ? 1 : 0;
12929
12930 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
12931 return 1;
12932 }
12933
12934 if (insn == BB_HEAD (block))
12935 break;
12936
12937 insn = PREV_INSN (insn);
12938 }
12939
12940 /* Look at live-in sets for the basic block that we were in. */
12941 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12942 if (REGNO_REG_SET_P (df_get_live_in (block), i))
12943 return 0;
12944
12945 return 1;
12946 }
12947
12948 /* Note hard registers in X that are used. */
12949
12950 static void
mark_used_regs_combine(rtx x)12951 mark_used_regs_combine (rtx x)
12952 {
12953 RTX_CODE code = GET_CODE (x);
12954 unsigned int regno;
12955 int i;
12956
12957 switch (code)
12958 {
12959 case LABEL_REF:
12960 case SYMBOL_REF:
12961 case CONST_INT:
12962 case CONST:
12963 case CONST_DOUBLE:
12964 case CONST_VECTOR:
12965 case PC:
12966 case ADDR_VEC:
12967 case ADDR_DIFF_VEC:
12968 case ASM_INPUT:
12969 #ifdef HAVE_cc0
12970 /* CC0 must die in the insn after it is set, so we don't need to take
12971 special note of it here. */
12972 case CC0:
12973 #endif
12974 return;
12975
12976 case CLOBBER:
12977 /* If we are clobbering a MEM, mark any hard registers inside the
12978 address as used. */
12979 if (MEM_P (XEXP (x, 0)))
12980 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
12981 return;
12982
12983 case REG:
12984 regno = REGNO (x);
12985 /* A hard reg in a wide mode may really be multiple registers.
12986 If so, mark all of them just like the first. */
12987 if (regno < FIRST_PSEUDO_REGISTER)
12988 {
12989 /* None of this applies to the stack, frame or arg pointers. */
12990 if (regno == STACK_POINTER_REGNUM
12991 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
12992 || regno == HARD_FRAME_POINTER_REGNUM
12993 #endif
12994 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12995 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
12996 #endif
12997 || regno == FRAME_POINTER_REGNUM)
12998 return;
12999
13000 add_to_hard_reg_set (&newpat_used_regs, GET_MODE (x), regno);
13001 }
13002 return;
13003
13004 case SET:
13005 {
13006 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
13007 the address. */
13008 rtx testreg = SET_DEST (x);
13009
13010 while (GET_CODE (testreg) == SUBREG
13011 || GET_CODE (testreg) == ZERO_EXTRACT
13012 || GET_CODE (testreg) == STRICT_LOW_PART)
13013 testreg = XEXP (testreg, 0);
13014
13015 if (MEM_P (testreg))
13016 mark_used_regs_combine (XEXP (testreg, 0));
13017
13018 mark_used_regs_combine (SET_SRC (x));
13019 }
13020 return;
13021
13022 default:
13023 break;
13024 }
13025
13026 /* Recursively scan the operands of this expression. */
13027
13028 {
13029 const char *fmt = GET_RTX_FORMAT (code);
13030
13031 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
13032 {
13033 if (fmt[i] == 'e')
13034 mark_used_regs_combine (XEXP (x, i));
13035 else if (fmt[i] == 'E')
13036 {
13037 int j;
13038
13039 for (j = 0; j < XVECLEN (x, i); j++)
13040 mark_used_regs_combine (XVECEXP (x, i, j));
13041 }
13042 }
13043 }
13044 }
13045
13046 /* Remove register number REGNO from the dead registers list of INSN.
13047
13048 Return the note used to record the death, if there was one. */
13049
13050 rtx
remove_death(unsigned int regno,rtx insn)13051 remove_death (unsigned int regno, rtx insn)
13052 {
13053 rtx note = find_regno_note (insn, REG_DEAD, regno);
13054
13055 if (note)
13056 remove_note (insn, note);
13057
13058 return note;
13059 }
13060
13061 /* For each register (hardware or pseudo) used within expression X, if its
13062 death is in an instruction with luid between FROM_LUID (inclusive) and
13063 TO_INSN (exclusive), put a REG_DEAD note for that register in the
13064 list headed by PNOTES.
13065
13066 That said, don't move registers killed by maybe_kill_insn.
13067
13068 This is done when X is being merged by combination into TO_INSN. These
13069 notes will then be distributed as needed. */
13070
13071 static void
move_deaths(rtx x,rtx maybe_kill_insn,int from_luid,rtx to_insn,rtx * pnotes)13072 move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx to_insn,
13073 rtx *pnotes)
13074 {
13075 const char *fmt;
13076 int len, i;
13077 enum rtx_code code = GET_CODE (x);
13078
13079 if (code == REG)
13080 {
13081 unsigned int regno = REGNO (x);
13082 rtx where_dead = VEC_index (reg_stat_type, reg_stat, regno)->last_death;
13083
13084 /* Don't move the register if it gets killed in between from and to. */
13085 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
13086 && ! reg_referenced_p (x, maybe_kill_insn))
13087 return;
13088
13089 if (where_dead
13090 && BLOCK_FOR_INSN (where_dead) == BLOCK_FOR_INSN (to_insn)
13091 && DF_INSN_LUID (where_dead) >= from_luid
13092 && DF_INSN_LUID (where_dead) < DF_INSN_LUID (to_insn))
13093 {
13094 rtx note = remove_death (regno, where_dead);
13095
13096 /* It is possible for the call above to return 0. This can occur
13097 when last_death points to I2 or I1 that we combined with.
13098 In that case make a new note.
13099
13100 We must also check for the case where X is a hard register
13101 and NOTE is a death note for a range of hard registers
13102 including X. In that case, we must put REG_DEAD notes for
13103 the remaining registers in place of NOTE. */
13104
13105 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
13106 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
13107 > GET_MODE_SIZE (GET_MODE (x))))
13108 {
13109 unsigned int deadregno = REGNO (XEXP (note, 0));
13110 unsigned int deadend = END_HARD_REGNO (XEXP (note, 0));
13111 unsigned int ourend = END_HARD_REGNO (x);
13112 unsigned int i;
13113
13114 for (i = deadregno; i < deadend; i++)
13115 if (i < regno || i >= ourend)
13116 add_reg_note (where_dead, REG_DEAD, regno_reg_rtx[i]);
13117 }
13118
13119 /* If we didn't find any note, or if we found a REG_DEAD note that
13120 covers only part of the given reg, and we have a multi-reg hard
13121 register, then to be safe we must check for REG_DEAD notes
13122 for each register other than the first. They could have
13123 their own REG_DEAD notes lying around. */
13124 else if ((note == 0
13125 || (note != 0
13126 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
13127 < GET_MODE_SIZE (GET_MODE (x)))))
13128 && regno < FIRST_PSEUDO_REGISTER
13129 && hard_regno_nregs[regno][GET_MODE (x)] > 1)
13130 {
13131 unsigned int ourend = END_HARD_REGNO (x);
13132 unsigned int i, offset;
13133 rtx oldnotes = 0;
13134
13135 if (note)
13136 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
13137 else
13138 offset = 1;
13139
13140 for (i = regno + offset; i < ourend; i++)
13141 move_deaths (regno_reg_rtx[i],
13142 maybe_kill_insn, from_luid, to_insn, &oldnotes);
13143 }
13144
13145 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
13146 {
13147 XEXP (note, 1) = *pnotes;
13148 *pnotes = note;
13149 }
13150 else
13151 *pnotes = alloc_reg_note (REG_DEAD, x, *pnotes);
13152 }
13153
13154 return;
13155 }
13156
13157 else if (GET_CODE (x) == SET)
13158 {
13159 rtx dest = SET_DEST (x);
13160
13161 move_deaths (SET_SRC (x), maybe_kill_insn, from_luid, to_insn, pnotes);
13162
13163 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13164 that accesses one word of a multi-word item, some
13165 piece of everything register in the expression is used by
13166 this insn, so remove any old death. */
13167 /* ??? So why do we test for equality of the sizes? */
13168
13169 if (GET_CODE (dest) == ZERO_EXTRACT
13170 || GET_CODE (dest) == STRICT_LOW_PART
13171 || (GET_CODE (dest) == SUBREG
13172 && (((GET_MODE_SIZE (GET_MODE (dest))
13173 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
13174 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
13175 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
13176 {
13177 move_deaths (dest, maybe_kill_insn, from_luid, to_insn, pnotes);
13178 return;
13179 }
13180
13181 /* If this is some other SUBREG, we know it replaces the entire
13182 value, so use that as the destination. */
13183 if (GET_CODE (dest) == SUBREG)
13184 dest = SUBREG_REG (dest);
13185
13186 /* If this is a MEM, adjust deaths of anything used in the address.
13187 For a REG (the only other possibility), the entire value is
13188 being replaced so the old value is not used in this insn. */
13189
13190 if (MEM_P (dest))
13191 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_luid,
13192 to_insn, pnotes);
13193 return;
13194 }
13195
13196 else if (GET_CODE (x) == CLOBBER)
13197 return;
13198
13199 len = GET_RTX_LENGTH (code);
13200 fmt = GET_RTX_FORMAT (code);
13201
13202 for (i = 0; i < len; i++)
13203 {
13204 if (fmt[i] == 'E')
13205 {
13206 int j;
13207 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
13208 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_luid,
13209 to_insn, pnotes);
13210 }
13211 else if (fmt[i] == 'e')
13212 move_deaths (XEXP (x, i), maybe_kill_insn, from_luid, to_insn, pnotes);
13213 }
13214 }
13215
13216 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13217 pattern of an insn. X must be a REG. */
13218
13219 static int
reg_bitfield_target_p(rtx x,rtx body)13220 reg_bitfield_target_p (rtx x, rtx body)
13221 {
13222 int i;
13223
13224 if (GET_CODE (body) == SET)
13225 {
13226 rtx dest = SET_DEST (body);
13227 rtx target;
13228 unsigned int regno, tregno, endregno, endtregno;
13229
13230 if (GET_CODE (dest) == ZERO_EXTRACT)
13231 target = XEXP (dest, 0);
13232 else if (GET_CODE (dest) == STRICT_LOW_PART)
13233 target = SUBREG_REG (XEXP (dest, 0));
13234 else
13235 return 0;
13236
13237 if (GET_CODE (target) == SUBREG)
13238 target = SUBREG_REG (target);
13239
13240 if (!REG_P (target))
13241 return 0;
13242
13243 tregno = REGNO (target), regno = REGNO (x);
13244 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
13245 return target == x;
13246
13247 endtregno = end_hard_regno (GET_MODE (target), tregno);
13248 endregno = end_hard_regno (GET_MODE (x), regno);
13249
13250 return endregno > tregno && regno < endtregno;
13251 }
13252
13253 else if (GET_CODE (body) == PARALLEL)
13254 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
13255 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
13256 return 1;
13257
13258 return 0;
13259 }
13260
13261 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13262 as appropriate. I3 and I2 are the insns resulting from the combination
13263 insns including FROM (I2 may be zero).
13264
13265 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13266 not need REG_DEAD notes because they are being substituted for. This
13267 saves searching in the most common cases.
13268
13269 Each note in the list is either ignored or placed on some insns, depending
13270 on the type of note. */
13271
13272 static void
distribute_notes(rtx notes,rtx from_insn,rtx i3,rtx i2,rtx elim_i2,rtx elim_i1,rtx elim_i0)13273 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2,
13274 rtx elim_i1, rtx elim_i0)
13275 {
13276 rtx note, next_note;
13277 rtx tem;
13278
13279 for (note = notes; note; note = next_note)
13280 {
13281 rtx place = 0, place2 = 0;
13282
13283 next_note = XEXP (note, 1);
13284 switch (REG_NOTE_KIND (note))
13285 {
13286 case REG_BR_PROB:
13287 case REG_BR_PRED:
13288 /* Doesn't matter much where we put this, as long as it's somewhere.
13289 It is preferable to keep these notes on branches, which is most
13290 likely to be i3. */
13291 place = i3;
13292 break;
13293
13294 case REG_NON_LOCAL_GOTO:
13295 if (JUMP_P (i3))
13296 place = i3;
13297 else
13298 {
13299 gcc_assert (i2 && JUMP_P (i2));
13300 place = i2;
13301 }
13302 break;
13303
13304 case REG_EH_REGION:
13305 /* These notes must remain with the call or trapping instruction. */
13306 if (CALL_P (i3))
13307 place = i3;
13308 else if (i2 && CALL_P (i2))
13309 place = i2;
13310 else
13311 {
13312 gcc_assert (cfun->can_throw_non_call_exceptions);
13313 if (may_trap_p (i3))
13314 place = i3;
13315 else if (i2 && may_trap_p (i2))
13316 place = i2;
13317 /* ??? Otherwise assume we've combined things such that we
13318 can now prove that the instructions can't trap. Drop the
13319 note in this case. */
13320 }
13321 break;
13322
13323 case REG_ARGS_SIZE:
13324 /* ??? How to distribute between i3-i1. Assume i3 contains the
13325 entire adjustment. Assert i3 contains at least some adjust. */
13326 if (!noop_move_p (i3))
13327 {
13328 int old_size, args_size = INTVAL (XEXP (note, 0));
13329 /* fixup_args_size_notes looks at REG_NORETURN note,
13330 so ensure the note is placed there first. */
13331 if (CALL_P (i3))
13332 {
13333 rtx *np;
13334 for (np = &next_note; *np; np = &XEXP (*np, 1))
13335 if (REG_NOTE_KIND (*np) == REG_NORETURN)
13336 {
13337 rtx n = *np;
13338 *np = XEXP (n, 1);
13339 XEXP (n, 1) = REG_NOTES (i3);
13340 REG_NOTES (i3) = n;
13341 break;
13342 }
13343 }
13344 old_size = fixup_args_size_notes (PREV_INSN (i3), i3, args_size);
13345 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
13346 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
13347 gcc_assert (old_size != args_size
13348 || (CALL_P (i3)
13349 && !ACCUMULATE_OUTGOING_ARGS
13350 && find_reg_note (i3, REG_NORETURN, NULL_RTX)));
13351 }
13352 break;
13353
13354 case REG_NORETURN:
13355 case REG_SETJMP:
13356 case REG_TM:
13357 /* These notes must remain with the call. It should not be
13358 possible for both I2 and I3 to be a call. */
13359 if (CALL_P (i3))
13360 place = i3;
13361 else
13362 {
13363 gcc_assert (i2 && CALL_P (i2));
13364 place = i2;
13365 }
13366 break;
13367
13368 case REG_UNUSED:
13369 /* Any clobbers for i3 may still exist, and so we must process
13370 REG_UNUSED notes from that insn.
13371
13372 Any clobbers from i2 or i1 can only exist if they were added by
13373 recog_for_combine. In that case, recog_for_combine created the
13374 necessary REG_UNUSED notes. Trying to keep any original
13375 REG_UNUSED notes from these insns can cause incorrect output
13376 if it is for the same register as the original i3 dest.
13377 In that case, we will notice that the register is set in i3,
13378 and then add a REG_UNUSED note for the destination of i3, which
13379 is wrong. However, it is possible to have REG_UNUSED notes from
13380 i2 or i1 for register which were both used and clobbered, so
13381 we keep notes from i2 or i1 if they will turn into REG_DEAD
13382 notes. */
13383
13384 /* If this register is set or clobbered in I3, put the note there
13385 unless there is one already. */
13386 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
13387 {
13388 if (from_insn != i3)
13389 break;
13390
13391 if (! (REG_P (XEXP (note, 0))
13392 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
13393 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
13394 place = i3;
13395 }
13396 /* Otherwise, if this register is used by I3, then this register
13397 now dies here, so we must put a REG_DEAD note here unless there
13398 is one already. */
13399 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
13400 && ! (REG_P (XEXP (note, 0))
13401 ? find_regno_note (i3, REG_DEAD,
13402 REGNO (XEXP (note, 0)))
13403 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
13404 {
13405 PUT_REG_NOTE_KIND (note, REG_DEAD);
13406 place = i3;
13407 }
13408 break;
13409
13410 case REG_EQUAL:
13411 case REG_EQUIV:
13412 case REG_NOALIAS:
13413 /* These notes say something about results of an insn. We can
13414 only support them if they used to be on I3 in which case they
13415 remain on I3. Otherwise they are ignored.
13416
13417 If the note refers to an expression that is not a constant, we
13418 must also ignore the note since we cannot tell whether the
13419 equivalence is still true. It might be possible to do
13420 slightly better than this (we only have a problem if I2DEST
13421 or I1DEST is present in the expression), but it doesn't
13422 seem worth the trouble. */
13423
13424 if (from_insn == i3
13425 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
13426 place = i3;
13427 break;
13428
13429 case REG_INC:
13430 /* These notes say something about how a register is used. They must
13431 be present on any use of the register in I2 or I3. */
13432 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
13433 place = i3;
13434
13435 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
13436 {
13437 if (place)
13438 place2 = i2;
13439 else
13440 place = i2;
13441 }
13442 break;
13443
13444 case REG_LABEL_TARGET:
13445 case REG_LABEL_OPERAND:
13446 /* This can show up in several ways -- either directly in the
13447 pattern, or hidden off in the constant pool with (or without?)
13448 a REG_EQUAL note. */
13449 /* ??? Ignore the without-reg_equal-note problem for now. */
13450 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
13451 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
13452 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
13453 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
13454 place = i3;
13455
13456 if (i2
13457 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
13458 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
13459 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
13460 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
13461 {
13462 if (place)
13463 place2 = i2;
13464 else
13465 place = i2;
13466 }
13467
13468 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13469 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13470 there. */
13471 if (place && JUMP_P (place)
13472 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
13473 && (JUMP_LABEL (place) == NULL
13474 || JUMP_LABEL (place) == XEXP (note, 0)))
13475 {
13476 rtx label = JUMP_LABEL (place);
13477
13478 if (!label)
13479 JUMP_LABEL (place) = XEXP (note, 0);
13480 else if (LABEL_P (label))
13481 LABEL_NUSES (label)--;
13482 }
13483
13484 if (place2 && JUMP_P (place2)
13485 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
13486 && (JUMP_LABEL (place2) == NULL
13487 || JUMP_LABEL (place2) == XEXP (note, 0)))
13488 {
13489 rtx label = JUMP_LABEL (place2);
13490
13491 if (!label)
13492 JUMP_LABEL (place2) = XEXP (note, 0);
13493 else if (LABEL_P (label))
13494 LABEL_NUSES (label)--;
13495 place2 = 0;
13496 }
13497 break;
13498
13499 case REG_NONNEG:
13500 /* This note says something about the value of a register prior
13501 to the execution of an insn. It is too much trouble to see
13502 if the note is still correct in all situations. It is better
13503 to simply delete it. */
13504 break;
13505
13506 case REG_DEAD:
13507 /* If we replaced the right hand side of FROM_INSN with a
13508 REG_EQUAL note, the original use of the dying register
13509 will not have been combined into I3 and I2. In such cases,
13510 FROM_INSN is guaranteed to be the first of the combined
13511 instructions, so we simply need to search back before
13512 FROM_INSN for the previous use or set of this register,
13513 then alter the notes there appropriately.
13514
13515 If the register is used as an input in I3, it dies there.
13516 Similarly for I2, if it is nonzero and adjacent to I3.
13517
13518 If the register is not used as an input in either I3 or I2
13519 and it is not one of the registers we were supposed to eliminate,
13520 there are two possibilities. We might have a non-adjacent I2
13521 or we might have somehow eliminated an additional register
13522 from a computation. For example, we might have had A & B where
13523 we discover that B will always be zero. In this case we will
13524 eliminate the reference to A.
13525
13526 In both cases, we must search to see if we can find a previous
13527 use of A and put the death note there. */
13528
13529 if (from_insn
13530 && from_insn == i2mod
13531 && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs))
13532 tem = from_insn;
13533 else
13534 {
13535 if (from_insn
13536 && CALL_P (from_insn)
13537 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
13538 place = from_insn;
13539 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
13540 place = i3;
13541 else if (i2 != 0 && next_nonnote_nondebug_insn (i2) == i3
13542 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
13543 place = i2;
13544 else if ((rtx_equal_p (XEXP (note, 0), elim_i2)
13545 && !(i2mod
13546 && reg_overlap_mentioned_p (XEXP (note, 0),
13547 i2mod_old_rhs)))
13548 || rtx_equal_p (XEXP (note, 0), elim_i1)
13549 || rtx_equal_p (XEXP (note, 0), elim_i0))
13550 break;
13551 tem = i3;
13552 }
13553
13554 if (place == 0)
13555 {
13556 basic_block bb = this_basic_block;
13557
13558 for (tem = PREV_INSN (tem); place == 0; tem = PREV_INSN (tem))
13559 {
13560 if (!NONDEBUG_INSN_P (tem))
13561 {
13562 if (tem == BB_HEAD (bb))
13563 break;
13564 continue;
13565 }
13566
13567 /* If the register is being set at TEM, see if that is all
13568 TEM is doing. If so, delete TEM. Otherwise, make this
13569 into a REG_UNUSED note instead. Don't delete sets to
13570 global register vars. */
13571 if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
13572 || !global_regs[REGNO (XEXP (note, 0))])
13573 && reg_set_p (XEXP (note, 0), PATTERN (tem)))
13574 {
13575 rtx set = single_set (tem);
13576 rtx inner_dest = 0;
13577 #ifdef HAVE_cc0
13578 rtx cc0_setter = NULL_RTX;
13579 #endif
13580
13581 if (set != 0)
13582 for (inner_dest = SET_DEST (set);
13583 (GET_CODE (inner_dest) == STRICT_LOW_PART
13584 || GET_CODE (inner_dest) == SUBREG
13585 || GET_CODE (inner_dest) == ZERO_EXTRACT);
13586 inner_dest = XEXP (inner_dest, 0))
13587 ;
13588
13589 /* Verify that it was the set, and not a clobber that
13590 modified the register.
13591
13592 CC0 targets must be careful to maintain setter/user
13593 pairs. If we cannot delete the setter due to side
13594 effects, mark the user with an UNUSED note instead
13595 of deleting it. */
13596
13597 if (set != 0 && ! side_effects_p (SET_SRC (set))
13598 && rtx_equal_p (XEXP (note, 0), inner_dest)
13599 #ifdef HAVE_cc0
13600 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
13601 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
13602 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
13603 #endif
13604 )
13605 {
13606 /* Move the notes and links of TEM elsewhere.
13607 This might delete other dead insns recursively.
13608 First set the pattern to something that won't use
13609 any register. */
13610 rtx old_notes = REG_NOTES (tem);
13611
13612 PATTERN (tem) = pc_rtx;
13613 REG_NOTES (tem) = NULL;
13614
13615 distribute_notes (old_notes, tem, tem, NULL_RTX,
13616 NULL_RTX, NULL_RTX, NULL_RTX);
13617 distribute_links (LOG_LINKS (tem));
13618
13619 SET_INSN_DELETED (tem);
13620 if (tem == i2)
13621 i2 = NULL_RTX;
13622
13623 #ifdef HAVE_cc0
13624 /* Delete the setter too. */
13625 if (cc0_setter)
13626 {
13627 PATTERN (cc0_setter) = pc_rtx;
13628 old_notes = REG_NOTES (cc0_setter);
13629 REG_NOTES (cc0_setter) = NULL;
13630
13631 distribute_notes (old_notes, cc0_setter,
13632 cc0_setter, NULL_RTX,
13633 NULL_RTX, NULL_RTX, NULL_RTX);
13634 distribute_links (LOG_LINKS (cc0_setter));
13635
13636 SET_INSN_DELETED (cc0_setter);
13637 if (cc0_setter == i2)
13638 i2 = NULL_RTX;
13639 }
13640 #endif
13641 }
13642 else
13643 {
13644 PUT_REG_NOTE_KIND (note, REG_UNUSED);
13645
13646 /* If there isn't already a REG_UNUSED note, put one
13647 here. Do not place a REG_DEAD note, even if
13648 the register is also used here; that would not
13649 match the algorithm used in lifetime analysis
13650 and can cause the consistency check in the
13651 scheduler to fail. */
13652 if (! find_regno_note (tem, REG_UNUSED,
13653 REGNO (XEXP (note, 0))))
13654 place = tem;
13655 break;
13656 }
13657 }
13658 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
13659 || (CALL_P (tem)
13660 && find_reg_fusage (tem, USE, XEXP (note, 0))))
13661 {
13662 place = tem;
13663
13664 /* If we are doing a 3->2 combination, and we have a
13665 register which formerly died in i3 and was not used
13666 by i2, which now no longer dies in i3 and is used in
13667 i2 but does not die in i2, and place is between i2
13668 and i3, then we may need to move a link from place to
13669 i2. */
13670 if (i2 && DF_INSN_LUID (place) > DF_INSN_LUID (i2)
13671 && from_insn
13672 && DF_INSN_LUID (from_insn) > DF_INSN_LUID (i2)
13673 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
13674 {
13675 struct insn_link *links = LOG_LINKS (place);
13676 LOG_LINKS (place) = NULL;
13677 distribute_links (links);
13678 }
13679 break;
13680 }
13681
13682 if (tem == BB_HEAD (bb))
13683 break;
13684 }
13685
13686 }
13687
13688 /* If the register is set or already dead at PLACE, we needn't do
13689 anything with this note if it is still a REG_DEAD note.
13690 We check here if it is set at all, not if is it totally replaced,
13691 which is what `dead_or_set_p' checks, so also check for it being
13692 set partially. */
13693
13694 if (place && REG_NOTE_KIND (note) == REG_DEAD)
13695 {
13696 unsigned int regno = REGNO (XEXP (note, 0));
13697 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
13698
13699 if (dead_or_set_p (place, XEXP (note, 0))
13700 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
13701 {
13702 /* Unless the register previously died in PLACE, clear
13703 last_death. [I no longer understand why this is
13704 being done.] */
13705 if (rsp->last_death != place)
13706 rsp->last_death = 0;
13707 place = 0;
13708 }
13709 else
13710 rsp->last_death = place;
13711
13712 /* If this is a death note for a hard reg that is occupying
13713 multiple registers, ensure that we are still using all
13714 parts of the object. If we find a piece of the object
13715 that is unused, we must arrange for an appropriate REG_DEAD
13716 note to be added for it. However, we can't just emit a USE
13717 and tag the note to it, since the register might actually
13718 be dead; so we recourse, and the recursive call then finds
13719 the previous insn that used this register. */
13720
13721 if (place && regno < FIRST_PSEUDO_REGISTER
13722 && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
13723 {
13724 unsigned int endregno = END_HARD_REGNO (XEXP (note, 0));
13725 int all_used = 1;
13726 unsigned int i;
13727
13728 for (i = regno; i < endregno; i++)
13729 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
13730 && ! find_regno_fusage (place, USE, i))
13731 || dead_or_set_regno_p (place, i))
13732 all_used = 0;
13733
13734 if (! all_used)
13735 {
13736 /* Put only REG_DEAD notes for pieces that are
13737 not already dead or set. */
13738
13739 for (i = regno; i < endregno;
13740 i += hard_regno_nregs[i][reg_raw_mode[i]])
13741 {
13742 rtx piece = regno_reg_rtx[i];
13743 basic_block bb = this_basic_block;
13744
13745 if (! dead_or_set_p (place, piece)
13746 && ! reg_bitfield_target_p (piece,
13747 PATTERN (place)))
13748 {
13749 rtx new_note = alloc_reg_note (REG_DEAD, piece,
13750 NULL_RTX);
13751
13752 distribute_notes (new_note, place, place,
13753 NULL_RTX, NULL_RTX, NULL_RTX,
13754 NULL_RTX);
13755 }
13756 else if (! refers_to_regno_p (i, i + 1,
13757 PATTERN (place), 0)
13758 && ! find_regno_fusage (place, USE, i))
13759 for (tem = PREV_INSN (place); ;
13760 tem = PREV_INSN (tem))
13761 {
13762 if (!NONDEBUG_INSN_P (tem))
13763 {
13764 if (tem == BB_HEAD (bb))
13765 break;
13766 continue;
13767 }
13768 if (dead_or_set_p (tem, piece)
13769 || reg_bitfield_target_p (piece,
13770 PATTERN (tem)))
13771 {
13772 add_reg_note (tem, REG_UNUSED, piece);
13773 break;
13774 }
13775 }
13776
13777 }
13778
13779 place = 0;
13780 }
13781 }
13782 }
13783 break;
13784
13785 default:
13786 /* Any other notes should not be present at this point in the
13787 compilation. */
13788 gcc_unreachable ();
13789 }
13790
13791 if (place)
13792 {
13793 XEXP (note, 1) = REG_NOTES (place);
13794 REG_NOTES (place) = note;
13795 }
13796
13797 if (place2)
13798 add_reg_note (place2, REG_NOTE_KIND (note), XEXP (note, 0));
13799 }
13800 }
13801
13802 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13803 I3, I2, and I1 to new locations. This is also called to add a link
13804 pointing at I3 when I3's destination is changed. */
13805
13806 static void
distribute_links(struct insn_link * links)13807 distribute_links (struct insn_link *links)
13808 {
13809 struct insn_link *link, *next_link;
13810
13811 for (link = links; link; link = next_link)
13812 {
13813 rtx place = 0;
13814 rtx insn;
13815 rtx set, reg;
13816
13817 next_link = link->next;
13818
13819 /* If the insn that this link points to is a NOTE or isn't a single
13820 set, ignore it. In the latter case, it isn't clear what we
13821 can do other than ignore the link, since we can't tell which
13822 register it was for. Such links wouldn't be used by combine
13823 anyway.
13824
13825 It is not possible for the destination of the target of the link to
13826 have been changed by combine. The only potential of this is if we
13827 replace I3, I2, and I1 by I3 and I2. But in that case the
13828 destination of I2 also remains unchanged. */
13829
13830 if (NOTE_P (link->insn)
13831 || (set = single_set (link->insn)) == 0)
13832 continue;
13833
13834 reg = SET_DEST (set);
13835 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
13836 || GET_CODE (reg) == STRICT_LOW_PART)
13837 reg = XEXP (reg, 0);
13838
13839 /* A LOG_LINK is defined as being placed on the first insn that uses
13840 a register and points to the insn that sets the register. Start
13841 searching at the next insn after the target of the link and stop
13842 when we reach a set of the register or the end of the basic block.
13843
13844 Note that this correctly handles the link that used to point from
13845 I3 to I2. Also note that not much searching is typically done here
13846 since most links don't point very far away. */
13847
13848 for (insn = NEXT_INSN (link->insn);
13849 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
13850 || BB_HEAD (this_basic_block->next_bb) != insn));
13851 insn = NEXT_INSN (insn))
13852 if (DEBUG_INSN_P (insn))
13853 continue;
13854 else if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
13855 {
13856 if (reg_referenced_p (reg, PATTERN (insn)))
13857 place = insn;
13858 break;
13859 }
13860 else if (CALL_P (insn)
13861 && find_reg_fusage (insn, USE, reg))
13862 {
13863 place = insn;
13864 break;
13865 }
13866 else if (INSN_P (insn) && reg_set_p (reg, insn))
13867 break;
13868
13869 /* If we found a place to put the link, place it there unless there
13870 is already a link to the same insn as LINK at that point. */
13871
13872 if (place)
13873 {
13874 struct insn_link *link2;
13875
13876 FOR_EACH_LOG_LINK (link2, place)
13877 if (link2->insn == link->insn)
13878 break;
13879
13880 if (link2 == NULL)
13881 {
13882 link->next = LOG_LINKS (place);
13883 LOG_LINKS (place) = link;
13884
13885 /* Set added_links_insn to the earliest insn we added a
13886 link to. */
13887 if (added_links_insn == 0
13888 || DF_INSN_LUID (added_links_insn) > DF_INSN_LUID (place))
13889 added_links_insn = place;
13890 }
13891 }
13892 }
13893 }
13894
13895 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
13896 Check whether the expression pointer to by LOC is a register or
13897 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
13898 Otherwise return zero. */
13899
13900 static int
unmentioned_reg_p_1(rtx * loc,void * expr)13901 unmentioned_reg_p_1 (rtx *loc, void *expr)
13902 {
13903 rtx x = *loc;
13904
13905 if (x != NULL_RTX
13906 && (REG_P (x) || MEM_P (x))
13907 && ! reg_mentioned_p (x, (rtx) expr))
13908 return 1;
13909 return 0;
13910 }
13911
13912 /* Check for any register or memory mentioned in EQUIV that is not
13913 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
13914 of EXPR where some registers may have been replaced by constants. */
13915
13916 static bool
unmentioned_reg_p(rtx equiv,rtx expr)13917 unmentioned_reg_p (rtx equiv, rtx expr)
13918 {
13919 return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
13920 }
13921
13922 void
dump_combine_stats(FILE * file)13923 dump_combine_stats (FILE *file)
13924 {
13925 fprintf
13926 (file,
13927 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13928 combine_attempts, combine_merges, combine_extras, combine_successes);
13929 }
13930
13931 void
dump_combine_total_stats(FILE * file)13932 dump_combine_total_stats (FILE *file)
13933 {
13934 fprintf
13935 (file,
13936 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13937 total_attempts, total_merges, total_extras, total_successes);
13938 }
13939
13940 static bool
gate_handle_combine(void)13941 gate_handle_combine (void)
13942 {
13943 return (optimize > 0);
13944 }
13945
13946 /* Try combining insns through substitution. */
13947 static unsigned int
rest_of_handle_combine(void)13948 rest_of_handle_combine (void)
13949 {
13950 int rebuild_jump_labels_after_combine;
13951
13952 df_set_flags (DF_LR_RUN_DCE + DF_DEFER_INSN_RESCAN);
13953 df_note_add_problem ();
13954 df_analyze ();
13955
13956 regstat_init_n_sets_and_refs ();
13957
13958 rebuild_jump_labels_after_combine
13959 = combine_instructions (get_insns (), max_reg_num ());
13960
13961 /* Combining insns may have turned an indirect jump into a
13962 direct jump. Rebuild the JUMP_LABEL fields of jumping
13963 instructions. */
13964 if (rebuild_jump_labels_after_combine)
13965 {
13966 timevar_push (TV_JUMP);
13967 rebuild_jump_labels (get_insns ());
13968 cleanup_cfg (0);
13969 timevar_pop (TV_JUMP);
13970 }
13971
13972 regstat_free_n_sets_and_refs ();
13973 return 0;
13974 }
13975
13976 struct rtl_opt_pass pass_combine =
13977 {
13978 {
13979 RTL_PASS,
13980 "combine", /* name */
13981 gate_handle_combine, /* gate */
13982 rest_of_handle_combine, /* execute */
13983 NULL, /* sub */
13984 NULL, /* next */
13985 0, /* static_pass_number */
13986 TV_COMBINE, /* tv_id */
13987 PROP_cfglayout, /* properties_required */
13988 0, /* properties_provided */
13989 0, /* properties_destroyed */
13990 0, /* todo_flags_start */
13991 TODO_df_finish | TODO_verify_rtl_sharing |
13992 TODO_ggc_collect, /* todo_flags_finish */
13993 }
13994 };
13995