1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 * Christian König
28 */
29 #include <linux/seq_file.h>
30 #include <linux/slab.h>
31 #include <drm/drmP.h>
32 #include <drm/amdgpu_drm.h>
33 #include "amdgpu.h"
34 #include "atom.h"
35
36 #define AMDGPU_IB_TEST_TIMEOUT msecs_to_jiffies(1000)
37
38 /*
39 * IB
40 * IBs (Indirect Buffers) and areas of GPU accessible memory where
41 * commands are stored. You can put a pointer to the IB in the
42 * command ring and the hw will fetch the commands from the IB
43 * and execute them. Generally userspace acceleration drivers
44 * produce command buffers which are send to the kernel and
45 * put in IBs for execution by the requested ring.
46 */
47 static int amdgpu_debugfs_sa_init(struct amdgpu_device *adev);
48
49 /**
50 * amdgpu_ib_get - request an IB (Indirect Buffer)
51 *
52 * @ring: ring index the IB is associated with
53 * @size: requested IB size
54 * @ib: IB object returned
55 *
56 * Request an IB (all asics). IBs are allocated using the
57 * suballocator.
58 * Returns 0 on success, error on failure.
59 */
amdgpu_ib_get(struct amdgpu_device * adev,struct amdgpu_vm * vm,unsigned size,struct amdgpu_ib * ib)60 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
61 unsigned size, struct amdgpu_ib *ib)
62 {
63 int r;
64
65 if (size) {
66 r = amdgpu_sa_bo_new(&adev->ring_tmp_bo,
67 &ib->sa_bo, size, 256);
68 if (r) {
69 dev_err(adev->dev, "failed to get a new IB (%d)\n", r);
70 return r;
71 }
72
73 ib->ptr = amdgpu_sa_bo_cpu_addr(ib->sa_bo);
74
75 if (!vm)
76 ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo);
77 }
78
79 return 0;
80 }
81
82 /**
83 * amdgpu_ib_free - free an IB (Indirect Buffer)
84 *
85 * @adev: amdgpu_device pointer
86 * @ib: IB object to free
87 * @f: the fence SA bo need wait on for the ib alloation
88 *
89 * Free an IB (all asics).
90 */
amdgpu_ib_free(struct amdgpu_device * adev,struct amdgpu_ib * ib,struct dma_fence * f)91 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
92 struct dma_fence *f)
93 {
94 amdgpu_sa_bo_free(adev, &ib->sa_bo, f);
95 }
96
97 /**
98 * amdgpu_ib_schedule - schedule an IB (Indirect Buffer) on the ring
99 *
100 * @adev: amdgpu_device pointer
101 * @num_ibs: number of IBs to schedule
102 * @ibs: IB objects to schedule
103 * @f: fence created during this submission
104 *
105 * Schedule an IB on the associated ring (all asics).
106 * Returns 0 on success, error on failure.
107 *
108 * On SI, there are two parallel engines fed from the primary ring,
109 * the CE (Constant Engine) and the DE (Drawing Engine). Since
110 * resource descriptors have moved to memory, the CE allows you to
111 * prime the caches while the DE is updating register state so that
112 * the resource descriptors will be already in cache when the draw is
113 * processed. To accomplish this, the userspace driver submits two
114 * IBs, one for the CE and one for the DE. If there is a CE IB (called
115 * a CONST_IB), it will be put on the ring prior to the DE IB. Prior
116 * to SI there was just a DE IB.
117 */
amdgpu_ib_schedule(struct amdgpu_ring * ring,unsigned num_ibs,struct amdgpu_ib * ibs,struct amdgpu_job * job,struct dma_fence ** f)118 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
119 struct amdgpu_ib *ibs, struct amdgpu_job *job,
120 struct dma_fence **f)
121 {
122 struct amdgpu_device *adev = ring->adev;
123 struct amdgpu_ib *ib = &ibs[0];
124 struct dma_fence *tmp = NULL;
125 bool skip_preamble, need_ctx_switch;
126 unsigned patch_offset = ~0;
127 struct amdgpu_vm *vm;
128 uint64_t fence_ctx;
129 uint32_t status = 0, alloc_size;
130 unsigned fence_flags = 0;
131
132 unsigned i;
133 int r = 0;
134 bool need_pipe_sync = false;
135
136 if (num_ibs == 0)
137 return -EINVAL;
138
139 /* ring tests don't use a job */
140 if (job) {
141 vm = job->vm;
142 fence_ctx = job->base.s_fence ?
143 job->base.s_fence->scheduled.context : 0;
144 } else {
145 vm = NULL;
146 fence_ctx = 0;
147 }
148
149 if (!ring->ready) {
150 dev_err(adev->dev, "couldn't schedule ib on ring <%s>\n", ring->name);
151 return -EINVAL;
152 }
153
154 if (vm && !job->vmid) {
155 dev_err(adev->dev, "VM IB without ID\n");
156 return -EINVAL;
157 }
158
159 alloc_size = ring->funcs->emit_frame_size + num_ibs *
160 ring->funcs->emit_ib_size;
161
162 r = amdgpu_ring_alloc(ring, alloc_size);
163 if (r) {
164 dev_err(adev->dev, "scheduling IB failed (%d).\n", r);
165 return r;
166 }
167
168 need_ctx_switch = ring->current_ctx != fence_ctx;
169 if (ring->funcs->emit_pipeline_sync && job &&
170 ((tmp = amdgpu_sync_get_fence(&job->sched_sync, NULL)) ||
171 (amdgpu_sriov_vf(adev) && need_ctx_switch) ||
172 amdgpu_vm_need_pipeline_sync(ring, job))) {
173 need_pipe_sync = true;
174 dma_fence_put(tmp);
175 }
176
177 if (ring->funcs->insert_start)
178 ring->funcs->insert_start(ring);
179
180 if (job) {
181 r = amdgpu_vm_flush(ring, job, need_pipe_sync);
182 if (r) {
183 amdgpu_ring_undo(ring);
184 return r;
185 }
186 }
187
188 if (job && ring->funcs->init_cond_exec)
189 patch_offset = amdgpu_ring_init_cond_exec(ring);
190
191 #ifdef CONFIG_X86_64
192 if (!(adev->flags & AMD_IS_APU))
193 #endif
194 {
195 if (ring->funcs->emit_hdp_flush)
196 amdgpu_ring_emit_hdp_flush(ring);
197 else
198 amdgpu_asic_flush_hdp(adev, ring);
199 }
200
201 skip_preamble = ring->current_ctx == fence_ctx;
202 if (job && ring->funcs->emit_cntxcntl) {
203 if (need_ctx_switch)
204 status |= AMDGPU_HAVE_CTX_SWITCH;
205 status |= job->preamble_status;
206
207 amdgpu_ring_emit_cntxcntl(ring, status);
208 }
209
210 for (i = 0; i < num_ibs; ++i) {
211 ib = &ibs[i];
212
213 /* drop preamble IBs if we don't have a context switch */
214 if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) &&
215 skip_preamble &&
216 !(status & AMDGPU_PREAMBLE_IB_PRESENT_FIRST) &&
217 !amdgpu_sriov_vf(adev)) /* for SRIOV preemption, Preamble CE ib must be inserted anyway */
218 continue;
219
220 amdgpu_ring_emit_ib(ring, ib, job ? job->vmid : 0,
221 need_ctx_switch);
222 need_ctx_switch = false;
223 }
224
225 if (ring->funcs->emit_tmz)
226 amdgpu_ring_emit_tmz(ring, false);
227
228 #ifdef CONFIG_X86_64
229 if (!(adev->flags & AMD_IS_APU))
230 #endif
231 amdgpu_asic_invalidate_hdp(adev, ring);
232
233 if (ib->flags & AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE)
234 fence_flags |= AMDGPU_FENCE_FLAG_TC_WB_ONLY;
235
236 /* wrap the last IB with fence */
237 if (job && job->uf_addr) {
238 amdgpu_ring_emit_fence(ring, job->uf_addr, job->uf_sequence,
239 fence_flags | AMDGPU_FENCE_FLAG_64BIT);
240 }
241
242 r = amdgpu_fence_emit(ring, f, fence_flags);
243 if (r) {
244 dev_err(adev->dev, "failed to emit fence (%d)\n", r);
245 if (job && job->vmid)
246 amdgpu_vmid_reset(adev, ring->funcs->vmhub, job->vmid);
247 amdgpu_ring_undo(ring);
248 return r;
249 }
250
251 if (ring->funcs->insert_end)
252 ring->funcs->insert_end(ring);
253
254 if (patch_offset != ~0 && ring->funcs->patch_cond_exec)
255 amdgpu_ring_patch_cond_exec(ring, patch_offset);
256
257 ring->current_ctx = fence_ctx;
258 if (vm && ring->funcs->emit_switch_buffer)
259 amdgpu_ring_emit_switch_buffer(ring);
260 amdgpu_ring_commit(ring);
261 return 0;
262 }
263
264 /**
265 * amdgpu_ib_pool_init - Init the IB (Indirect Buffer) pool
266 *
267 * @adev: amdgpu_device pointer
268 *
269 * Initialize the suballocator to manage a pool of memory
270 * for use as IBs (all asics).
271 * Returns 0 on success, error on failure.
272 */
amdgpu_ib_pool_init(struct amdgpu_device * adev)273 int amdgpu_ib_pool_init(struct amdgpu_device *adev)
274 {
275 int r;
276
277 if (adev->ib_pool_ready) {
278 return 0;
279 }
280 r = amdgpu_sa_bo_manager_init(adev, &adev->ring_tmp_bo,
281 AMDGPU_IB_POOL_SIZE*64*1024,
282 AMDGPU_GPU_PAGE_SIZE,
283 AMDGPU_GEM_DOMAIN_GTT);
284 if (r) {
285 return r;
286 }
287
288 adev->ib_pool_ready = true;
289 if (amdgpu_debugfs_sa_init(adev)) {
290 dev_err(adev->dev, "failed to register debugfs file for SA\n");
291 }
292 return 0;
293 }
294
295 /**
296 * amdgpu_ib_pool_fini - Free the IB (Indirect Buffer) pool
297 *
298 * @adev: amdgpu_device pointer
299 *
300 * Tear down the suballocator managing the pool of memory
301 * for use as IBs (all asics).
302 */
amdgpu_ib_pool_fini(struct amdgpu_device * adev)303 void amdgpu_ib_pool_fini(struct amdgpu_device *adev)
304 {
305 if (adev->ib_pool_ready) {
306 amdgpu_sa_bo_manager_fini(adev, &adev->ring_tmp_bo);
307 adev->ib_pool_ready = false;
308 }
309 }
310
311 /**
312 * amdgpu_ib_ring_tests - test IBs on the rings
313 *
314 * @adev: amdgpu_device pointer
315 *
316 * Test an IB (Indirect Buffer) on each ring.
317 * If the test fails, disable the ring.
318 * Returns 0 on success, error if the primary GFX ring
319 * IB test fails.
320 */
amdgpu_ib_ring_tests(struct amdgpu_device * adev)321 int amdgpu_ib_ring_tests(struct amdgpu_device *adev)
322 {
323 unsigned i;
324 int r, ret = 0;
325 long tmo_gfx, tmo_mm;
326
327 tmo_mm = tmo_gfx = AMDGPU_IB_TEST_TIMEOUT;
328 if (amdgpu_sriov_vf(adev)) {
329 /* for MM engines in hypervisor side they are not scheduled together
330 * with CP and SDMA engines, so even in exclusive mode MM engine could
331 * still running on other VF thus the IB TEST TIMEOUT for MM engines
332 * under SR-IOV should be set to a long time. 8 sec should be enough
333 * for the MM comes back to this VF.
334 */
335 tmo_mm = 8 * AMDGPU_IB_TEST_TIMEOUT;
336 }
337
338 if (amdgpu_sriov_runtime(adev)) {
339 /* for CP & SDMA engines since they are scheduled together so
340 * need to make the timeout width enough to cover the time
341 * cost waiting for it coming back under RUNTIME only
342 */
343 tmo_gfx = 8 * AMDGPU_IB_TEST_TIMEOUT;
344 }
345
346 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
347 struct amdgpu_ring *ring = adev->rings[i];
348 long tmo;
349
350 if (!ring || !ring->ready)
351 continue;
352
353 /* MM engine need more time */
354 if (ring->funcs->type == AMDGPU_RING_TYPE_UVD ||
355 ring->funcs->type == AMDGPU_RING_TYPE_VCE ||
356 ring->funcs->type == AMDGPU_RING_TYPE_UVD_ENC ||
357 ring->funcs->type == AMDGPU_RING_TYPE_VCN_DEC ||
358 ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC ||
359 ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG)
360 tmo = tmo_mm;
361 else
362 tmo = tmo_gfx;
363
364 r = amdgpu_ring_test_ib(ring, tmo);
365 if (r) {
366 ring->ready = false;
367
368 if (ring == &adev->gfx.gfx_ring[0]) {
369 /* oh, oh, that's really bad */
370 DRM_ERROR("amdgpu: failed testing IB on GFX ring (%d).\n", r);
371 adev->accel_working = false;
372 return r;
373
374 } else {
375 /* still not good, but we can live with it */
376 DRM_ERROR("amdgpu: failed testing IB on ring %d (%d).\n", i, r);
377 ret = r;
378 }
379 }
380 }
381 return ret;
382 }
383
384 /*
385 * Debugfs info
386 */
387 #if defined(CONFIG_DEBUG_FS)
388
amdgpu_debugfs_sa_info(struct seq_file * m,void * data)389 static int amdgpu_debugfs_sa_info(struct seq_file *m, void *data)
390 {
391 struct drm_info_node *node = (struct drm_info_node *) m->private;
392 struct drm_device *dev = node->minor->dev;
393 struct amdgpu_device *adev = dev->dev_private;
394
395 amdgpu_sa_bo_dump_debug_info(&adev->ring_tmp_bo, m);
396
397 return 0;
398
399 }
400
401 static const struct drm_info_list amdgpu_debugfs_sa_list[] = {
402 {"amdgpu_sa_info", &amdgpu_debugfs_sa_info, 0, NULL},
403 };
404
405 #endif
406
amdgpu_debugfs_sa_init(struct amdgpu_device * adev)407 static int amdgpu_debugfs_sa_init(struct amdgpu_device *adev)
408 {
409 #if defined(CONFIG_DEBUG_FS)
410 return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_sa_list, 1);
411 #else
412 return 0;
413 #endif
414 }
415