1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include <linux/firmware.h>
24 #include <linux/slab.h>
25 #include <linux/module.h>
26 #include <drm/drmP.h>
27 #include "amdgpu.h"
28 #include "amdgpu_atombios.h"
29 #include "amdgpu_ih.h"
30 #include "amdgpu_uvd.h"
31 #include "amdgpu_vce.h"
32 #include "amdgpu_ucode.h"
33 #include "amdgpu_psp.h"
34 #include "atom.h"
35 #include "amd_pcie.h"
36
37 #include "uvd/uvd_7_0_offset.h"
38 #include "gc/gc_9_0_offset.h"
39 #include "gc/gc_9_0_sh_mask.h"
40 #include "sdma0/sdma0_4_0_offset.h"
41 #include "sdma1/sdma1_4_0_offset.h"
42 #include "hdp/hdp_4_0_offset.h"
43 #include "hdp/hdp_4_0_sh_mask.h"
44 #include "smuio/smuio_9_0_offset.h"
45 #include "smuio/smuio_9_0_sh_mask.h"
46
47 #include "soc15.h"
48 #include "soc15_common.h"
49 #include "gfx_v9_0.h"
50 #include "gmc_v9_0.h"
51 #include "gfxhub_v1_0.h"
52 #include "mmhub_v1_0.h"
53 #include "df_v1_7.h"
54 #include "df_v3_6.h"
55 #include "vega10_ih.h"
56 #include "sdma_v4_0.h"
57 #include "uvd_v7_0.h"
58 #include "vce_v4_0.h"
59 #include "vcn_v1_0.h"
60 #include "dce_virtual.h"
61 #include "mxgpu_ai.h"
62
63 #define mmMP0_MISC_CGTT_CTRL0 0x01b9
64 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0
65 #define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba
66 #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0
67
68 /*
69 * Indirect registers accessor
70 */
soc15_pcie_rreg(struct amdgpu_device * adev,u32 reg)71 static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg)
72 {
73 unsigned long flags, address, data;
74 u32 r;
75 address = adev->nbio_funcs->get_pcie_index_offset(adev);
76 data = adev->nbio_funcs->get_pcie_data_offset(adev);
77
78 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
79 WREG32(address, reg);
80 (void)RREG32(address);
81 r = RREG32(data);
82 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
83 return r;
84 }
85
soc15_pcie_wreg(struct amdgpu_device * adev,u32 reg,u32 v)86 static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
87 {
88 unsigned long flags, address, data;
89
90 address = adev->nbio_funcs->get_pcie_index_offset(adev);
91 data = adev->nbio_funcs->get_pcie_data_offset(adev);
92
93 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
94 WREG32(address, reg);
95 (void)RREG32(address);
96 WREG32(data, v);
97 (void)RREG32(data);
98 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
99 }
100
soc15_uvd_ctx_rreg(struct amdgpu_device * adev,u32 reg)101 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
102 {
103 unsigned long flags, address, data;
104 u32 r;
105
106 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
107 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
108
109 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
110 WREG32(address, ((reg) & 0x1ff));
111 r = RREG32(data);
112 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
113 return r;
114 }
115
soc15_uvd_ctx_wreg(struct amdgpu_device * adev,u32 reg,u32 v)116 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
117 {
118 unsigned long flags, address, data;
119
120 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
121 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
122
123 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
124 WREG32(address, ((reg) & 0x1ff));
125 WREG32(data, (v));
126 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
127 }
128
soc15_didt_rreg(struct amdgpu_device * adev,u32 reg)129 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg)
130 {
131 unsigned long flags, address, data;
132 u32 r;
133
134 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
135 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
136
137 spin_lock_irqsave(&adev->didt_idx_lock, flags);
138 WREG32(address, (reg));
139 r = RREG32(data);
140 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
141 return r;
142 }
143
soc15_didt_wreg(struct amdgpu_device * adev,u32 reg,u32 v)144 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
145 {
146 unsigned long flags, address, data;
147
148 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
149 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
150
151 spin_lock_irqsave(&adev->didt_idx_lock, flags);
152 WREG32(address, (reg));
153 WREG32(data, (v));
154 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
155 }
156
soc15_gc_cac_rreg(struct amdgpu_device * adev,u32 reg)157 static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
158 {
159 unsigned long flags;
160 u32 r;
161
162 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
163 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
164 r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA);
165 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
166 return r;
167 }
168
soc15_gc_cac_wreg(struct amdgpu_device * adev,u32 reg,u32 v)169 static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
170 {
171 unsigned long flags;
172
173 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
174 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
175 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v));
176 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
177 }
178
soc15_se_cac_rreg(struct amdgpu_device * adev,u32 reg)179 static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg)
180 {
181 unsigned long flags;
182 u32 r;
183
184 spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
185 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
186 r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA);
187 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
188 return r;
189 }
190
soc15_se_cac_wreg(struct amdgpu_device * adev,u32 reg,u32 v)191 static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
192 {
193 unsigned long flags;
194
195 spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
196 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
197 WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v));
198 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
199 }
200
soc15_get_config_memsize(struct amdgpu_device * adev)201 static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
202 {
203 return adev->nbio_funcs->get_memsize(adev);
204 }
205
soc15_get_xclk(struct amdgpu_device * adev)206 static u32 soc15_get_xclk(struct amdgpu_device *adev)
207 {
208 u32 reference_clock = adev->clock.spll.reference_freq;
209
210 if (adev->asic_type == CHIP_RAVEN)
211 return reference_clock / 4;
212
213 return reference_clock;
214 }
215
216
soc15_grbm_select(struct amdgpu_device * adev,u32 me,u32 pipe,u32 queue,u32 vmid)217 void soc15_grbm_select(struct amdgpu_device *adev,
218 u32 me, u32 pipe, u32 queue, u32 vmid)
219 {
220 u32 grbm_gfx_cntl = 0;
221 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
222 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
223 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
224 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
225
226 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl);
227 }
228
soc15_vga_set_state(struct amdgpu_device * adev,bool state)229 static void soc15_vga_set_state(struct amdgpu_device *adev, bool state)
230 {
231 /* todo */
232 }
233
soc15_read_disabled_bios(struct amdgpu_device * adev)234 static bool soc15_read_disabled_bios(struct amdgpu_device *adev)
235 {
236 /* todo */
237 return false;
238 }
239
soc15_read_bios_from_rom(struct amdgpu_device * adev,u8 * bios,u32 length_bytes)240 static bool soc15_read_bios_from_rom(struct amdgpu_device *adev,
241 u8 *bios, u32 length_bytes)
242 {
243 u32 *dw_ptr;
244 u32 i, length_dw;
245
246 if (bios == NULL)
247 return false;
248 if (length_bytes == 0)
249 return false;
250 /* APU vbios image is part of sbios image */
251 if (adev->flags & AMD_IS_APU)
252 return false;
253
254 dw_ptr = (u32 *)bios;
255 length_dw = ALIGN(length_bytes, 4) / 4;
256
257 /* set rom index to 0 */
258 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0);
259 /* read out the rom data */
260 for (i = 0; i < length_dw; i++)
261 dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA));
262
263 return true;
264 }
265
266 struct soc15_allowed_register_entry {
267 uint32_t hwip;
268 uint32_t inst;
269 uint32_t seg;
270 uint32_t reg_offset;
271 bool grbm_indexed;
272 };
273
274
275 static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = {
276 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
277 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
278 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
279 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
280 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
281 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
282 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
283 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
284 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
285 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
286 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
287 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
288 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
289 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
290 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
291 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
292 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
293 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
294 { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)},
295 };
296
soc15_read_indexed_register(struct amdgpu_device * adev,u32 se_num,u32 sh_num,u32 reg_offset)297 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
298 u32 sh_num, u32 reg_offset)
299 {
300 uint32_t val;
301
302 mutex_lock(&adev->grbm_idx_mutex);
303 if (se_num != 0xffffffff || sh_num != 0xffffffff)
304 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
305
306 val = RREG32(reg_offset);
307
308 if (se_num != 0xffffffff || sh_num != 0xffffffff)
309 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
310 mutex_unlock(&adev->grbm_idx_mutex);
311 return val;
312 }
313
soc15_get_register_value(struct amdgpu_device * adev,bool indexed,u32 se_num,u32 sh_num,u32 reg_offset)314 static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
315 bool indexed, u32 se_num,
316 u32 sh_num, u32 reg_offset)
317 {
318 if (indexed) {
319 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
320 } else {
321 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
322 return adev->gfx.config.gb_addr_config;
323 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))
324 return adev->gfx.config.db_debug2;
325 return RREG32(reg_offset);
326 }
327 }
328
soc15_read_register(struct amdgpu_device * adev,u32 se_num,u32 sh_num,u32 reg_offset,u32 * value)329 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
330 u32 sh_num, u32 reg_offset, u32 *value)
331 {
332 uint32_t i;
333 struct soc15_allowed_register_entry *en;
334
335 *value = 0;
336 for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) {
337 en = &soc15_allowed_read_registers[i];
338 if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
339 + en->reg_offset))
340 continue;
341
342 *value = soc15_get_register_value(adev,
343 soc15_allowed_read_registers[i].grbm_indexed,
344 se_num, sh_num, reg_offset);
345 return 0;
346 }
347 return -EINVAL;
348 }
349
350
351 /**
352 * soc15_program_register_sequence - program an array of registers.
353 *
354 * @adev: amdgpu_device pointer
355 * @regs: pointer to the register array
356 * @array_size: size of the register array
357 *
358 * Programs an array or registers with and and or masks.
359 * This is a helper for setting golden registers.
360 */
361
soc15_program_register_sequence(struct amdgpu_device * adev,const struct soc15_reg_golden * regs,const u32 array_size)362 void soc15_program_register_sequence(struct amdgpu_device *adev,
363 const struct soc15_reg_golden *regs,
364 const u32 array_size)
365 {
366 const struct soc15_reg_golden *entry;
367 u32 tmp, reg;
368 int i;
369
370 for (i = 0; i < array_size; ++i) {
371 entry = ®s[i];
372 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
373
374 if (entry->and_mask == 0xffffffff) {
375 tmp = entry->or_mask;
376 } else {
377 tmp = RREG32(reg);
378 tmp &= ~(entry->and_mask);
379 tmp |= entry->or_mask;
380 }
381 WREG32(reg, tmp);
382 }
383
384 }
385
386
soc15_asic_reset(struct amdgpu_device * adev)387 static int soc15_asic_reset(struct amdgpu_device *adev)
388 {
389 u32 i;
390
391 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
392
393 dev_info(adev->dev, "GPU reset\n");
394
395 /* disable BM */
396 pci_clear_master(adev->pdev);
397
398 pci_save_state(device_get_parent(adev->dev->bsddev));
399
400 psp_gpu_reset(adev);
401
402 pci_restore_state(device_get_parent(adev->dev->bsddev));
403
404 /* wait for asic to come out of reset */
405 for (i = 0; i < adev->usec_timeout; i++) {
406 u32 memsize = adev->nbio_funcs->get_memsize(adev);
407
408 if (memsize != 0xffffffff)
409 break;
410 udelay(1);
411 }
412
413 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
414
415 return 0;
416 }
417
418 /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
419 u32 cntl_reg, u32 status_reg)
420 {
421 return 0;
422 }*/
423
soc15_set_uvd_clocks(struct amdgpu_device * adev,u32 vclk,u32 dclk)424 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
425 {
426 /*int r;
427
428 r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
429 if (r)
430 return r;
431
432 r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
433 */
434 return 0;
435 }
436
soc15_set_vce_clocks(struct amdgpu_device * adev,u32 evclk,u32 ecclk)437 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
438 {
439 /* todo */
440
441 return 0;
442 }
443
soc15_pcie_gen3_enable(struct amdgpu_device * adev)444 static void soc15_pcie_gen3_enable(struct amdgpu_device *adev)
445 {
446 #if 0
447 if (pci_is_root_bus(adev->pdev->bus))
448 return;
449 #endif
450
451 if (amdgpu_pcie_gen2 == 0)
452 return;
453
454 if (adev->flags & AMD_IS_APU)
455 return;
456
457 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
458 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
459 return;
460
461 /* todo */
462 }
463
soc15_program_aspm(struct amdgpu_device * adev)464 static void soc15_program_aspm(struct amdgpu_device *adev)
465 {
466
467 if (amdgpu_aspm == 0)
468 return;
469
470 /* todo */
471 }
472
soc15_enable_doorbell_aperture(struct amdgpu_device * adev,bool enable)473 static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev,
474 bool enable)
475 {
476 adev->nbio_funcs->enable_doorbell_aperture(adev, enable);
477 adev->nbio_funcs->enable_doorbell_selfring_aperture(adev, enable);
478 }
479
480 static const struct amdgpu_ip_block_version vega10_common_ip_block =
481 {
482 .type = AMD_IP_BLOCK_TYPE_COMMON,
483 .major = 2,
484 .minor = 0,
485 .rev = 0,
486 .funcs = &soc15_common_ip_funcs,
487 };
488
soc15_set_ip_blocks(struct amdgpu_device * adev)489 int soc15_set_ip_blocks(struct amdgpu_device *adev)
490 {
491 /* Set IP register base before any HW register access */
492 switch (adev->asic_type) {
493 case CHIP_VEGA10:
494 case CHIP_VEGA12:
495 case CHIP_RAVEN:
496 vega10_reg_base_init(adev);
497 break;
498 case CHIP_VEGA20:
499 vega20_reg_base_init(adev);
500 break;
501 default:
502 return -EINVAL;
503 }
504
505 if (adev->flags & AMD_IS_APU)
506 adev->nbio_funcs = &nbio_v7_0_funcs;
507 else if (adev->asic_type == CHIP_VEGA20)
508 adev->nbio_funcs = &nbio_v7_0_funcs;
509 else
510 adev->nbio_funcs = &nbio_v6_1_funcs;
511
512 if (adev->asic_type == CHIP_VEGA20)
513 adev->df_funcs = &df_v3_6_funcs;
514 else
515 adev->df_funcs = &df_v1_7_funcs;
516 adev->nbio_funcs->detect_hw_virt(adev);
517
518 if (amdgpu_sriov_vf(adev))
519 adev->virt.ops = &xgpu_ai_virt_ops;
520
521 switch (adev->asic_type) {
522 case CHIP_VEGA10:
523 case CHIP_VEGA12:
524 case CHIP_VEGA20:
525 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
526 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
527 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
528 if (adev->asic_type != CHIP_VEGA20) {
529 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
530 if (!amdgpu_sriov_vf(adev))
531 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
532 }
533 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
534 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
535 #if defined(CONFIG_DRM_AMD_DC)
536 else if (amdgpu_device_has_dc_support(adev))
537 amdgpu_device_ip_block_add(adev, &dm_ip_block);
538 #else
539 # warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15."
540 #endif
541 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
542 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
543 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
544 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
545 break;
546 case CHIP_RAVEN:
547 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
548 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
549 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
550 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
551 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
552 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
553 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
554 #if defined(CONFIG_DRM_AMD_DC)
555 else if (amdgpu_device_has_dc_support(adev))
556 amdgpu_device_ip_block_add(adev, &dm_ip_block);
557 #else
558 # warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15."
559 #endif
560 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
561 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
562 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
563 break;
564 default:
565 return -EINVAL;
566 }
567
568 return 0;
569 }
570
soc15_get_rev_id(struct amdgpu_device * adev)571 static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
572 {
573 return adev->nbio_funcs->get_rev_id(adev);
574 }
575
soc15_flush_hdp(struct amdgpu_device * adev,struct amdgpu_ring * ring)576 static void soc15_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
577 {
578 adev->nbio_funcs->hdp_flush(adev, ring);
579 }
580
soc15_invalidate_hdp(struct amdgpu_device * adev,struct amdgpu_ring * ring)581 static void soc15_invalidate_hdp(struct amdgpu_device *adev,
582 struct amdgpu_ring *ring)
583 {
584 if (!ring || !ring->funcs->emit_wreg)
585 WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
586 else
587 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
588 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
589 }
590
soc15_need_full_reset(struct amdgpu_device * adev)591 static bool soc15_need_full_reset(struct amdgpu_device *adev)
592 {
593 /* change this when we implement soft reset */
594 return true;
595 }
596
597 static const struct amdgpu_asic_funcs soc15_asic_funcs =
598 {
599 .read_disabled_bios = &soc15_read_disabled_bios,
600 .read_bios_from_rom = &soc15_read_bios_from_rom,
601 .read_register = &soc15_read_register,
602 .reset = &soc15_asic_reset,
603 .set_vga_state = &soc15_vga_set_state,
604 .get_xclk = &soc15_get_xclk,
605 .set_uvd_clocks = &soc15_set_uvd_clocks,
606 .set_vce_clocks = &soc15_set_vce_clocks,
607 .get_config_memsize = &soc15_get_config_memsize,
608 .flush_hdp = &soc15_flush_hdp,
609 .invalidate_hdp = &soc15_invalidate_hdp,
610 .need_full_reset = &soc15_need_full_reset,
611 };
612
soc15_common_early_init(void * handle)613 static int soc15_common_early_init(void *handle)
614 {
615 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
616
617 adev->smc_rreg = NULL;
618 adev->smc_wreg = NULL;
619 adev->pcie_rreg = &soc15_pcie_rreg;
620 adev->pcie_wreg = &soc15_pcie_wreg;
621 adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg;
622 adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg;
623 adev->didt_rreg = &soc15_didt_rreg;
624 adev->didt_wreg = &soc15_didt_wreg;
625 adev->gc_cac_rreg = &soc15_gc_cac_rreg;
626 adev->gc_cac_wreg = &soc15_gc_cac_wreg;
627 adev->se_cac_rreg = &soc15_se_cac_rreg;
628 adev->se_cac_wreg = &soc15_se_cac_wreg;
629
630 adev->asic_funcs = &soc15_asic_funcs;
631
632 adev->rev_id = soc15_get_rev_id(adev);
633 adev->external_rev_id = 0xFF;
634 switch (adev->asic_type) {
635 case CHIP_VEGA10:
636 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
637 AMD_CG_SUPPORT_GFX_MGLS |
638 AMD_CG_SUPPORT_GFX_RLC_LS |
639 AMD_CG_SUPPORT_GFX_CP_LS |
640 AMD_CG_SUPPORT_GFX_3D_CGCG |
641 AMD_CG_SUPPORT_GFX_3D_CGLS |
642 AMD_CG_SUPPORT_GFX_CGCG |
643 AMD_CG_SUPPORT_GFX_CGLS |
644 AMD_CG_SUPPORT_BIF_MGCG |
645 AMD_CG_SUPPORT_BIF_LS |
646 AMD_CG_SUPPORT_HDP_LS |
647 AMD_CG_SUPPORT_DRM_MGCG |
648 AMD_CG_SUPPORT_DRM_LS |
649 AMD_CG_SUPPORT_ROM_MGCG |
650 AMD_CG_SUPPORT_DF_MGCG |
651 AMD_CG_SUPPORT_SDMA_MGCG |
652 AMD_CG_SUPPORT_SDMA_LS |
653 AMD_CG_SUPPORT_MC_MGCG |
654 AMD_CG_SUPPORT_MC_LS;
655 adev->pg_flags = 0;
656 adev->external_rev_id = 0x1;
657 break;
658 case CHIP_VEGA12:
659 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
660 AMD_CG_SUPPORT_GFX_MGLS |
661 AMD_CG_SUPPORT_GFX_CGCG |
662 AMD_CG_SUPPORT_GFX_CGLS |
663 AMD_CG_SUPPORT_GFX_3D_CGCG |
664 AMD_CG_SUPPORT_GFX_3D_CGLS |
665 AMD_CG_SUPPORT_GFX_CP_LS |
666 AMD_CG_SUPPORT_MC_LS |
667 AMD_CG_SUPPORT_MC_MGCG |
668 AMD_CG_SUPPORT_SDMA_MGCG |
669 AMD_CG_SUPPORT_SDMA_LS |
670 AMD_CG_SUPPORT_BIF_MGCG |
671 AMD_CG_SUPPORT_BIF_LS |
672 AMD_CG_SUPPORT_HDP_MGCG |
673 AMD_CG_SUPPORT_HDP_LS |
674 AMD_CG_SUPPORT_ROM_MGCG |
675 AMD_CG_SUPPORT_VCE_MGCG |
676 AMD_CG_SUPPORT_UVD_MGCG;
677 adev->pg_flags = 0;
678 adev->external_rev_id = adev->rev_id + 0x14;
679 break;
680 case CHIP_VEGA20:
681 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
682 AMD_CG_SUPPORT_GFX_MGLS |
683 AMD_CG_SUPPORT_GFX_CGCG |
684 AMD_CG_SUPPORT_GFX_CGLS |
685 AMD_CG_SUPPORT_GFX_3D_CGCG |
686 AMD_CG_SUPPORT_GFX_3D_CGLS |
687 AMD_CG_SUPPORT_GFX_CP_LS |
688 AMD_CG_SUPPORT_MC_LS |
689 AMD_CG_SUPPORT_MC_MGCG |
690 AMD_CG_SUPPORT_SDMA_MGCG |
691 AMD_CG_SUPPORT_SDMA_LS |
692 AMD_CG_SUPPORT_BIF_MGCG |
693 AMD_CG_SUPPORT_BIF_LS |
694 AMD_CG_SUPPORT_HDP_MGCG |
695 AMD_CG_SUPPORT_HDP_LS |
696 AMD_CG_SUPPORT_ROM_MGCG |
697 AMD_CG_SUPPORT_VCE_MGCG |
698 AMD_CG_SUPPORT_UVD_MGCG;
699 adev->pg_flags = 0;
700 adev->external_rev_id = adev->rev_id + 0x28;
701 break;
702 case CHIP_RAVEN:
703 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
704 AMD_CG_SUPPORT_GFX_MGLS |
705 AMD_CG_SUPPORT_GFX_RLC_LS |
706 AMD_CG_SUPPORT_GFX_CP_LS |
707 AMD_CG_SUPPORT_GFX_3D_CGCG |
708 AMD_CG_SUPPORT_GFX_3D_CGLS |
709 AMD_CG_SUPPORT_GFX_CGCG |
710 AMD_CG_SUPPORT_GFX_CGLS |
711 AMD_CG_SUPPORT_BIF_MGCG |
712 AMD_CG_SUPPORT_BIF_LS |
713 AMD_CG_SUPPORT_HDP_MGCG |
714 AMD_CG_SUPPORT_HDP_LS |
715 AMD_CG_SUPPORT_DRM_MGCG |
716 AMD_CG_SUPPORT_DRM_LS |
717 AMD_CG_SUPPORT_ROM_MGCG |
718 AMD_CG_SUPPORT_MC_MGCG |
719 AMD_CG_SUPPORT_MC_LS |
720 AMD_CG_SUPPORT_SDMA_MGCG |
721 AMD_CG_SUPPORT_SDMA_LS |
722 AMD_CG_SUPPORT_VCN_MGCG;
723
724 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
725
726 if (adev->powerplay.pp_feature & PP_GFXOFF_MASK)
727 adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
728 AMD_PG_SUPPORT_CP |
729 AMD_PG_SUPPORT_RLC_SMU_HS;
730
731 adev->external_rev_id = 0x1;
732 break;
733 default:
734 /* FIXME: not supported yet */
735 return -EINVAL;
736 }
737
738 if (amdgpu_sriov_vf(adev)) {
739 amdgpu_virt_init_setting(adev);
740 xgpu_ai_mailbox_set_irq_funcs(adev);
741 }
742
743 return 0;
744 }
745
soc15_common_late_init(void * handle)746 static int soc15_common_late_init(void *handle)
747 {
748 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
749
750 if (amdgpu_sriov_vf(adev))
751 xgpu_ai_mailbox_get_irq(adev);
752
753 return 0;
754 }
755
soc15_common_sw_init(void * handle)756 static int soc15_common_sw_init(void *handle)
757 {
758 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
759
760 if (amdgpu_sriov_vf(adev))
761 xgpu_ai_mailbox_add_irq_id(adev);
762
763 return 0;
764 }
765
soc15_common_sw_fini(void * handle)766 static int soc15_common_sw_fini(void *handle)
767 {
768 return 0;
769 }
770
soc15_common_hw_init(void * handle)771 static int soc15_common_hw_init(void *handle)
772 {
773 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
774
775 /* enable pcie gen2/3 link */
776 soc15_pcie_gen3_enable(adev);
777 /* enable aspm */
778 soc15_program_aspm(adev);
779 /* setup nbio registers */
780 adev->nbio_funcs->init_registers(adev);
781 /* enable the doorbell aperture */
782 soc15_enable_doorbell_aperture(adev, true);
783
784 return 0;
785 }
786
soc15_common_hw_fini(void * handle)787 static int soc15_common_hw_fini(void *handle)
788 {
789 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
790
791 /* disable the doorbell aperture */
792 soc15_enable_doorbell_aperture(adev, false);
793 if (amdgpu_sriov_vf(adev))
794 xgpu_ai_mailbox_put_irq(adev);
795
796 return 0;
797 }
798
soc15_common_suspend(void * handle)799 static int soc15_common_suspend(void *handle)
800 {
801 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
802
803 return soc15_common_hw_fini(adev);
804 }
805
soc15_common_resume(void * handle)806 static int soc15_common_resume(void *handle)
807 {
808 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
809
810 return soc15_common_hw_init(adev);
811 }
812
soc15_common_is_idle(void * handle)813 static bool soc15_common_is_idle(void *handle)
814 {
815 return true;
816 }
817
soc15_common_wait_for_idle(void * handle)818 static int soc15_common_wait_for_idle(void *handle)
819 {
820 return 0;
821 }
822
soc15_common_soft_reset(void * handle)823 static int soc15_common_soft_reset(void *handle)
824 {
825 return 0;
826 }
827
soc15_update_hdp_light_sleep(struct amdgpu_device * adev,bool enable)828 static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable)
829 {
830 uint32_t def, data;
831
832 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
833
834 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
835 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
836 else
837 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
838
839 if (def != data)
840 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);
841 }
842
soc15_update_drm_clock_gating(struct amdgpu_device * adev,bool enable)843 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)
844 {
845 uint32_t def, data;
846
847 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
848
849 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG))
850 data &= ~(0x01000000 |
851 0x02000000 |
852 0x04000000 |
853 0x08000000 |
854 0x10000000 |
855 0x20000000 |
856 0x40000000 |
857 0x80000000);
858 else
859 data |= (0x01000000 |
860 0x02000000 |
861 0x04000000 |
862 0x08000000 |
863 0x10000000 |
864 0x20000000 |
865 0x40000000 |
866 0x80000000);
867
868 if (def != data)
869 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data);
870 }
871
soc15_update_drm_light_sleep(struct amdgpu_device * adev,bool enable)872 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable)
873 {
874 uint32_t def, data;
875
876 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
877
878 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
879 data |= 1;
880 else
881 data &= ~1;
882
883 if (def != data)
884 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);
885 }
886
soc15_update_rom_medium_grain_clock_gating(struct amdgpu_device * adev,bool enable)887 static void soc15_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
888 bool enable)
889 {
890 uint32_t def, data;
891
892 def = data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
893
894 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
895 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
896 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
897 else
898 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
899 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
900
901 if (def != data)
902 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0), data);
903 }
904
soc15_common_set_clockgating_state(void * handle,enum amd_clockgating_state state)905 static int soc15_common_set_clockgating_state(void *handle,
906 enum amd_clockgating_state state)
907 {
908 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
909
910 if (amdgpu_sriov_vf(adev))
911 return 0;
912
913 switch (adev->asic_type) {
914 case CHIP_VEGA10:
915 case CHIP_VEGA12:
916 case CHIP_VEGA20:
917 adev->nbio_funcs->update_medium_grain_clock_gating(adev,
918 state == AMD_CG_STATE_GATE ? true : false);
919 adev->nbio_funcs->update_medium_grain_light_sleep(adev,
920 state == AMD_CG_STATE_GATE ? true : false);
921 soc15_update_hdp_light_sleep(adev,
922 state == AMD_CG_STATE_GATE ? true : false);
923 soc15_update_drm_clock_gating(adev,
924 state == AMD_CG_STATE_GATE ? true : false);
925 soc15_update_drm_light_sleep(adev,
926 state == AMD_CG_STATE_GATE ? true : false);
927 soc15_update_rom_medium_grain_clock_gating(adev,
928 state == AMD_CG_STATE_GATE ? true : false);
929 adev->df_funcs->update_medium_grain_clock_gating(adev,
930 state == AMD_CG_STATE_GATE ? true : false);
931 break;
932 case CHIP_RAVEN:
933 adev->nbio_funcs->update_medium_grain_clock_gating(adev,
934 state == AMD_CG_STATE_GATE ? true : false);
935 adev->nbio_funcs->update_medium_grain_light_sleep(adev,
936 state == AMD_CG_STATE_GATE ? true : false);
937 soc15_update_hdp_light_sleep(adev,
938 state == AMD_CG_STATE_GATE ? true : false);
939 soc15_update_drm_clock_gating(adev,
940 state == AMD_CG_STATE_GATE ? true : false);
941 soc15_update_drm_light_sleep(adev,
942 state == AMD_CG_STATE_GATE ? true : false);
943 soc15_update_rom_medium_grain_clock_gating(adev,
944 state == AMD_CG_STATE_GATE ? true : false);
945 break;
946 default:
947 break;
948 }
949 return 0;
950 }
951
soc15_common_get_clockgating_state(void * handle,u32 * flags)952 static void soc15_common_get_clockgating_state(void *handle, u32 *flags)
953 {
954 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
955 int data;
956
957 if (amdgpu_sriov_vf(adev))
958 *flags = 0;
959
960 adev->nbio_funcs->get_clockgating_state(adev, flags);
961
962 /* AMD_CG_SUPPORT_HDP_LS */
963 data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
964 if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
965 *flags |= AMD_CG_SUPPORT_HDP_LS;
966
967 /* AMD_CG_SUPPORT_DRM_MGCG */
968 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
969 if (!(data & 0x01000000))
970 *flags |= AMD_CG_SUPPORT_DRM_MGCG;
971
972 /* AMD_CG_SUPPORT_DRM_LS */
973 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
974 if (data & 0x1)
975 *flags |= AMD_CG_SUPPORT_DRM_LS;
976
977 /* AMD_CG_SUPPORT_ROM_MGCG */
978 data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
979 if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
980 *flags |= AMD_CG_SUPPORT_ROM_MGCG;
981
982 adev->df_funcs->get_clockgating_state(adev, flags);
983 }
984
soc15_common_set_powergating_state(void * handle,enum amd_powergating_state state)985 static int soc15_common_set_powergating_state(void *handle,
986 enum amd_powergating_state state)
987 {
988 /* todo */
989 return 0;
990 }
991
992 const struct amd_ip_funcs soc15_common_ip_funcs = {
993 .name = "soc15_common",
994 .early_init = soc15_common_early_init,
995 .late_init = soc15_common_late_init,
996 .sw_init = soc15_common_sw_init,
997 .sw_fini = soc15_common_sw_fini,
998 .hw_init = soc15_common_hw_init,
999 .hw_fini = soc15_common_hw_fini,
1000 .suspend = soc15_common_suspend,
1001 .resume = soc15_common_resume,
1002 .is_idle = soc15_common_is_idle,
1003 .wait_for_idle = soc15_common_wait_for_idle,
1004 .soft_reset = soc15_common_soft_reset,
1005 .set_clockgating_state = soc15_common_set_clockgating_state,
1006 .set_powergating_state = soc15_common_set_powergating_state,
1007 .get_clockgating_state= soc15_common_get_clockgating_state,
1008 };
1009