1 /*
2 * Copyright (c) 2003 Hidetoshi Shimokawa
3 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the acknowledgement as bellow:
16 *
17 * This product includes software developed by K. Kobayashi and H. Shimokawa
18 *
19 * 4. The name of the author may not be used to endorse or promote products
20 * derived from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32 * POSSIBILITY OF SUCH DAMAGE.
33 *
34 *
35 */
36
37 #include <stand.h>
38 #include <btxv86.h>
39 #include <bootstrap.h>
40
41 #include <dev/firewire/firewire.h>
42 #include "fwohci.h"
43 #include <dev/firewire/fwohcireg.h>
44 #include <dev/firewire/firewire_phy.h>
45
46 static uint32_t fwphy_wrdata ( struct fwohci_softc *, uint32_t, uint32_t);
47 static uint32_t fwphy_rddata ( struct fwohci_softc *, uint32_t);
48 int firewire_debug=0;
49
50 #if 0
51 #define device_printf(a, x, ...) printf("FW1394: " x, ## __VA_ARGS__)
52 #else
53 #define device_printf(a, x, ...)
54 #endif
55
56 #define device_t int
57 #define DELAY(x) delay(x)
58
59 #define MAX_SPEED 3
60 #define MAXREC(x) (2 << (x))
61 char *linkspeed[] = {
62 "S100", "S200", "S400", "S800",
63 "S1600", "S3200", "undef", "undef"
64 };
65
66 /*
67 * Communication with PHY device
68 */
69 static uint32_t
fwphy_wrdata(struct fwohci_softc * sc,uint32_t addr,uint32_t data)70 fwphy_wrdata( struct fwohci_softc *sc, uint32_t addr, uint32_t data)
71 {
72 uint32_t fun;
73
74 addr &= 0xf;
75 data &= 0xff;
76
77 fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA));
78 OWRITE(sc, OHCI_PHYACCESS, fun);
79 DELAY(100);
80
81 return(fwphy_rddata( sc, addr));
82 }
83
84 static uint32_t
fwphy_rddata(struct fwohci_softc * sc,u_int addr)85 fwphy_rddata(struct fwohci_softc *sc, u_int addr)
86 {
87 uint32_t fun, stat;
88 u_int i, retry = 0;
89
90 addr &= 0xf;
91 #define MAX_RETRY 100
92 again:
93 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL);
94 fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR);
95 OWRITE(sc, OHCI_PHYACCESS, fun);
96 for ( i = 0 ; i < MAX_RETRY ; i ++ ){
97 fun = OREAD(sc, OHCI_PHYACCESS);
98 if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0)
99 break;
100 DELAY(100);
101 }
102 if(i >= MAX_RETRY) {
103 if (firewire_debug)
104 device_printf(sc->fc.dev, "phy read failed(1).\n");
105 if (++retry < MAX_RETRY) {
106 DELAY(100);
107 goto again;
108 }
109 }
110 /* Make sure that SCLK is started */
111 stat = OREAD(sc, FWOHCI_INTSTAT);
112 if ((stat & OHCI_INT_REG_FAIL) != 0 ||
113 ((fun >> PHYDEV_REGADDR) & 0xf) != addr) {
114 if (firewire_debug)
115 device_printf(sc->fc.dev, "phy read failed(2).\n");
116 if (++retry < MAX_RETRY) {
117 DELAY(100);
118 goto again;
119 }
120 }
121 if (firewire_debug || retry >= MAX_RETRY)
122 device_printf(sc->fc.dev,
123 "fwphy_rddata: 0x%x loop=%d, retry=%d\n", addr, i, retry);
124 #undef MAX_RETRY
125 return((fun >> PHYDEV_RDDATA )& 0xff);
126 }
127
128
129 static int
fwohci_probe_phy(struct fwohci_softc * sc,device_t dev)130 fwohci_probe_phy(struct fwohci_softc *sc, device_t dev)
131 {
132 uint32_t reg, reg2;
133 int e1394a = 1;
134 int nport, speed;
135 /*
136 * probe PHY parameters
137 * 0. to prove PHY version, whether compliance of 1394a.
138 * 1. to probe maximum speed supported by the PHY and
139 * number of port supported by core-logic.
140 * It is not actually available port on your PC .
141 */
142 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS);
143 DELAY(500);
144
145 reg = fwphy_rddata(sc, FW_PHY_SPD_REG);
146
147 if((reg >> 5) != 7 ){
148 nport = reg & FW_PHY_NP;
149 speed = reg & FW_PHY_SPD >> 6;
150 if (speed > MAX_SPEED) {
151 device_printf(dev, "invalid speed %d (fixed to %d).\n",
152 speed, MAX_SPEED);
153 speed = MAX_SPEED;
154 }
155 device_printf(dev,
156 "Phy 1394 only %s, %d ports.\n",
157 linkspeed[speed], nport);
158 }else{
159 reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG);
160 nport = reg & FW_PHY_NP;
161 speed = (reg2 & FW_PHY_ESPD) >> 5;
162 if (speed > MAX_SPEED) {
163 device_printf(dev, "invalid speed %d (fixed to %d).\n",
164 speed, MAX_SPEED);
165 speed = MAX_SPEED;
166 }
167 device_printf(dev,
168 "Phy 1394a available %s, %d ports.\n",
169 linkspeed[speed], nport);
170
171 /* check programPhyEnable */
172 reg2 = fwphy_rddata(sc, 5);
173 #if 0
174 if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) {
175 #else /* XXX force to enable 1394a */
176 if (e1394a) {
177 #endif
178 if (firewire_debug)
179 device_printf(dev,
180 "Enable 1394a Enhancements\n");
181 /* enable EAA EMC */
182 reg2 |= 0x03;
183 /* set aPhyEnhanceEnable */
184 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN);
185 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY);
186 } else {
187 /* for safe */
188 reg2 &= ~0x83;
189 }
190 reg2 = fwphy_wrdata(sc, 5, reg2);
191 }
192 sc->speed = speed;
193
194 reg = fwphy_rddata(sc, FW_PHY_SPD_REG);
195 if((reg >> 5) == 7 ){
196 reg = fwphy_rddata(sc, 4);
197 reg |= 1 << 6;
198 fwphy_wrdata(sc, 4, reg);
199 reg = fwphy_rddata(sc, 4);
200 }
201 return 0;
202 }
203
204
205 void
206 fwohci_reset(struct fwohci_softc *sc, device_t dev)
207 {
208 int i, max_rec, speed;
209 uint32_t reg, reg2;
210
211 /* Disable interrupts */
212 OWRITE(sc, FWOHCI_INTMASKCLR, ~0);
213
214 /* FLUSH FIFO and reset Transmitter/Receiver */
215 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET);
216 if (firewire_debug)
217 device_printf(dev, "resetting OHCI...");
218 i = 0;
219 while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) {
220 if (i++ > 100) break;
221 DELAY(1000);
222 }
223 if (firewire_debug)
224 printf("done (loop=%d)\n", i);
225
226 /* Probe phy */
227 fwohci_probe_phy(sc, dev);
228
229 /* Probe link */
230 reg = OREAD(sc, OHCI_BUS_OPT);
231 reg2 = reg | OHCI_BUSFNC;
232 max_rec = (reg & 0x0000f000) >> 12;
233 speed = (reg & 0x00000007);
234 device_printf(dev, "Link %s, max_rec %d bytes.\n",
235 linkspeed[speed], MAXREC(max_rec));
236 /* XXX fix max_rec */
237 sc->maxrec = sc->speed + 8;
238 if (max_rec != sc->maxrec) {
239 reg2 = (reg2 & 0xffff0fff) | (sc->maxrec << 12);
240 device_printf(dev, "max_rec %d -> %d\n",
241 MAXREC(max_rec), MAXREC(sc->maxrec));
242 }
243 if (firewire_debug)
244 device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2);
245 OWRITE(sc, OHCI_BUS_OPT, reg2);
246
247 /* Initialize registers */
248 OWRITE(sc, OHCI_CROMHDR, sc->config_rom[0]);
249 OWRITE(sc, OHCI_CROMPTR, VTOP(sc->config_rom));
250 #if 0
251 OWRITE(sc, OHCI_SID_BUF, sc->sid_dma.bus_addr);
252 #endif
253 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND);
254 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR);
255 #if 0
256 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID);
257 #endif
258
259 /* Enable link */
260 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN);
261 }
262
263 int
264 fwohci_init(struct fwohci_softc *sc, device_t dev)
265 {
266 int i, mver;
267 uint32_t reg;
268 uint8_t ui[8];
269
270 /* OHCI version */
271 reg = OREAD(sc, OHCI_VERSION);
272 mver = (reg >> 16) & 0xff;
273 device_printf(dev, "OHCI version %x.%x (ROM=%d)\n",
274 mver, reg & 0xff, (reg>>24) & 1);
275 if (mver < 1 || mver > 9) {
276 device_printf(dev, "invalid OHCI version\n");
277 return (ENXIO);
278 }
279
280 /* Available Isochronous DMA channel probe */
281 OWRITE(sc, OHCI_IT_MASK, 0xffffffff);
282 OWRITE(sc, OHCI_IR_MASK, 0xffffffff);
283 reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK);
284 OWRITE(sc, OHCI_IT_MASKCLR, 0xffffffff);
285 OWRITE(sc, OHCI_IR_MASKCLR, 0xffffffff);
286 for (i = 0; i < 0x20; i++)
287 if ((reg & (1 << i)) == 0)
288 break;
289 device_printf(dev, "No. of Isochronous channels is %d.\n", i);
290 if (i == 0)
291 return (ENXIO);
292
293 #if 0
294 /* SID receive buffer must align 2^11 */
295 #define OHCI_SIDSIZE (1 << 11)
296 sc->sid_buf = fwdma_malloc(&sc->fc, OHCI_SIDSIZE, OHCI_SIDSIZE,
297 &sc->sid_dma, BUS_DMA_WAITOK);
298 if (sc->sid_buf == NULL) {
299 device_printf(dev, "sid_buf alloc failed.");
300 return ENOMEM;
301 }
302 #endif
303
304 sc->eui.hi = OREAD(sc, FWOHCIGUID_H);
305 sc->eui.lo = OREAD(sc, FWOHCIGUID_L);
306 for( i = 0 ; i < 8 ; i ++)
307 ui[i] = FW_EUI64_BYTE(&sc->eui,i);
308 device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n",
309 ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]);
310 fwohci_reset(sc, dev);
311
312 return 0;
313 }
314
315 void
316 fwohci_ibr(struct fwohci_softc *sc)
317 {
318 uint32_t fun;
319
320 device_printf(sc->dev, "Initiate bus reset\n");
321
322 /*
323 * Make sure our cached values from the config rom are
324 * initialised.
325 */
326 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->config_rom[0]));
327 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->config_rom[2]));
328
329 /*
330 * Set root hold-off bit so that non cyclemaster capable node
331 * shouldn't became the root node.
332 */
333 #if 1
334 fun = fwphy_rddata(sc, FW_PHY_IBR_REG);
335 fun |= FW_PHY_IBR;
336 fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun);
337 #else /* Short bus reset */
338 fun = fwphy_rddata(sc, FW_PHY_ISBR_REG);
339 fun |= FW_PHY_ISBR;
340 fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun);
341 #endif
342 }
343
344
345 void
346 fwohci_sid(struct fwohci_softc *sc)
347 {
348 uint32_t node_id;
349 int plen;
350
351 node_id = OREAD(sc, FWOHCI_NODEID);
352 if (!(node_id & OHCI_NODE_VALID)) {
353 #if 0
354 printf("Bus reset failure\n");
355 #endif
356 return;
357 }
358
359 /* Enable bus reset interrupt */
360 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R);
361 /* Allow async. request to us */
362 OWRITE(sc, OHCI_AREQHI, 1 << 31);
363 /* XXX insecure ?? */
364 OWRITE(sc, OHCI_PREQHI, 0x7fffffff);
365 OWRITE(sc, OHCI_PREQLO, 0xffffffff);
366 OWRITE(sc, OHCI_PREQUPPER, 0x10000);
367 /* Set ATRetries register */
368 OWRITE(sc, OHCI_ATRETRY, 1<<(13+16) | 0xfff);
369 /*
370 ** Checking whether the node is root or not. If root, turn on
371 ** cycle master.
372 */
373 plen = OREAD(sc, OHCI_SID_CNT);
374 device_printf(fc->dev, "node_id=0x%08x, gen=%d, ",
375 node_id, (plen >> 16) & 0xff);
376 if (node_id & OHCI_NODE_ROOT) {
377 device_printf(sc->dev, "CYCLEMASTER mode\n");
378 OWRITE(sc, OHCI_LNKCTL,
379 OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER);
380 } else {
381 device_printf(sc->dev, "non CYCLEMASTER mode\n");
382 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR);
383 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER);
384 }
385 if (plen & OHCI_SID_ERR) {
386 device_printf(fc->dev, "SID Error\n");
387 return;
388 }
389 device_printf(sc->dev, "bus reset phase done\n");
390 sc->state = FWOHCI_STATE_NORMAL;
391 }
392
393 static void
394 fwohci_intr_body(struct fwohci_softc *sc, uint32_t stat, int count)
395 {
396 #undef OHCI_DEBUG
397 #ifdef OHCI_DEBUG
398 #if 0
399 if(stat & OREAD(sc, FWOHCI_INTMASK))
400 #else
401 if (1)
402 #endif
403 device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n",
404 stat & OHCI_INT_EN ? "DMA_EN ":"",
405 stat & OHCI_INT_PHY_REG ? "PHY_REG ":"",
406 stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"",
407 stat & OHCI_INT_ERR ? "INT_ERR ":"",
408 stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"",
409 stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"",
410 stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"",
411 stat & OHCI_INT_CYC_START ? "CYC_START ":"",
412 stat & OHCI_INT_PHY_INT ? "PHY_INT ":"",
413 stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"",
414 stat & OHCI_INT_PHY_SID ? "SID ":"",
415 stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"",
416 stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"",
417 stat & OHCI_INT_DMA_IR ? "DMA_IR ":"",
418 stat & OHCI_INT_DMA_IT ? "DMA_IT " :"",
419 stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"",
420 stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"",
421 stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"",
422 stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"",
423 stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"",
424 stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"",
425 stat, OREAD(sc, FWOHCI_INTMASK)
426 );
427 #endif
428 /* Bus reset */
429 if(stat & OHCI_INT_PHY_BUS_R ){
430 device_printf(fc->dev, "BUS reset\n");
431 if (sc->state == FWOHCI_STATE_BUSRESET)
432 goto busresetout;
433 sc->state = FWOHCI_STATE_BUSRESET;
434 /* Disable bus reset interrupt until sid recv. */
435 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_PHY_BUS_R);
436
437 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST);
438 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC);
439
440 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->config_rom[0]));
441 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->config_rom[2]));
442 } else if (sc->state == FWOHCI_STATE_BUSRESET) {
443 fwohci_sid(sc);
444 }
445 busresetout:
446 return;
447 }
448
449 static uint32_t
450 fwochi_check_stat(struct fwohci_softc *sc)
451 {
452 uint32_t stat;
453
454 stat = OREAD(sc, FWOHCI_INTSTAT);
455 if (stat == 0xffffffff) {
456 device_printf(sc->fc.dev,
457 "device physically ejected?\n");
458 return(stat);
459 }
460 if (stat)
461 OWRITE(sc, FWOHCI_INTSTATCLR, stat);
462 return(stat);
463 }
464
465 void
466 fwohci_poll(struct fwohci_softc *sc)
467 {
468 uint32_t stat;
469
470 stat = fwochi_check_stat(sc);
471 if (stat != 0xffffffff)
472 fwohci_intr_body(sc, stat, 1);
473 }
474