1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 1998 Doug Rabson
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28 #ifndef _MACHINE_ATOMIC_H_
29 #define _MACHINE_ATOMIC_H_
30
31 #ifndef _SYS_CDEFS_H_
32 #error this file needs sys/cdefs.h as a prerequisite
33 #endif
34
35 /*
36 * To express interprocessor (as opposed to processor and device) memory
37 * ordering constraints, use the atomic_*() functions with acquire and release
38 * semantics rather than the *mb() functions. An architecture's memory
39 * ordering (or memory consistency) model governs the order in which a
40 * program's accesses to different locations may be performed by an
41 * implementation of that architecture. In general, for memory regions
42 * defined as writeback cacheable, the memory ordering implemented by amd64
43 * processors preserves the program ordering of a load followed by a load, a
44 * load followed by a store, and a store followed by a store. Only a store
45 * followed by a load to a different memory location may be reordered.
46 * Therefore, except for special cases, like non-temporal memory accesses or
47 * memory regions defined as write combining, the memory ordering effects
48 * provided by the sfence instruction in the wmb() function and the lfence
49 * instruction in the rmb() function are redundant. In contrast, the
50 * atomic_*() functions with acquire and release semantics do not perform
51 * redundant instructions for ordinary cases of interprocessor memory
52 * ordering on any architecture.
53 */
54 #define mb() __asm __volatile("mfence;" : : : "memory")
55 #define wmb() __asm __volatile("sfence;" : : : "memory")
56 #define rmb() __asm __volatile("lfence;" : : : "memory")
57
58 #ifdef _KERNEL
59 /*
60 * OFFSETOF_MONITORBUF == __pcpu_offset(pc_monitorbuf).
61 *
62 * The open-coded number is used instead of the symbolic expression to
63 * avoid a dependency on sys/pcpu.h in machine/atomic.h consumers.
64 * An assertion in amd64/vm_machdep.c ensures that the value is correct.
65 */
66 #define OFFSETOF_MONITORBUF 0x100
67 #endif
68
69 #if defined(SAN_NEEDS_INTERCEPTORS) && !defined(SAN_RUNTIME)
70 #include <sys/atomic_san.h>
71 #else
72 #include <sys/atomic_common.h>
73
74 /*
75 * Various simple operations on memory, each of which is atomic in the
76 * presence of interrupts and multiple processors.
77 *
78 * atomic_set_char(P, V) (*(u_char *)(P) |= (V))
79 * atomic_clear_char(P, V) (*(u_char *)(P) &= ~(V))
80 * atomic_add_char(P, V) (*(u_char *)(P) += (V))
81 * atomic_subtract_char(P, V) (*(u_char *)(P) -= (V))
82 *
83 * atomic_set_short(P, V) (*(u_short *)(P) |= (V))
84 * atomic_clear_short(P, V) (*(u_short *)(P) &= ~(V))
85 * atomic_add_short(P, V) (*(u_short *)(P) += (V))
86 * atomic_subtract_short(P, V) (*(u_short *)(P) -= (V))
87 *
88 * atomic_set_int(P, V) (*(u_int *)(P) |= (V))
89 * atomic_clear_int(P, V) (*(u_int *)(P) &= ~(V))
90 * atomic_add_int(P, V) (*(u_int *)(P) += (V))
91 * atomic_subtract_int(P, V) (*(u_int *)(P) -= (V))
92 * atomic_swap_int(P, V) (return (*(u_int *)(P)); *(u_int *)(P) = (V);)
93 * atomic_readandclear_int(P) (return (*(u_int *)(P)); *(u_int *)(P) = 0;)
94 *
95 * atomic_set_long(P, V) (*(u_long *)(P) |= (V))
96 * atomic_clear_long(P, V) (*(u_long *)(P) &= ~(V))
97 * atomic_add_long(P, V) (*(u_long *)(P) += (V))
98 * atomic_subtract_long(P, V) (*(u_long *)(P) -= (V))
99 * atomic_swap_long(P, V) (return (*(u_long *)(P)); *(u_long *)(P) = (V);)
100 * atomic_readandclear_long(P) (return (*(u_long *)(P)); *(u_long *)(P) = 0;)
101 */
102
103 #if !defined(__GNUCLIKE_ASM)
104 #define ATOMIC_ASM(NAME, TYPE, OP, CONS, V) \
105 void atomic_##NAME##_##TYPE(volatile u_##TYPE *p, u_##TYPE v); \
106 void atomic_##NAME##_barr_##TYPE(volatile u_##TYPE *p, u_##TYPE v)
107
108 int atomic_cmpset_char(volatile u_char *dst, u_char expect, u_char src);
109 int atomic_cmpset_short(volatile u_short *dst, u_short expect, u_short src);
110 int atomic_cmpset_int(volatile u_int *dst, u_int expect, u_int src);
111 int atomic_cmpset_long(volatile u_long *dst, u_long expect, u_long src);
112 int atomic_fcmpset_char(volatile u_char *dst, u_char *expect, u_char src);
113 int atomic_fcmpset_short(volatile u_short *dst, u_short *expect,
114 u_short src);
115 int atomic_fcmpset_int(volatile u_int *dst, u_int *expect, u_int src);
116 int atomic_fcmpset_long(volatile u_long *dst, u_long *expect, u_long src);
117 u_int atomic_fetchadd_int(volatile u_int *p, u_int v);
118 u_long atomic_fetchadd_long(volatile u_long *p, u_long v);
119 int atomic_testandset_int(volatile u_int *p, u_int v);
120 int atomic_testandset_long(volatile u_long *p, u_int v);
121 int atomic_testandclear_int(volatile u_int *p, u_int v);
122 int atomic_testandclear_long(volatile u_long *p, u_int v);
123 void atomic_thread_fence_acq(void);
124 void atomic_thread_fence_acq_rel(void);
125 void atomic_thread_fence_rel(void);
126 void atomic_thread_fence_seq_cst(void);
127
128 #define ATOMIC_LOAD(TYPE) \
129 u_##TYPE atomic_load_acq_##TYPE(volatile u_##TYPE *p)
130 #define ATOMIC_STORE(TYPE) \
131 void atomic_store_rel_##TYPE(volatile u_##TYPE *p, u_##TYPE v)
132
133 #else /* !__GNUCLIKE_ASM */
134
135 /*
136 * Always use lock prefixes. The result is slighly less optimal for
137 * UP systems, but it matters less now, and sometimes UP is emulated
138 * over SMP.
139 *
140 * The assembly is volatilized to avoid code chunk removal by the compiler.
141 * GCC aggressively reorders operations and memory clobbering is necessary
142 * in order to avoid that for memory barriers.
143 */
144 #define ATOMIC_ASM(NAME, TYPE, OP, CONS, V) \
145 static __inline void \
146 atomic_##NAME##_##TYPE(volatile u_##TYPE *p, u_##TYPE v)\
147 { \
148 __asm __volatile("lock; " OP \
149 : "+m" (*p) \
150 : CONS (V) \
151 : "cc"); \
152 } \
153 \
154 static __inline void \
155 atomic_##NAME##_barr_##TYPE(volatile u_##TYPE *p, u_##TYPE v)\
156 { \
157 __asm __volatile("lock; " OP \
158 : "+m" (*p) \
159 : CONS (V) \
160 : "memory", "cc"); \
161 } \
162 struct __hack
163
164 /*
165 * Atomic compare and set, used by the mutex functions.
166 *
167 * cmpset:
168 * if (*dst == expect)
169 * *dst = src
170 *
171 * fcmpset:
172 * if (*dst == *expect)
173 * *dst = src
174 * else
175 * *expect = *dst
176 *
177 * Returns 0 on failure, non-zero on success.
178 */
179 #define ATOMIC_CMPSET(TYPE) \
180 static __inline int \
181 atomic_cmpset_##TYPE(volatile u_##TYPE *dst, u_##TYPE expect, u_##TYPE src) \
182 { \
183 u_char res; \
184 \
185 __asm __volatile( \
186 " lock; cmpxchg %3,%1 ; " \
187 "# atomic_cmpset_" #TYPE " " \
188 : "=@cce" (res), /* 0 */ \
189 "+m" (*dst), /* 1 */ \
190 "+a" (expect) /* 2 */ \
191 : "r" (src) /* 3 */ \
192 : "memory", "cc"); \
193 return (res); \
194 } \
195 \
196 static __inline int \
197 atomic_fcmpset_##TYPE(volatile u_##TYPE *dst, u_##TYPE *expect, u_##TYPE src) \
198 { \
199 u_char res; \
200 \
201 __asm __volatile( \
202 " lock; cmpxchg %3,%1 ; " \
203 "# atomic_fcmpset_" #TYPE " " \
204 : "=@cce" (res), /* 0 */ \
205 "+m" (*dst), /* 1 */ \
206 "+a" (*expect) /* 2 */ \
207 : "r" (src) /* 3 */ \
208 : "memory", "cc"); \
209 return (res); \
210 }
211
212 ATOMIC_CMPSET(char);
213 ATOMIC_CMPSET(short);
214 ATOMIC_CMPSET(int);
215 ATOMIC_CMPSET(long);
216
217 /*
218 * Atomically add the value of v to the integer pointed to by p and return
219 * the previous value of *p.
220 */
221 static __inline u_int
atomic_fetchadd_int(volatile u_int * p,u_int v)222 atomic_fetchadd_int(volatile u_int *p, u_int v)
223 {
224
225 __asm __volatile(
226 " lock; xaddl %0,%1 ; "
227 "# atomic_fetchadd_int"
228 : "+r" (v), /* 0 */
229 "+m" (*p) /* 1 */
230 : : "cc");
231 return (v);
232 }
233
234 /*
235 * Atomically add the value of v to the long integer pointed to by p and return
236 * the previous value of *p.
237 */
238 static __inline u_long
atomic_fetchadd_long(volatile u_long * p,u_long v)239 atomic_fetchadd_long(volatile u_long *p, u_long v)
240 {
241
242 __asm __volatile(
243 " lock; xaddq %0,%1 ; "
244 "# atomic_fetchadd_long"
245 : "+r" (v), /* 0 */
246 "+m" (*p) /* 1 */
247 : : "cc");
248 return (v);
249 }
250
251 static __inline int
atomic_testandset_int(volatile u_int * p,u_int v)252 atomic_testandset_int(volatile u_int *p, u_int v)
253 {
254 u_char res;
255
256 __asm __volatile(
257 " lock; btsl %2,%1 ; "
258 "# atomic_testandset_int"
259 : "=@ccc" (res), /* 0 */
260 "+m" (*p) /* 1 */
261 : "Ir" (v & 0x1f) /* 2 */
262 : "cc");
263 return (res);
264 }
265
266 static __inline int
atomic_testandset_long(volatile u_long * p,u_int v)267 atomic_testandset_long(volatile u_long *p, u_int v)
268 {
269 u_char res;
270
271 __asm __volatile(
272 " lock; btsq %2,%1 ; "
273 "# atomic_testandset_long"
274 : "=@ccc" (res), /* 0 */
275 "+m" (*p) /* 1 */
276 : "Jr" ((u_long)(v & 0x3f)) /* 2 */
277 : "cc");
278 return (res);
279 }
280
281 static __inline int
atomic_testandclear_int(volatile u_int * p,u_int v)282 atomic_testandclear_int(volatile u_int *p, u_int v)
283 {
284 u_char res;
285
286 __asm __volatile(
287 " lock; btrl %2,%1 ; "
288 "# atomic_testandclear_int"
289 : "=@ccc" (res), /* 0 */
290 "+m" (*p) /* 1 */
291 : "Ir" (v & 0x1f) /* 2 */
292 : "cc");
293 return (res);
294 }
295
296 static __inline int
atomic_testandclear_long(volatile u_long * p,u_int v)297 atomic_testandclear_long(volatile u_long *p, u_int v)
298 {
299 u_char res;
300
301 __asm __volatile(
302 " lock; btrq %2,%1 ; "
303 "# atomic_testandclear_long"
304 : "=@ccc" (res), /* 0 */
305 "+m" (*p) /* 1 */
306 : "Jr" ((u_long)(v & 0x3f)) /* 2 */
307 : "cc");
308 return (res);
309 }
310
311 /*
312 * We assume that a = b will do atomic loads and stores. Due to the
313 * IA32 memory model, a simple store guarantees release semantics.
314 *
315 * However, a load may pass a store if they are performed on distinct
316 * addresses, so we need a Store/Load barrier for sequentially
317 * consistent fences in SMP kernels. We use "lock addl $0,mem" for a
318 * Store/Load barrier, as recommended by the AMD Software Optimization
319 * Guide, and not mfence. To avoid false data dependencies, we use a
320 * special address for "mem". In the kernel, we use a private per-cpu
321 * cache line. In user space, we use a word in the stack's red zone
322 * (-8(%rsp)).
323 */
324
325 static __inline void
__storeload_barrier(void)326 __storeload_barrier(void)
327 {
328 #if defined(_KERNEL)
329 __asm __volatile("lock; addl $0,%%gs:%0"
330 : "+m" (*(u_int *)OFFSETOF_MONITORBUF) : : "memory", "cc");
331 #else /* !_KERNEL */
332 __asm __volatile("lock; addl $0,-8(%%rsp)" : : : "memory", "cc");
333 #endif /* _KERNEL*/
334 }
335
336 #define ATOMIC_LOAD(TYPE) \
337 static __inline u_##TYPE \
338 atomic_load_acq_##TYPE(const volatile u_##TYPE *p) \
339 { \
340 u_##TYPE res; \
341 \
342 res = *p; \
343 __compiler_membar(); \
344 return (res); \
345 } \
346 struct __hack
347
348 #define ATOMIC_STORE(TYPE) \
349 static __inline void \
350 atomic_store_rel_##TYPE(volatile u_##TYPE *p, u_##TYPE v) \
351 { \
352 \
353 __compiler_membar(); \
354 *p = v; \
355 } \
356 struct __hack
357
358 static __inline void
atomic_thread_fence_acq(void)359 atomic_thread_fence_acq(void)
360 {
361
362 __compiler_membar();
363 }
364
365 static __inline void
atomic_thread_fence_rel(void)366 atomic_thread_fence_rel(void)
367 {
368
369 __compiler_membar();
370 }
371
372 static __inline void
atomic_thread_fence_acq_rel(void)373 atomic_thread_fence_acq_rel(void)
374 {
375
376 __compiler_membar();
377 }
378
379 static __inline void
atomic_thread_fence_seq_cst(void)380 atomic_thread_fence_seq_cst(void)
381 {
382
383 __storeload_barrier();
384 }
385
386 #endif /* !__GNUCLIKE_ASM */
387
388 ATOMIC_ASM(set, char, "orb %b1,%0", "iq", v);
389 ATOMIC_ASM(clear, char, "andb %b1,%0", "iq", ~v);
390 ATOMIC_ASM(add, char, "addb %b1,%0", "iq", v);
391 ATOMIC_ASM(subtract, char, "subb %b1,%0", "iq", v);
392
393 ATOMIC_ASM(set, short, "orw %w1,%0", "ir", v);
394 ATOMIC_ASM(clear, short, "andw %w1,%0", "ir", ~v);
395 ATOMIC_ASM(add, short, "addw %w1,%0", "ir", v);
396 ATOMIC_ASM(subtract, short, "subw %w1,%0", "ir", v);
397
398 ATOMIC_ASM(set, int, "orl %1,%0", "ir", v);
399 ATOMIC_ASM(clear, int, "andl %1,%0", "ir", ~v);
400 ATOMIC_ASM(add, int, "addl %1,%0", "ir", v);
401 ATOMIC_ASM(subtract, int, "subl %1,%0", "ir", v);
402
403 ATOMIC_ASM(set, long, "orq %1,%0", "er", v);
404 ATOMIC_ASM(clear, long, "andq %1,%0", "er", ~v);
405 ATOMIC_ASM(add, long, "addq %1,%0", "er", v);
406 ATOMIC_ASM(subtract, long, "subq %1,%0", "er", v);
407
408 #define ATOMIC_LOADSTORE(TYPE) \
409 ATOMIC_LOAD(TYPE); \
410 ATOMIC_STORE(TYPE)
411
412 ATOMIC_LOADSTORE(char);
413 ATOMIC_LOADSTORE(short);
414 ATOMIC_LOADSTORE(int);
415 ATOMIC_LOADSTORE(long);
416
417 #undef ATOMIC_ASM
418 #undef ATOMIC_LOAD
419 #undef ATOMIC_STORE
420 #undef ATOMIC_LOADSTORE
421
422 /* Read the current value and store a new value in the destination. */
423 #ifdef __GNUCLIKE_ASM
424
425 static __inline u_int
atomic_swap_int(volatile u_int * p,u_int v)426 atomic_swap_int(volatile u_int *p, u_int v)
427 {
428
429 __asm __volatile(
430 " xchgl %1,%0 ; "
431 "# atomic_swap_int"
432 : "+r" (v), /* 0 */
433 "+m" (*p)); /* 1 */
434 return (v);
435 }
436
437 static __inline u_long
atomic_swap_long(volatile u_long * p,u_long v)438 atomic_swap_long(volatile u_long *p, u_long v)
439 {
440
441 __asm __volatile(
442 " xchgq %1,%0 ; "
443 "# atomic_swap_long"
444 : "+r" (v), /* 0 */
445 "+m" (*p)); /* 1 */
446 return (v);
447 }
448
449 #else /* !__GNUCLIKE_ASM */
450
451 u_int atomic_swap_int(volatile u_int *p, u_int v);
452 u_long atomic_swap_long(volatile u_long *p, u_long v);
453
454 #endif /* __GNUCLIKE_ASM */
455
456 #define atomic_set_acq_char atomic_set_barr_char
457 #define atomic_set_rel_char atomic_set_barr_char
458 #define atomic_clear_acq_char atomic_clear_barr_char
459 #define atomic_clear_rel_char atomic_clear_barr_char
460 #define atomic_add_acq_char atomic_add_barr_char
461 #define atomic_add_rel_char atomic_add_barr_char
462 #define atomic_subtract_acq_char atomic_subtract_barr_char
463 #define atomic_subtract_rel_char atomic_subtract_barr_char
464 #define atomic_cmpset_acq_char atomic_cmpset_char
465 #define atomic_cmpset_rel_char atomic_cmpset_char
466 #define atomic_fcmpset_acq_char atomic_fcmpset_char
467 #define atomic_fcmpset_rel_char atomic_fcmpset_char
468
469 #define atomic_set_acq_short atomic_set_barr_short
470 #define atomic_set_rel_short atomic_set_barr_short
471 #define atomic_clear_acq_short atomic_clear_barr_short
472 #define atomic_clear_rel_short atomic_clear_barr_short
473 #define atomic_add_acq_short atomic_add_barr_short
474 #define atomic_add_rel_short atomic_add_barr_short
475 #define atomic_subtract_acq_short atomic_subtract_barr_short
476 #define atomic_subtract_rel_short atomic_subtract_barr_short
477 #define atomic_cmpset_acq_short atomic_cmpset_short
478 #define atomic_cmpset_rel_short atomic_cmpset_short
479 #define atomic_fcmpset_acq_short atomic_fcmpset_short
480 #define atomic_fcmpset_rel_short atomic_fcmpset_short
481
482 #define atomic_set_acq_int atomic_set_barr_int
483 #define atomic_set_rel_int atomic_set_barr_int
484 #define atomic_clear_acq_int atomic_clear_barr_int
485 #define atomic_clear_rel_int atomic_clear_barr_int
486 #define atomic_add_acq_int atomic_add_barr_int
487 #define atomic_add_rel_int atomic_add_barr_int
488 #define atomic_subtract_acq_int atomic_subtract_barr_int
489 #define atomic_subtract_rel_int atomic_subtract_barr_int
490 #define atomic_cmpset_acq_int atomic_cmpset_int
491 #define atomic_cmpset_rel_int atomic_cmpset_int
492 #define atomic_fcmpset_acq_int atomic_fcmpset_int
493 #define atomic_fcmpset_rel_int atomic_fcmpset_int
494
495 #define atomic_set_acq_long atomic_set_barr_long
496 #define atomic_set_rel_long atomic_set_barr_long
497 #define atomic_clear_acq_long atomic_clear_barr_long
498 #define atomic_clear_rel_long atomic_clear_barr_long
499 #define atomic_add_acq_long atomic_add_barr_long
500 #define atomic_add_rel_long atomic_add_barr_long
501 #define atomic_subtract_acq_long atomic_subtract_barr_long
502 #define atomic_subtract_rel_long atomic_subtract_barr_long
503 #define atomic_cmpset_acq_long atomic_cmpset_long
504 #define atomic_cmpset_rel_long atomic_cmpset_long
505 #define atomic_fcmpset_acq_long atomic_fcmpset_long
506 #define atomic_fcmpset_rel_long atomic_fcmpset_long
507
508 #define atomic_readandclear_int(p) atomic_swap_int(p, 0)
509 #define atomic_readandclear_long(p) atomic_swap_long(p, 0)
510 #define atomic_testandset_acq_long atomic_testandset_long
511
512 /* Operations on 8-bit bytes. */
513 #define atomic_set_8 atomic_set_char
514 #define atomic_set_acq_8 atomic_set_acq_char
515 #define atomic_set_rel_8 atomic_set_rel_char
516 #define atomic_clear_8 atomic_clear_char
517 #define atomic_clear_acq_8 atomic_clear_acq_char
518 #define atomic_clear_rel_8 atomic_clear_rel_char
519 #define atomic_add_8 atomic_add_char
520 #define atomic_add_acq_8 atomic_add_acq_char
521 #define atomic_add_rel_8 atomic_add_rel_char
522 #define atomic_subtract_8 atomic_subtract_char
523 #define atomic_subtract_acq_8 atomic_subtract_acq_char
524 #define atomic_subtract_rel_8 atomic_subtract_rel_char
525 #define atomic_load_acq_8 atomic_load_acq_char
526 #define atomic_store_rel_8 atomic_store_rel_char
527 #define atomic_cmpset_8 atomic_cmpset_char
528 #define atomic_cmpset_acq_8 atomic_cmpset_acq_char
529 #define atomic_cmpset_rel_8 atomic_cmpset_rel_char
530 #define atomic_fcmpset_8 atomic_fcmpset_char
531 #define atomic_fcmpset_acq_8 atomic_fcmpset_acq_char
532 #define atomic_fcmpset_rel_8 atomic_fcmpset_rel_char
533
534 /* Operations on 16-bit words. */
535 #define atomic_set_16 atomic_set_short
536 #define atomic_set_acq_16 atomic_set_acq_short
537 #define atomic_set_rel_16 atomic_set_rel_short
538 #define atomic_clear_16 atomic_clear_short
539 #define atomic_clear_acq_16 atomic_clear_acq_short
540 #define atomic_clear_rel_16 atomic_clear_rel_short
541 #define atomic_add_16 atomic_add_short
542 #define atomic_add_acq_16 atomic_add_acq_short
543 #define atomic_add_rel_16 atomic_add_rel_short
544 #define atomic_subtract_16 atomic_subtract_short
545 #define atomic_subtract_acq_16 atomic_subtract_acq_short
546 #define atomic_subtract_rel_16 atomic_subtract_rel_short
547 #define atomic_load_acq_16 atomic_load_acq_short
548 #define atomic_store_rel_16 atomic_store_rel_short
549 #define atomic_cmpset_16 atomic_cmpset_short
550 #define atomic_cmpset_acq_16 atomic_cmpset_acq_short
551 #define atomic_cmpset_rel_16 atomic_cmpset_rel_short
552 #define atomic_fcmpset_16 atomic_fcmpset_short
553 #define atomic_fcmpset_acq_16 atomic_fcmpset_acq_short
554 #define atomic_fcmpset_rel_16 atomic_fcmpset_rel_short
555
556 /* Operations on 32-bit double words. */
557 #define atomic_set_32 atomic_set_int
558 #define atomic_set_acq_32 atomic_set_acq_int
559 #define atomic_set_rel_32 atomic_set_rel_int
560 #define atomic_clear_32 atomic_clear_int
561 #define atomic_clear_acq_32 atomic_clear_acq_int
562 #define atomic_clear_rel_32 atomic_clear_rel_int
563 #define atomic_add_32 atomic_add_int
564 #define atomic_add_acq_32 atomic_add_acq_int
565 #define atomic_add_rel_32 atomic_add_rel_int
566 #define atomic_subtract_32 atomic_subtract_int
567 #define atomic_subtract_acq_32 atomic_subtract_acq_int
568 #define atomic_subtract_rel_32 atomic_subtract_rel_int
569 #define atomic_load_acq_32 atomic_load_acq_int
570 #define atomic_store_rel_32 atomic_store_rel_int
571 #define atomic_cmpset_32 atomic_cmpset_int
572 #define atomic_cmpset_acq_32 atomic_cmpset_acq_int
573 #define atomic_cmpset_rel_32 atomic_cmpset_rel_int
574 #define atomic_fcmpset_32 atomic_fcmpset_int
575 #define atomic_fcmpset_acq_32 atomic_fcmpset_acq_int
576 #define atomic_fcmpset_rel_32 atomic_fcmpset_rel_int
577 #define atomic_swap_32 atomic_swap_int
578 #define atomic_readandclear_32 atomic_readandclear_int
579 #define atomic_fetchadd_32 atomic_fetchadd_int
580 #define atomic_testandset_32 atomic_testandset_int
581 #define atomic_testandclear_32 atomic_testandclear_int
582
583 /* Operations on 64-bit quad words. */
584 #define atomic_set_64 atomic_set_long
585 #define atomic_set_acq_64 atomic_set_acq_long
586 #define atomic_set_rel_64 atomic_set_rel_long
587 #define atomic_clear_64 atomic_clear_long
588 #define atomic_clear_acq_64 atomic_clear_acq_long
589 #define atomic_clear_rel_64 atomic_clear_rel_long
590 #define atomic_add_64 atomic_add_long
591 #define atomic_add_acq_64 atomic_add_acq_long
592 #define atomic_add_rel_64 atomic_add_rel_long
593 #define atomic_subtract_64 atomic_subtract_long
594 #define atomic_subtract_acq_64 atomic_subtract_acq_long
595 #define atomic_subtract_rel_64 atomic_subtract_rel_long
596 #define atomic_load_acq_64 atomic_load_acq_long
597 #define atomic_store_rel_64 atomic_store_rel_long
598 #define atomic_cmpset_64 atomic_cmpset_long
599 #define atomic_cmpset_acq_64 atomic_cmpset_acq_long
600 #define atomic_cmpset_rel_64 atomic_cmpset_rel_long
601 #define atomic_fcmpset_64 atomic_fcmpset_long
602 #define atomic_fcmpset_acq_64 atomic_fcmpset_acq_long
603 #define atomic_fcmpset_rel_64 atomic_fcmpset_rel_long
604 #define atomic_swap_64 atomic_swap_long
605 #define atomic_readandclear_64 atomic_readandclear_long
606 #define atomic_fetchadd_64 atomic_fetchadd_long
607 #define atomic_testandset_64 atomic_testandset_long
608 #define atomic_testandclear_64 atomic_testandclear_long
609
610 /* Operations on pointers. */
611 #define atomic_set_ptr atomic_set_long
612 #define atomic_set_acq_ptr atomic_set_acq_long
613 #define atomic_set_rel_ptr atomic_set_rel_long
614 #define atomic_clear_ptr atomic_clear_long
615 #define atomic_clear_acq_ptr atomic_clear_acq_long
616 #define atomic_clear_rel_ptr atomic_clear_rel_long
617 #define atomic_add_ptr atomic_add_long
618 #define atomic_add_acq_ptr atomic_add_acq_long
619 #define atomic_add_rel_ptr atomic_add_rel_long
620 #define atomic_subtract_ptr atomic_subtract_long
621 #define atomic_subtract_acq_ptr atomic_subtract_acq_long
622 #define atomic_subtract_rel_ptr atomic_subtract_rel_long
623 #define atomic_load_acq_ptr atomic_load_acq_long
624 #define atomic_store_rel_ptr atomic_store_rel_long
625 #define atomic_cmpset_ptr atomic_cmpset_long
626 #define atomic_cmpset_acq_ptr atomic_cmpset_acq_long
627 #define atomic_cmpset_rel_ptr atomic_cmpset_rel_long
628 #define atomic_fcmpset_ptr atomic_fcmpset_long
629 #define atomic_fcmpset_acq_ptr atomic_fcmpset_acq_long
630 #define atomic_fcmpset_rel_ptr atomic_fcmpset_rel_long
631 #define atomic_swap_ptr atomic_swap_long
632 #define atomic_readandclear_ptr atomic_readandclear_long
633
634 #endif /* !SAN_NEEDS_INTERCEPTORS || SAN_RUNTIME */
635
636 #endif /* !_MACHINE_ATOMIC_H_ */
637