1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2011 NetApp, Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 #include <sys/param.h>
31 #include <sys/pcpu.h>
32 #include <sys/systm.h>
33 #include <sys/sysctl.h>
34
35 #include <machine/clock.h>
36 #include <machine/cpufunc.h>
37 #include <machine/md_var.h>
38 #include <machine/segments.h>
39 #include <machine/specialreg.h>
40
41 #include <machine/vmm.h>
42
43 #include "vmm_host.h"
44 #include "vmm_ktr.h"
45 #include "vmm_util.h"
46 #include "x86.h"
47
48 SYSCTL_DECL(_hw_vmm);
49 static SYSCTL_NODE(_hw_vmm, OID_AUTO, topology, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
50 NULL);
51
52 #define CPUID_VM_HIGH 0x40000000
53
54 static const char bhyve_id[12] = "bhyve bhyve ";
55
56 static uint64_t bhyve_xcpuids;
57 SYSCTL_ULONG(_hw_vmm, OID_AUTO, bhyve_xcpuids, CTLFLAG_RW, &bhyve_xcpuids, 0,
58 "Number of times an unknown cpuid leaf was accessed");
59
60 #if __FreeBSD_version < 1200060 /* Remove after 11 EOL helps MFCing */
61 extern u_int threads_per_core;
62 SYSCTL_UINT(_hw_vmm_topology, OID_AUTO, threads_per_core, CTLFLAG_RDTUN,
63 &threads_per_core, 0, NULL);
64
65 extern u_int cores_per_package;
66 SYSCTL_UINT(_hw_vmm_topology, OID_AUTO, cores_per_package, CTLFLAG_RDTUN,
67 &cores_per_package, 0, NULL);
68 #endif
69
70 static int cpuid_leaf_b = 1;
71 SYSCTL_INT(_hw_vmm_topology, OID_AUTO, cpuid_leaf_b, CTLFLAG_RDTUN,
72 &cpuid_leaf_b, 0, NULL);
73
74 /*
75 * Round up to the next power of two, if necessary, and then take log2.
76 * Returns -1 if argument is zero.
77 */
78 static __inline int
log2(u_int x)79 log2(u_int x)
80 {
81
82 return (fls(x << (1 - powerof2(x))) - 1);
83 }
84
85 int
x86_emulate_cpuid(struct vcpu * vcpu,uint64_t * rax,uint64_t * rbx,uint64_t * rcx,uint64_t * rdx)86 x86_emulate_cpuid(struct vcpu *vcpu, uint64_t *rax, uint64_t *rbx,
87 uint64_t *rcx, uint64_t *rdx)
88 {
89 struct vm *vm = vcpu_vm(vcpu);
90 int vcpu_id = vcpu_vcpuid(vcpu);
91 const struct xsave_limits *limits;
92 uint64_t cr4;
93 int error, enable_invpcid, enable_rdpid, enable_rdtscp, level,
94 width, x2apic_id;
95 unsigned int func, regs[4], logical_cpus, param;
96 enum x2apic_state x2apic_state;
97 uint16_t cores, maxcpus, sockets, threads;
98
99 /*
100 * The function of CPUID is controlled through the provided value of
101 * %eax (and secondarily %ecx, for certain leaf data).
102 */
103 func = (uint32_t)*rax;
104 param = (uint32_t)*rcx;
105
106 VCPU_CTR2(vm, vcpu_id, "cpuid %#x,%#x", func, param);
107
108 /*
109 * Requests for invalid CPUID levels should map to the highest
110 * available level instead.
111 */
112 if (cpu_exthigh != 0 && func >= 0x80000000) {
113 if (func > cpu_exthigh)
114 func = cpu_exthigh;
115 } else if (func >= 0x40000000) {
116 if (func > CPUID_VM_HIGH)
117 func = CPUID_VM_HIGH;
118 } else if (func > cpu_high) {
119 func = cpu_high;
120 }
121
122 /*
123 * In general the approach used for CPU topology is to
124 * advertise a flat topology where all CPUs are packages with
125 * no multi-core or SMT.
126 */
127 switch (func) {
128 /*
129 * Pass these through to the guest
130 */
131 case CPUID_0000_0000:
132 case CPUID_0000_0002:
133 case CPUID_0000_0003:
134 case CPUID_8000_0000:
135 case CPUID_8000_0002:
136 case CPUID_8000_0003:
137 case CPUID_8000_0004:
138 case CPUID_8000_0006:
139 cpuid_count(func, param, regs);
140 break;
141 case CPUID_8000_0008:
142 cpuid_count(func, param, regs);
143 if (vmm_is_svm()) {
144 /*
145 * As on Intel (0000_0007:0, EDX), mask out
146 * unsupported or unsafe AMD extended features
147 * (8000_0008 EBX).
148 */
149 regs[1] &= (AMDFEID_CLZERO | AMDFEID_IRPERF |
150 AMDFEID_XSAVEERPTR);
151
152 vm_get_topology(vm, &sockets, &cores, &threads,
153 &maxcpus);
154 /*
155 * Here, width is ApicIdCoreIdSize, present on
156 * at least Family 15h and newer. It
157 * represents the "number of bits in the
158 * initial apicid that indicate thread id
159 * within a package."
160 *
161 * Our topo_probe_amd() uses it for
162 * pkg_id_shift and other OSes may rely on it.
163 */
164 width = MIN(0xF, log2(threads * cores));
165 if (width < 0x4)
166 width = 0;
167 logical_cpus = MIN(0xFF, threads * cores - 1);
168 regs[2] = (width << AMDID_COREID_SIZE_SHIFT) | logical_cpus;
169 }
170 break;
171
172 case CPUID_8000_0001:
173 cpuid_count(func, param, regs);
174
175 /*
176 * Hide SVM from guest.
177 */
178 regs[2] &= ~AMDID2_SVM;
179
180 /*
181 * Don't advertise extended performance counter MSRs
182 * to the guest.
183 */
184 regs[2] &= ~AMDID2_PCXC;
185 regs[2] &= ~AMDID2_PNXC;
186 regs[2] &= ~AMDID2_PTSCEL2I;
187
188 /*
189 * Don't advertise Instruction Based Sampling feature.
190 */
191 regs[2] &= ~AMDID2_IBS;
192
193 /* NodeID MSR not available */
194 regs[2] &= ~AMDID2_NODE_ID;
195
196 /* Don't advertise the OS visible workaround feature */
197 regs[2] &= ~AMDID2_OSVW;
198
199 /* Hide mwaitx/monitorx capability from the guest */
200 regs[2] &= ~AMDID2_MWAITX;
201
202 /* Advertise RDTSCP if it is enabled. */
203 error = vm_get_capability(vcpu,
204 VM_CAP_RDTSCP, &enable_rdtscp);
205 if (error == 0 && enable_rdtscp)
206 regs[3] |= AMDID_RDTSCP;
207 else
208 regs[3] &= ~AMDID_RDTSCP;
209 break;
210
211 case CPUID_8000_0007:
212 /*
213 * AMD uses this leaf to advertise the processor's
214 * power monitoring and RAS capabilities. These
215 * features are hardware-specific and exposing
216 * them to a guest doesn't make a lot of sense.
217 *
218 * Intel uses this leaf only to advertise the
219 * "Invariant TSC" feature with all other bits
220 * being reserved (set to zero).
221 */
222 regs[0] = 0;
223 regs[1] = 0;
224 regs[2] = 0;
225 regs[3] = 0;
226
227 /*
228 * "Invariant TSC" can be advertised to the guest if:
229 * - host TSC frequency is invariant
230 * - host TSCs are synchronized across physical cpus
231 *
232 * XXX This still falls short because the vcpu
233 * can observe the TSC moving backwards as it
234 * migrates across physical cpus. But at least
235 * it should discourage the guest from using the
236 * TSC to keep track of time.
237 */
238 if (tsc_is_invariant && smp_tsc)
239 regs[3] |= AMDPM_TSC_INVARIANT;
240 break;
241
242 case CPUID_8000_001D:
243 /* AMD Cache topology, like 0000_0004 for Intel. */
244 if (!vmm_is_svm())
245 goto default_leaf;
246
247 /*
248 * Similar to Intel, generate a ficticious cache
249 * topology for the guest with L3 shared by the
250 * package, and L1 and L2 local to a core.
251 */
252 vm_get_topology(vm, &sockets, &cores, &threads,
253 &maxcpus);
254 switch (param) {
255 case 0:
256 logical_cpus = threads;
257 level = 1;
258 func = 1; /* data cache */
259 break;
260 case 1:
261 logical_cpus = threads;
262 level = 2;
263 func = 3; /* unified cache */
264 break;
265 case 2:
266 logical_cpus = threads * cores;
267 level = 3;
268 func = 3; /* unified cache */
269 break;
270 default:
271 logical_cpus = 0;
272 level = 0;
273 func = 0;
274 break;
275 }
276
277 logical_cpus = MIN(0xfff, logical_cpus - 1);
278 regs[0] = (logical_cpus << 14) | (1 << 8) |
279 (level << 5) | func;
280 regs[1] = (func > 0) ? (CACHE_LINE_SIZE - 1) : 0;
281 regs[2] = 0;
282 regs[3] = 0;
283 break;
284
285 case CPUID_8000_001E:
286 /*
287 * AMD Family 16h+ and Hygon Family 18h additional
288 * identifiers.
289 */
290 if (!vmm_is_svm() || CPUID_TO_FAMILY(cpu_id) < 0x16)
291 goto default_leaf;
292
293 vm_get_topology(vm, &sockets, &cores, &threads,
294 &maxcpus);
295 regs[0] = vcpu_id;
296 threads = MIN(0xFF, threads - 1);
297 regs[1] = (threads << 8) |
298 (vcpu_id >> log2(threads + 1));
299 /*
300 * XXX Bhyve topology cannot yet represent >1 node per
301 * processor.
302 */
303 regs[2] = 0;
304 regs[3] = 0;
305 break;
306
307 case CPUID_0000_0001:
308 do_cpuid(1, regs);
309
310 error = vm_get_x2apic_state(vcpu, &x2apic_state);
311 if (error) {
312 panic("x86_emulate_cpuid: error %d "
313 "fetching x2apic state", error);
314 }
315
316 /*
317 * Override the APIC ID only in ebx
318 */
319 regs[1] &= ~(CPUID_LOCAL_APIC_ID);
320 regs[1] |= (vcpu_id << CPUID_0000_0001_APICID_SHIFT);
321
322 /*
323 * Don't expose VMX, SpeedStep, TME or SMX capability.
324 * Advertise x2APIC capability and Hypervisor guest.
325 */
326 regs[2] &= ~(CPUID2_VMX | CPUID2_EST | CPUID2_TM2);
327 regs[2] &= ~(CPUID2_SMX);
328
329 regs[2] |= CPUID2_HV;
330
331 if (x2apic_state != X2APIC_DISABLED)
332 regs[2] |= CPUID2_X2APIC;
333 else
334 regs[2] &= ~CPUID2_X2APIC;
335
336 /*
337 * Only advertise CPUID2_XSAVE in the guest if
338 * the host is using XSAVE.
339 */
340 if (!(regs[2] & CPUID2_OSXSAVE))
341 regs[2] &= ~CPUID2_XSAVE;
342
343 /*
344 * If CPUID2_XSAVE is being advertised and the
345 * guest has set CR4_XSAVE, set
346 * CPUID2_OSXSAVE.
347 */
348 regs[2] &= ~CPUID2_OSXSAVE;
349 if (regs[2] & CPUID2_XSAVE) {
350 error = vm_get_register(vcpu,
351 VM_REG_GUEST_CR4, &cr4);
352 if (error)
353 panic("x86_emulate_cpuid: error %d "
354 "fetching %%cr4", error);
355 if (cr4 & CR4_XSAVE)
356 regs[2] |= CPUID2_OSXSAVE;
357 }
358
359 /*
360 * Hide monitor/mwait until we know how to deal with
361 * these instructions.
362 */
363 regs[2] &= ~CPUID2_MON;
364
365 /*
366 * Hide the performance and debug features.
367 */
368 regs[2] &= ~CPUID2_PDCM;
369
370 /*
371 * No TSC deadline support in the APIC yet
372 */
373 regs[2] &= ~CPUID2_TSCDLT;
374
375 /*
376 * Hide thermal monitoring
377 */
378 regs[3] &= ~(CPUID_ACPI | CPUID_TM);
379
380 /*
381 * Hide the debug store capability.
382 */
383 regs[3] &= ~CPUID_DS;
384
385 /*
386 * Advertise the Machine Check and MTRR capability.
387 *
388 * Some guest OSes (e.g. Windows) will not boot if
389 * these features are absent.
390 */
391 regs[3] |= (CPUID_MCA | CPUID_MCE | CPUID_MTRR);
392
393 vm_get_topology(vm, &sockets, &cores, &threads,
394 &maxcpus);
395 logical_cpus = threads * cores;
396 regs[1] &= ~CPUID_HTT_CORES;
397 regs[1] |= (logical_cpus & 0xff) << 16;
398 regs[3] |= CPUID_HTT;
399 break;
400
401 case CPUID_0000_0004:
402 cpuid_count(func, param, regs);
403
404 if (regs[0] || regs[1] || regs[2] || regs[3]) {
405 vm_get_topology(vm, &sockets, &cores, &threads,
406 &maxcpus);
407 regs[0] &= 0x3ff;
408 regs[0] |= (cores - 1) << 26;
409 /*
410 * Cache topology:
411 * - L1 and L2 are shared only by the logical
412 * processors in a single core.
413 * - L3 and above are shared by all logical
414 * processors in the package.
415 */
416 logical_cpus = threads;
417 level = (regs[0] >> 5) & 0x7;
418 if (level >= 3)
419 logical_cpus *= cores;
420 regs[0] |= (logical_cpus - 1) << 14;
421 }
422 break;
423
424 case CPUID_0000_0007:
425 regs[0] = 0;
426 regs[1] = 0;
427 regs[2] = 0;
428 regs[3] = 0;
429
430 /* leaf 0 */
431 if (param == 0) {
432 cpuid_count(func, param, regs);
433
434 /* Only leaf 0 is supported */
435 regs[0] = 0;
436
437 /*
438 * Expose known-safe features.
439 */
440 regs[1] &= CPUID_STDEXT_FSGSBASE |
441 CPUID_STDEXT_BMI1 | CPUID_STDEXT_HLE |
442 CPUID_STDEXT_AVX2 | CPUID_STDEXT_SMEP |
443 CPUID_STDEXT_BMI2 |
444 CPUID_STDEXT_ERMS | CPUID_STDEXT_RTM |
445 CPUID_STDEXT_AVX512F |
446 CPUID_STDEXT_AVX512DQ |
447 CPUID_STDEXT_RDSEED |
448 CPUID_STDEXT_SMAP |
449 CPUID_STDEXT_AVX512PF |
450 CPUID_STDEXT_AVX512ER |
451 CPUID_STDEXT_AVX512CD | CPUID_STDEXT_SHA |
452 CPUID_STDEXT_AVX512BW |
453 CPUID_STDEXT_AVX512VL;
454 regs[2] &= CPUID_STDEXT2_VAES |
455 CPUID_STDEXT2_VPCLMULQDQ;
456 regs[3] &= CPUID_STDEXT3_MD_CLEAR;
457
458 /* Advertise RDPID if it is enabled. */
459 error = vm_get_capability(vcpu, VM_CAP_RDPID,
460 &enable_rdpid);
461 if (error == 0 && enable_rdpid)
462 regs[2] |= CPUID_STDEXT2_RDPID;
463
464 /* Advertise INVPCID if it is enabled. */
465 error = vm_get_capability(vcpu,
466 VM_CAP_ENABLE_INVPCID, &enable_invpcid);
467 if (error == 0 && enable_invpcid)
468 regs[1] |= CPUID_STDEXT_INVPCID;
469 }
470 break;
471
472 case CPUID_0000_0006:
473 regs[0] = CPUTPM1_ARAT;
474 regs[1] = 0;
475 regs[2] = 0;
476 regs[3] = 0;
477 break;
478
479 case CPUID_0000_000A:
480 /*
481 * Handle the access, but report 0 for
482 * all options
483 */
484 regs[0] = 0;
485 regs[1] = 0;
486 regs[2] = 0;
487 regs[3] = 0;
488 break;
489
490 case CPUID_0000_000B:
491 /*
492 * Intel processor topology enumeration
493 */
494 if (vmm_is_intel()) {
495 vm_get_topology(vm, &sockets, &cores, &threads,
496 &maxcpus);
497 if (param == 0) {
498 logical_cpus = threads;
499 width = log2(logical_cpus);
500 level = CPUID_TYPE_SMT;
501 x2apic_id = vcpu_id;
502 }
503
504 if (param == 1) {
505 logical_cpus = threads * cores;
506 width = log2(logical_cpus);
507 level = CPUID_TYPE_CORE;
508 x2apic_id = vcpu_id;
509 }
510
511 if (!cpuid_leaf_b || param >= 2) {
512 width = 0;
513 logical_cpus = 0;
514 level = 0;
515 x2apic_id = 0;
516 }
517
518 regs[0] = width & 0x1f;
519 regs[1] = logical_cpus & 0xffff;
520 regs[2] = (level << 8) | (param & 0xff);
521 regs[3] = x2apic_id;
522 } else {
523 regs[0] = 0;
524 regs[1] = 0;
525 regs[2] = 0;
526 regs[3] = 0;
527 }
528 break;
529
530 case CPUID_0000_000D:
531 limits = vmm_get_xsave_limits();
532 if (!limits->xsave_enabled) {
533 regs[0] = 0;
534 regs[1] = 0;
535 regs[2] = 0;
536 regs[3] = 0;
537 break;
538 }
539
540 cpuid_count(func, param, regs);
541 switch (param) {
542 case 0:
543 /*
544 * Only permit the guest to use bits
545 * that are active in the host in
546 * %xcr0. Also, claim that the
547 * maximum save area size is
548 * equivalent to the host's current
549 * save area size. Since this runs
550 * "inside" of vmrun(), it runs with
551 * the guest's xcr0, so the current
552 * save area size is correct as-is.
553 */
554 regs[0] &= limits->xcr0_allowed;
555 regs[2] = limits->xsave_max_size;
556 regs[3] &= (limits->xcr0_allowed >> 32);
557 break;
558 case 1:
559 /* Only permit XSAVEOPT. */
560 regs[0] &= CPUID_EXTSTATE_XSAVEOPT;
561 regs[1] = 0;
562 regs[2] = 0;
563 regs[3] = 0;
564 break;
565 default:
566 /*
567 * If the leaf is for a permitted feature,
568 * pass through as-is, otherwise return
569 * all zeroes.
570 */
571 if (!(limits->xcr0_allowed & (1ul << param))) {
572 regs[0] = 0;
573 regs[1] = 0;
574 regs[2] = 0;
575 regs[3] = 0;
576 }
577 break;
578 }
579 break;
580
581 case CPUID_0000_000F:
582 case CPUID_0000_0010:
583 /*
584 * Do not report any Resource Director Technology
585 * capabilities. Exposing control of cache or memory
586 * controller resource partitioning to the guest is not
587 * at all sensible.
588 *
589 * This is already hidden at a high level by masking of
590 * leaf 0x7. Even still, a guest may look here for
591 * detailed capability information.
592 */
593 regs[0] = 0;
594 regs[1] = 0;
595 regs[2] = 0;
596 regs[3] = 0;
597 break;
598
599 case CPUID_0000_0015:
600 /*
601 * Don't report CPU TSC/Crystal ratio and clock
602 * values since guests may use these to derive the
603 * local APIC frequency..
604 */
605 regs[0] = 0;
606 regs[1] = 0;
607 regs[2] = 0;
608 regs[3] = 0;
609 break;
610
611 case 0x40000000:
612 regs[0] = CPUID_VM_HIGH;
613 bcopy(bhyve_id, ®s[1], 4);
614 bcopy(bhyve_id + 4, ®s[2], 4);
615 bcopy(bhyve_id + 8, ®s[3], 4);
616 break;
617
618 default:
619 default_leaf:
620 /*
621 * The leaf value has already been clamped so
622 * simply pass this through, keeping count of
623 * how many unhandled leaf values have been seen.
624 */
625 atomic_add_long(&bhyve_xcpuids, 1);
626 cpuid_count(func, param, regs);
627 break;
628 }
629
630 /*
631 * CPUID clears the upper 32-bits of the long-mode registers.
632 */
633 *rax = regs[0];
634 *rbx = regs[1];
635 *rcx = regs[2];
636 *rdx = regs[3];
637
638 return (1);
639 }
640
641 bool
vm_cpuid_capability(struct vcpu * vcpu,enum vm_cpuid_capability cap)642 vm_cpuid_capability(struct vcpu *vcpu, enum vm_cpuid_capability cap)
643 {
644 bool rv;
645
646 KASSERT(cap > 0 && cap < VCC_LAST, ("%s: invalid vm_cpu_capability %d",
647 __func__, cap));
648
649 /*
650 * Simply passthrough the capabilities of the host cpu for now.
651 */
652 rv = false;
653 switch (cap) {
654 case VCC_NO_EXECUTE:
655 if (amd_feature & AMDID_NX)
656 rv = true;
657 break;
658 case VCC_FFXSR:
659 if (amd_feature & AMDID_FFXSR)
660 rv = true;
661 break;
662 case VCC_TCE:
663 if (amd_feature2 & AMDID2_TCE)
664 rv = true;
665 break;
666 default:
667 panic("%s: unknown vm_cpu_capability %d", __func__, cap);
668 }
669 return (rv);
670 }
671
672 int
vm_rdmtrr(struct vm_mtrr * mtrr,u_int num,uint64_t * val)673 vm_rdmtrr(struct vm_mtrr *mtrr, u_int num, uint64_t *val)
674 {
675 switch (num) {
676 case MSR_MTRRcap:
677 *val = MTRR_CAP_WC | MTRR_CAP_FIXED | VMM_MTRR_VAR_MAX;
678 break;
679 case MSR_MTRRdefType:
680 *val = mtrr->def_type;
681 break;
682 case MSR_MTRR4kBase ... MSR_MTRR4kBase + 7:
683 *val = mtrr->fixed4k[num - MSR_MTRR4kBase];
684 break;
685 case MSR_MTRR16kBase ... MSR_MTRR16kBase + 1:
686 *val = mtrr->fixed16k[num - MSR_MTRR16kBase];
687 break;
688 case MSR_MTRR64kBase:
689 *val = mtrr->fixed64k;
690 break;
691 case MSR_MTRRVarBase ... MSR_MTRRVarBase + (VMM_MTRR_VAR_MAX * 2) - 1: {
692 u_int offset = num - MSR_MTRRVarBase;
693 if (offset % 2 == 0) {
694 *val = mtrr->var[offset / 2].base;
695 } else {
696 *val = mtrr->var[offset / 2].mask;
697 }
698 break;
699 }
700 default:
701 return (-1);
702 }
703
704 return (0);
705 }
706
707 int
vm_wrmtrr(struct vm_mtrr * mtrr,u_int num,uint64_t val)708 vm_wrmtrr(struct vm_mtrr *mtrr, u_int num, uint64_t val)
709 {
710 switch (num) {
711 case MSR_MTRRcap:
712 /* MTRRCAP is read only */
713 return (-1);
714 case MSR_MTRRdefType:
715 if (val & ~VMM_MTRR_DEF_MASK) {
716 /* generate #GP on writes to reserved fields */
717 return (-1);
718 }
719 mtrr->def_type = val;
720 break;
721 case MSR_MTRR4kBase ... MSR_MTRR4kBase + 7:
722 mtrr->fixed4k[num - MSR_MTRR4kBase] = val;
723 break;
724 case MSR_MTRR16kBase ... MSR_MTRR16kBase + 1:
725 mtrr->fixed16k[num - MSR_MTRR16kBase] = val;
726 break;
727 case MSR_MTRR64kBase:
728 mtrr->fixed64k = val;
729 break;
730 case MSR_MTRRVarBase ... MSR_MTRRVarBase + (VMM_MTRR_VAR_MAX * 2) - 1: {
731 u_int offset = num - MSR_MTRRVarBase;
732 if (offset % 2 == 0) {
733 if (val & ~VMM_MTRR_PHYSBASE_MASK) {
734 /* generate #GP on writes to reserved fields */
735 return (-1);
736 }
737 mtrr->var[offset / 2].base = val;
738 } else {
739 if (val & ~VMM_MTRR_PHYSMASK_MASK) {
740 /* generate #GP on writes to reserved fields */
741 return (-1);
742 }
743 mtrr->var[offset / 2].mask = val;
744 }
745 break;
746 }
747 default:
748 return (-1);
749 }
750
751 return (0);
752 }
753