1 /*-
2 * Copyright (c) 2016 Ganbold Tsagaankhuu <ganbold@freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 /*
28 * Allwinner Consumer IR controller
29 */
30
31 #include <sys/cdefs.h>
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/bus.h>
35 #include <sys/kernel.h>
36 #include <sys/module.h>
37 #include <sys/rman.h>
38 #include <sys/sysctl.h>
39 #include <machine/bus.h>
40
41 #include <dev/ofw/openfirm.h>
42 #include <dev/ofw/ofw_bus.h>
43 #include <dev/ofw/ofw_bus_subr.h>
44 #include <dev/extres/clk/clk.h>
45 #include <dev/extres/hwreset/hwreset.h>
46
47 #include <dev/evdev/input.h>
48 #include <dev/evdev/evdev.h>
49
50 #define READ(_sc, _r) bus_read_4((_sc)->res[0], (_r))
51 #define WRITE(_sc, _r, _v) bus_write_4((_sc)->res[0], (_r), (_v))
52
53 /* IR Control */
54 #define AW_IR_CTL 0x00
55 /* Global Enable */
56 #define AW_IR_CTL_GEN (1 << 0)
57 /* RX enable */
58 #define AW_IR_CTL_RXEN (1 << 1)
59 /* CIR mode enable */
60 #define AW_IR_CTL_MD (1 << 4) | (1 << 5)
61
62 /* RX Config Reg */
63 #define AW_IR_RXCTL 0x10
64 /* Pulse Polarity Invert flag */
65 #define AW_IR_RXCTL_RPPI (1 << 2)
66
67 /* RX Data */
68 #define AW_IR_RXFIFO 0x20
69
70 /* RX Interrupt Control */
71 #define AW_IR_RXINT 0x2C
72 /* RX FIFO Overflow */
73 #define AW_IR_RXINT_ROI_EN (1 << 0)
74 /* RX Packet End */
75 #define AW_IR_RXINT_RPEI_EN (1 << 1)
76 /* RX FIFO Data Available */
77 #define AW_IR_RXINT_RAI_EN (1 << 4)
78 /* RX FIFO available byte level */
79 #define AW_IR_RXINT_RAL(val) ((val) << 8)
80
81 /* RX Interrupt Status Reg */
82 #define AW_IR_RXSTA 0x30
83 /* RX FIFO Get Available Counter */
84 #define AW_IR_RXSTA_COUNTER(val) (((val) >> 8) & (sc->fifo_size * 2 - 1))
85 /* Clear all interrupt status */
86 #define AW_IR_RXSTA_CLEARALL 0xff
87
88 /* IR Sample Configure Reg */
89 #define AW_IR_CIR 0x34
90
91 /*
92 * Frequency sample: 23437.5Hz (Cycle: 42.7us)
93 * Pulse of NEC Remote > 560us
94 */
95 /* Filter Threshold = 8 * 42.7 = ~341us < 500us */
96 #define AW_IR_RXFILT_VAL (((8) & 0x3f) << 2)
97 /* Idle Threshold = (2 + 1) * 128 * 42.7 = ~16.4ms > 9ms */
98 #define AW_IR_RXIDLE_VAL (((2) & 0xff) << 8)
99
100 /* Bit 15 - value (pulse/space) */
101 #define VAL_MASK 0x80
102 /* Bits 0:14 - sample duration */
103 #define PERIOD_MASK 0x7f
104
105 /* Clock rate for IR0 or IR1 clock in CIR mode */
106 #define AW_IR_BASE_CLK 3000000
107 /* Frequency sample 3MHz/64 = 46875Hz (21.3us) */
108 #define AW_IR_SAMPLE_64 (0 << 0)
109 /* Frequency sample 3MHz/128 = 23437.5Hz (42.7us) */
110 #define AW_IR_SAMPLE_128 (1 << 0)
111
112 #define AW_IR_ERROR_CODE 0xffffffff
113 #define AW_IR_REPEAT_CODE 0x0
114
115 /* 80 * 42.7 = ~3.4ms, Lead1(4.5ms) > AW_IR_L1_MIN */
116 #define AW_IR_L1_MIN 80
117 /* 40 * 42.7 = ~1.7ms, Lead0(4.5ms) Lead0R(2.25ms) > AW_IR_L0_MIN */
118 #define AW_IR_L0_MIN 40
119 /* 26 * 42.7 = ~1109us ~= 561 * 2, Pulse < AW_IR_PMAX */
120 #define AW_IR_PMAX 26
121 /* 26 * 42.7 = ~1109us ~= 561 * 2, D1 > AW_IR_DMID, D0 <= AW_IR_DMID */
122 #define AW_IR_DMID 26
123 /* 53 * 42.7 = ~2263us ~= 561 * 4, D < AW_IR_DMAX */
124 #define AW_IR_DMAX 53
125
126 /* Active Thresholds */
127 #define AW_IR_ACTIVE_T_VAL AW_IR_L1_MIN
128 #define AW_IR_ACTIVE_T (((AW_IR_ACTIVE_T_VAL - 1) & 0xff) << 16)
129 #define AW_IR_ACTIVE_T_C_VAL 0
130 #define AW_IR_ACTIVE_T_C ((AW_IR_ACTIVE_T_C_VAL & 0xff) << 23)
131
132 /* Code masks */
133 #define CODE_MASK 0x00ff00ff
134 #define INV_CODE_MASK 0xff00ff00
135 #define VALID_CODE_MASK 0x00ff0000
136
137 enum {
138 A10_IR = 1,
139 A13_IR,
140 A31_IR,
141 };
142
143 #define AW_IR_RAW_BUF_SIZE 128
144
145 struct aw_ir_softc {
146 device_t dev;
147 struct resource *res[2];
148 void * intrhand;
149 int fifo_size;
150 int dcnt; /* Packet Count */
151 unsigned char buf[AW_IR_RAW_BUF_SIZE];
152 struct evdev_dev *sc_evdev;
153 };
154
155 static struct resource_spec aw_ir_spec[] = {
156 { SYS_RES_MEMORY, 0, RF_ACTIVE },
157 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
158 { -1, 0 }
159 };
160
161 static struct ofw_compat_data compat_data[] = {
162 { "allwinner,sun4i-a10-ir", A10_IR },
163 { "allwinner,sun5i-a13-ir", A13_IR },
164 { "allwinner,sun6i-a31-ir", A31_IR },
165 { NULL, 0 }
166 };
167
168 static void
aw_ir_buf_reset(struct aw_ir_softc * sc)169 aw_ir_buf_reset(struct aw_ir_softc *sc)
170 {
171
172 sc->dcnt = 0;
173 }
174
175 static void
aw_ir_buf_write(struct aw_ir_softc * sc,unsigned char data)176 aw_ir_buf_write(struct aw_ir_softc *sc, unsigned char data)
177 {
178
179 if (sc->dcnt < AW_IR_RAW_BUF_SIZE)
180 sc->buf[sc->dcnt++] = data;
181 else
182 if (bootverbose)
183 device_printf(sc->dev, "IR RX Buffer Full!\n");
184 }
185
186 static int
aw_ir_buf_full(struct aw_ir_softc * sc)187 aw_ir_buf_full(struct aw_ir_softc *sc)
188 {
189
190 return (sc->dcnt >= AW_IR_RAW_BUF_SIZE);
191 }
192
193 static unsigned char
aw_ir_read_data(struct aw_ir_softc * sc)194 aw_ir_read_data(struct aw_ir_softc *sc)
195 {
196
197 return (unsigned char)(READ(sc, AW_IR_RXFIFO) & 0xff);
198 }
199
200 static unsigned long
aw_ir_decode_packets(struct aw_ir_softc * sc)201 aw_ir_decode_packets(struct aw_ir_softc *sc)
202 {
203 unsigned int len, code;
204 unsigned int active_delay;
205 unsigned char val, last;
206 int i, bitcount;
207
208 if (bootverbose)
209 device_printf(sc->dev, "sc->dcnt = %d\n", sc->dcnt);
210
211 /* Find Lead 1 (bit separator) */
212 active_delay = AW_IR_ACTIVE_T_VAL *
213 (AW_IR_ACTIVE_T_C_VAL != 0 ? 128 : 1);
214 len = active_delay;
215 if (bootverbose)
216 device_printf(sc->dev, "Initial len: %d\n", len);
217 for (i = 0; i < sc->dcnt; i++) {
218 val = sc->buf[i];
219 if (val & VAL_MASK)
220 len += (val & PERIOD_MASK) + 1;
221 else {
222 if (len > AW_IR_L1_MIN)
223 break;
224 len = 0;
225 }
226 }
227 if (bootverbose)
228 device_printf(sc->dev, "len = %d\n", len);
229 if ((val & VAL_MASK) || (len <= AW_IR_L1_MIN)) {
230 if (bootverbose)
231 device_printf(sc->dev, "Bit separator error\n");
232 goto error_code;
233 }
234
235 /* Find Lead 0 (bit length) */
236 len = 0;
237 for (; i < sc->dcnt; i++) {
238 val = sc->buf[i];
239 if (val & VAL_MASK) {
240 if(len > AW_IR_L0_MIN)
241 break;
242 len = 0;
243 } else
244 len += (val & PERIOD_MASK) + 1;
245 }
246 if ((!(val & VAL_MASK)) || (len <= AW_IR_L0_MIN)) {
247 if (bootverbose)
248 device_printf(sc->dev, "Bit length error\n");
249 goto error_code;
250 }
251
252 /* Start decoding */
253 code = 0;
254 bitcount = 0;
255 last = 1;
256 len = 0;
257 for (; i < sc->dcnt; i++) {
258 val = sc->buf[i];
259 if (last) {
260 if (val & VAL_MASK)
261 len += (val & PERIOD_MASK) + 1;
262 else {
263 if (len > AW_IR_PMAX) {
264 if (bootverbose)
265 device_printf(sc->dev,
266 "Pulse error, len=%d\n",
267 len);
268 goto error_code;
269 }
270 last = 0;
271 len = (val & PERIOD_MASK) + 1;
272 }
273 } else {
274 if (val & VAL_MASK) {
275 if (len > AW_IR_DMAX) {
276 if (bootverbose)
277 device_printf(sc->dev,
278 "Distance error, len=%d\n",
279 len);
280 goto error_code;
281 } else {
282 if (len > AW_IR_DMID) {
283 /* Decode */
284 code |= 1 << bitcount;
285 }
286 bitcount++;
287 if (bitcount == 32)
288 break; /* Finish decoding */
289 }
290 last = 1;
291 len = (val & PERIOD_MASK) + 1;
292 } else
293 len += (val & PERIOD_MASK) + 1;
294 }
295 }
296 return (code);
297
298 error_code:
299
300 return (AW_IR_ERROR_CODE);
301 }
302
303 static int
aw_ir_validate_code(unsigned long code)304 aw_ir_validate_code(unsigned long code)
305 {
306 unsigned long v1, v2;
307
308 /* Don't check address */
309 v1 = code & CODE_MASK;
310 v2 = (code & INV_CODE_MASK) >> 8;
311
312 if (((v1 ^ v2) & VALID_CODE_MASK) == VALID_CODE_MASK)
313 return (0); /* valid */
314 else
315 return (1); /* invalid */
316 }
317
318 static void
aw_ir_intr(void * arg)319 aw_ir_intr(void *arg)
320 {
321 struct aw_ir_softc *sc;
322 uint32_t val;
323 int i, dcnt;
324 unsigned long ir_code;
325 int stat;
326
327 sc = (struct aw_ir_softc *)arg;
328
329 /* Read RX interrupt status */
330 val = READ(sc, AW_IR_RXSTA);
331 if (bootverbose)
332 device_printf(sc->dev, "RX interrupt status: %x\n", val);
333
334 /* Clean all pending interrupt statuses */
335 WRITE(sc, AW_IR_RXSTA, val | AW_IR_RXSTA_CLEARALL);
336
337 /* When Rx FIFO Data available or Packet end */
338 if (val & (AW_IR_RXINT_RAI_EN | AW_IR_RXINT_RPEI_EN)) {
339 if (bootverbose)
340 device_printf(sc->dev,
341 "RX FIFO Data available or Packet end\n");
342 /* Get available message count in RX FIFO */
343 dcnt = AW_IR_RXSTA_COUNTER(val);
344 /* Read FIFO */
345 for (i = 0; i < dcnt; i++) {
346 if (aw_ir_buf_full(sc)) {
347 if (bootverbose)
348 device_printf(sc->dev,
349 "raw buffer full\n");
350 break;
351 } else
352 aw_ir_buf_write(sc, aw_ir_read_data(sc));
353 }
354 }
355
356 if (val & AW_IR_RXINT_RPEI_EN) {
357 /* RX Packet end */
358 if (bootverbose)
359 device_printf(sc->dev, "RX Packet end\n");
360 ir_code = aw_ir_decode_packets(sc);
361 stat = aw_ir_validate_code(ir_code);
362 if (stat == 0) {
363 evdev_push_event(sc->sc_evdev,
364 EV_MSC, MSC_SCAN, ir_code);
365 evdev_sync(sc->sc_evdev);
366 }
367 if (bootverbose) {
368 device_printf(sc->dev, "Final IR code: %lx\n",
369 ir_code);
370 device_printf(sc->dev, "IR code status: %d\n",
371 stat);
372 }
373 aw_ir_buf_reset(sc);
374 }
375 if (val & AW_IR_RXINT_ROI_EN) {
376 /* RX FIFO overflow */
377 if (bootverbose)
378 device_printf(sc->dev, "RX FIFO overflow\n");
379 /* Flush raw buffer */
380 aw_ir_buf_reset(sc);
381 }
382 }
383
384 static int
aw_ir_probe(device_t dev)385 aw_ir_probe(device_t dev)
386 {
387
388 if (!ofw_bus_status_okay(dev))
389 return (ENXIO);
390
391 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
392 return (ENXIO);
393
394 device_set_desc(dev, "Allwinner CIR controller");
395 return (BUS_PROBE_DEFAULT);
396 }
397
398 static int
aw_ir_attach(device_t dev)399 aw_ir_attach(device_t dev)
400 {
401 struct aw_ir_softc *sc;
402 hwreset_t rst_apb;
403 clk_t clk_ir, clk_gate;
404 int err;
405 uint32_t val = 0;
406
407 clk_ir = clk_gate = NULL;
408 rst_apb = NULL;
409
410 sc = device_get_softc(dev);
411 sc->dev = dev;
412
413 if (bus_alloc_resources(dev, aw_ir_spec, sc->res) != 0) {
414 device_printf(dev, "could not allocate memory resource\n");
415 return (ENXIO);
416 }
417
418 switch (ofw_bus_search_compatible(dev, compat_data)->ocd_data) {
419 case A10_IR:
420 sc->fifo_size = 16;
421 break;
422 case A13_IR:
423 case A31_IR:
424 sc->fifo_size = 64;
425 break;
426 }
427
428 /* De-assert reset */
429 if (hwreset_get_by_ofw_idx(dev, 0, 0, &rst_apb) == 0) {
430 err = hwreset_deassert(rst_apb);
431 if (err != 0) {
432 device_printf(dev, "cannot de-assert reset\n");
433 goto error;
434 }
435 }
436
437 /* Reset buffer */
438 aw_ir_buf_reset(sc);
439
440 /* Get clocks and enable them */
441 err = clk_get_by_ofw_name(dev, 0, "apb", &clk_gate);
442 if (err != 0) {
443 device_printf(dev, "Cannot get gate clock\n");
444 goto error;
445 }
446 err = clk_get_by_ofw_name(dev, 0, "ir", &clk_ir);
447 if (err != 0) {
448 device_printf(dev, "Cannot get IR clock\n");
449 goto error;
450 }
451 /* Set clock rate */
452 err = clk_set_freq(clk_ir, AW_IR_BASE_CLK, 0);
453 if (err != 0) {
454 device_printf(dev, "cannot set IR clock rate\n");
455 goto error;
456 }
457 /* Enable clocks */
458 err = clk_enable(clk_gate);
459 if (err != 0) {
460 device_printf(dev, "Cannot enable clk gate\n");
461 goto error;
462 }
463 err = clk_enable(clk_ir);
464 if (err != 0) {
465 device_printf(dev, "Cannot enable IR clock\n");
466 goto error;
467 }
468
469 if (bus_setup_intr(dev, sc->res[1],
470 INTR_TYPE_MISC | INTR_MPSAFE, NULL, aw_ir_intr, sc,
471 &sc->intrhand)) {
472 bus_release_resources(dev, aw_ir_spec, sc->res);
473 device_printf(dev, "cannot setup interrupt handler\n");
474 err = ENXIO;
475 goto error;
476 }
477
478 /* Enable CIR Mode */
479 WRITE(sc, AW_IR_CTL, AW_IR_CTL_MD);
480
481 /*
482 * Set clock sample, filter, idle thresholds.
483 * Frequency sample = 3MHz/128 = 23437.5Hz (42.7us)
484 */
485 val = AW_IR_SAMPLE_128;
486 val |= (AW_IR_RXFILT_VAL | AW_IR_RXIDLE_VAL);
487 val |= (AW_IR_ACTIVE_T | AW_IR_ACTIVE_T_C);
488 WRITE(sc, AW_IR_CIR, val);
489
490 /* Invert Input Signal */
491 WRITE(sc, AW_IR_RXCTL, AW_IR_RXCTL_RPPI);
492
493 /* Clear All RX Interrupt Status */
494 WRITE(sc, AW_IR_RXSTA, AW_IR_RXSTA_CLEARALL);
495
496 /*
497 * Enable RX interrupt in case of overflow, packet end
498 * and FIFO available.
499 * RX FIFO Threshold = FIFO size / 2
500 */
501 WRITE(sc, AW_IR_RXINT, AW_IR_RXINT_ROI_EN | AW_IR_RXINT_RPEI_EN |
502 AW_IR_RXINT_RAI_EN | AW_IR_RXINT_RAL((sc->fifo_size >> 1) - 1));
503
504 /* Enable IR Module */
505 val = READ(sc, AW_IR_CTL);
506 WRITE(sc, AW_IR_CTL, val | AW_IR_CTL_GEN | AW_IR_CTL_RXEN);
507
508 sc->sc_evdev = evdev_alloc();
509 evdev_set_name(sc->sc_evdev, device_get_desc(sc->dev));
510 evdev_set_phys(sc->sc_evdev, device_get_nameunit(sc->dev));
511 evdev_set_id(sc->sc_evdev, BUS_HOST, 0, 0, 0);
512 evdev_support_event(sc->sc_evdev, EV_SYN);
513 evdev_support_event(sc->sc_evdev, EV_MSC);
514 evdev_support_msc(sc->sc_evdev, MSC_SCAN);
515
516 err = evdev_register(sc->sc_evdev);
517 if (err) {
518 device_printf(dev,
519 "failed to register evdev: error=%d\n", err);
520 goto error;
521 }
522
523 return (0);
524 error:
525 if (clk_gate != NULL)
526 clk_release(clk_gate);
527 if (clk_ir != NULL)
528 clk_release(clk_ir);
529 if (rst_apb != NULL)
530 hwreset_release(rst_apb);
531 evdev_free(sc->sc_evdev);
532 sc->sc_evdev = NULL; /* Avoid double free */
533
534 bus_release_resources(dev, aw_ir_spec, sc->res);
535 return (ENXIO);
536 }
537
538 static device_method_t aw_ir_methods[] = {
539 DEVMETHOD(device_probe, aw_ir_probe),
540 DEVMETHOD(device_attach, aw_ir_attach),
541
542 DEVMETHOD_END
543 };
544
545 static driver_t aw_ir_driver = {
546 "aw_ir",
547 aw_ir_methods,
548 sizeof(struct aw_ir_softc),
549 };
550 static devclass_t aw_ir_devclass;
551
552 DRIVER_MODULE(aw_ir, simplebus, aw_ir_driver, aw_ir_devclass, 0, 0);
553 MODULE_DEPEND(aw_ir, evdev, 1, 1, 1);
554