1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2017,2018 Emmanuel Vadot <manu@freebsd.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/bus.h> 32 #include <sys/rman.h> 33 #include <sys/kernel.h> 34 #include <sys/module.h> 35 #include <machine/bus.h> 36 37 #include <dev/fdt/simplebus.h> 38 39 #include <dev/ofw/ofw_bus.h> 40 #include <dev/ofw/ofw_bus_subr.h> 41 42 #include <dev/extres/clk/clk_div.h> 43 #include <dev/extres/clk/clk_fixed.h> 44 #include <dev/extres/clk/clk_mux.h> 45 46 #include <arm/allwinner/clkng/aw_ccung.h> 47 48 #include <dt-bindings/clock/sun50i-a64-ccu.h> 49 #include <dt-bindings/reset/sun50i-a64-ccu.h> 50 51 /* Non-exported clocks */ 52 53 #define CLK_OSC_12M 0 54 #define CLK_PLL_CPUX 1 55 #define CLK_PLL_AUDIO_BASE 2 56 #define CLK_PLL_AUDIO 3 57 #define CLK_PLL_AUDIO_2X 4 58 #define CLK_PLL_AUDIO_4X 5 59 #define CLK_PLL_AUDIO_8X 6 60 #define CLK_PLL_VIDEO0 7 61 #define CLK_PLL_VIDEO0_2X 8 62 #define CLK_PLL_VE 9 63 #define CLK_PLL_DDR0 10 64 #define CLK_PLL_PERIPH0_2X 12 65 #define CLK_PLL_PERIPH1 13 66 #define CLK_PLL_PERIPH1_2X 14 67 #define CLK_PLL_VIDEO1 15 68 #define CLK_PLL_GPU 16 69 #define CLK_PLL_MIPI 17 70 #define CLK_PLL_HSIC 18 71 #define CLK_PLL_DE 19 72 #define CLK_PLL_DDR1 20 73 #define CLK_CPUX 21 74 #define CLK_AXI 22 75 #define CLK_APB 23 76 #define CLK_AHB1 24 77 #define CLK_APB1 25 78 #define CLK_APB2 26 79 #define CLK_AHB2 27 80 #define CLK_DRAM 94 81 82 #define CLK_MBUS 112 83 84 static struct aw_ccung_reset a64_ccu_resets[] = { 85 CCU_RESET(RST_USB_PHY0, 0x0cc, 0) 86 CCU_RESET(RST_USB_PHY1, 0x0cc, 1) 87 CCU_RESET(RST_USB_HSIC, 0x0cc, 2) 88 89 CCU_RESET(RST_BUS_MIPI_DSI, 0x2c0, 1) 90 CCU_RESET(RST_BUS_CE, 0x2c0, 5) 91 CCU_RESET(RST_BUS_DMA, 0x2c0, 6) 92 CCU_RESET(RST_BUS_MMC0, 0x2c0, 8) 93 CCU_RESET(RST_BUS_MMC1, 0x2c0, 9) 94 CCU_RESET(RST_BUS_MMC2, 0x2c0, 10) 95 CCU_RESET(RST_BUS_NAND, 0x2c0, 13) 96 CCU_RESET(RST_BUS_DRAM, 0x2c0, 14) 97 CCU_RESET(RST_BUS_EMAC, 0x2c0, 17) 98 CCU_RESET(RST_BUS_TS, 0x2c0, 18) 99 CCU_RESET(RST_BUS_HSTIMER, 0x2c0, 19) 100 CCU_RESET(RST_BUS_SPI0, 0x2c0, 20) 101 CCU_RESET(RST_BUS_SPI1, 0x2c0, 21) 102 CCU_RESET(RST_BUS_OTG, 0x2c0, 23) 103 CCU_RESET(RST_BUS_EHCI0, 0x2c0, 24) 104 CCU_RESET(RST_BUS_EHCI1, 0x2c0, 25) 105 CCU_RESET(RST_BUS_OHCI0, 0x2c0, 28) 106 CCU_RESET(RST_BUS_OHCI1, 0x2c0, 29) 107 108 CCU_RESET(RST_BUS_VE, 0x2c4, 0) 109 CCU_RESET(RST_BUS_TCON0, 0x2c4, 3) 110 CCU_RESET(RST_BUS_TCON1, 0x2c4, 4) 111 CCU_RESET(RST_BUS_DEINTERLACE, 0x2c4, 5) 112 CCU_RESET(RST_BUS_CSI, 0x2c4, 8) 113 CCU_RESET(RST_BUS_HDMI0, 0x2c4, 10) 114 CCU_RESET(RST_BUS_HDMI1, 0x2c4, 11) 115 CCU_RESET(RST_BUS_DE, 0x2c4, 12) 116 CCU_RESET(RST_BUS_GPU, 0x2c4, 20) 117 CCU_RESET(RST_BUS_MSGBOX, 0x2c4, 21) 118 CCU_RESET(RST_BUS_SPINLOCK, 0x2c4, 22) 119 CCU_RESET(RST_BUS_DBG, 0x2c4, 31) 120 121 CCU_RESET(RST_BUS_LVDS, 0x2C8, 31) 122 123 CCU_RESET(RST_BUS_CODEC, 0x2D0, 0) 124 CCU_RESET(RST_BUS_SPDIF, 0x2D0, 1) 125 CCU_RESET(RST_BUS_THS, 0x2D0, 8) 126 CCU_RESET(RST_BUS_I2S0, 0x2D0, 12) 127 CCU_RESET(RST_BUS_I2S1, 0x2D0, 13) 128 CCU_RESET(RST_BUS_I2S2, 0x2D0, 14) 129 130 CCU_RESET(RST_BUS_I2C0, 0x2D8, 0) 131 CCU_RESET(RST_BUS_I2C1, 0x2D8, 1) 132 CCU_RESET(RST_BUS_I2C2, 0x2D8, 2) 133 CCU_RESET(RST_BUS_SCR, 0x2D8, 5) 134 CCU_RESET(RST_BUS_UART0, 0x2D8, 16) 135 CCU_RESET(RST_BUS_UART1, 0x2D8, 17) 136 CCU_RESET(RST_BUS_UART2, 0x2D8, 18) 137 CCU_RESET(RST_BUS_UART3, 0x2D8, 19) 138 CCU_RESET(RST_BUS_UART4, 0x2D8, 20) 139 }; 140 141 static struct aw_ccung_gate a64_ccu_gates[] = { 142 CCU_GATE(CLK_BUS_MIPI_DSI, "bus-mipi-dsi", "ahb1", 0x60, 1) 143 CCU_GATE(CLK_BUS_CE, "bus-ce", "ahb1", 0x60, 5) 144 CCU_GATE(CLK_BUS_DMA, "bus-dma", "ahb1", 0x60, 6) 145 CCU_GATE(CLK_BUS_MMC0, "bus-mmc0", "ahb1", 0x60, 8) 146 CCU_GATE(CLK_BUS_MMC1, "bus-mmc1", "ahb1", 0x60, 9) 147 CCU_GATE(CLK_BUS_MMC2, "bus-mmc2", "ahb1", 0x60, 10) 148 CCU_GATE(CLK_BUS_NAND, "bus-nand", "ahb1", 0x60, 13) 149 CCU_GATE(CLK_BUS_DRAM, "bus-dram", "ahb1", 0x60, 14) 150 CCU_GATE(CLK_BUS_EMAC, "bus-emac", "ahb2", 0x60, 16) 151 CCU_GATE(CLK_BUS_TS, "bus-ts", "ahb1", 0x60, 18) 152 CCU_GATE(CLK_BUS_HSTIMER, "bus-hstimer", "ahb1", 0x60, 19) 153 CCU_GATE(CLK_BUS_SPI0, "bus-spi0", "ahb1", 0x60, 20) 154 CCU_GATE(CLK_BUS_SPI1, "bus-spi1", "ahb1", 0x60, 21) 155 CCU_GATE(CLK_BUS_OTG, "bus-otg", "ahb1", 0x60, 23) 156 CCU_GATE(CLK_BUS_EHCI0, "bus-ehci0", "ahb1", 0x60, 24) 157 CCU_GATE(CLK_BUS_EHCI1, "bus-ehci1", "ahb2", 0x60, 25) 158 CCU_GATE(CLK_BUS_OHCI0, "bus-ohci0", "ahb1", 0x60, 28) 159 CCU_GATE(CLK_BUS_OHCI1, "bus-ohci1", "ahb2", 0x60, 29) 160 161 CCU_GATE(CLK_BUS_VE, "bus-ve", "ahb1", 0x64, 0) 162 CCU_GATE(CLK_BUS_TCON0, "bus-tcon0", "ahb1", 0x64, 3) 163 CCU_GATE(CLK_BUS_TCON1, "bus-tcon1", "ahb1", 0x64, 4) 164 CCU_GATE(CLK_BUS_DEINTERLACE, "bus-deinterlace", "ahb1", 0x64, 5) 165 CCU_GATE(CLK_BUS_CSI, "bus-csi", "ahb1", 0x64, 8) 166 CCU_GATE(CLK_BUS_HDMI, "bus-hdmi", "ahb1", 0x64, 11) 167 CCU_GATE(CLK_BUS_DE, "bus-de", "ahb1", 0x64, 12) 168 CCU_GATE(CLK_BUS_GPU, "bus-gpu", "ahb1", 0x64, 20) 169 CCU_GATE(CLK_BUS_MSGBOX, "bus-msgbox", "ahb1", 0x64, 21) 170 CCU_GATE(CLK_BUS_SPINLOCK, "bus-spinlock", "ahb1", 0x64, 22) 171 172 CCU_GATE(CLK_BUS_CODEC, "bus-codec", "apb1", 0x68, 0) 173 CCU_GATE(CLK_BUS_SPDIF, "bus-spdif", "apb1", 0x68, 1) 174 CCU_GATE(CLK_BUS_PIO, "bus-pio", "apb1", 0x68, 5) 175 CCU_GATE(CLK_BUS_THS, "bus-ths", "apb1", 0x68, 8) 176 CCU_GATE(CLK_BUS_I2S0, "bus-i2s0", "apb1", 0x68, 12) 177 CCU_GATE(CLK_BUS_I2S1, "bus-i2s1", "apb1", 0x68, 13) 178 CCU_GATE(CLK_BUS_I2S2, "bus-i2s2", "apb1", 0x68, 14) 179 180 CCU_GATE(CLK_BUS_I2C0, "bus-i2c0", "apb2", 0x6C, 0) 181 CCU_GATE(CLK_BUS_I2C1, "bus-i2c1", "apb2", 0x6C, 1) 182 CCU_GATE(CLK_BUS_I2C2, "bus-i2c2", "apb2", 0x6C, 2) 183 CCU_GATE(CLK_BUS_SCR, "bus-src", "apb2", 0x6C, 5) 184 CCU_GATE(CLK_BUS_UART0, "bus-uart0", "apb2", 0x6C, 16) 185 CCU_GATE(CLK_BUS_UART1, "bus-uart1", "apb2", 0x6C, 17) 186 CCU_GATE(CLK_BUS_UART2, "bus-uart2", "apb2", 0x6C, 18) 187 CCU_GATE(CLK_BUS_UART3, "bus-uart3", "apb2", 0x6C, 19) 188 CCU_GATE(CLK_BUS_UART4, "bus-uart4", "apb2", 0x6C, 20) 189 190 CCU_GATE(CLK_BUS_DBG, "bus-dbg", "ahb1", 0x70, 7) 191 192 CCU_GATE(CLK_THS, "ths", "thsdiv", 0x74, 31) 193 194 CCU_GATE(CLK_USB_PHY0, "usb-phy0", "osc24M", 0xcc, 8) 195 CCU_GATE(CLK_USB_PHY1, "usb-phy1", "osc24M", 0xcc, 9) 196 CCU_GATE(CLK_USB_HSIC, "usb-hsic", "pll_hsic", 0xcc, 10) 197 CCU_GATE(CLK_USB_HSIC_12M, "usb-hsic-12M", "osc12M", 0xcc, 11) 198 CCU_GATE(CLK_USB_OHCI0, "usb-ohci0", "osc12M", 0xcc, 16) 199 CCU_GATE(CLK_USB_OHCI1, "usb-ohci1", "usb-ohci0", 0xcc, 17) 200 201 CCU_GATE(CLK_DRAM_VE, "dram-ve", "dram", 0x100, 0) 202 CCU_GATE(CLK_DRAM_CSI, "dram-csi", "dram", 0x100, 1) 203 CCU_GATE(CLK_DRAM_DEINTERLACE, "dram-deinterlace", "dram", 0x100, 2) 204 CCU_GATE(CLK_DRAM_TS, "dram-ts", "dram", 0x100, 3) 205 206 CCU_GATE(CLK_CSI_MISC, "csi-misc", "osc24M", 0x130, 31) 207 208 CCU_GATE(CLK_AC_DIG_4X, "ac-dig-4x", "pll_audio-4x", 0x140, 30) 209 CCU_GATE(CLK_AC_DIG, "ac-dig", "pll_audio", 0x140, 31) 210 211 CCU_GATE(CLK_AVS, "avs", "osc24M", 0x144, 31) 212 213 CCU_GATE(CLK_HDMI_DDC, "hdmi-ddc", "osc24M", 0x154, 31) 214 }; 215 216 static const char *osc12m_parents[] = {"osc24M"}; 217 FIXED_CLK(osc12m_clk, 218 CLK_OSC_12M, /* id */ 219 "osc12M", /* name */ 220 osc12m_parents, /* parent */ 221 0, /* freq */ 222 1, /* mult */ 223 2, /* div */ 224 0); /* flags */ 225 226 static const char *pll_cpux_parents[] = {"osc24M"}; 227 NKMP_CLK(pll_cpux_clk, 228 CLK_PLL_CPUX, /* id */ 229 "pll_cpux", pll_cpux_parents, /* name, parents */ 230 0x00, /* offset */ 231 8, 5, 0, 0, /* n factor */ 232 4, 2, 0, 0, /* k factor */ 233 0, 2, 0, 0, /* m factor */ 234 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* p factor */ 235 31, /* gate */ 236 28, 1000, /* lock */ 237 AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK | AW_CLK_SCALE_CHANGE); /* flags */ 238 239 static const char *pll_audio_parents[] = {"osc24M"}; 240 NKMP_CLK(pll_audio_clk, 241 CLK_PLL_AUDIO, /* id */ 242 "pll_audio", pll_audio_parents, /* name, parents */ 243 0x08, /* offset */ 244 8, 7, 0, 0, /* n factor */ 245 0, 0, 1, AW_CLK_FACTOR_FIXED, /* k factor (fake) */ 246 0, 5, 0, 0, /* m factor */ 247 16, 4, 0, 0, /* p factor */ 248 31, /* gate */ 249 28, 1000, /* lock */ 250 AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */ 251 252 static const char *pll_audio_mult_parents[] = {"pll_audio"}; 253 FIXED_CLK(pll_audio_2x_clk, 254 CLK_PLL_AUDIO_2X, /* id */ 255 "pll_audio-2x", /* name */ 256 pll_audio_mult_parents, /* parent */ 257 0, /* freq */ 258 2, /* mult */ 259 1, /* div */ 260 0); /* flags */ 261 FIXED_CLK(pll_audio_4x_clk, 262 CLK_PLL_AUDIO_4X, /* id */ 263 "pll_audio-4x", /* name */ 264 pll_audio_mult_parents, /* parent */ 265 0, /* freq */ 266 4, /* mult */ 267 1, /* div */ 268 0); /* flags */ 269 FIXED_CLK(pll_audio_8x_clk, 270 CLK_PLL_AUDIO_8X, /* id */ 271 "pll_audio-8x", /* name */ 272 pll_audio_mult_parents, /* parent */ 273 0, /* freq */ 274 8, /* mult */ 275 1, /* div */ 276 0); /* flags */ 277 278 static const char *pll_video0_parents[] = {"osc24M"}; 279 FRAC_CLK(pll_video0_clk, 280 CLK_PLL_VIDEO0, /* id */ 281 "pll_video0", pll_video0_parents, /* name, parents */ 282 0x10, /* offset */ 283 8, 7, 0, 0, /* n factor */ 284 0, 4, 0, 0, /* m factor */ 285 31, 28, 1000, /* gate, lock, lock retries */ 286 AW_CLK_HAS_LOCK, /* flags */ 287 270000000, 297000000, /* freq0, freq1 */ 288 24, 25, /* mode sel, freq sel */ 289 192000000, 600000000); /* min freq, max freq */ 290 static const char *pll_video0_2x_parents[] = {"pll_video0"}; 291 FIXED_CLK(pll_video0_2x_clk, 292 CLK_PLL_VIDEO0_2X, /* id */ 293 "pll_video0-2x", /* name */ 294 pll_video0_2x_parents, /* parent */ 295 0, /* freq */ 296 2, /* mult */ 297 1, /* div */ 298 0); /* flags */ 299 300 static const char *pll_ve_parents[] = {"osc24M"}; 301 FRAC_CLK(pll_ve_clk, 302 CLK_PLL_VE, /* id */ 303 "pll_ve", pll_ve_parents, /* name, parents */ 304 0x18, /* offset */ 305 8, 7, 0, 0, /* n factor */ 306 0, 4, 0, 0, /* m factor */ 307 31, 28, 1000, /* gate, lock, lock retries */ 308 AW_CLK_HAS_LOCK, /* flags */ 309 270000000, 297000000, /* freq0, freq1 */ 310 24, 25, /* mode sel, freq sel */ 311 192000000, 600000000); /* min freq, max freq */ 312 313 static const char *pll_ddr0_parents[] = {"osc24M"}; 314 NKMP_CLK_WITH_UPDATE(pll_ddr0_clk, 315 CLK_PLL_DDR0, /* id */ 316 "pll_ddr0", pll_ddr0_parents, /* name, parents */ 317 0x20, /* offset */ 318 8, 5, 0, 0, /* n factor */ 319 4, 2, 0, 0, /* k factor */ 320 0, 2, 0, 0, /* m factor */ 321 0, 0, 1, AW_CLK_FACTOR_FIXED, /* p factor (fake) */ 322 31, /* gate */ 323 28, 1000, /* lock */ 324 20, /* update */ 325 AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */ 326 327 static const char *pll_periph0_2x_parents[] = {"osc24M"}; 328 static const char *pll_periph0_parents[] = {"pll_periph0_2x"}; 329 NKMP_CLK(pll_periph0_2x_clk, 330 CLK_PLL_PERIPH0_2X, /* id */ 331 "pll_periph0_2x", pll_periph0_2x_parents, /* name, parents */ 332 0x28, /* offset */ 333 8, 5, 0, 0, /* n factor */ 334 4, 2, 0, 0, /* k factor */ 335 0, 0, 2, AW_CLK_FACTOR_FIXED, /* m factor (fake) */ 336 0, 0, 1, AW_CLK_FACTOR_FIXED, /* p factor (fake) */ 337 31, /* gate */ 338 28, 1000, /* lock */ 339 AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */ 340 FIXED_CLK(pll_periph0_clk, 341 CLK_PLL_PERIPH0, /* id */ 342 "pll_periph0", /* name */ 343 pll_periph0_parents, /* parent */ 344 0, /* freq */ 345 1, /* mult */ 346 2, /* div */ 347 0); /* flags */ 348 349 static const char *pll_periph1_2x_parents[] = {"osc24M"}; 350 static const char *pll_periph1_parents[] = {"pll_periph1_2x"}; 351 NKMP_CLK(pll_periph1_2x_clk, 352 CLK_PLL_PERIPH1_2X, /* id */ 353 "pll_periph1_2x", pll_periph1_2x_parents, /* name, parents */ 354 0x2C, /* offset */ 355 8, 5, 0, 0, /* n factor */ 356 4, 2, 0, 0, /* k factor */ 357 0, 0, 2, AW_CLK_FACTOR_FIXED, /* m factor (fake) */ 358 0, 0, 1, AW_CLK_FACTOR_FIXED, /* p factor (fake) */ 359 31, /* gate */ 360 28, 1000, /* lock */ 361 AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */ 362 FIXED_CLK(pll_periph1_clk, 363 CLK_PLL_PERIPH1, /* id */ 364 "pll_periph1", /* name */ 365 pll_periph1_parents, /* parent */ 366 0, /* freq */ 367 1, /* mult */ 368 2, /* div */ 369 0); /* flags */ 370 371 static const char *pll_video1_parents[] = {"osc24M"}; 372 FRAC_CLK(pll_video1_clk, 373 CLK_PLL_VIDEO1, /* id */ 374 "pll_video1", pll_video1_parents, /* name, parents */ 375 0x30, /* offset */ 376 8, 7, 0, 0, /* n factor */ 377 0, 4, 0, 0, /* m factor */ 378 31, 28, 1000, /* gate, lock, lock retries */ 379 AW_CLK_HAS_LOCK, /* flags */ 380 270000000, 297000000, /* freq0, freq1 */ 381 24, 25, /* mode sel, freq sel */ 382 192000000, 600000000); /* min freq, max freq */ 383 384 static const char *pll_gpu_parents[] = {"osc24M"}; 385 FRAC_CLK(pll_gpu_clk, 386 CLK_PLL_GPU, /* id */ 387 "pll_gpu", pll_gpu_parents, /* name, parents */ 388 0x38, /* offset */ 389 8, 7, 0, 0, /* n factor */ 390 0, 4, 0, 0, /* m factor */ 391 31, 28, 1000, /* gate, lock, lock retries */ 392 AW_CLK_HAS_LOCK, /* flags */ 393 270000000, 297000000, /* freq0, freq1 */ 394 24, 25, /* mode sel, freq sel */ 395 192000000, 600000000); /* min freq, max freq */ 396 397 static const char *pll_mipi_parents[] = {"pll_video0"}; 398 MIPI_CLK(pll_mipi_clk, 399 CLK_PLL_MIPI, 400 "pll_mipi", pll_mipi_parents, 401 0x40, 402 4, 2, AW_CLK_FACTOR_MIN_VALUE, 2, 403 0, 3, 404 8, 4, 405 31, 28); 406 407 static const char *pll_hsic_parents[] = {"osc24M"}; 408 FRAC_CLK(pll_hsic_clk, 409 CLK_PLL_HSIC, /* id */ 410 "pll_hsic", pll_hsic_parents, /* name, parents */ 411 0x44, /* offset */ 412 8, 7, 0, 0, /* n factor */ 413 0, 4, 0, 0, /* m factor */ 414 31, 28, 1000, /* gate, lock, lock retries */ 415 AW_CLK_HAS_LOCK, /* flags */ 416 270000000, 297000000, /* freq0, freq1 */ 417 24, 25, /* mode sel, freq sel */ 418 192000000, 600000000); /* min freq, max freq */ 419 420 static const char *pll_de_parents[] = {"osc24M"}; 421 FRAC_CLK(pll_de_clk, 422 CLK_PLL_DE, /* id */ 423 "pll_de", pll_de_parents, /* name, parents */ 424 0x48, /* offset */ 425 8, 7, 0, 0, /* n factor */ 426 0, 4, 0, 0, /* m factor */ 427 31, 28, 1000, /* gate, lock, lock retries */ 428 AW_CLK_HAS_LOCK, /* flags */ 429 270000000, 297000000, /* freq0, freq1 */ 430 24, 25, /* mode sel, freq sel */ 431 192000000, 600000000); /* min freq, max freq */ 432 433 static const char *pll_ddr1_parents[] = {"osc24M"}; 434 NKMP_CLK_WITH_UPDATE(pll_ddr1_clk, 435 CLK_PLL_DDR1, /* id */ 436 "pll_ddr1", pll_ddr1_parents, /* name, parents */ 437 0x4C, /* offset */ 438 8, 7, 0, 0, /* n factor */ 439 0, 0, 1, AW_CLK_FACTOR_FIXED, /* k factor (fake) */ 440 0, 2, 0, 0, /* m factor */ 441 0, 0, 1, AW_CLK_FACTOR_FIXED, /* p factor (fake) */ 442 31, /* gate */ 443 28, 1000, /* lock */ 444 20, /* update */ 445 AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */ 446 447 static const char *cpux_parents[] = {"osc32k", "osc24M", "pll_cpux"}; 448 MUX_CLK(cpux_clk, 449 CLK_CPUX, /* id */ 450 "cpux", cpux_parents, /* name, parents */ 451 0x50, 16, 2); /* offset, shift, width */ 452 453 static const char *axi_parents[] = {"cpux"}; 454 DIV_CLK(axi_clk, 455 CLK_AXI, /* id */ 456 "axi", axi_parents, /* name, parents */ 457 0x50, /* offset */ 458 0, 2, /* shift, width */ 459 0, NULL); /* flags, div table */ 460 461 static const char *apb_parents[] = {"cpux"}; 462 DIV_CLK(apb_clk, 463 CLK_APB, /* id */ 464 "apb", apb_parents, /* name, parents */ 465 0x50, /* offset */ 466 8, 2, /* shift, width */ 467 0, NULL); /* flags, div table */ 468 469 static const char *ahb1_parents[] = {"osc32k", "osc24M", "axi", "pll_periph0"}; 470 PREDIV_CLK(ahb1_clk, CLK_AHB1, /* id */ 471 "ahb1", ahb1_parents, /* name, parents */ 472 0x54, /* offset */ 473 12, 2, /* mux */ 474 4, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* div */ 475 6, 2, 0, AW_CLK_FACTOR_HAS_COND, /* prediv */ 476 12, 2, 3); /* prediv condition */ 477 478 static const char *apb1_parents[] = {"ahb1"}; 479 static struct clk_div_table apb1_div_table[] = { 480 { .value = 0, .divider = 2, }, 481 { .value = 1, .divider = 2, }, 482 { .value = 2, .divider = 4, }, 483 { .value = 3, .divider = 8, }, 484 { }, 485 }; 486 DIV_CLK(apb1_clk, 487 CLK_APB1, /* id */ 488 "apb1", apb1_parents, /* name, parents */ 489 0x54, /* offset */ 490 8, 2, /* shift, width */ 491 CLK_DIV_WITH_TABLE, /* flags */ 492 apb1_div_table); /* div table */ 493 494 static const char *apb2_parents[] = {"osc32k", "osc24M", "pll_periph0_2x", "pll_periph0_2x"}; 495 NM_CLK(apb2_clk, 496 CLK_APB2, /* id */ 497 "apb2", apb2_parents, /* name, parents */ 498 0x58, /* offset */ 499 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 500 0, 5, 0, 0, /* m factor */ 501 24, 2, /* mux */ 502 0, /* gate */ 503 AW_CLK_HAS_MUX); 504 505 static const char *ahb2_parents[] = {"ahb1", "pll_periph0"}; 506 PREDIV_CLK(ahb2_clk, CLK_AHB2, /* id */ 507 "ahb2", ahb2_parents, /* name, parents */ 508 0x5c, /* offset */ 509 0, 2, /* mux */ 510 0, 0, 1, AW_CLK_FACTOR_FIXED, /* div */ 511 0, 0, 2, AW_CLK_FACTOR_HAS_COND | AW_CLK_FACTOR_FIXED, /* prediv */ 512 0, 2, 1); /* prediv condition */ 513 514 static const char *ths_parents[] = {"osc24M"}; 515 static struct clk_div_table ths_div_table[] = { 516 { .value = 0, .divider = 1, }, 517 { .value = 1, .divider = 2, }, 518 { .value = 2, .divider = 4, }, 519 { .value = 3, .divider = 6, }, 520 { }, 521 }; 522 DIV_CLK(ths_clk, 523 0, /* id */ 524 "thsdiv", ths_parents, /* name, parents */ 525 0x74, /* offset */ 526 0, 2, /* div shift, div width */ 527 CLK_DIV_WITH_TABLE, /* flags */ 528 ths_div_table); /* div table */ 529 530 static const char *mod_parents[] = {"osc24M", "pll_periph0_2x", "pll_periph1_2x"}; 531 NM_CLK(nand_clk, 532 CLK_NAND, "nand", mod_parents, /* id, name, parents */ 533 0x80, /* offset */ 534 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 535 0, 4, 0, 0, /* m factor */ 536 24, 2, /* mux */ 537 31, /* gate */ 538 AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); /* flags */ 539 540 NM_CLK(mmc0_clk, 541 CLK_MMC0, "mmc0", mod_parents, /* id, name, parents */ 542 0x88, /* offset */ 543 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 544 0, 4, 0, 0, /* m factor */ 545 24, 2, /* mux */ 546 31, /* gate */ 547 AW_CLK_HAS_GATE | AW_CLK_HAS_MUX | 548 AW_CLK_REPARENT); /* flags */ 549 550 NM_CLK(mmc1_clk, 551 CLK_MMC1, "mmc1", mod_parents, /* id, name, parents */ 552 0x8c, /* offset */ 553 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 554 0, 4, 0, 0, /* m factor */ 555 24, 2, /* mux */ 556 31, /* gate */ 557 AW_CLK_HAS_GATE | AW_CLK_HAS_MUX | 558 AW_CLK_REPARENT); /* flags */ 559 560 NM_CLK(mmc2_clk, 561 CLK_MMC2, "mmc2", mod_parents, /* id, name, parents */ 562 0x90, /* offset */ 563 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 564 0, 4, 0, 0, /* m factor */ 565 24, 2, /* mux */ 566 31, /* gate */ 567 AW_CLK_HAS_GATE | AW_CLK_HAS_MUX | 568 AW_CLK_REPARENT); /* flags */ 569 570 static const char *ts_parents[] = {"osc24M", "pll_periph0"}; 571 NM_CLK(ts_clk, 572 CLK_TS, "ts", ts_parents, /* id, name, parents */ 573 0x98, /* offset */ 574 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 575 0, 4, 0, 0, /* m factor */ 576 24, 2, /* mux */ 577 31, /* gate */ 578 AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); /* flags */ 579 580 NM_CLK(ce_clk, 581 CLK_CE, "ce", mod_parents, /* id, name, parents */ 582 0x9C, /* offset */ 583 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 584 0, 4, 0, 0, /* m factor */ 585 24, 2, /* mux */ 586 31, /* gate */ 587 AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); /* flags */ 588 589 NM_CLK(spi0_clk, 590 CLK_SPI0, "spi0", mod_parents, /* id, name, parents */ 591 0xA0, /* offset */ 592 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 593 0, 4, 0, 0, /* m factor */ 594 24, 2, /* mux */ 595 31, /* gate */ 596 AW_CLK_HAS_GATE | AW_CLK_HAS_MUX | 597 AW_CLK_REPARENT); /* flags */ 598 599 NM_CLK(spi1_clk, 600 CLK_SPI1, "spi1", mod_parents, /* id, name, parents */ 601 0xA4, /* offset */ 602 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 603 0, 4, 0, 0, /* m factor */ 604 24, 2, /* mux */ 605 31, /* gate */ 606 AW_CLK_HAS_GATE | AW_CLK_HAS_MUX | 607 AW_CLK_REPARENT); /* flags */ 608 609 static const char *i2s_parents[] = {"pll_audio-8x", "pll_audio-4x", "pll_audio-2x", "pll_audio"}; 610 MUX_CLK(i2s0mux_clk, 611 0, "i2s0mux", i2s_parents, /* id, name, parents */ 612 0xb0, 16, 2); /* offset, mux shift, mux width */ 613 MUX_CLK(i2s1mux_clk, 614 0, "i2s1mux", i2s_parents, /* id, name, parents */ 615 0xb4, 16, 2); /* offset, mux shift, mux width */ 616 MUX_CLK(i2s2mux_clk, 617 0, "i2s2mux", i2s_parents, /* id, name, parents */ 618 0xb8, 16, 2); /* offset, mux shift, mux width */ 619 620 static const char *spdif_parents[] = {"pll_audio"}; 621 M_CLK(spdif_clk, 622 CLK_SPDIF, "spdif", spdif_parents, /* id, name, parents */ 623 0xC0, /* offset */ 624 0, 4, 0, 0, /* m factor */ 625 0, 0, /* mux */ 626 31, /* gate */ 627 AW_CLK_HAS_GATE); /* flags */ 628 629 /* USBPHY clk sel */ 630 631 /* DRAM needs update bit */ 632 static const char *dram_parents[] = {"pll_ddr0", "pll_ddr1"}; 633 M_CLK(dram_clk, 634 CLK_DRAM, "dram", dram_parents, /* id, name, parents */ 635 0xF4, /* offset */ 636 0, 2, 0, 0, /* m factor */ 637 20, 2, /* mux */ 638 0, /* gate */ 639 AW_CLK_HAS_MUX); /* flags */ 640 641 static const char *de_parents[] = {"pll_periph0_2x", "pll_de"}; 642 M_CLK(de_clk, 643 CLK_DE, "de", de_parents, /* id, name, parents */ 644 0x104, /* offset */ 645 0, 4, 0, 0, /* m factor */ 646 24, 2, /* mux */ 647 31, /* gate */ 648 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ 649 650 static const char *tcon0_parents[] = {"pll_mipi", NULL, "pll_video0-2x"}; 651 MUX_CLK(tcon0_clk, 652 CLK_TCON0, /* id */ 653 "tcon0", tcon0_parents, /* name, parents */ 654 0x118, 24, 2); /* offset, shift, width */ 655 656 static const char *tcon1_parents[] = {"pll_video0", NULL, "pll_video1"}; 657 M_CLK(tcon1_clk, 658 CLK_TCON1, "tcon1", tcon1_parents, /* id, name, parents */ 659 0x11C, /* offset */ 660 0, 5, 0, 0, /* m factor */ 661 24, 2, /* mux */ 662 31, /* gate */ 663 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE | 664 AW_CLK_SET_PARENT); /* flags */ 665 666 static const char *deinterlace_parents[] = {"pll_periph0", "pll_periph1"}; 667 M_CLK(deinterlace_clk, 668 CLK_DEINTERLACE, "deinterlace", deinterlace_parents, /* id, name, parents */ 669 0x124, /* offset */ 670 0, 4, 0, 0, /* m factor */ 671 24, 2, /* mux */ 672 31, /* gate */ 673 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ 674 675 static const char *csi_sclk_parents[] = {"pll_periph0", "pll_periph1"}; 676 M_CLK(csi_sclk_clk, 677 CLK_CSI_SCLK, "csi-sclk", csi_sclk_parents, /* id, name, parents */ 678 0x134, /* offset */ 679 16, 4, 0, 0, /* m factor */ 680 24, 2, /* mux */ 681 31, /* gate */ 682 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ 683 684 static const char *csi_mclk_parents[] = {"osc24M", "pll_video0", "pll_periph1"}; 685 M_CLK(csi_mclk_clk, 686 CLK_CSI_MCLK, "csi-mclk", csi_mclk_parents, /* id, name, parents */ 687 0x134, /* offset */ 688 0, 4, 0, 0, /* m factor */ 689 8, 2, /* mux */ 690 15, /* gate */ 691 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ 692 693 static const char *ve_parents[] = {"pll_ve"}; 694 M_CLK(ve_clk, 695 CLK_VE, "ve", ve_parents, /* id, name, parents */ 696 0x13C, /* offset */ 697 16, 3, 0, 0, /* m factor */ 698 0, 0, /* mux */ 699 31, /* gate */ 700 AW_CLK_HAS_GATE); /* flags */ 701 702 static const char *hdmi_parents[] = {"pll_video0"}; 703 M_CLK(hdmi_clk, 704 CLK_HDMI, "hdmi", hdmi_parents, /* id, name, parents */ 705 0x150, /* offset */ 706 0, 4, 0, 0, /* m factor */ 707 24, 2, /* mux */ 708 31, /* gate */ 709 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE | AW_CLK_SET_PARENT); /* flags */ 710 711 static const char *mbus_parents[] = {"osc24M", "pll_periph0_2x", "pll_ddr0"}; 712 M_CLK(mbus_clk, 713 CLK_MBUS, "mbus", mbus_parents, /* id, name, parents */ 714 0x15C, /* offset */ 715 0, 3, 0, 0, /* m factor */ 716 24, 2, /* mux */ 717 31, /* gate */ 718 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ 719 720 static const char *gpu_parents[] = {"pll_gpu"}; 721 M_CLK(gpu_clk, 722 CLK_GPU, "gpu", gpu_parents, /* id, name, parents */ 723 0x1A0, /* offset */ 724 0, 2, 0, 0, /* m factor */ 725 0, 0, /* mux */ 726 31, /* gate */ 727 AW_CLK_HAS_GATE); /* flags */ 728 729 static struct aw_ccung_clk a64_ccu_clks[] = { 730 { .type = AW_CLK_NKMP, .clk.nkmp = &pll_cpux_clk}, 731 { .type = AW_CLK_NKMP, .clk.nkmp = &pll_audio_clk}, 732 { .type = AW_CLK_FRAC, .clk.frac = &pll_video0_clk}, 733 { .type = AW_CLK_FRAC, .clk.frac = &pll_ve_clk}, 734 { .type = AW_CLK_NKMP, .clk.nkmp = &pll_ddr0_clk}, 735 { .type = AW_CLK_NKMP, .clk.nkmp = &pll_periph0_2x_clk}, 736 { .type = AW_CLK_NKMP, .clk.nkmp = &pll_periph1_2x_clk}, 737 { .type = AW_CLK_FRAC, .clk.frac = &pll_video1_clk}, 738 { .type = AW_CLK_FRAC, .clk.frac = &pll_gpu_clk}, 739 { .type = AW_CLK_MIPI, .clk.mipi = &pll_mipi_clk}, 740 { .type = AW_CLK_FRAC, .clk.frac = &pll_hsic_clk}, 741 { .type = AW_CLK_FRAC, .clk.frac = &pll_de_clk}, 742 { .type = AW_CLK_NKMP, .clk.nkmp = &pll_ddr1_clk}, 743 744 { .type = AW_CLK_NM, .clk.nm = &apb2_clk}, 745 { .type = AW_CLK_NM, .clk.nm = &nand_clk}, 746 { .type = AW_CLK_NM, .clk.nm = &mmc0_clk}, 747 { .type = AW_CLK_NM, .clk.nm = &mmc1_clk}, 748 { .type = AW_CLK_NM, .clk.nm = &mmc2_clk}, 749 { .type = AW_CLK_NM, .clk.nm = &ts_clk}, 750 { .type = AW_CLK_NM, .clk.nm = &ce_clk}, 751 { .type = AW_CLK_NM, .clk.nm = &spi0_clk}, 752 { .type = AW_CLK_NM, .clk.nm = &spi1_clk}, 753 { .type = AW_CLK_M, .clk.m = &spdif_clk}, 754 { .type = AW_CLK_M, .clk.m = &dram_clk}, 755 { .type = AW_CLK_M, .clk.m = &de_clk}, 756 { .type = AW_CLK_M, .clk.m = &tcon1_clk}, 757 { .type = AW_CLK_M, .clk.m = &deinterlace_clk}, 758 { .type = AW_CLK_M, .clk.m = &csi_sclk_clk}, 759 { .type = AW_CLK_M, .clk.m = &csi_mclk_clk}, 760 { .type = AW_CLK_M, .clk.m = &ve_clk}, 761 { .type = AW_CLK_M, .clk.m = &hdmi_clk}, 762 { .type = AW_CLK_M, .clk.m = &mbus_clk}, 763 { .type = AW_CLK_M, .clk.m = &gpu_clk}, 764 { .type = AW_CLK_PREDIV_MUX, .clk.prediv_mux = &ahb1_clk}, 765 { .type = AW_CLK_PREDIV_MUX, .clk.prediv_mux = &ahb2_clk}, 766 { .type = AW_CLK_MUX, .clk.mux = &cpux_clk}, 767 { .type = AW_CLK_MUX, .clk.mux = &i2s0mux_clk}, 768 { .type = AW_CLK_MUX, .clk.mux = &i2s1mux_clk}, 769 { .type = AW_CLK_MUX, .clk.mux = &i2s2mux_clk}, 770 { .type = AW_CLK_MUX, .clk.mux = &tcon0_clk}, 771 { .type = AW_CLK_DIV, .clk.div = &axi_clk}, 772 { .type = AW_CLK_DIV, .clk.div = &apb1_clk}, 773 { .type = AW_CLK_DIV, .clk.div = &apb_clk}, 774 { .type = AW_CLK_DIV, .clk.div = &ths_clk}, 775 { .type = AW_CLK_FIXED, .clk.fixed = &osc12m_clk}, 776 { .type = AW_CLK_FIXED, .clk.fixed = &pll_periph0_clk}, 777 { .type = AW_CLK_FIXED, .clk.fixed = &pll_periph1_clk}, 778 { .type = AW_CLK_FIXED, .clk.fixed = &pll_audio_2x_clk}, 779 { .type = AW_CLK_FIXED, .clk.fixed = &pll_audio_4x_clk}, 780 { .type = AW_CLK_FIXED, .clk.fixed = &pll_audio_8x_clk}, 781 { .type = AW_CLK_FIXED, .clk.fixed = &pll_video0_2x_clk}, 782 }; 783 784 static struct aw_clk_init a64_init_clks[] = { 785 {"ahb1", "pll_periph0", 0, false}, 786 {"ahb2", "pll_periph0", 0, false}, 787 {"dram", "pll_ddr0", 0, false}, 788 {"pll_de", NULL, 432000000, true}, 789 {"de", "pll_de", 0, true}, 790 }; 791 792 static int 793 ccu_a64_probe(device_t dev) 794 { 795 796 if (!ofw_bus_status_okay(dev)) 797 return (ENXIO); 798 799 if (!ofw_bus_is_compatible(dev, "allwinner,sun50i-a64-ccu")) 800 return (ENXIO); 801 802 device_set_desc(dev, "Allwinner A64 Clock Control Unit NG"); 803 return (BUS_PROBE_DEFAULT); 804 } 805 806 static int 807 ccu_a64_attach(device_t dev) 808 { 809 struct aw_ccung_softc *sc; 810 811 sc = device_get_softc(dev); 812 813 sc->resets = a64_ccu_resets; 814 sc->nresets = nitems(a64_ccu_resets); 815 sc->gates = a64_ccu_gates; 816 sc->ngates = nitems(a64_ccu_gates); 817 sc->clks = a64_ccu_clks; 818 sc->nclks = nitems(a64_ccu_clks); 819 sc->clk_init = a64_init_clks; 820 sc->n_clk_init = nitems(a64_init_clks); 821 822 return (aw_ccung_attach(dev)); 823 } 824 825 static device_method_t ccu_a64ng_methods[] = { 826 /* Device interface */ 827 DEVMETHOD(device_probe, ccu_a64_probe), 828 DEVMETHOD(device_attach, ccu_a64_attach), 829 830 DEVMETHOD_END 831 }; 832 833 static devclass_t ccu_a64ng_devclass; 834 835 DEFINE_CLASS_1(ccu_a64ng, ccu_a64ng_driver, ccu_a64ng_methods, 836 sizeof(struct aw_ccung_softc), aw_ccung_driver); 837 838 EARLY_DRIVER_MODULE(ccu_a64ng, simplebus, ccu_a64ng_driver, 839 ccu_a64ng_devclass, 0, 0, BUS_PASS_RESOURCE + BUS_PASS_ORDER_MIDDLE); 840