1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2017 Kyle Evans <kevans@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/bus.h> 32 #include <sys/rman.h> 33 #include <sys/kernel.h> 34 #include <sys/module.h> 35 #include <machine/bus.h> 36 37 #include <dev/fdt/simplebus.h> 38 39 #include <dev/ofw/ofw_bus.h> 40 #include <dev/ofw/ofw_bus_subr.h> 41 42 #include <dev/extres/clk/clk_div.h> 43 #include <dev/extres/clk/clk_fixed.h> 44 #include <dev/extres/clk/clk_mux.h> 45 46 #include <arm/allwinner/clkng/aw_ccung.h> 47 48 #include <dt-bindings/clock/sun8i-a83t-ccu.h> 49 #include <dt-bindings/reset/sun8i-a83t-ccu.h> 50 51 /* Non-exported clocks */ 52 53 #define CLK_PLL_C0CPUX 0 54 #define CLK_PLL_C1CPUX 1 55 #define CLK_PLL_AUDIO 2 56 #define CLK_PLL_VIDEO0 3 57 #define CLK_PLL_VE 4 58 #define CLK_PLL_DDR 5 59 60 #define CLK_PLL_GPU 7 61 #define CLK_PLL_HSIC 8 62 #define CLK_PLL_VIDEO1 10 63 64 #define CLK_AXI0 13 65 #define CLK_AXI1 14 66 #define CLK_AHB1 15 67 #define CLK_APB1 16 68 #define CLK_APB2 17 69 #define CLK_AHB2 18 70 71 #define CLK_CCI400 58 72 73 #define CLK_DRAM 82 74 75 #define CLK_MBUS 95 76 77 /* Non-exported fixed clocks */ 78 #define CLK_OSC_12M 150 79 80 static struct aw_ccung_reset a83t_ccu_resets[] = { 81 CCU_RESET(RST_USB_PHY0, 0xcc, 0) 82 CCU_RESET(RST_USB_PHY1, 0xcc, 1) 83 CCU_RESET(RST_USB_HSIC, 0xcc, 2) 84 85 CCU_RESET(RST_DRAM, 0xf4, 31) 86 CCU_RESET(RST_MBUS, 0xfc, 31) 87 88 CCU_RESET(RST_BUS_MIPI_DSI, 0x2c0, 1) 89 CCU_RESET(RST_BUS_SS, 0x2c0, 5) 90 CCU_RESET(RST_BUS_DMA, 0x2c0, 6) 91 CCU_RESET(RST_BUS_MMC0, 0x2c0, 8) 92 CCU_RESET(RST_BUS_MMC1, 0x2c0, 9) 93 CCU_RESET(RST_BUS_MMC2, 0x2c0, 10) 94 CCU_RESET(RST_BUS_NAND, 0x2c0, 13) 95 CCU_RESET(RST_BUS_DRAM, 0x2c0, 14) 96 CCU_RESET(RST_BUS_EMAC, 0x2c0, 17) 97 CCU_RESET(RST_BUS_HSTIMER, 0x2c0, 19) 98 CCU_RESET(RST_BUS_SPI0, 0x2c0, 20) 99 CCU_RESET(RST_BUS_SPI1, 0x2c0, 21) 100 CCU_RESET(RST_BUS_OTG, 0x2c0, 24) 101 CCU_RESET(RST_BUS_EHCI0, 0x2c0, 26) 102 CCU_RESET(RST_BUS_EHCI1, 0x2c0, 27) 103 CCU_RESET(RST_BUS_OHCI0, 0x2c0, 29) 104 105 CCU_RESET(RST_BUS_VE, 0x2c4, 0) 106 CCU_RESET(RST_BUS_TCON0, 0x2c4, 4) 107 CCU_RESET(RST_BUS_TCON1, 0x2c4, 5) 108 CCU_RESET(RST_BUS_CSI, 0x2c4, 8) 109 CCU_RESET(RST_BUS_HDMI0, 0x2c4, 10) 110 CCU_RESET(RST_BUS_HDMI1, 0x2c4, 11) 111 CCU_RESET(RST_BUS_DE, 0x2c4, 12) 112 CCU_RESET(RST_BUS_GPU, 0x2c4, 20) 113 CCU_RESET(RST_BUS_MSGBOX, 0x2c4, 21) 114 CCU_RESET(RST_BUS_SPINLOCK, 0x2c4, 22) 115 116 CCU_RESET(RST_BUS_LVDS, 0x2c8, 0) 117 118 CCU_RESET(RST_BUS_SPDIF, 0x2d0, 1) 119 CCU_RESET(RST_BUS_I2S0, 0x2d0, 12) 120 CCU_RESET(RST_BUS_I2S1, 0x2d0, 13) 121 CCU_RESET(RST_BUS_I2S2, 0x2d0, 14) 122 CCU_RESET(RST_BUS_TDM, 0x2d0, 15) 123 124 CCU_RESET(RST_BUS_I2C0, 0x2d8, 0) 125 CCU_RESET(RST_BUS_I2C1, 0x2d8, 1) 126 CCU_RESET(RST_BUS_I2C2, 0x2d8, 2) 127 CCU_RESET(RST_BUS_UART0, 0x2d8, 16) 128 CCU_RESET(RST_BUS_UART1, 0x2d8, 17) 129 CCU_RESET(RST_BUS_UART2, 0x2d8, 18) 130 CCU_RESET(RST_BUS_UART3, 0x2d8, 19) 131 CCU_RESET(RST_BUS_UART4, 0x2d8, 20) 132 }; 133 134 static struct aw_ccung_gate a83t_ccu_gates[] = { 135 CCU_GATE(CLK_BUS_MIPI_DSI, "bus-mipi-dsi", "ahb1", 0x60, 1) 136 CCU_GATE(CLK_BUS_SS, "bus-ss", "ahb1", 0x60, 5) 137 CCU_GATE(CLK_BUS_DMA, "bus-dma", "ahb1", 0x60, 6) 138 CCU_GATE(CLK_BUS_MMC0, "bus-mmc0", "ahb1", 0x60, 8) 139 CCU_GATE(CLK_BUS_MMC1, "bus-mmc1", "ahb1", 0x60, 9) 140 CCU_GATE(CLK_BUS_MMC2, "bus-mmc2", "ahb1", 0x60, 10) 141 CCU_GATE(CLK_BUS_NAND, "bus-nand", "ahb1", 0x60, 13) 142 CCU_GATE(CLK_BUS_DRAM, "bus-dram", "ahb1", 0x60, 14) 143 CCU_GATE(CLK_BUS_EMAC, "bus-emac", "ahb1", 0x60, 17) 144 CCU_GATE(CLK_BUS_HSTIMER, "bus-hstimer", "ahb1", 0x60, 19) 145 CCU_GATE(CLK_BUS_SPI0, "bus-spi0", "ahb1", 0x60, 20) 146 CCU_GATE(CLK_BUS_SPI1, "bus-spi1", "ahb1", 0x60, 21) 147 CCU_GATE(CLK_BUS_OTG, "bus-otg", "ahb1", 0x60, 24) 148 CCU_GATE(CLK_BUS_EHCI0, "bus-ehci0", "ahb2", 0x60, 26) 149 CCU_GATE(CLK_BUS_EHCI1, "bus-ehci1", "ahb2", 0x60, 27) 150 CCU_GATE(CLK_BUS_OHCI0, "bus-ohci0", "ahb2", 0x60, 29) 151 152 CCU_GATE(CLK_BUS_VE, "bus-ve", "ahb1", 0x64, 0) 153 CCU_GATE(CLK_BUS_TCON0, "bus-tcon0", "ahb1", 0x64, 4) 154 CCU_GATE(CLK_BUS_TCON1, "bus-tcon1", "ahb1", 0x64, 5) 155 CCU_GATE(CLK_BUS_CSI, "bus-csi", "ahb1", 0x64, 8) 156 CCU_GATE(CLK_BUS_HDMI, "bus-hdmi", "ahb1", 0x64, 11) 157 CCU_GATE(CLK_BUS_DE, "bus-de", "ahb1", 0x64, 12) 158 CCU_GATE(CLK_BUS_GPU, "bus-gpu", "ahb1", 0x64, 20) 159 CCU_GATE(CLK_BUS_MSGBOX, "bus-msgbox", "ahb1", 0x64, 21) 160 CCU_GATE(CLK_BUS_SPINLOCK, "bus-spinlock", "ahb1", 0x64, 22) 161 162 CCU_GATE(CLK_BUS_SPDIF, "bus-spdif", "apb1", 0x68, 1) 163 CCU_GATE(CLK_BUS_PIO, "bus-pio", "apb1", 0x68, 5) 164 CCU_GATE(CLK_BUS_I2S0, "bus-i2s0", "apb1", 0x68, 12) 165 CCU_GATE(CLK_BUS_I2S1, "bus-i2s1", "apb1", 0x68, 13) 166 CCU_GATE(CLK_BUS_I2S2, "bus-i2s2", "apb1", 0x68, 14) 167 CCU_GATE(CLK_BUS_TDM, "bus-tdm", "apb1", 0x68, 15) 168 169 CCU_GATE(CLK_BUS_I2C0, "bus-i2c0", "apb2", 0x6c, 0) 170 CCU_GATE(CLK_BUS_I2C1, "bus-i2c1", "apb2", 0x6c, 1) 171 CCU_GATE(CLK_BUS_I2C2, "bus-i2c2", "apb2", 0x6c, 2) 172 CCU_GATE(CLK_BUS_UART0, "bus-uart0", "apb2", 0x6c, 16) 173 CCU_GATE(CLK_BUS_UART1, "bus-uart1", "apb2", 0x6c, 17) 174 CCU_GATE(CLK_BUS_UART2, "bus-uart2", "apb2", 0x6c, 18) 175 CCU_GATE(CLK_BUS_UART3, "bus-uart3", "apb2", 0x6c, 19) 176 CCU_GATE(CLK_BUS_UART4, "bus-uart4", "apb2", 0x6c, 20) 177 178 CCU_GATE(CLK_USB_PHY0, "usb-phy0", "osc24M", 0xcc, 8) 179 CCU_GATE(CLK_USB_PHY1, "usb-phy1", "osc24M", 0xcc, 9) 180 CCU_GATE(CLK_USB_HSIC, "usb-hsic", "pll_hsic", 0xcc, 10) 181 CCU_GATE(CLK_USB_HSIC_12M, "usb-hsic-12M", "osc12M", 0xcc, 11) 182 CCU_GATE(CLK_USB_OHCI0, "usb-ohci0", "osc12M", 0xcc, 16) 183 184 CCU_GATE(CLK_DRAM_VE, "dram-ve", "dram", 0x100, 0) 185 CCU_GATE(CLK_DRAM_CSI, "dram-csi", "dram", 0x100, 1) 186 187 CCU_GATE(CLK_CSI_MISC, "csi-misc", "osc24M", 0x130, 16) 188 CCU_GATE(CLK_MIPI_CSI, "mipi-csi", "osc24M", 0x130, 31) 189 190 CCU_GATE(CLK_AVS, "avs", "osc24M", 0x144, 31) 191 192 CCU_GATE(CLK_HDMI_SLOW, "hdmi-ddc", "osc24M", 0x154, 31) 193 }; 194 195 static const char *osc12m_parents[] = {"osc24M"}; 196 FIXED_CLK(osc12m_clk, 197 CLK_OSC_12M, /* id */ 198 "osc12M", osc12m_parents, /* name, parents */ 199 0, /* freq */ 200 1, /* mult */ 201 2, /* div */ 202 0); /* flags */ 203 204 /* CPU PLL are 24Mhz * N / P */ 205 static const char *pll_c0cpux_parents[] = {"osc24M"}; 206 static const char *pll_c1cpux_parents[] = {"osc24M"}; 207 NKMP_CLK(pll_c0cpux_clk, 208 CLK_PLL_C0CPUX, /* id */ 209 "pll_c0cpux", pll_c0cpux_parents, /* name, parents */ 210 0x00, /* offset */ 211 8, 8, 0, AW_CLK_FACTOR_ZERO_BASED, /* n factor */ 212 0, 0, 1, AW_CLK_FACTOR_FIXED, /* k factor (fake) */ 213 0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor */ 214 0, 0, 1, AW_CLK_FACTOR_FIXED, /* p factor (fake) */ 215 0, 0, /* lock */ 216 31, /* gate */ 217 AW_CLK_HAS_GATE | AW_CLK_SCALE_CHANGE); /* flags */ 218 NKMP_CLK(pll_c1cpux_clk, 219 CLK_PLL_C1CPUX, /* id */ 220 "pll_c1cpux", pll_c1cpux_parents, /* name, parents */ 221 0x04, /* offset */ 222 8, 8, 0, AW_CLK_FACTOR_ZERO_BASED, /* n factor */ 223 0, 0, 1, AW_CLK_FACTOR_FIXED, /* k factor (fake) */ 224 0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor */ 225 0, 0, 1, AW_CLK_FACTOR_FIXED, /* p factor (fake) */ 226 0, 0, /* lock */ 227 31, /* gate */ 228 AW_CLK_HAS_GATE | AW_CLK_SCALE_CHANGE); /* flags */ 229 230 static const char *pll_audio_parents[] = {"osc24M"}; 231 NKMP_CLK(pll_audio_clk, 232 CLK_PLL_AUDIO, /* id */ 233 "pll_audio", pll_audio_parents, /* name, parents */ 234 0x08, /* offset */ 235 8, 8, 0, AW_CLK_FACTOR_ZERO_BASED, /* n factor */ 236 0, 0, 1, AW_CLK_FACTOR_FIXED, /* k factor (fake) */ 237 16, 1, 0, 0, /* m factor */ 238 18, 1, 0, 0, /* p factor */ 239 31, /* gate */ 240 0, 0, /* lock */ 241 AW_CLK_HAS_GATE); /* flags */ 242 243 static const char *pll_video0_parents[] = {"osc24M"}; 244 NKMP_CLK(pll_video0_clk, 245 CLK_PLL_VIDEO0, /* id */ 246 "pll_video0", pll_video0_parents, /* name, parents */ 247 0x10, /* offset */ 248 8, 8, 0, AW_CLK_FACTOR_ZERO_BASED, /* n factor */ 249 0, 0, 1, AW_CLK_FACTOR_FIXED, /* k factor (fake) */ 250 16, 1, 0, 0, /* m factor */ 251 0, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* p factor */ 252 31, /* gate */ 253 0, 0, /* lock */ 254 AW_CLK_HAS_GATE); /* flags */ 255 256 static const char *pll_ve_parents[] = {"osc24M"}; 257 NKMP_CLK(pll_ve_clk, 258 CLK_PLL_VE, /* id */ 259 "pll_ve", pll_ve_parents, /* name, parents */ 260 0x18, /* offset */ 261 8, 8, 0, AW_CLK_FACTOR_ZERO_BASED, /* n factor */ 262 0, 0, 1, AW_CLK_FACTOR_FIXED, /* k factor (fake) */ 263 16, 1, 0, 0, /* m factor */ 264 18, 1, 0, 0, /* p factor */ 265 31, /* gate */ 266 0, 0, /* lock */ 267 AW_CLK_HAS_GATE); /* flags */ 268 269 static const char *pll_ddr_parents[] = {"osc24M"}; 270 NKMP_CLK(pll_ddr_clk, 271 CLK_PLL_DDR, /* id */ 272 "pll_ddr", pll_ddr_parents, /* name, parents */ 273 0x20, /* offset */ 274 8, 5, 0, 0, /* n factor */ 275 0, 0, 1, AW_CLK_FACTOR_FIXED, /* k factor (fake) */ 276 16, 1, 0, 0, /* m factor */ 277 18, 1, 0, 0, /* p factor */ 278 31, /* gate */ 279 0, 0, /* lock */ 280 AW_CLK_HAS_GATE); /* flags */ 281 282 static const char *pll_periph_parents[] = {"osc24M"}; 283 NKMP_CLK(pll_periph_clk, 284 CLK_PLL_PERIPH, /* id */ 285 "pll_periph", pll_periph_parents, /* name, parents */ 286 0x28, /* offset */ 287 8, 8, 0, AW_CLK_FACTOR_ZERO_BASED, /* n factor */ 288 0, 0, 1, AW_CLK_FACTOR_FIXED, /* k factor (fake) */ 289 16, 1, 1, 0, /* m factor */ 290 18, 1, 1, 0, /* p factor */ 291 31, /* gate */ 292 0, 0, /* lock */ 293 AW_CLK_HAS_GATE); /* flags */ 294 295 static const char *pll_gpu_parents[] = {"osc24M"}; 296 NKMP_CLK(pll_gpu_clk, 297 CLK_PLL_GPU, /* id */ 298 "pll_gpu", pll_gpu_parents, /* name, parents */ 299 0x38, /* offset */ 300 8, 8, 0, AW_CLK_FACTOR_ZERO_BASED, /* n factor */ 301 0, 0, 1, AW_CLK_FACTOR_FIXED, /* k factor (fake) */ 302 16, 1, 1, 0, /* m factor */ 303 18, 1, 1, 0, /* p factor */ 304 31, /* gate */ 305 0, 0, /* lock */ 306 AW_CLK_HAS_GATE); /* flags */ 307 308 static const char *pll_hsic_parents[] = {"osc24M"}; 309 NKMP_CLK(pll_hsic_clk, 310 CLK_PLL_HSIC, /* id */ 311 "pll_hsic", pll_hsic_parents, /* name, parents */ 312 0x44, /* offset */ 313 8, 8, 0, AW_CLK_FACTOR_ZERO_BASED, /* n factor */ 314 0, 0, 1, AW_CLK_FACTOR_FIXED, /* k factor (fake) */ 315 16, 1, 1, 0, /* m factor */ 316 18, 1, 1, 0, /* p factor */ 317 31, /* gate */ 318 0, 0, /* lock */ 319 AW_CLK_HAS_GATE); /* flags */ 320 321 static const char *pll_de_parents[] = {"osc24M"}; 322 NKMP_CLK(pll_de_clk, 323 CLK_PLL_DE, /* id */ 324 "pll_de", pll_de_parents, /* name, parents */ 325 0x48, /* offset */ 326 8, 8, 0, AW_CLK_FACTOR_ZERO_BASED, /* n factor */ 327 0, 0, 1, AW_CLK_FACTOR_FIXED, /* k factor (fake) */ 328 16, 1, 1, 0, /* m factor */ 329 18, 1, 1, 0, /* p factor */ 330 31, /* gate */ 331 0, 0, /* lock */ 332 AW_CLK_HAS_GATE); /* flags */ 333 334 static const char *pll_video1_parents[] = {"osc24M"}; 335 NKMP_CLK(pll_video1_clk, 336 CLK_PLL_VIDEO1, /* id */ 337 "pll_video1", pll_video1_parents, /* name, parents */ 338 0x4c, /* offset */ 339 8, 8, 0, AW_CLK_FACTOR_ZERO_BASED, /* n factor */ 340 0, 0, 1, AW_CLK_FACTOR_FIXED, /* k factor (fake) */ 341 16, 1, 1, 0, /* m factor */ 342 0, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* p factor */ 343 31, /* gate */ 344 0, 0, /* lock */ 345 AW_CLK_HAS_GATE); /* flags */ 346 347 static const char *c0cpux_parents[] = {"osc24M", "pll_c0cpux"}; 348 MUX_CLK(c0cpux_clk, 349 CLK_C0CPUX, /* id */ 350 "c0cpux", c0cpux_parents, /* name, parents */ 351 0x50, 12, 1); /* offset, shift, width */ 352 353 static const char *c1cpux_parents[] = {"osc24M", "pll_c1cpux"}; 354 MUX_CLK(c1cpux_clk, 355 CLK_C1CPUX, /* id */ 356 "c1cpux", c1cpux_parents, /* name, parents */ 357 0x50, 28, 1); /* offset, shift, width */ 358 359 static const char *axi0_parents[] = {"c0cpux"}; 360 DIV_CLK(axi0_clk, 361 CLK_AXI0, /* id */ 362 "axi0", axi0_parents, /* name, parents */ 363 0x50, /* offset */ 364 0, 2, /* shift, width */ 365 0, NULL); /* flags, div table */ 366 367 static const char *axi1_parents[] = {"c1cpux"}; 368 DIV_CLK(axi1_clk, 369 CLK_AXI1, /* id */ 370 "axi1", axi1_parents, /* name, parents */ 371 0x50, /* offset */ 372 16, 2, /* shift, width */ 373 0, NULL); /* flags, div table */ 374 375 static const char *ahb1_parents[] = {"osc16M-d512", "osc24M", "pll_periph", "pll_periph"}; 376 PREDIV_CLK_WITH_MASK(ahb1_clk, 377 CLK_AHB1, /* id */ 378 "ahb1", ahb1_parents, /* name, parents */ 379 0x54, /* offset */ 380 12, 2, /* mux */ 381 4, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* div */ 382 6, 2, 0, AW_CLK_FACTOR_HAS_COND, /* prediv */ 383 (2 << 12), (2 << 12)); /* prediv condition */ 384 385 static const char *apb1_parents[] = {"ahb1"}; 386 DIV_CLK(apb1_clk, 387 CLK_APB1, /* id */ 388 "apb1", apb1_parents, /* name, parents */ 389 0x54, /* offset */ 390 8, 2, /* shift, width */ 391 0, NULL); /* flags, div table */ 392 393 static const char *apb2_parents[] = {"osc16M-d512", "osc24M", "pll_periph", "pll_periph"}; 394 NM_CLK(apb2_clk, 395 CLK_APB2, /* id */ 396 "apb2", apb2_parents, /* name, parents */ 397 0x58, /* offset */ 398 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 399 0, 5, 0, 0, /* m factor */ 400 24, 2, /* mux */ 401 0, /* gate */ 402 AW_CLK_HAS_MUX); 403 404 static const char *ahb2_parents[] = {"ahb1", "pll_periph"}; 405 PREDIV_CLK(ahb2_clk, 406 CLK_AHB2, /* id */ 407 "ahb2", ahb2_parents, /* name, parents */ 408 0x5c, 409 0, 2, /* mux */ 410 0, 0, 1, AW_CLK_FACTOR_FIXED, /* div (fake) */ 411 0, 0, 2, AW_CLK_FACTOR_HAS_COND | AW_CLK_FACTOR_FIXED, /* prediv */ 412 0, 2, 1); /* prediv cond */ 413 414 /* Actually has a divider, but we don't use it */ 415 static const char *cci400_parents[] = {"osc24M", "pll_periph", "pll_hsic"}; 416 MUX_CLK(cci400_clk, 417 CLK_CCI400, /* id */ 418 "cci400", cci400_parents, /* name, parents */ 419 0x78, 24, 2); /* offset, shift, width */ 420 421 static const char *mod_parents[] = {"osc24M", "pll_periph"}; 422 423 NM_CLK(nand_clk, 424 CLK_NAND, /* id */ 425 "nand", mod_parents, /* name, parents */ 426 0x80, /* offset */ 427 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 428 0, 4, 0, 0, /* m factor */ 429 24, 2, /* mux */ 430 31, /* gate */ 431 AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); 432 433 NM_CLK(mmc0_clk, 434 CLK_MMC0, /* id */ 435 "mmc0", mod_parents, /* name, parents */ 436 0x88, /* offset */ 437 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 438 0, 4, 0, 0, /* m factor */ 439 24, 2, /* mux */ 440 31, /* gate */ 441 AW_CLK_HAS_GATE | AW_CLK_HAS_MUX | 442 AW_CLK_REPARENT); 443 NM_CLK(mmc1_clk, 444 CLK_MMC1, /* id */ 445 "mmc1", mod_parents, /* name, parents */ 446 0x8c, /* offset */ 447 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 448 0, 4, 0, 0, /* m factor */ 449 24, 2, /* mux */ 450 31, /* gate */ 451 AW_CLK_HAS_GATE | AW_CLK_HAS_MUX | 452 AW_CLK_REPARENT); 453 NM_CLK(mmc2_clk, 454 CLK_MMC2, /* id */ 455 "mmc2", mod_parents, /* name, parents */ 456 0x90, /* offset */ 457 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 458 0, 4, 0, 0, /* m factor */ 459 24, 2, /* mux */ 460 31, /* gate */ 461 AW_CLK_HAS_GATE | AW_CLK_HAS_MUX | 462 AW_CLK_REPARENT); 463 464 NM_CLK(ss_clk, 465 CLK_SS, /* id */ 466 "ss", mod_parents, /* name, parents */ 467 0x9c, /* offset */ 468 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 469 0, 4, 0, 0, /* m factor */ 470 24, 2, /* mux */ 471 31, /* gate */ 472 AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); 473 474 NM_CLK(spi0_clk, 475 CLK_SPI0, /* id */ 476 "spi0", mod_parents, /* name, parents */ 477 0xa0, /* offset */ 478 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 479 0, 4, 0, 0, /* m factor */ 480 24, 2, /* mux */ 481 31, /* gate */ 482 AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); 483 NM_CLK(spi1_clk, 484 CLK_SPI1, /* id */ 485 "spi1", mod_parents, /* name, parents */ 486 0xa4, /* offset */ 487 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 488 0, 4, 0, 0, /* m factor */ 489 24, 2, /* mux */ 490 31, /* gate */ 491 AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); 492 493 static const char *daudio_parents[] = {"pll_audio"}; 494 NM_CLK(i2s0_clk, 495 CLK_I2S0, /* id */ 496 "i2s0", daudio_parents, /* name, parents */ 497 0xb0, /* offset */ 498 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 499 0, 4, 0, 0, /* m factor */ 500 0, 0, /* mux */ 501 31, /* gate */ 502 AW_CLK_HAS_GATE); 503 NM_CLK(i2s1_clk, 504 CLK_I2S1, /* id */ 505 "i2s1", daudio_parents, /* name, parents */ 506 0xb4, /* offset */ 507 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 508 0, 4, 0, 0, /* m factor */ 509 0, 0, /* mux */ 510 31, /* gate */ 511 AW_CLK_HAS_GATE); 512 NM_CLK(i2s2_clk, 513 CLK_I2S2, /* id */ 514 "i2s2", daudio_parents, /* name, parents */ 515 0xb8, /* offset */ 516 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 517 0, 4, 0, 0, /* m factor */ 518 0, 0, /* mux */ 519 31, /* gate */ 520 AW_CLK_HAS_GATE); 521 522 static const char *tdm_parents[] = {"pll_audio"}; 523 NM_CLK(tdm_clk, 524 CLK_TDM, /* id */ 525 "tdm", tdm_parents, /* name, parents */ 526 0xbc, /* offset */ 527 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 528 0, 4, 0, 0, /* m factor */ 529 0, 0, /* mux */ 530 31, /* gate */ 531 AW_CLK_HAS_GATE); 532 533 static const char *spdif_parents[] = {"pll_audio"}; 534 NM_CLK(spdif_clk, 535 CLK_SPDIF, /* id */ 536 "spdif", spdif_parents, /* name, parents */ 537 0xc0, /* offset */ 538 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 539 0, 4, 0, 0, /* m factor */ 540 0, 0, /* mux */ 541 31, /* gate */ 542 AW_CLK_HAS_GATE); 543 544 static const char *dram_parents[] = {"pll_ddr"}; 545 NM_CLK(dram_clk, 546 CLK_DRAM, /* id */ 547 "dram", dram_parents, /* name, parents */ 548 0xf4, /* offset */ 549 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 550 0, 4, 0, 0, /* m factor */ 551 0, 0, /* mux */ 552 0, /* gate */ 553 0); 554 555 static const char *tcon0_parents[] = {"pll_video0"}; 556 MUX_CLK(tcon0_clk, 557 CLK_TCON0, /* id */ 558 "tcon0", tcon0_parents, /* name, parents */ 559 0x118, 24, 2); /* offset, shift, width */ 560 561 static const char *tcon1_parents[] = {"pll_video1"}; 562 NM_CLK(tcon1_clk, 563 CLK_TCON1, /* id */ 564 "tcon1", tcon1_parents, /* name, parents */ 565 0x11c, /* offset */ 566 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 567 0, 4, 0, 0, /* m factor */ 568 0, 0, /* mux */ 569 31, /* gate */ 570 AW_CLK_HAS_GATE); 571 572 static const char *csi_mclk_parents[] = {"pll_de", "osc24M"}; 573 NM_CLK(csi_mclk_clk, 574 CLK_CSI_MCLK, /* id */ 575 "csi-mclk", csi_mclk_parents, /* name, parents */ 576 0x134, /* offset */ 577 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 578 0, 4, 0, 0, /* m factor */ 579 8, 3, /* mux */ 580 15, /* gate */ 581 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); 582 583 static const char *csi_sclk_parents[] = {"pll_periph", "pll_ve"}; 584 NM_CLK(csi_sclk_clk, 585 CLK_CSI_SCLK, /* id */ 586 "csi-sclk", csi_sclk_parents, /* name, parents */ 587 0x134, /* offset */ 588 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 589 16, 4, 0, 0, /* m factor */ 590 24, 3, /* mux */ 591 31, /* gate */ 592 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); 593 594 static const char *ve_parents[] = {"pll_ve"}; 595 NM_CLK(ve_clk, 596 CLK_VE, /* id */ 597 "ve", ve_parents, /* name, parents */ 598 0x13c, /* offset */ 599 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 600 16, 3, 0, 0, /* m factor */ 601 0, 0, /* mux */ 602 31, /* gate */ 603 AW_CLK_HAS_GATE); 604 605 static const char *hdmi_parents[] = {"pll_video1"}; 606 NM_CLK(hdmi_clk, 607 CLK_HDMI, /* id */ 608 "hdmi", hdmi_parents, /* name, parents */ 609 0x150, /* offset */ 610 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 611 0, 4, 0, 0, /* m factor */ 612 24, 2, /* mux */ 613 31, /* gate */ 614 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); 615 616 static const char *mbus_parents[] = {"osc24M", "pll_periph", "pll_ddr"}; 617 NM_CLK(mbus_clk, 618 CLK_MBUS, /* id */ 619 "mbus", mbus_parents, /* name, parents */ 620 0x15c, /* offset */ 621 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 622 0, 3, 0, 0, /* m factor */ 623 24, 2, /* mux */ 624 31, /* gate */ 625 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); 626 627 static const char *mipi_dsi0_parents[] = {"pll_video0"}; 628 NM_CLK(mipi_dsi0_clk, 629 CLK_MIPI_DSI0, /* id */ 630 "mipi-dsi0", mipi_dsi0_parents, /* name, parents */ 631 0x168, /* offset */ 632 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 633 0, 4, 0, 0, /* m factor */ 634 24, 4, /* mux */ 635 31, /* gate */ 636 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); 637 638 static const char *mipi_dsi1_parents[] = {"osc24M", "pll_video0"}; 639 NM_CLK(mipi_dsi1_clk, 640 CLK_MIPI_DSI1, /* id */ 641 "mipi-dsi1", mipi_dsi1_parents, /* name, parents */ 642 0x16c, /* offset */ 643 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 644 0, 4, 0, 0, /* m factor */ 645 24, 4, /* mux */ 646 31, /* gate */ 647 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); 648 649 static const char *gpu_core_parents[] = {"pll_gpu"}; 650 NM_CLK(gpu_core_clk, 651 CLK_GPU_CORE, /* id */ 652 "gpu-core", gpu_core_parents, /* name, parents */ 653 0x1a0, /* offset */ 654 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 655 0, 3, 0, 0, /* m factor */ 656 0, 0, /* mux */ 657 31, /* gate */ 658 AW_CLK_HAS_GATE); 659 660 static const char *gpu_memory_parents[] = {"pll_gpu", "pll_periph"}; 661 NM_CLK(gpu_memory_clk, 662 CLK_GPU_MEMORY, /* id */ 663 "gpu-memory", gpu_memory_parents, /* name, parents */ 664 0x1a4, /* offset */ 665 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 666 0, 3, 0, 0, /* m factor */ 667 24, 1, /* mux */ 668 31, /* gate */ 669 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); 670 671 static const char *gpu_hyd_parents[] = {"pll_gpu"}; 672 NM_CLK(gpu_hyd_clk, 673 CLK_GPU_HYD, /* id */ 674 "gpu-hyd", gpu_hyd_parents, /* name, parents */ 675 0x1a0, /* offset */ 676 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 677 0, 3, 0, 0, /* m factor */ 678 0, 0, /* mux */ 679 31, /* gate */ 680 AW_CLK_HAS_GATE); 681 682 static struct aw_ccung_clk a83t_clks[] = { 683 { .type = AW_CLK_NKMP, .clk.nkmp = &pll_audio_clk}, 684 { .type = AW_CLK_NKMP, .clk.nkmp = &pll_video0_clk}, 685 { .type = AW_CLK_NKMP, .clk.nkmp = &pll_ve_clk}, 686 { .type = AW_CLK_NKMP, .clk.nkmp = &pll_ddr_clk}, 687 { .type = AW_CLK_NKMP, .clk.nkmp = &pll_periph_clk}, 688 { .type = AW_CLK_NKMP, .clk.nkmp = &pll_gpu_clk}, 689 { .type = AW_CLK_NKMP, .clk.nkmp = &pll_hsic_clk}, 690 { .type = AW_CLK_NKMP, .clk.nkmp = &pll_de_clk}, 691 { .type = AW_CLK_NKMP, .clk.nkmp = &pll_video1_clk}, 692 { .type = AW_CLK_NKMP, .clk.nkmp = &pll_c0cpux_clk}, 693 { .type = AW_CLK_NKMP, .clk.nkmp = &pll_c1cpux_clk}, 694 { .type = AW_CLK_NM, .clk.nm = &apb2_clk}, 695 { .type = AW_CLK_NM, .clk.nm = &nand_clk}, 696 { .type = AW_CLK_NM, .clk.nm = &mmc0_clk}, 697 { .type = AW_CLK_NM, .clk.nm = &mmc1_clk}, 698 { .type = AW_CLK_NM, .clk.nm = &mmc2_clk}, 699 { .type = AW_CLK_NM, .clk.nm = &ss_clk}, 700 { .type = AW_CLK_NM, .clk.nm = &spi0_clk}, 701 { .type = AW_CLK_NM, .clk.nm = &spi1_clk}, 702 { .type = AW_CLK_NM, .clk.nm = &i2s0_clk}, 703 { .type = AW_CLK_NM, .clk.nm = &i2s1_clk}, 704 { .type = AW_CLK_NM, .clk.nm = &i2s2_clk}, 705 { .type = AW_CLK_NM, .clk.nm = &tdm_clk}, 706 { .type = AW_CLK_NM, .clk.nm = &spdif_clk}, 707 { .type = AW_CLK_NM, .clk.nm = &dram_clk}, 708 { .type = AW_CLK_NM, .clk.nm = &tcon1_clk}, 709 { .type = AW_CLK_NM, .clk.nm = &csi_mclk_clk}, 710 { .type = AW_CLK_NM, .clk.nm = &csi_sclk_clk}, 711 { .type = AW_CLK_NM, .clk.nm = &ve_clk}, 712 { .type = AW_CLK_NM, .clk.nm = &hdmi_clk}, 713 { .type = AW_CLK_NM, .clk.nm = &mbus_clk}, 714 { .type = AW_CLK_NM, .clk.nm = &mipi_dsi0_clk}, 715 { .type = AW_CLK_NM, .clk.nm = &mipi_dsi1_clk}, 716 { .type = AW_CLK_NM, .clk.nm = &gpu_core_clk}, 717 { .type = AW_CLK_NM, .clk.nm = &gpu_memory_clk}, 718 { .type = AW_CLK_NM, .clk.nm = &gpu_hyd_clk}, 719 { .type = AW_CLK_PREDIV_MUX, .clk.prediv_mux = &ahb1_clk}, 720 { .type = AW_CLK_PREDIV_MUX, .clk.prediv_mux = &ahb2_clk}, 721 { .type = AW_CLK_MUX, .clk.mux = &c0cpux_clk}, 722 { .type = AW_CLK_MUX, .clk.mux = &c1cpux_clk}, 723 { .type = AW_CLK_MUX, .clk.mux = &cci400_clk}, 724 { .type = AW_CLK_MUX, .clk.mux = &tcon0_clk}, 725 { .type = AW_CLK_DIV, .clk.div = &axi0_clk}, 726 { .type = AW_CLK_DIV, .clk.div = &axi1_clk}, 727 { .type = AW_CLK_DIV, .clk.div = &apb1_clk}, 728 { .type = AW_CLK_FIXED, .clk.fixed = &osc12m_clk}, 729 }; 730 731 static struct aw_clk_init a83t_init_clks[] = { 732 {"ahb1", "pll_periph", 0, false}, 733 {"ahb2", "ahb1", 0, false}, 734 {"dram", "pll_ddr", 0, false}, 735 }; 736 737 static int 738 ccu_a83t_probe(device_t dev) 739 { 740 741 if (!ofw_bus_status_okay(dev)) 742 return (ENXIO); 743 744 if (!ofw_bus_is_compatible(dev, "allwinner,sun8i-a83t-ccu")) 745 return (ENXIO); 746 747 device_set_desc(dev, "Allwinner A83T Clock Control Unit NG"); 748 return (BUS_PROBE_DEFAULT); 749 } 750 751 static int 752 ccu_a83t_attach(device_t dev) 753 { 754 struct aw_ccung_softc *sc; 755 756 sc = device_get_softc(dev); 757 758 sc->resets = a83t_ccu_resets; 759 sc->nresets = nitems(a83t_ccu_resets); 760 sc->gates = a83t_ccu_gates; 761 sc->ngates = nitems(a83t_ccu_gates); 762 sc->clks = a83t_clks; 763 sc->nclks = nitems(a83t_clks); 764 sc->clk_init = a83t_init_clks; 765 sc->n_clk_init = nitems(a83t_init_clks); 766 767 return (aw_ccung_attach(dev)); 768 } 769 770 static device_method_t ccu_a83tng_methods[] = { 771 /* Device interface */ 772 DEVMETHOD(device_probe, ccu_a83t_probe), 773 DEVMETHOD(device_attach, ccu_a83t_attach), 774 775 DEVMETHOD_END 776 }; 777 778 static devclass_t ccu_a83tng_devclass; 779 780 DEFINE_CLASS_1(ccu_a83tng, ccu_a83tng_driver, ccu_a83tng_methods, 781 sizeof(struct aw_ccung_softc), aw_ccung_driver); 782 783 EARLY_DRIVER_MODULE(ccu_a83tng, simplebus, ccu_a83tng_driver, 784 ccu_a83tng_devclass, 0, 0, BUS_PASS_RESOURCE + BUS_PASS_ORDER_MIDDLE); 785