1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
5 * Copyright (c) 2012, 2013 The FreeBSD Foundation
6 * All rights reserved.
7 *
8 * Portions of this software were developed by Oleksandr Rybalko
9 * under sponsorship from the FreeBSD Foundation.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * SUCH DAMAGE.
31 *
32 */
33 #include <sys/cdefs.h>
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/bio.h>
37 #include <sys/bus.h>
38 #include <sys/conf.h>
39 #include <sys/endian.h>
40 #include <sys/kernel.h>
41 #include <sys/kthread.h>
42 #include <sys/lock.h>
43 #include <sys/malloc.h>
44 #include <sys/module.h>
45 #include <sys/mutex.h>
46 #include <sys/queue.h>
47 #include <sys/resource.h>
48 #include <sys/rman.h>
49 #include <sys/time.h>
50 #include <sys/timetc.h>
51 #include <sys/fbio.h>
52 #include <sys/consio.h>
53 #include <sys/eventhandler.h>
54
55 #include <sys/kdb.h>
56
57 #include <machine/bus.h>
58 #include <machine/resource.h>
59 #include <machine/frame.h>
60 #include <machine/intr.h>
61
62 #include <dev/ofw/ofw_bus.h>
63 #include <dev/ofw/ofw_bus_subr.h>
64
65 #include <dev/vt/vt.h>
66 #include <dev/vt/colors/vt_termcolors.h>
67
68 #include <arm/freescale/imx/imx51_ccmvar.h>
69
70 #include <arm/freescale/imx/imx51_ipuv3reg.h>
71
72 #include "fb_if.h"
73
74 #define IMX51_IPU_HSP_CLOCK 665000000
75
76 struct ipu3sc_softc {
77 device_t dev;
78 device_t sc_fbd; /* fbd child */
79 struct fb_info sc_info;
80
81 bus_space_tag_t iot;
82 bus_space_handle_t ioh;
83 bus_space_handle_t cm_ioh;
84 bus_space_handle_t dp_ioh;
85 bus_space_handle_t di0_ioh;
86 bus_space_handle_t di1_ioh;
87 bus_space_handle_t dctmpl_ioh;
88 bus_space_handle_t dc_ioh;
89 bus_space_handle_t dmfc_ioh;
90 bus_space_handle_t idmac_ioh;
91 bus_space_handle_t cpmem_ioh;
92 };
93
94 static struct ipu3sc_softc *ipu3sc_softc;
95
96 #define IPUV3_READ(ipuv3, module, reg) \
97 bus_space_read_4((ipuv3)->iot, (ipuv3)->module##_ioh, (reg))
98 #define IPUV3_WRITE(ipuv3, module, reg, val) \
99 bus_space_write_4((ipuv3)->iot, (ipuv3)->module##_ioh, (reg), (val))
100
101 #define CPMEM_CHANNEL_OFFSET(_c) ((_c) * 0x40)
102 #define CPMEM_WORD_OFFSET(_w) ((_w) * 0x20)
103 #define CPMEM_DP_OFFSET(_d) ((_d) * 0x10000)
104 #define IMX_IPU_DP0 0
105 #define IMX_IPU_DP1 1
106 #define CPMEM_CHANNEL(_dp, _ch, _w) \
107 (CPMEM_DP_OFFSET(_dp) + CPMEM_CHANNEL_OFFSET(_ch) + \
108 CPMEM_WORD_OFFSET(_w))
109 #define CPMEM_OFFSET(_dp, _ch, _w, _o) \
110 (CPMEM_CHANNEL((_dp), (_ch), (_w)) + (_o))
111
112 static int ipu3_fb_probe(device_t);
113 static int ipu3_fb_attach(device_t);
114
115 static void
ipu3_fb_init(struct ipu3sc_softc * sc)116 ipu3_fb_init(struct ipu3sc_softc *sc)
117 {
118 uint64_t w0sh96;
119 uint32_t w1sh96;
120
121 /* FW W0[137:125] - 96 = [41:29] */
122 /* FH W0[149:138] - 96 = [53:42] */
123 w0sh96 = IPUV3_READ(sc, cpmem, CPMEM_OFFSET(IMX_IPU_DP1, 23, 0, 16));
124 w0sh96 <<= 32;
125 w0sh96 |= IPUV3_READ(sc, cpmem, CPMEM_OFFSET(IMX_IPU_DP1, 23, 0, 12));
126
127 sc->sc_info.fb_width = ((w0sh96 >> 29) & 0x1fff) + 1;
128 sc->sc_info.fb_height = ((w0sh96 >> 42) & 0x0fff) + 1;
129
130 /* SLY W1[115:102] - 96 = [19:6] */
131 w1sh96 = IPUV3_READ(sc, cpmem, CPMEM_OFFSET(IMX_IPU_DP1, 23, 1, 12));
132 sc->sc_info.fb_stride = ((w1sh96 >> 6) & 0x3fff) + 1;
133
134 printf("%dx%d [%d]\n", sc->sc_info.fb_width, sc->sc_info.fb_height,
135 sc->sc_info.fb_stride);
136 sc->sc_info.fb_size = sc->sc_info.fb_height * sc->sc_info.fb_stride;
137
138 sc->sc_info.fb_vbase = (intptr_t)contigmalloc(sc->sc_info.fb_size,
139 M_DEVBUF, M_ZERO, 0, ~0, PAGE_SIZE, 0);
140 sc->sc_info.fb_pbase = (intptr_t)vtophys(sc->sc_info.fb_vbase);
141
142 /* DP1 + config_ch_23 + word_2 */
143 IPUV3_WRITE(sc, cpmem, CPMEM_OFFSET(IMX_IPU_DP1, 23, 1, 0),
144 (((uint32_t)sc->sc_info.fb_pbase >> 3) |
145 (((uint32_t)sc->sc_info.fb_pbase >> 3) << 29)) & 0xffffffff);
146
147 IPUV3_WRITE(sc, cpmem, CPMEM_OFFSET(IMX_IPU_DP1, 23, 1, 4),
148 (((uint32_t)sc->sc_info.fb_pbase >> 3) >> 3) & 0xffffffff);
149
150 /* XXX: fetch or set it from/to IPU. */
151 sc->sc_info.fb_bpp = sc->sc_info.fb_depth = sc->sc_info.fb_stride /
152 sc->sc_info.fb_width * 8;
153 }
154
155 /* Use own color map, because of different RGB offset. */
156 static int
ipu3_fb_init_cmap(uint32_t * cmap,int bytespp)157 ipu3_fb_init_cmap(uint32_t *cmap, int bytespp)
158 {
159
160 switch (bytespp) {
161 case 8:
162 return (vt_generate_cons_palette(cmap, COLOR_FORMAT_RGB,
163 0x7, 5, 0x7, 2, 0x3, 0));
164 case 15:
165 return (vt_generate_cons_palette(cmap, COLOR_FORMAT_RGB,
166 0x1f, 10, 0x1f, 5, 0x1f, 0));
167 case 16:
168 return (vt_generate_cons_palette(cmap, COLOR_FORMAT_RGB,
169 0x1f, 11, 0x3f, 5, 0x1f, 0));
170 case 24:
171 case 32: /* Ignore alpha. */
172 return (vt_generate_cons_palette(cmap, COLOR_FORMAT_RGB,
173 0xff, 0, 0xff, 8, 0xff, 16));
174 default:
175 return (1);
176 }
177 }
178
179 static int
ipu3_fb_probe(device_t dev)180 ipu3_fb_probe(device_t dev)
181 {
182
183 if (!ofw_bus_status_okay(dev))
184 return (ENXIO);
185
186 if (!ofw_bus_is_compatible(dev, "fsl,ipu3"))
187 return (ENXIO);
188
189 device_set_desc(dev, "i.MX5x Image Processing Unit v3 (FB)");
190
191 return (BUS_PROBE_DEFAULT);
192 }
193
194 static int
ipu3_fb_attach(device_t dev)195 ipu3_fb_attach(device_t dev)
196 {
197 struct ipu3sc_softc *sc = device_get_softc(dev);
198 bus_space_tag_t iot;
199 bus_space_handle_t ioh;
200 phandle_t node;
201 pcell_t reg;
202 int err;
203 uintptr_t base;
204
205 ipu3sc_softc = sc;
206
207 if (bootverbose)
208 device_printf(dev, "clock gate status is %d\n",
209 imx51_get_clk_gating(IMX51CLK_IPU_HSP_CLK_ROOT));
210
211 sc->dev = dev;
212
213 sc = device_get_softc(dev);
214 sc->iot = iot = fdtbus_bs_tag;
215
216 /*
217 * Retrieve the device address based on the start address in the
218 * DTS. The DTS for i.MX51 specifies 0x5e000000 as the first register
219 * address, so we just subtract IPU_CM_BASE to get the offset at which
220 * the IPU device was memory mapped.
221 * On i.MX53, the offset is 0.
222 */
223 node = ofw_bus_get_node(dev);
224 if ((OF_getencprop(node, "reg", ®, sizeof(reg))) <= 0)
225 base = 0;
226 else
227 base = reg - IPU_CM_BASE(0);
228 /* map controller registers */
229 err = bus_space_map(iot, IPU_CM_BASE(base), IPU_CM_SIZE, 0, &ioh);
230 if (err)
231 goto fail_retarn_cm;
232 sc->cm_ioh = ioh;
233
234 /* map Display Multi FIFO Controller registers */
235 err = bus_space_map(iot, IPU_DMFC_BASE(base), IPU_DMFC_SIZE, 0, &ioh);
236 if (err)
237 goto fail_retarn_dmfc;
238 sc->dmfc_ioh = ioh;
239
240 /* map Display Interface 0 registers */
241 err = bus_space_map(iot, IPU_DI0_BASE(base), IPU_DI0_SIZE, 0, &ioh);
242 if (err)
243 goto fail_retarn_di0;
244 sc->di0_ioh = ioh;
245
246 /* map Display Interface 1 registers */
247 err = bus_space_map(iot, IPU_DI1_BASE(base), IPU_DI0_SIZE, 0, &ioh);
248 if (err)
249 goto fail_retarn_di1;
250 sc->di1_ioh = ioh;
251
252 /* map Display Processor registers */
253 err = bus_space_map(iot, IPU_DP_BASE(base), IPU_DP_SIZE, 0, &ioh);
254 if (err)
255 goto fail_retarn_dp;
256 sc->dp_ioh = ioh;
257
258 /* map Display Controller registers */
259 err = bus_space_map(iot, IPU_DC_BASE(base), IPU_DC_SIZE, 0, &ioh);
260 if (err)
261 goto fail_retarn_dc;
262 sc->dc_ioh = ioh;
263
264 /* map Image DMA Controller registers */
265 err = bus_space_map(iot, IPU_IDMAC_BASE(base), IPU_IDMAC_SIZE, 0,
266 &ioh);
267 if (err)
268 goto fail_retarn_idmac;
269 sc->idmac_ioh = ioh;
270
271 /* map CPMEM registers */
272 err = bus_space_map(iot, IPU_CPMEM_BASE(base), IPU_CPMEM_SIZE, 0,
273 &ioh);
274 if (err)
275 goto fail_retarn_cpmem;
276 sc->cpmem_ioh = ioh;
277
278 /* map DCTEMPL registers */
279 err = bus_space_map(iot, IPU_DCTMPL_BASE(base), IPU_DCTMPL_SIZE, 0,
280 &ioh);
281 if (err)
282 goto fail_retarn_dctmpl;
283 sc->dctmpl_ioh = ioh;
284
285 #ifdef notyet
286 sc->ih = imx51_ipuv3_intr_establish(IMX51_INT_IPUV3, IPL_BIO,
287 ipuv3intr, sc);
288 if (sc->ih == NULL) {
289 device_printf(sc->dev,
290 "unable to establish interrupt at irq %d\n",
291 IMX51_INT_IPUV3);
292 return (ENXIO);
293 }
294 #endif
295
296 /*
297 * We have to wait until interrupts are enabled.
298 * Mailbox relies on it to get data from VideoCore
299 */
300 ipu3_fb_init(sc);
301
302 sc->sc_info.fb_name = device_get_nameunit(dev);
303
304 ipu3_fb_init_cmap(sc->sc_info.fb_cmap, sc->sc_info.fb_depth);
305 sc->sc_info.fb_cmsize = 16;
306
307 /* Ask newbus to attach framebuffer device to me. */
308 sc->sc_fbd = device_add_child(dev, "fbd", device_get_unit(dev));
309 if (sc->sc_fbd == NULL)
310 device_printf(dev, "Can't attach fbd device\n");
311
312 return (bus_generic_attach(dev));
313
314 fail_retarn_dctmpl:
315 bus_space_unmap(sc->iot, sc->cpmem_ioh, IPU_CPMEM_SIZE);
316 fail_retarn_cpmem:
317 bus_space_unmap(sc->iot, sc->idmac_ioh, IPU_IDMAC_SIZE);
318 fail_retarn_idmac:
319 bus_space_unmap(sc->iot, sc->dc_ioh, IPU_DC_SIZE);
320 fail_retarn_dp:
321 bus_space_unmap(sc->iot, sc->dp_ioh, IPU_DP_SIZE);
322 fail_retarn_dc:
323 bus_space_unmap(sc->iot, sc->di1_ioh, IPU_DI1_SIZE);
324 fail_retarn_di1:
325 bus_space_unmap(sc->iot, sc->di0_ioh, IPU_DI0_SIZE);
326 fail_retarn_di0:
327 bus_space_unmap(sc->iot, sc->dmfc_ioh, IPU_DMFC_SIZE);
328 fail_retarn_dmfc:
329 bus_space_unmap(sc->iot, sc->dc_ioh, IPU_CM_SIZE);
330 fail_retarn_cm:
331 device_printf(sc->dev,
332 "failed to map registers (errno=%d)\n", err);
333 return (err);
334 }
335
336 static struct fb_info *
ipu3_fb_getinfo(device_t dev)337 ipu3_fb_getinfo(device_t dev)
338 {
339 struct ipu3sc_softc *sc = device_get_softc(dev);
340
341 return (&sc->sc_info);
342 }
343
344 static device_method_t ipu3_fb_methods[] = {
345 /* Device interface */
346 DEVMETHOD(device_probe, ipu3_fb_probe),
347 DEVMETHOD(device_attach, ipu3_fb_attach),
348
349 /* Framebuffer service methods */
350 DEVMETHOD(fb_getinfo, ipu3_fb_getinfo),
351 { 0, 0 }
352 };
353
354 static devclass_t ipu3_fb_devclass;
355
356 static driver_t ipu3_fb_driver = {
357 "fb",
358 ipu3_fb_methods,
359 sizeof(struct ipu3sc_softc),
360 };
361
362 DRIVER_MODULE(fb, simplebus, ipu3_fb_driver, ipu3_fb_devclass, 0, 0);
363