1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2018 Rubicon Communications, LLC (Netgate)
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28 #include <sys/cdefs.h>
29 #include <sys/param.h>
30 #include <sys/systm.h>
31 #include <sys/bus.h>
32
33 #include <sys/kernel.h>
34 #include <sys/module.h>
35 #include <sys/rman.h>
36 #include <sys/lock.h>
37 #include <sys/mutex.h>
38
39 #include <machine/bus.h>
40 #include <machine/resource.h>
41 #include <machine/intr.h>
42
43 #include <dev/extres/clk/clk_fixed.h>
44 #include <dev/extres/syscon/syscon.h>
45
46 #include <dev/ofw/ofw_bus.h>
47 #include <dev/ofw/ofw_bus_subr.h>
48
49 #include "syscon_if.h"
50
51 static struct clk_fixed_def ap806_clk_cluster_0 = {
52 .clkdef.id = 0,
53 .clkdef.name = "ap806-cpu-cluster-0",
54 .freq = 0,
55 };
56
57 static struct clk_fixed_def ap806_clk_cluster_1 = {
58 .clkdef.id = 1,
59 .clkdef.name = "ap806-cpu-cluster-1",
60 .freq = 0,
61 };
62
63 static struct clk_fixed_def ap806_clk_fixed = {
64 .clkdef.id = 2,
65 .clkdef.name = "ap806-fixed",
66 .freq = 1200000000,
67 };
68
69 /* Thoses are the only exported clocks AFAICT */
70
71 static const char *mss_parents[] = {"ap806-fixed"};
72 static struct clk_fixed_def ap806_clk_mss = {
73 .clkdef.id = 3,
74 .clkdef.name = "ap806-mss",
75 .clkdef.parent_names = mss_parents,
76 .clkdef.parent_cnt = 1,
77 .mult = 1,
78 .div = 6,
79 };
80
81 static const char *sdio_parents[] = {"ap806-fixed"};
82 static struct clk_fixed_def ap806_clk_sdio = {
83 .clkdef.id = 4,
84 .clkdef.name = "ap806-sdio",
85 .clkdef.parent_names = sdio_parents,
86 .clkdef.parent_cnt = 1,
87 .mult = 1,
88 .div = 3,
89 };
90
91 struct mv_ap806_clock_softc {
92 device_t dev;
93 struct syscon *syscon;
94 };
95
96 static struct ofw_compat_data compat_data[] = {
97 {"marvell,ap806-clock", 1},
98 {NULL, 0}
99 };
100
101 #define RD4(sc, reg) SYSCON_READ_4((sc)->syscon, (reg))
102 #define WR4(sc, reg, val) SYSCON_WRITE_4((sc)->syscon, (reg), (val))
103
104 static int
mv_ap806_clock_probe(device_t dev)105 mv_ap806_clock_probe(device_t dev)
106 {
107
108 if (!ofw_bus_status_okay(dev))
109 return (ENXIO);
110
111 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
112 return (ENXIO);
113
114 device_set_desc(dev, "Marvell AP806 Clock Controller");
115 return (BUS_PROBE_DEFAULT);
116 }
117
118 static int
mv_ap806_clock_attach(device_t dev)119 mv_ap806_clock_attach(device_t dev)
120 {
121 struct mv_ap806_clock_softc *sc;
122 struct clkdom *clkdom;
123 uint64_t clock_freq;
124 uint32_t reg;
125
126 sc = device_get_softc(dev);
127 sc->dev = dev;
128
129 if (SYSCON_GET_HANDLE(sc->dev, &sc->syscon) != 0 ||
130 sc->syscon == NULL) {
131 device_printf(dev, "cannot get syscon for device\n");
132 return (ENXIO);
133 }
134
135 reg = RD4(sc, 0x400);
136 switch (reg & 0x1f) {
137 case 0x0:
138 case 0x1:
139 clock_freq = 2000000000;
140 break;
141 case 0x4:
142 clock_freq = 1600000000;
143 break;
144 case 0x6:
145 clock_freq = 1800000000;
146 break;
147 case 0x7:
148 clock_freq = 1800000000;
149 break;
150 case 0xb:
151 clock_freq = 1600000000;
152 break;
153 case 0xd:
154 clock_freq = 1600000000;
155 break;
156 case 0x13:
157 clock_freq = 1000000000;
158 break;
159 case 0x14:
160 clock_freq = 1333000000;
161 break;
162 case 0x17:
163 clock_freq = 1333000000;
164 break;
165 case 0x19:
166 clock_freq = 1200000000;
167 break;
168 case 0x1a:
169 clock_freq = 1400000000;
170 break;
171 case 0x1b:
172 clock_freq = 600000000;
173 break;
174 case 0x1c:
175 clock_freq = 800000000;
176 break;
177 case 0x1d:
178 clock_freq = 1000000000;
179 break;
180 default:
181 device_printf(dev, "Cannot guess clock freq with reg %x\n",
182 reg & 0x1f);
183 return (ENXIO);
184 break;
185 };
186
187 ap806_clk_cluster_0.freq = clock_freq;
188 ap806_clk_cluster_1.freq = clock_freq;
189 clkdom = clkdom_create(dev);
190
191 clknode_fixed_register(clkdom, &ap806_clk_cluster_0);
192 clknode_fixed_register(clkdom, &ap806_clk_cluster_1);
193 clknode_fixed_register(clkdom, &ap806_clk_fixed);
194 clknode_fixed_register(clkdom, &ap806_clk_mss);
195 clknode_fixed_register(clkdom, &ap806_clk_sdio);
196
197 clkdom_finit(clkdom);
198
199 if (bootverbose)
200 clkdom_dump(clkdom);
201 return (0);
202 }
203
204 static int
mv_ap806_clock_detach(device_t dev)205 mv_ap806_clock_detach(device_t dev)
206 {
207
208 return (EBUSY);
209 }
210
211 static device_method_t mv_ap806_clock_methods[] = {
212 /* Device interface */
213 DEVMETHOD(device_probe, mv_ap806_clock_probe),
214 DEVMETHOD(device_attach, mv_ap806_clock_attach),
215 DEVMETHOD(device_detach, mv_ap806_clock_detach),
216
217 DEVMETHOD_END
218 };
219
220 static devclass_t mv_ap806_clock_devclass;
221
222 static driver_t mv_ap806_clock_driver = {
223 "mv_ap806_clock",
224 mv_ap806_clock_methods,
225 sizeof(struct mv_ap806_clock_softc),
226 };
227
228 EARLY_DRIVER_MODULE(mv_ap806_clock, simplebus, mv_ap806_clock_driver,
229 mv_ap806_clock_devclass, 0, 0, BUS_PASS_RESOURCE + BUS_PASS_ORDER_LATE);
230