1 /*-
2 * Copyright (c) 2013 Oleksandr Tymoshenko <gonzo@freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 #include <sys/param.h>
29 #include <sys/systm.h>
30 #include <sys/bus.h>
31 #include <sys/kernel.h>
32 #include <sys/limits.h>
33 #include <sys/lock.h>
34 #include <sys/module.h>
35 #include <sys/mutex.h>
36 #include <sys/resource.h>
37 #include <sys/rman.h>
38 #include <sys/sysctl.h>
39
40 #include <machine/bus.h>
41
42 #include <dev/ofw/openfirm.h>
43 #include <dev/ofw/ofw_bus.h>
44 #include <dev/ofw/ofw_bus_subr.h>
45
46 #include "pwmbus_if.h"
47
48 #include "am335x_pwm.h"
49
50 /*******************************************************************************
51 * Enhanced resolution PWM driver. Many of the advanced featues of the hardware
52 * are not supported by this driver. What is implemented here is simple
53 * variable-duty-cycle PWM output.
54 *
55 * Note that this driver was historically configured using a set of sysctl
56 * variables/procs, and later gained support for the PWM(9) API. The sysctl
57 * code is still present to support existing apps, but that interface is
58 * considered deprecated.
59 *
60 * An important caveat is that the original sysctl interface and the new PWM API
61 * cannot both be used at once. If both interfaces are used to change
62 * configuration, it's quite likely you won't get the expected results. Also,
63 * reading the sysctl values after configuring via PWM will not return the right
64 * results.
65 ******************************************************************************/
66
67 /* In ticks */
68 #define DEFAULT_PWM_PERIOD 1000
69 #define PWM_CLOCK 100000000UL
70
71 #define NS_PER_SEC 1000000000
72
73 #define PWM_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
74 #define PWM_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
75 #define PWM_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
76 #define PWM_LOCK_INIT(_sc) mtx_init(&(_sc)->sc_mtx, \
77 device_get_nameunit(_sc->sc_dev), "am335x_ehrpwm softc", MTX_DEF)
78 #define PWM_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx)
79
80 #define EPWM_READ2(_sc, reg) bus_read_2((_sc)->sc_mem_res, reg)
81 #define EPWM_WRITE2(_sc, reg, value) \
82 bus_write_2((_sc)->sc_mem_res, reg, value)
83
84 #define EPWM_TBCTL 0x00
85 #define TBCTL_FREERUN (2 << 14)
86 #define TBCTL_PHDIR_UP (1 << 13)
87 #define TBCTL_PHDIR_DOWN (0 << 13)
88 #define TBCTL_CLKDIV(x) ((x) << 10)
89 #define TBCTL_CLKDIV_MASK (3 << 10)
90 #define TBCTL_HSPCLKDIV(x) ((x) << 7)
91 #define TBCTL_HSPCLKDIV_MASK (3 << 7)
92 #define TBCTL_SYNCOSEL_DISABLED (3 << 4)
93 #define TBCTL_PRDLD_SHADOW (0 << 3)
94 #define TBCTL_PRDLD_IMMEDIATE (0 << 3)
95 #define TBCTL_PHSEN_ENABLED (1 << 2)
96 #define TBCTL_PHSEN_DISABLED (0 << 2)
97 #define TBCTL_CTRMODE_MASK (3)
98 #define TBCTL_CTRMODE_UP (0 << 0)
99 #define TBCTL_CTRMODE_DOWN (1 << 0)
100 #define TBCTL_CTRMODE_UPDOWN (2 << 0)
101 #define TBCTL_CTRMODE_FREEZE (3 << 0)
102
103 #define EPWM_TBSTS 0x02
104 #define EPWM_TBPHSHR 0x04
105 #define EPWM_TBPHS 0x06
106 #define EPWM_TBCNT 0x08
107 #define EPWM_TBPRD 0x0a
108 /* Counter-compare */
109 #define EPWM_CMPCTL 0x0e
110 #define CMPCTL_SHDWBMODE_SHADOW (1 << 6)
111 #define CMPCTL_SHDWBMODE_IMMEDIATE (0 << 6)
112 #define CMPCTL_SHDWAMODE_SHADOW (1 << 4)
113 #define CMPCTL_SHDWAMODE_IMMEDIATE (0 << 4)
114 #define CMPCTL_LOADBMODE_ZERO (0 << 2)
115 #define CMPCTL_LOADBMODE_PRD (1 << 2)
116 #define CMPCTL_LOADBMODE_EITHER (2 << 2)
117 #define CMPCTL_LOADBMODE_FREEZE (3 << 2)
118 #define CMPCTL_LOADAMODE_ZERO (0 << 0)
119 #define CMPCTL_LOADAMODE_PRD (1 << 0)
120 #define CMPCTL_LOADAMODE_EITHER (2 << 0)
121 #define CMPCTL_LOADAMODE_FREEZE (3 << 0)
122 #define EPWM_CMPAHR 0x10
123 #define EPWM_CMPA 0x12
124 #define EPWM_CMPB 0x14
125 /* CMPCTL_LOADAMODE_ZERO */
126 #define EPWM_AQCTLA 0x16
127 #define EPWM_AQCTLB 0x18
128 #define AQCTL_CBU_NONE (0 << 8)
129 #define AQCTL_CBU_CLEAR (1 << 8)
130 #define AQCTL_CBU_SET (2 << 8)
131 #define AQCTL_CBU_TOGGLE (3 << 8)
132 #define AQCTL_CAU_NONE (0 << 4)
133 #define AQCTL_CAU_CLEAR (1 << 4)
134 #define AQCTL_CAU_SET (2 << 4)
135 #define AQCTL_CAU_TOGGLE (3 << 4)
136 #define AQCTL_ZRO_NONE (0 << 0)
137 #define AQCTL_ZRO_CLEAR (1 << 0)
138 #define AQCTL_ZRO_SET (2 << 0)
139 #define AQCTL_ZRO_TOGGLE (3 << 0)
140 #define EPWM_AQSFRC 0x1a
141 #define EPWM_AQCSFRC 0x1c
142 #define AQCSFRC_OFF 0
143 #define AQCSFRC_LO 1
144 #define AQCSFRC_HI 2
145 #define AQCSFRC_MASK 3
146 #define AQCSFRC(chan, hilo) ((hilo) << (2 * chan))
147
148 /* Trip-Zone module */
149 #define EPWM_TZCTL 0x28
150 #define EPWM_TZFLG 0x2C
151 /* High-Resolution PWM */
152 #define EPWM_HRCTL 0x40
153 #define HRCTL_DELMODE_BOTH 3
154 #define HRCTL_DELMODE_FALL 2
155 #define HRCTL_DELMODE_RISE 1
156
157 static device_probe_t am335x_ehrpwm_probe;
158 static device_attach_t am335x_ehrpwm_attach;
159 static device_detach_t am335x_ehrpwm_detach;
160
161 static int am335x_ehrpwm_clkdiv[8] = { 1, 2, 4, 8, 16, 32, 64, 128 };
162
163 struct ehrpwm_channel {
164 u_int duty; /* on duration, in ns */
165 bool enabled; /* channel enabled? */
166 bool inverted; /* signal inverted? */
167 };
168 #define NUM_CHANNELS 2
169
170 struct am335x_ehrpwm_softc {
171 device_t sc_dev;
172 device_t sc_busdev;
173 struct mtx sc_mtx;
174 struct resource *sc_mem_res;
175 int sc_mem_rid;
176
177 /* Things used for configuration via sysctl [deprecated]. */
178 int sc_pwm_clkdiv;
179 int sc_pwm_freq;
180 struct sysctl_oid *sc_clkdiv_oid;
181 struct sysctl_oid *sc_freq_oid;
182 struct sysctl_oid *sc_period_oid;
183 struct sysctl_oid *sc_chanA_oid;
184 struct sysctl_oid *sc_chanB_oid;
185 uint32_t sc_pwm_period;
186 uint32_t sc_pwm_dutyA;
187 uint32_t sc_pwm_dutyB;
188
189 /* Things used for configuration via pwm(9) api. */
190 u_int sc_clkfreq; /* frequency in Hz */
191 u_int sc_clktick; /* duration in ns */
192 u_int sc_period; /* duration in ns */
193 struct ehrpwm_channel sc_channels[NUM_CHANNELS];
194 };
195
196 static struct ofw_compat_data compat_data[] = {
197 {"ti,am33xx-ehrpwm", true},
198 {NULL, false},
199 };
200 SIMPLEBUS_PNP_INFO(compat_data);
201
202 static void
am335x_ehrpwm_cfg_duty(struct am335x_ehrpwm_softc * sc,u_int chan,u_int duty)203 am335x_ehrpwm_cfg_duty(struct am335x_ehrpwm_softc *sc, u_int chan, u_int duty)
204 {
205 u_int tbcmp;
206
207 if (duty == 0)
208 tbcmp = 0;
209 else
210 tbcmp = max(1, duty / sc->sc_clktick);
211
212 sc->sc_channels[chan].duty = tbcmp * sc->sc_clktick;
213
214 PWM_LOCK_ASSERT(sc);
215 EPWM_WRITE2(sc, (chan == 0) ? EPWM_CMPA : EPWM_CMPB, tbcmp);
216 }
217
218 static void
am335x_ehrpwm_cfg_enable(struct am335x_ehrpwm_softc * sc,u_int chan,bool enable)219 am335x_ehrpwm_cfg_enable(struct am335x_ehrpwm_softc *sc, u_int chan, bool enable)
220 {
221 uint16_t regval;
222
223 sc->sc_channels[chan].enabled = enable;
224
225 /*
226 * Turn off any existing software-force of the channel, then force
227 * it in the right direction (high or low) if it's not being enabled.
228 */
229 PWM_LOCK_ASSERT(sc);
230 regval = EPWM_READ2(sc, EPWM_AQCSFRC);
231 regval &= ~AQCSFRC(chan, AQCSFRC_MASK);
232 if (!sc->sc_channels[chan].enabled) {
233 if (sc->sc_channels[chan].inverted)
234 regval |= AQCSFRC(chan, AQCSFRC_HI);
235 else
236 regval |= AQCSFRC(chan, AQCSFRC_LO);
237 }
238 EPWM_WRITE2(sc, EPWM_AQCSFRC, regval);
239 }
240
241 static bool
am335x_ehrpwm_cfg_period(struct am335x_ehrpwm_softc * sc,u_int period)242 am335x_ehrpwm_cfg_period(struct am335x_ehrpwm_softc *sc, u_int period)
243 {
244 uint16_t regval;
245 u_int clkdiv, hspclkdiv, pwmclk, pwmtick, tbprd;
246
247 /* Can't do a period shorter than 2 clock ticks. */
248 if (period < 2 * NS_PER_SEC / PWM_CLOCK) {
249 sc->sc_clkfreq = 0;
250 sc->sc_clktick = 0;
251 sc->sc_period = 0;
252 return (false);
253 }
254
255 /*
256 * Figure out how much we have to divide down the base 100MHz clock so
257 * that we can express the requested period as a 16-bit tick count.
258 */
259 tbprd = 0;
260 for (clkdiv = 0; clkdiv < 8; ++clkdiv) {
261 const u_int cd = 1 << clkdiv;
262 for (hspclkdiv = 0; hspclkdiv < 8; ++hspclkdiv) {
263 const u_int cdhs = max(1, hspclkdiv * 2);
264 pwmclk = PWM_CLOCK / (cd * cdhs);
265 pwmtick = NS_PER_SEC / pwmclk;
266 if (period / pwmtick < 65536) {
267 tbprd = period / pwmtick;
268 break;
269 }
270 }
271 if (tbprd != 0)
272 break;
273 }
274
275 /* Handle requested period too long for available clock divisors. */
276 if (tbprd == 0)
277 return (false);
278
279 /*
280 * If anything has changed from the current settings, reprogram the
281 * clock divisors and period register.
282 */
283 if (sc->sc_clkfreq != pwmclk || sc->sc_clktick != pwmtick ||
284 sc->sc_period != tbprd * pwmtick) {
285 sc->sc_clkfreq = pwmclk;
286 sc->sc_clktick = pwmtick;
287 sc->sc_period = tbprd * pwmtick;
288
289 PWM_LOCK_ASSERT(sc);
290 regval = EPWM_READ2(sc, EPWM_TBCTL);
291 regval &= ~(TBCTL_CLKDIV_MASK | TBCTL_HSPCLKDIV_MASK);
292 regval |= TBCTL_CLKDIV(clkdiv) | TBCTL_HSPCLKDIV(hspclkdiv);
293 EPWM_WRITE2(sc, EPWM_TBCTL, regval);
294 EPWM_WRITE2(sc, EPWM_TBPRD, tbprd - 1);
295 #if 0
296 device_printf(sc->sc_dev, "clkdiv %u hspclkdiv %u tbprd %u "
297 "clkfreq %u Hz clktick %u ns period got %u requested %u\n",
298 clkdiv, hspclkdiv, tbprd - 1,
299 sc->sc_clkfreq, sc->sc_clktick, sc->sc_period, period);
300 #endif
301 /*
302 * If the period changed, that invalidates the current CMP
303 * registers (duty values), just zero them out.
304 */
305 am335x_ehrpwm_cfg_duty(sc, 0, 0);
306 am335x_ehrpwm_cfg_duty(sc, 1, 0);
307 }
308
309 return (true);
310 }
311
312 static void
am335x_ehrpwm_freq(struct am335x_ehrpwm_softc * sc)313 am335x_ehrpwm_freq(struct am335x_ehrpwm_softc *sc)
314 {
315 int clkdiv;
316
317 clkdiv = am335x_ehrpwm_clkdiv[sc->sc_pwm_clkdiv];
318 sc->sc_pwm_freq = PWM_CLOCK / (1 * clkdiv) / sc->sc_pwm_period;
319 }
320
321 static int
am335x_ehrpwm_sysctl_freq(SYSCTL_HANDLER_ARGS)322 am335x_ehrpwm_sysctl_freq(SYSCTL_HANDLER_ARGS)
323 {
324 int clkdiv, error, freq, i, period;
325 struct am335x_ehrpwm_softc *sc;
326 uint32_t reg;
327
328 sc = (struct am335x_ehrpwm_softc *)arg1;
329
330 PWM_LOCK(sc);
331 freq = sc->sc_pwm_freq;
332 PWM_UNLOCK(sc);
333
334 error = sysctl_handle_int(oidp, &freq, sizeof(freq), req);
335 if (error != 0 || req->newptr == NULL)
336 return (error);
337
338 if (freq > PWM_CLOCK)
339 freq = PWM_CLOCK;
340
341 PWM_LOCK(sc);
342 if (freq != sc->sc_pwm_freq) {
343 for (i = nitems(am335x_ehrpwm_clkdiv) - 1; i >= 0; i--) {
344 clkdiv = am335x_ehrpwm_clkdiv[i];
345 period = PWM_CLOCK / clkdiv / freq;
346 if (period > USHRT_MAX)
347 break;
348 sc->sc_pwm_clkdiv = i;
349 sc->sc_pwm_period = period;
350 }
351 /* Reset the duty cycle settings. */
352 sc->sc_pwm_dutyA = 0;
353 sc->sc_pwm_dutyB = 0;
354 EPWM_WRITE2(sc, EPWM_CMPA, sc->sc_pwm_dutyA);
355 EPWM_WRITE2(sc, EPWM_CMPB, sc->sc_pwm_dutyB);
356 /* Update the clkdiv settings. */
357 reg = EPWM_READ2(sc, EPWM_TBCTL);
358 reg &= ~TBCTL_CLKDIV_MASK;
359 reg |= TBCTL_CLKDIV(sc->sc_pwm_clkdiv);
360 EPWM_WRITE2(sc, EPWM_TBCTL, reg);
361 /* Update the period settings. */
362 EPWM_WRITE2(sc, EPWM_TBPRD, sc->sc_pwm_period - 1);
363 am335x_ehrpwm_freq(sc);
364 }
365 PWM_UNLOCK(sc);
366
367 return (0);
368 }
369
370 static int
am335x_ehrpwm_sysctl_clkdiv(SYSCTL_HANDLER_ARGS)371 am335x_ehrpwm_sysctl_clkdiv(SYSCTL_HANDLER_ARGS)
372 {
373 int error, i, clkdiv;
374 struct am335x_ehrpwm_softc *sc;
375 uint32_t reg;
376
377 sc = (struct am335x_ehrpwm_softc *)arg1;
378
379 PWM_LOCK(sc);
380 clkdiv = am335x_ehrpwm_clkdiv[sc->sc_pwm_clkdiv];
381 PWM_UNLOCK(sc);
382
383 error = sysctl_handle_int(oidp, &clkdiv, sizeof(clkdiv), req);
384 if (error != 0 || req->newptr == NULL)
385 return (error);
386
387 PWM_LOCK(sc);
388 if (clkdiv != am335x_ehrpwm_clkdiv[sc->sc_pwm_clkdiv]) {
389 for (i = 0; i < nitems(am335x_ehrpwm_clkdiv); i++)
390 if (clkdiv >= am335x_ehrpwm_clkdiv[i])
391 sc->sc_pwm_clkdiv = i;
392
393 reg = EPWM_READ2(sc, EPWM_TBCTL);
394 reg &= ~TBCTL_CLKDIV_MASK;
395 reg |= TBCTL_CLKDIV(sc->sc_pwm_clkdiv);
396 EPWM_WRITE2(sc, EPWM_TBCTL, reg);
397 am335x_ehrpwm_freq(sc);
398 }
399 PWM_UNLOCK(sc);
400
401 return (0);
402 }
403
404 static int
am335x_ehrpwm_sysctl_duty(SYSCTL_HANDLER_ARGS)405 am335x_ehrpwm_sysctl_duty(SYSCTL_HANDLER_ARGS)
406 {
407 struct am335x_ehrpwm_softc *sc = (struct am335x_ehrpwm_softc*)arg1;
408 int error;
409 uint32_t duty;
410
411 if (oidp == sc->sc_chanA_oid)
412 duty = sc->sc_pwm_dutyA;
413 else
414 duty = sc->sc_pwm_dutyB;
415 error = sysctl_handle_int(oidp, &duty, 0, req);
416
417 if (error != 0 || req->newptr == NULL)
418 return (error);
419
420 if (duty > sc->sc_pwm_period) {
421 device_printf(sc->sc_dev, "Duty cycle can't be greater then period\n");
422 return (EINVAL);
423 }
424
425 PWM_LOCK(sc);
426 if (oidp == sc->sc_chanA_oid) {
427 sc->sc_pwm_dutyA = duty;
428 EPWM_WRITE2(sc, EPWM_CMPA, sc->sc_pwm_dutyA);
429 }
430 else {
431 sc->sc_pwm_dutyB = duty;
432 EPWM_WRITE2(sc, EPWM_CMPB, sc->sc_pwm_dutyB);
433 }
434 PWM_UNLOCK(sc);
435
436 return (error);
437 }
438
439 static int
am335x_ehrpwm_sysctl_period(SYSCTL_HANDLER_ARGS)440 am335x_ehrpwm_sysctl_period(SYSCTL_HANDLER_ARGS)
441 {
442 struct am335x_ehrpwm_softc *sc = (struct am335x_ehrpwm_softc*)arg1;
443 int error;
444 uint32_t period;
445
446 period = sc->sc_pwm_period;
447 error = sysctl_handle_int(oidp, &period, 0, req);
448
449 if (error != 0 || req->newptr == NULL)
450 return (error);
451
452 if (period < 1)
453 return (EINVAL);
454
455 if (period > USHRT_MAX)
456 period = USHRT_MAX;
457
458 PWM_LOCK(sc);
459 /* Reset the duty cycle settings. */
460 sc->sc_pwm_dutyA = 0;
461 sc->sc_pwm_dutyB = 0;
462 EPWM_WRITE2(sc, EPWM_CMPA, sc->sc_pwm_dutyA);
463 EPWM_WRITE2(sc, EPWM_CMPB, sc->sc_pwm_dutyB);
464 /* Update the period settings. */
465 sc->sc_pwm_period = period;
466 EPWM_WRITE2(sc, EPWM_TBPRD, period - 1);
467 am335x_ehrpwm_freq(sc);
468 PWM_UNLOCK(sc);
469
470 return (error);
471 }
472
473 static int
am335x_ehrpwm_channel_count(device_t dev,u_int * nchannel)474 am335x_ehrpwm_channel_count(device_t dev, u_int *nchannel)
475 {
476
477 *nchannel = NUM_CHANNELS;
478
479 return (0);
480 }
481
482 static int
am335x_ehrpwm_channel_config(device_t dev,u_int channel,u_int period,u_int duty)483 am335x_ehrpwm_channel_config(device_t dev, u_int channel, u_int period, u_int duty)
484 {
485 struct am335x_ehrpwm_softc *sc;
486 bool status;
487
488 if (channel >= NUM_CHANNELS)
489 return (EINVAL);
490
491 sc = device_get_softc(dev);
492
493 PWM_LOCK(sc);
494 status = am335x_ehrpwm_cfg_period(sc, period);
495 if (status)
496 am335x_ehrpwm_cfg_duty(sc, channel, duty);
497 PWM_UNLOCK(sc);
498
499 return (status ? 0 : EINVAL);
500 }
501
502 static int
am335x_ehrpwm_channel_get_config(device_t dev,u_int channel,u_int * period,u_int * duty)503 am335x_ehrpwm_channel_get_config(device_t dev, u_int channel,
504 u_int *period, u_int *duty)
505 {
506 struct am335x_ehrpwm_softc *sc;
507
508 if (channel >= NUM_CHANNELS)
509 return (EINVAL);
510
511 sc = device_get_softc(dev);
512 *period = sc->sc_period;
513 *duty = sc->sc_channels[channel].duty;
514 return (0);
515 }
516
517 static int
am335x_ehrpwm_channel_enable(device_t dev,u_int channel,bool enable)518 am335x_ehrpwm_channel_enable(device_t dev, u_int channel, bool enable)
519 {
520 struct am335x_ehrpwm_softc *sc;
521
522 if (channel >= NUM_CHANNELS)
523 return (EINVAL);
524
525 sc = device_get_softc(dev);
526
527 PWM_LOCK(sc);
528 am335x_ehrpwm_cfg_enable(sc, channel, enable);
529 PWM_UNLOCK(sc);
530
531 return (0);
532 }
533
534 static int
am335x_ehrpwm_channel_is_enabled(device_t dev,u_int channel,bool * enabled)535 am335x_ehrpwm_channel_is_enabled(device_t dev, u_int channel, bool *enabled)
536 {
537 struct am335x_ehrpwm_softc *sc;
538
539 if (channel >= NUM_CHANNELS)
540 return (EINVAL);
541
542 sc = device_get_softc(dev);
543
544 *enabled = sc->sc_channels[channel].enabled;
545
546 return (0);
547 }
548
549 static int
am335x_ehrpwm_probe(device_t dev)550 am335x_ehrpwm_probe(device_t dev)
551 {
552
553 if (!ofw_bus_status_okay(dev))
554 return (ENXIO);
555
556 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
557 return (ENXIO);
558
559 device_set_desc(dev, "AM335x EHRPWM");
560
561 return (BUS_PROBE_DEFAULT);
562 }
563
564 static int
am335x_ehrpwm_attach(device_t dev)565 am335x_ehrpwm_attach(device_t dev)
566 {
567 struct am335x_ehrpwm_softc *sc;
568 uint32_t reg;
569 struct sysctl_ctx_list *ctx;
570 struct sysctl_oid *tree;
571
572 sc = device_get_softc(dev);
573 sc->sc_dev = dev;
574
575 PWM_LOCK_INIT(sc);
576
577 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
578 &sc->sc_mem_rid, RF_ACTIVE);
579 if (sc->sc_mem_res == NULL) {
580 device_printf(dev, "cannot allocate memory resources\n");
581 goto fail;
582 }
583
584 /* Init sysctl interface */
585 ctx = device_get_sysctl_ctx(sc->sc_dev);
586 tree = device_get_sysctl_tree(sc->sc_dev);
587
588 sc->sc_clkdiv_oid = SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
589 "clkdiv", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0,
590 am335x_ehrpwm_sysctl_clkdiv, "I", "PWM clock prescaler");
591
592 sc->sc_freq_oid = SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
593 "freq", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0,
594 am335x_ehrpwm_sysctl_freq, "I", "PWM frequency");
595
596 sc->sc_period_oid = SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
597 "period", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0,
598 am335x_ehrpwm_sysctl_period, "I", "PWM period");
599
600 sc->sc_chanA_oid = SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
601 "dutyA", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0,
602 am335x_ehrpwm_sysctl_duty, "I", "Channel A duty cycles");
603
604 sc->sc_chanB_oid = SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
605 "dutyB", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0,
606 am335x_ehrpwm_sysctl_duty, "I", "Channel B duty cycles");
607
608 /* CONFIGURE EPWM1 */
609 reg = EPWM_READ2(sc, EPWM_TBCTL);
610 reg &= ~(TBCTL_CLKDIV_MASK | TBCTL_HSPCLKDIV_MASK);
611 EPWM_WRITE2(sc, EPWM_TBCTL, reg);
612
613 sc->sc_pwm_period = DEFAULT_PWM_PERIOD;
614 sc->sc_pwm_dutyA = 0;
615 sc->sc_pwm_dutyB = 0;
616 am335x_ehrpwm_freq(sc);
617
618 EPWM_WRITE2(sc, EPWM_TBPRD, sc->sc_pwm_period - 1);
619 EPWM_WRITE2(sc, EPWM_CMPA, sc->sc_pwm_dutyA);
620 EPWM_WRITE2(sc, EPWM_CMPB, sc->sc_pwm_dutyB);
621
622 EPWM_WRITE2(sc, EPWM_AQCTLA, (AQCTL_ZRO_SET | AQCTL_CAU_CLEAR));
623 EPWM_WRITE2(sc, EPWM_AQCTLB, (AQCTL_ZRO_SET | AQCTL_CBU_CLEAR));
624
625 /* START EPWM */
626 reg &= ~TBCTL_CTRMODE_MASK;
627 reg |= TBCTL_CTRMODE_UP | TBCTL_FREERUN;
628 EPWM_WRITE2(sc, EPWM_TBCTL, reg);
629
630 EPWM_WRITE2(sc, EPWM_TZCTL, 0xf);
631 reg = EPWM_READ2(sc, EPWM_TZFLG);
632
633 if ((sc->sc_busdev = device_add_child(dev, "pwmbus", -1)) == NULL) {
634 device_printf(dev, "Cannot add child pwmbus\n");
635 // This driver can still do things even without the bus child.
636 }
637
638 bus_generic_probe(dev);
639 return (bus_generic_attach(dev));
640 fail:
641 PWM_LOCK_DESTROY(sc);
642 if (sc->sc_mem_res)
643 bus_release_resource(dev, SYS_RES_MEMORY,
644 sc->sc_mem_rid, sc->sc_mem_res);
645
646 return(ENXIO);
647 }
648
649 static int
am335x_ehrpwm_detach(device_t dev)650 am335x_ehrpwm_detach(device_t dev)
651 {
652 struct am335x_ehrpwm_softc *sc;
653 int error;
654
655 sc = device_get_softc(dev);
656
657 if ((error = bus_generic_detach(sc->sc_dev)) != 0)
658 return (error);
659
660 PWM_LOCK(sc);
661
662 if (sc->sc_busdev != NULL)
663 device_delete_child(dev, sc->sc_busdev);
664
665 if (sc->sc_mem_res)
666 bus_release_resource(dev, SYS_RES_MEMORY,
667 sc->sc_mem_rid, sc->sc_mem_res);
668
669 PWM_UNLOCK(sc);
670
671 PWM_LOCK_DESTROY(sc);
672
673 return (0);
674 }
675
676 static phandle_t
am335x_ehrpwm_get_node(device_t bus,device_t dev)677 am335x_ehrpwm_get_node(device_t bus, device_t dev)
678 {
679
680 /*
681 * Share our controller node with our pwmbus child; it instantiates
682 * devices by walking the children contained within our node.
683 */
684 return ofw_bus_get_node(bus);
685 }
686
687 static device_method_t am335x_ehrpwm_methods[] = {
688 DEVMETHOD(device_probe, am335x_ehrpwm_probe),
689 DEVMETHOD(device_attach, am335x_ehrpwm_attach),
690 DEVMETHOD(device_detach, am335x_ehrpwm_detach),
691
692 /* ofw_bus_if */
693 DEVMETHOD(ofw_bus_get_node, am335x_ehrpwm_get_node),
694
695 /* pwm interface */
696 DEVMETHOD(pwmbus_channel_count, am335x_ehrpwm_channel_count),
697 DEVMETHOD(pwmbus_channel_config, am335x_ehrpwm_channel_config),
698 DEVMETHOD(pwmbus_channel_get_config, am335x_ehrpwm_channel_get_config),
699 DEVMETHOD(pwmbus_channel_enable, am335x_ehrpwm_channel_enable),
700 DEVMETHOD(pwmbus_channel_is_enabled, am335x_ehrpwm_channel_is_enabled),
701
702 DEVMETHOD_END
703 };
704
705 static driver_t am335x_ehrpwm_driver = {
706 "pwm",
707 am335x_ehrpwm_methods,
708 sizeof(struct am335x_ehrpwm_softc),
709 };
710
711 static devclass_t am335x_ehrpwm_devclass;
712
713 DRIVER_MODULE(am335x_ehrpwm, am335x_pwmss, am335x_ehrpwm_driver, am335x_ehrpwm_devclass, 0, 0);
714 MODULE_VERSION(am335x_ehrpwm, 1);
715 MODULE_DEPEND(am335x_ehrpwm, am335x_pwmss, 1, 1, 1);
716 MODULE_DEPEND(am335x_ehrpwm, pwmbus, 1, 1, 1);
717