1 /*-
2 * Copyright 2014 Luiz Otavio O Souza <loos@freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 #include "opt_evdev.h"
29
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <sys/bus.h>
33
34 #include <sys/conf.h>
35 #include <sys/kernel.h>
36 #include <sys/limits.h>
37 #include <sys/lock.h>
38 #include <sys/module.h>
39 #include <sys/mutex.h>
40 #include <sys/condvar.h>
41 #include <sys/resource.h>
42 #include <sys/rman.h>
43 #include <sys/sysctl.h>
44 #include <sys/selinfo.h>
45 #include <sys/poll.h>
46 #include <sys/uio.h>
47
48 #include <machine/bus.h>
49
50 #include <dev/ofw/openfirm.h>
51 #include <dev/ofw/ofw_bus.h>
52 #include <dev/ofw/ofw_bus_subr.h>
53
54 #ifdef EVDEV_SUPPORT
55 #include <dev/evdev/input.h>
56 #include <dev/evdev/evdev.h>
57 #endif
58
59 #include <arm/ti/ti_sysc.h>
60 #include <arm/ti/ti_adcreg.h>
61 #include <arm/ti/ti_adcvar.h>
62
63 #undef DEBUG_TSC
64
65 #define DEFAULT_CHARGE_DELAY 0x400
66 #define STEPDLY_OPEN 0x98
67
68 #define ORDER_XP 0
69 #define ORDER_XN 1
70 #define ORDER_YP 2
71 #define ORDER_YN 3
72
73 /* Define our 8 steps, one for each input channel. */
74 static struct ti_adc_input ti_adc_inputs[TI_ADC_NPINS] = {
75 { .stepconfig = ADC_STEPCFG(1), .stepdelay = ADC_STEPDLY(1) },
76 { .stepconfig = ADC_STEPCFG(2), .stepdelay = ADC_STEPDLY(2) },
77 { .stepconfig = ADC_STEPCFG(3), .stepdelay = ADC_STEPDLY(3) },
78 { .stepconfig = ADC_STEPCFG(4), .stepdelay = ADC_STEPDLY(4) },
79 { .stepconfig = ADC_STEPCFG(5), .stepdelay = ADC_STEPDLY(5) },
80 { .stepconfig = ADC_STEPCFG(6), .stepdelay = ADC_STEPDLY(6) },
81 { .stepconfig = ADC_STEPCFG(7), .stepdelay = ADC_STEPDLY(7) },
82 { .stepconfig = ADC_STEPCFG(8), .stepdelay = ADC_STEPDLY(8) },
83 };
84
85 static int ti_adc_samples[5] = { 0, 2, 4, 8, 16 };
86
87 static int ti_adc_detach(device_t dev);
88
89 #ifdef EVDEV_SUPPORT
90 static void
ti_adc_ev_report(struct ti_adc_softc * sc)91 ti_adc_ev_report(struct ti_adc_softc *sc)
92 {
93
94 evdev_push_event(sc->sc_evdev, EV_ABS, ABS_X, sc->sc_x);
95 evdev_push_event(sc->sc_evdev, EV_ABS, ABS_Y, sc->sc_y);
96 evdev_push_event(sc->sc_evdev, EV_KEY, BTN_TOUCH, sc->sc_pen_down);
97 evdev_sync(sc->sc_evdev);
98 }
99 #endif /* EVDEV */
100
101 static void
ti_adc_enable(struct ti_adc_softc * sc)102 ti_adc_enable(struct ti_adc_softc *sc)
103 {
104 uint32_t reg;
105
106 TI_ADC_LOCK_ASSERT(sc);
107
108 if (sc->sc_last_state == 1)
109 return;
110
111 /* Enable the FIFO0 threshold and the end of sequence interrupt. */
112 ADC_WRITE4(sc, ADC_IRQENABLE_SET,
113 ADC_IRQ_FIFO0_THRES | ADC_IRQ_FIFO1_THRES | ADC_IRQ_END_OF_SEQ);
114
115 reg = ADC_CTRL_STEP_WP | ADC_CTRL_STEP_ID;
116 if (sc->sc_tsc_wires > 0) {
117 reg |= ADC_CTRL_TSC_ENABLE;
118 switch (sc->sc_tsc_wires) {
119 case 4:
120 reg |= ADC_CTRL_TSC_4WIRE;
121 break;
122 case 5:
123 reg |= ADC_CTRL_TSC_5WIRE;
124 break;
125 case 8:
126 reg |= ADC_CTRL_TSC_8WIRE;
127 break;
128 default:
129 break;
130 }
131 }
132 reg |= ADC_CTRL_ENABLE;
133 /* Enable the ADC. Run thru enabled steps, start the conversions. */
134 ADC_WRITE4(sc, ADC_CTRL, reg);
135
136 sc->sc_last_state = 1;
137 }
138
139 static void
ti_adc_disable(struct ti_adc_softc * sc)140 ti_adc_disable(struct ti_adc_softc *sc)
141 {
142 int count;
143 uint32_t data;
144
145 TI_ADC_LOCK_ASSERT(sc);
146
147 if (sc->sc_last_state == 0)
148 return;
149
150 /* Disable all the enabled steps. */
151 ADC_WRITE4(sc, ADC_STEPENABLE, 0);
152
153 /* Disable the ADC. */
154 ADC_WRITE4(sc, ADC_CTRL, ADC_READ4(sc, ADC_CTRL) & ~ADC_CTRL_ENABLE);
155
156 /* Disable the FIFO0 threshold and the end of sequence interrupt. */
157 ADC_WRITE4(sc, ADC_IRQENABLE_CLR,
158 ADC_IRQ_FIFO0_THRES | ADC_IRQ_FIFO1_THRES | ADC_IRQ_END_OF_SEQ);
159
160 /* ACK any pending interrupt. */
161 ADC_WRITE4(sc, ADC_IRQSTATUS, ADC_READ4(sc, ADC_IRQSTATUS));
162
163 /* Drain the FIFO data. */
164 count = ADC_READ4(sc, ADC_FIFO0COUNT) & ADC_FIFO_COUNT_MSK;
165 while (count > 0) {
166 data = ADC_READ4(sc, ADC_FIFO0DATA);
167 count = ADC_READ4(sc, ADC_FIFO0COUNT) & ADC_FIFO_COUNT_MSK;
168 }
169
170 count = ADC_READ4(sc, ADC_FIFO1COUNT) & ADC_FIFO_COUNT_MSK;
171 while (count > 0) {
172 data = ADC_READ4(sc, ADC_FIFO1DATA);
173 count = ADC_READ4(sc, ADC_FIFO1COUNT) & ADC_FIFO_COUNT_MSK;
174 }
175
176 sc->sc_last_state = 0;
177 }
178
179 static int
ti_adc_setup(struct ti_adc_softc * sc)180 ti_adc_setup(struct ti_adc_softc *sc)
181 {
182 int ain, i;
183 uint32_t enabled;
184
185 TI_ADC_LOCK_ASSERT(sc);
186
187 /* Check for enabled inputs. */
188 enabled = sc->sc_tsc_enabled;
189 for (i = 0; i < sc->sc_adc_nchannels; i++) {
190 ain = sc->sc_adc_channels[i];
191 if (ti_adc_inputs[ain].enable)
192 enabled |= (1U << (ain + 1));
193 }
194
195 /* Set the ADC global status. */
196 if (enabled != 0) {
197 ti_adc_enable(sc);
198 /* Update the enabled steps. */
199 if (enabled != ADC_READ4(sc, ADC_STEPENABLE))
200 ADC_WRITE4(sc, ADC_STEPENABLE, enabled);
201 } else
202 ti_adc_disable(sc);
203
204 return (0);
205 }
206
207 static void
ti_adc_input_setup(struct ti_adc_softc * sc,int32_t ain)208 ti_adc_input_setup(struct ti_adc_softc *sc, int32_t ain)
209 {
210 struct ti_adc_input *input;
211 uint32_t reg, val;
212
213 TI_ADC_LOCK_ASSERT(sc);
214
215 input = &ti_adc_inputs[ain];
216 reg = input->stepconfig;
217 val = ADC_READ4(sc, reg);
218
219 /* Set single ended operation. */
220 val &= ~ADC_STEP_DIFF_CNTRL;
221
222 /* Set the negative voltage reference. */
223 val &= ~ADC_STEP_RFM_MSK;
224
225 /* Set the positive voltage reference. */
226 val &= ~ADC_STEP_RFP_MSK;
227
228 /* Set the samples average. */
229 val &= ~ADC_STEP_AVG_MSK;
230 val |= input->samples << ADC_STEP_AVG_SHIFT;
231
232 /* Select the desired input. */
233 val &= ~ADC_STEP_INP_MSK;
234 val |= ain << ADC_STEP_INP_SHIFT;
235
236 /* Set the ADC to one-shot mode. */
237 val &= ~ADC_STEP_MODE_MSK;
238
239 ADC_WRITE4(sc, reg, val);
240 }
241
242 static void
ti_adc_reset(struct ti_adc_softc * sc)243 ti_adc_reset(struct ti_adc_softc *sc)
244 {
245 int ain, i;
246
247 TI_ADC_LOCK_ASSERT(sc);
248
249 /* Disable all the inputs. */
250 for (i = 0; i < sc->sc_adc_nchannels; i++) {
251 ain = sc->sc_adc_channels[i];
252 ti_adc_inputs[ain].enable = 0;
253 }
254 }
255
256 static int
ti_adc_clockdiv_proc(SYSCTL_HANDLER_ARGS)257 ti_adc_clockdiv_proc(SYSCTL_HANDLER_ARGS)
258 {
259 int error, reg;
260 struct ti_adc_softc *sc;
261
262 sc = (struct ti_adc_softc *)arg1;
263
264 TI_ADC_LOCK(sc);
265 reg = (int)ADC_READ4(sc, ADC_CLKDIV) + 1;
266 TI_ADC_UNLOCK(sc);
267
268 error = sysctl_handle_int(oidp, ®, sizeof(reg), req);
269 if (error != 0 || req->newptr == NULL)
270 return (error);
271
272 /*
273 * The actual written value is the prescaler setting - 1.
274 * Enforce a minimum value of 10 (i.e. 9) which limits the maximum
275 * ADC clock to ~2.4Mhz (CLK_M_OSC / 10).
276 */
277 reg--;
278 if (reg < 9)
279 reg = 9;
280 if (reg > USHRT_MAX)
281 reg = USHRT_MAX;
282
283 TI_ADC_LOCK(sc);
284 /* Disable the ADC. */
285 ti_adc_disable(sc);
286 /* Update the ADC prescaler setting. */
287 ADC_WRITE4(sc, ADC_CLKDIV, reg);
288 /* Enable the ADC again. */
289 ti_adc_setup(sc);
290 TI_ADC_UNLOCK(sc);
291
292 return (0);
293 }
294
295 static int
ti_adc_enable_proc(SYSCTL_HANDLER_ARGS)296 ti_adc_enable_proc(SYSCTL_HANDLER_ARGS)
297 {
298 int error;
299 int32_t enable;
300 struct ti_adc_softc *sc;
301 struct ti_adc_input *input;
302
303 input = (struct ti_adc_input *)arg1;
304 sc = input->sc;
305
306 enable = input->enable;
307 error = sysctl_handle_int(oidp, &enable, sizeof(enable),
308 req);
309 if (error != 0 || req->newptr == NULL)
310 return (error);
311
312 if (enable)
313 enable = 1;
314
315 TI_ADC_LOCK(sc);
316 /* Setup the ADC as needed. */
317 if (input->enable != enable) {
318 input->enable = enable;
319 ti_adc_setup(sc);
320 if (input->enable == 0)
321 input->value = 0;
322 }
323 TI_ADC_UNLOCK(sc);
324
325 return (0);
326 }
327
328 static int
ti_adc_open_delay_proc(SYSCTL_HANDLER_ARGS)329 ti_adc_open_delay_proc(SYSCTL_HANDLER_ARGS)
330 {
331 int error, reg;
332 struct ti_adc_softc *sc;
333 struct ti_adc_input *input;
334
335 input = (struct ti_adc_input *)arg1;
336 sc = input->sc;
337
338 TI_ADC_LOCK(sc);
339 reg = (int)ADC_READ4(sc, input->stepdelay) & ADC_STEP_OPEN_DELAY;
340 TI_ADC_UNLOCK(sc);
341
342 error = sysctl_handle_int(oidp, ®, sizeof(reg), req);
343 if (error != 0 || req->newptr == NULL)
344 return (error);
345
346 if (reg < 0)
347 reg = 0;
348
349 TI_ADC_LOCK(sc);
350 ADC_WRITE4(sc, input->stepdelay, reg & ADC_STEP_OPEN_DELAY);
351 TI_ADC_UNLOCK(sc);
352
353 return (0);
354 }
355
356 static int
ti_adc_samples_avg_proc(SYSCTL_HANDLER_ARGS)357 ti_adc_samples_avg_proc(SYSCTL_HANDLER_ARGS)
358 {
359 int error, samples, i;
360 struct ti_adc_softc *sc;
361 struct ti_adc_input *input;
362
363 input = (struct ti_adc_input *)arg1;
364 sc = input->sc;
365
366 if (input->samples > nitems(ti_adc_samples))
367 input->samples = nitems(ti_adc_samples);
368 samples = ti_adc_samples[input->samples];
369
370 error = sysctl_handle_int(oidp, &samples, 0, req);
371 if (error != 0 || req->newptr == NULL)
372 return (error);
373
374 TI_ADC_LOCK(sc);
375 if (samples != ti_adc_samples[input->samples]) {
376 input->samples = 0;
377 for (i = 0; i < nitems(ti_adc_samples); i++)
378 if (samples >= ti_adc_samples[i])
379 input->samples = i;
380 ti_adc_input_setup(sc, input->input);
381 }
382 TI_ADC_UNLOCK(sc);
383
384 return (error);
385 }
386
387 static void
ti_adc_read_data(struct ti_adc_softc * sc)388 ti_adc_read_data(struct ti_adc_softc *sc)
389 {
390 int count, ain;
391 struct ti_adc_input *input;
392 uint32_t data;
393
394 TI_ADC_LOCK_ASSERT(sc);
395
396 /* Read the available data. */
397 count = ADC_READ4(sc, ADC_FIFO0COUNT) & ADC_FIFO_COUNT_MSK;
398 while (count > 0) {
399 data = ADC_READ4(sc, ADC_FIFO0DATA);
400 ain = (data & ADC_FIFO_STEP_ID_MSK) >> ADC_FIFO_STEP_ID_SHIFT;
401 input = &ti_adc_inputs[ain];
402 if (input->enable == 0)
403 input->value = 0;
404 else
405 input->value = (int32_t)(data & ADC_FIFO_DATA_MSK);
406 count = ADC_READ4(sc, ADC_FIFO0COUNT) & ADC_FIFO_COUNT_MSK;
407 }
408 }
409
410 static int
cmp_values(const void * a,const void * b)411 cmp_values(const void *a, const void *b)
412 {
413 const uint32_t *v1, *v2;
414 v1 = a;
415 v2 = b;
416 if (*v1 < *v2)
417 return -1;
418 if (*v1 > *v2)
419 return 1;
420
421 return (0);
422 }
423
424 static void
ti_adc_tsc_read_data(struct ti_adc_softc * sc)425 ti_adc_tsc_read_data(struct ti_adc_softc *sc)
426 {
427 int count;
428 uint32_t data[16];
429 uint32_t x, y;
430 int i, start, end;
431
432 TI_ADC_LOCK_ASSERT(sc);
433
434 /* Read the available data. */
435 count = ADC_READ4(sc, ADC_FIFO1COUNT) & ADC_FIFO_COUNT_MSK;
436 if (count == 0)
437 return;
438
439 i = 0;
440 while (count > 0) {
441 data[i++] = ADC_READ4(sc, ADC_FIFO1DATA) & ADC_FIFO_DATA_MSK;
442 count = ADC_READ4(sc, ADC_FIFO1COUNT) & ADC_FIFO_COUNT_MSK;
443 }
444
445 if (sc->sc_coord_readouts > 3) {
446 start = 1;
447 end = sc->sc_coord_readouts - 1;
448 qsort(data, sc->sc_coord_readouts,
449 sizeof(data[0]), &cmp_values);
450 qsort(&data[sc->sc_coord_readouts + 2],
451 sc->sc_coord_readouts,
452 sizeof(data[0]), &cmp_values);
453 }
454 else {
455 start = 0;
456 end = sc->sc_coord_readouts;
457 }
458
459 x = y = 0;
460 for (i = start; i < end; i++)
461 y += data[i];
462 y /= (end - start);
463
464 for (i = sc->sc_coord_readouts + 2 + start; i < sc->sc_coord_readouts + 2 + end; i++)
465 x += data[i];
466 x /= (end - start);
467
468 #ifdef DEBUG_TSC
469 device_printf(sc->sc_dev, "touchscreen x: %d, y: %d\n", x, y);
470 #endif
471
472 #ifdef EVDEV_SUPPORT
473 if ((sc->sc_x != x) || (sc->sc_y != y)) {
474 sc->sc_x = x;
475 sc->sc_y = y;
476 ti_adc_ev_report(sc);
477 }
478 #endif
479 }
480
481 static void
ti_adc_intr_locked(struct ti_adc_softc * sc,uint32_t status)482 ti_adc_intr_locked(struct ti_adc_softc *sc, uint32_t status)
483 {
484 /* Read the available data. */
485 if (status & ADC_IRQ_FIFO0_THRES)
486 ti_adc_read_data(sc);
487 }
488
489 static void
ti_adc_tsc_intr_locked(struct ti_adc_softc * sc,uint32_t status)490 ti_adc_tsc_intr_locked(struct ti_adc_softc *sc, uint32_t status)
491 {
492 /* Read the available data. */
493 if (status & ADC_IRQ_FIFO1_THRES)
494 ti_adc_tsc_read_data(sc);
495
496 }
497
498 static void
ti_adc_intr(void * arg)499 ti_adc_intr(void *arg)
500 {
501 struct ti_adc_softc *sc;
502 uint32_t status, rawstatus;
503
504 sc = (struct ti_adc_softc *)arg;
505
506 TI_ADC_LOCK(sc);
507
508 rawstatus = ADC_READ4(sc, ADC_IRQSTATUS_RAW);
509 status = ADC_READ4(sc, ADC_IRQSTATUS);
510
511 if (rawstatus & ADC_IRQ_HW_PEN_ASYNC) {
512 sc->sc_pen_down = 1;
513 status |= ADC_IRQ_HW_PEN_ASYNC;
514 ADC_WRITE4(sc, ADC_IRQENABLE_CLR,
515 ADC_IRQ_HW_PEN_ASYNC);
516 #ifdef EVDEV_SUPPORT
517 ti_adc_ev_report(sc);
518 #endif
519 }
520
521 if (rawstatus & ADC_IRQ_PEN_UP) {
522 sc->sc_pen_down = 0;
523 status |= ADC_IRQ_PEN_UP;
524 #ifdef EVDEV_SUPPORT
525 ti_adc_ev_report(sc);
526 #endif
527 }
528
529 if (status & ADC_IRQ_FIFO0_THRES)
530 ti_adc_intr_locked(sc, status);
531
532 if (status & ADC_IRQ_FIFO1_THRES)
533 ti_adc_tsc_intr_locked(sc, status);
534
535 if (status) {
536 /* ACK the interrupt. */
537 ADC_WRITE4(sc, ADC_IRQSTATUS, status);
538 }
539
540 /* Start the next conversion ? */
541 if (status & ADC_IRQ_END_OF_SEQ)
542 ti_adc_setup(sc);
543
544 TI_ADC_UNLOCK(sc);
545 }
546
547 static void
ti_adc_sysctl_init(struct ti_adc_softc * sc)548 ti_adc_sysctl_init(struct ti_adc_softc *sc)
549 {
550 char pinbuf[3];
551 struct sysctl_ctx_list *ctx;
552 struct sysctl_oid *tree_node, *inp_node, *inpN_node;
553 struct sysctl_oid_list *tree, *inp_tree, *inpN_tree;
554 int ain, i;
555
556 /*
557 * Add per-pin sysctl tree/handlers.
558 */
559 ctx = device_get_sysctl_ctx(sc->sc_dev);
560 tree_node = device_get_sysctl_tree(sc->sc_dev);
561 tree = SYSCTL_CHILDREN(tree_node);
562 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "clockdiv",
563 CTLFLAG_RW | CTLTYPE_UINT | CTLFLAG_NEEDGIANT, sc, 0,
564 ti_adc_clockdiv_proc, "IU", "ADC clock prescaler");
565 inp_node = SYSCTL_ADD_NODE(ctx, tree, OID_AUTO, "ain",
566 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "ADC inputs");
567 inp_tree = SYSCTL_CHILDREN(inp_node);
568
569 for (i = 0; i < sc->sc_adc_nchannels; i++) {
570 ain = sc->sc_adc_channels[i];
571
572 snprintf(pinbuf, sizeof(pinbuf), "%d", ain);
573 inpN_node = SYSCTL_ADD_NODE(ctx, inp_tree, OID_AUTO, pinbuf,
574 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "ADC input");
575 inpN_tree = SYSCTL_CHILDREN(inpN_node);
576
577 SYSCTL_ADD_PROC(ctx, inpN_tree, OID_AUTO, "enable",
578 CTLFLAG_RW | CTLTYPE_UINT | CTLFLAG_NEEDGIANT,
579 &ti_adc_inputs[ain], 0,
580 ti_adc_enable_proc, "IU", "Enable ADC input");
581 SYSCTL_ADD_PROC(ctx, inpN_tree, OID_AUTO, "open_delay",
582 CTLFLAG_RW | CTLTYPE_UINT | CTLFLAG_NEEDGIANT,
583 &ti_adc_inputs[ain], 0,
584 ti_adc_open_delay_proc, "IU", "ADC open delay");
585 SYSCTL_ADD_PROC(ctx, inpN_tree, OID_AUTO, "samples_avg",
586 CTLFLAG_RW | CTLTYPE_UINT | CTLFLAG_NEEDGIANT,
587 &ti_adc_inputs[ain], 0,
588 ti_adc_samples_avg_proc, "IU", "ADC samples average");
589 SYSCTL_ADD_INT(ctx, inpN_tree, OID_AUTO, "input",
590 CTLFLAG_RD, &ti_adc_inputs[ain].value, 0,
591 "Converted raw value for the ADC input");
592 }
593 }
594
595 static void
ti_adc_inputs_init(struct ti_adc_softc * sc)596 ti_adc_inputs_init(struct ti_adc_softc *sc)
597 {
598 int ain, i;
599 struct ti_adc_input *input;
600
601 TI_ADC_LOCK(sc);
602 for (i = 0; i < sc->sc_adc_nchannels; i++) {
603 ain = sc->sc_adc_channels[i];
604 input = &ti_adc_inputs[ain];
605 input->sc = sc;
606 input->input = ain;
607 input->value = 0;
608 input->enable = 0;
609 input->samples = 0;
610 ti_adc_input_setup(sc, ain);
611 }
612 TI_ADC_UNLOCK(sc);
613 }
614
615 static void
ti_adc_tsc_init(struct ti_adc_softc * sc)616 ti_adc_tsc_init(struct ti_adc_softc *sc)
617 {
618 int i, start_step, end_step;
619 uint32_t stepconfig, val;
620
621 TI_ADC_LOCK(sc);
622
623 /* X coordinates */
624 stepconfig = ADC_STEP_FIFO1 | (4 << ADC_STEP_AVG_SHIFT) |
625 ADC_STEP_MODE_HW_ONESHOT | sc->sc_xp_bit;
626 if (sc->sc_tsc_wires == 4)
627 stepconfig |= ADC_STEP_INP(sc->sc_yp_inp) | sc->sc_xn_bit;
628 else if (sc->sc_tsc_wires == 5)
629 stepconfig |= ADC_STEP_INP(4) |
630 sc->sc_xn_bit | sc->sc_yn_bit | sc->sc_yp_bit;
631 else if (sc->sc_tsc_wires == 8)
632 stepconfig |= ADC_STEP_INP(sc->sc_yp_inp) | sc->sc_xn_bit;
633
634 start_step = ADC_STEPS - sc->sc_coord_readouts + 1;
635 end_step = start_step + sc->sc_coord_readouts - 1;
636 for (i = start_step; i <= end_step; i++) {
637 ADC_WRITE4(sc, ADC_STEPCFG(i), stepconfig);
638 ADC_WRITE4(sc, ADC_STEPDLY(i), STEPDLY_OPEN);
639 }
640
641 /* Y coordinates */
642 stepconfig = ADC_STEP_FIFO1 | (4 << ADC_STEP_AVG_SHIFT) |
643 ADC_STEP_MODE_HW_ONESHOT | sc->sc_yn_bit |
644 ADC_STEP_INM(8);
645 if (sc->sc_tsc_wires == 4)
646 stepconfig |= ADC_STEP_INP(sc->sc_xp_inp) | sc->sc_yp_bit;
647 else if (sc->sc_tsc_wires == 5)
648 stepconfig |= ADC_STEP_INP(4) |
649 sc->sc_xp_bit | sc->sc_xn_bit | sc->sc_yp_bit;
650 else if (sc->sc_tsc_wires == 8)
651 stepconfig |= ADC_STEP_INP(sc->sc_xp_inp) | sc->sc_yp_bit;
652
653 start_step = ADC_STEPS - (sc->sc_coord_readouts*2 + 2) + 1;
654 end_step = start_step + sc->sc_coord_readouts - 1;
655 for (i = start_step; i <= end_step; i++) {
656 ADC_WRITE4(sc, ADC_STEPCFG(i), stepconfig);
657 ADC_WRITE4(sc, ADC_STEPDLY(i), STEPDLY_OPEN);
658 }
659
660 /* Charge config */
661 val = ADC_READ4(sc, ADC_IDLECONFIG);
662 ADC_WRITE4(sc, ADC_TC_CHARGE_STEPCONFIG, val);
663 ADC_WRITE4(sc, ADC_TC_CHARGE_DELAY, sc->sc_charge_delay);
664
665 /* 2 steps for Z */
666 start_step = ADC_STEPS - (sc->sc_coord_readouts + 2) + 1;
667 stepconfig = ADC_STEP_FIFO1 | (4 << ADC_STEP_AVG_SHIFT) |
668 ADC_STEP_MODE_HW_ONESHOT | sc->sc_yp_bit |
669 sc->sc_xn_bit | ADC_STEP_INP(sc->sc_xp_inp) |
670 ADC_STEP_INM(8);
671 ADC_WRITE4(sc, ADC_STEPCFG(start_step), stepconfig);
672 ADC_WRITE4(sc, ADC_STEPDLY(start_step), STEPDLY_OPEN);
673 start_step++;
674 stepconfig |= ADC_STEP_INP(sc->sc_yn_inp);
675 ADC_WRITE4(sc, ADC_STEPCFG(start_step), stepconfig);
676 ADC_WRITE4(sc, ADC_STEPDLY(start_step), STEPDLY_OPEN);
677
678 ADC_WRITE4(sc, ADC_FIFO1THRESHOLD, (sc->sc_coord_readouts*2 + 2) - 1);
679
680 sc->sc_tsc_enabled = 1;
681 start_step = ADC_STEPS - (sc->sc_coord_readouts*2 + 2) + 1;
682 end_step = ADC_STEPS;
683 for (i = start_step; i <= end_step; i++) {
684 sc->sc_tsc_enabled |= (1 << i);
685 }
686
687 TI_ADC_UNLOCK(sc);
688 }
689
690 static void
ti_adc_idlestep_init(struct ti_adc_softc * sc)691 ti_adc_idlestep_init(struct ti_adc_softc *sc)
692 {
693 uint32_t val;
694
695 val = ADC_STEP_YNN_SW | ADC_STEP_INM(8) | ADC_STEP_INP(8) | ADC_STEP_YPN_SW;
696
697 ADC_WRITE4(sc, ADC_IDLECONFIG, val);
698 }
699
700 static int
ti_adc_config_wires(struct ti_adc_softc * sc,int * wire_configs,int nwire_configs)701 ti_adc_config_wires(struct ti_adc_softc *sc, int *wire_configs, int nwire_configs)
702 {
703 int i;
704 int wire, ai;
705
706 for (i = 0; i < nwire_configs; i++) {
707 wire = wire_configs[i] & 0xf;
708 ai = (wire_configs[i] >> 4) & 0xf;
709 switch (wire) {
710 case ORDER_XP:
711 sc->sc_xp_bit = ADC_STEP_XPP_SW;
712 sc->sc_xp_inp = ai;
713 break;
714 case ORDER_XN:
715 sc->sc_xn_bit = ADC_STEP_XNN_SW;
716 sc->sc_xn_inp = ai;
717 break;
718 case ORDER_YP:
719 sc->sc_yp_bit = ADC_STEP_YPP_SW;
720 sc->sc_yp_inp = ai;
721 break;
722 case ORDER_YN:
723 sc->sc_yn_bit = ADC_STEP_YNN_SW;
724 sc->sc_yn_inp = ai;
725 break;
726 default:
727 device_printf(sc->sc_dev, "Invalid wire config\n");
728 return (-1);
729 }
730 }
731 return (0);
732 }
733
734 static int
ti_adc_probe(device_t dev)735 ti_adc_probe(device_t dev)
736 {
737
738 if (!ofw_bus_is_compatible(dev, "ti,am3359-tscadc"))
739 return (ENXIO);
740 device_set_desc(dev, "TI ADC controller");
741
742 return (BUS_PROBE_DEFAULT);
743 }
744
745 static int
ti_adc_attach(device_t dev)746 ti_adc_attach(device_t dev)
747 {
748 int err, rid, i;
749 struct ti_adc_softc *sc;
750 uint32_t rev, reg;
751 phandle_t node, child;
752 pcell_t cell;
753 int *channels;
754 int nwire_configs;
755 int *wire_configs;
756
757 sc = device_get_softc(dev);
758 sc->sc_dev = dev;
759
760 node = ofw_bus_get_node(dev);
761
762 sc->sc_tsc_wires = 0;
763 sc->sc_coord_readouts = 1;
764 sc->sc_x_plate_resistance = 0;
765 sc->sc_charge_delay = DEFAULT_CHARGE_DELAY;
766 /* Read "tsc" node properties */
767 child = ofw_bus_find_child(node, "tsc");
768 if (child != 0 && OF_hasprop(child, "ti,wires")) {
769 if ((OF_getencprop(child, "ti,wires", &cell, sizeof(cell))) > 0)
770 sc->sc_tsc_wires = cell;
771 if ((OF_getencprop(child, "ti,coordinate-readouts", &cell,
772 sizeof(cell))) > 0)
773 sc->sc_coord_readouts = cell;
774 if ((OF_getencprop(child, "ti,x-plate-resistance", &cell,
775 sizeof(cell))) > 0)
776 sc->sc_x_plate_resistance = cell;
777 if ((OF_getencprop(child, "ti,charge-delay", &cell,
778 sizeof(cell))) > 0)
779 sc->sc_charge_delay = cell;
780 nwire_configs = OF_getencprop_alloc_multi(child,
781 "ti,wire-config", sizeof(*wire_configs),
782 (void **)&wire_configs);
783 if (nwire_configs != sc->sc_tsc_wires) {
784 device_printf(sc->sc_dev,
785 "invalid number of ti,wire-config: %d (should be %d)\n",
786 nwire_configs, sc->sc_tsc_wires);
787 OF_prop_free(wire_configs);
788 return (EINVAL);
789 }
790 err = ti_adc_config_wires(sc, wire_configs, nwire_configs);
791 OF_prop_free(wire_configs);
792 if (err)
793 return (EINVAL);
794 }
795
796 /* Read "adc" node properties */
797 child = ofw_bus_find_child(node, "adc");
798 if (child != 0) {
799 sc->sc_adc_nchannels = OF_getencprop_alloc_multi(child,
800 "ti,adc-channels", sizeof(*channels), (void **)&channels);
801 if (sc->sc_adc_nchannels > 0) {
802 for (i = 0; i < sc->sc_adc_nchannels; i++)
803 sc->sc_adc_channels[i] = channels[i];
804 OF_prop_free(channels);
805 }
806 }
807
808 /* Sanity check FDT data */
809 if (sc->sc_tsc_wires + sc->sc_adc_nchannels > TI_ADC_NPINS) {
810 device_printf(dev, "total number of channels (%d) is larger than %d\n",
811 sc->sc_tsc_wires + sc->sc_adc_nchannels, TI_ADC_NPINS);
812 return (ENXIO);
813 }
814
815 rid = 0;
816 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
817 RF_ACTIVE);
818 if (!sc->sc_mem_res) {
819 device_printf(dev, "cannot allocate memory window\n");
820 return (ENXIO);
821 }
822
823 /* Activate the ADC_TSC module. */
824 err = ti_sysc_clock_enable(device_get_parent(dev));
825 if (err)
826 return (err);
827
828 rid = 0;
829 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
830 RF_ACTIVE);
831 if (!sc->sc_irq_res) {
832 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
833 device_printf(dev, "cannot allocate interrupt\n");
834 return (ENXIO);
835 }
836
837 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
838 NULL, ti_adc_intr, sc, &sc->sc_intrhand) != 0) {
839 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
840 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
841 device_printf(dev, "Unable to setup the irq handler.\n");
842 return (ENXIO);
843 }
844
845 /* Check the ADC revision. */
846 rev = ADC_READ4(sc, ti_sysc_get_rev_address_offset_host(device_get_parent(dev)));
847 device_printf(dev,
848 "scheme: %#x func: %#x rtl: %d rev: %d.%d custom rev: %d\n",
849 (rev & ADC_REV_SCHEME_MSK) >> ADC_REV_SCHEME_SHIFT,
850 (rev & ADC_REV_FUNC_MSK) >> ADC_REV_FUNC_SHIFT,
851 (rev & ADC_REV_RTL_MSK) >> ADC_REV_RTL_SHIFT,
852 (rev & ADC_REV_MAJOR_MSK) >> ADC_REV_MAJOR_SHIFT,
853 rev & ADC_REV_MINOR_MSK,
854 (rev & ADC_REV_CUSTOM_MSK) >> ADC_REV_CUSTOM_SHIFT);
855
856 reg = ADC_READ4(sc, ADC_CTRL);
857 ADC_WRITE4(sc, ADC_CTRL, reg | ADC_CTRL_STEP_WP | ADC_CTRL_STEP_ID);
858
859 /*
860 * Set the ADC prescaler to 2400 if touchscreen is not enabled
861 * and to 24 if it is. This sets the ADC clock to ~10Khz and
862 * ~1Mhz respectively (CLK_M_OSC / prescaler).
863 */
864 if (sc->sc_tsc_wires)
865 ADC_WRITE4(sc, ADC_CLKDIV, 24 - 1);
866 else
867 ADC_WRITE4(sc, ADC_CLKDIV, 2400 - 1);
868
869 TI_ADC_LOCK_INIT(sc);
870
871 ti_adc_idlestep_init(sc);
872 ti_adc_inputs_init(sc);
873 ti_adc_sysctl_init(sc);
874 ti_adc_tsc_init(sc);
875
876 TI_ADC_LOCK(sc);
877 ti_adc_setup(sc);
878 TI_ADC_UNLOCK(sc);
879
880 #ifdef EVDEV_SUPPORT
881 if (sc->sc_tsc_wires > 0) {
882 sc->sc_evdev = evdev_alloc();
883 evdev_set_name(sc->sc_evdev, device_get_desc(dev));
884 evdev_set_phys(sc->sc_evdev, device_get_nameunit(dev));
885 evdev_set_id(sc->sc_evdev, BUS_VIRTUAL, 0, 0, 0);
886 evdev_support_prop(sc->sc_evdev, INPUT_PROP_DIRECT);
887 evdev_support_event(sc->sc_evdev, EV_SYN);
888 evdev_support_event(sc->sc_evdev, EV_ABS);
889 evdev_support_event(sc->sc_evdev, EV_KEY);
890
891 evdev_support_abs(sc->sc_evdev, ABS_X, 0,
892 ADC_MAX_VALUE, 0, 0, 0);
893 evdev_support_abs(sc->sc_evdev, ABS_Y, 0,
894 ADC_MAX_VALUE, 0, 0, 0);
895
896 evdev_support_key(sc->sc_evdev, BTN_TOUCH);
897
898 err = evdev_register(sc->sc_evdev);
899 if (err) {
900 device_printf(dev,
901 "failed to register evdev: error=%d\n", err);
902 ti_adc_detach(dev);
903 return (err);
904 }
905
906 sc->sc_pen_down = 0;
907 sc->sc_x = -1;
908 sc->sc_y = -1;
909 }
910 #endif /* EVDEV */
911
912 return (0);
913 }
914
915 static int
ti_adc_detach(device_t dev)916 ti_adc_detach(device_t dev)
917 {
918 struct ti_adc_softc *sc;
919
920 sc = device_get_softc(dev);
921
922 /* Turn off the ADC. */
923 TI_ADC_LOCK(sc);
924 ti_adc_reset(sc);
925 ti_adc_setup(sc);
926
927 #ifdef EVDEV_SUPPORT
928 evdev_free(sc->sc_evdev);
929 #endif
930
931 TI_ADC_UNLOCK(sc);
932
933 TI_ADC_LOCK_DESTROY(sc);
934
935 if (sc->sc_intrhand)
936 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand);
937 if (sc->sc_irq_res)
938 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
939 if (sc->sc_mem_res)
940 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
941
942 return (bus_generic_detach(dev));
943 }
944
945 static device_method_t ti_adc_methods[] = {
946 DEVMETHOD(device_probe, ti_adc_probe),
947 DEVMETHOD(device_attach, ti_adc_attach),
948 DEVMETHOD(device_detach, ti_adc_detach),
949
950 DEVMETHOD_END
951 };
952
953 static driver_t ti_adc_driver = {
954 "ti_adc",
955 ti_adc_methods,
956 sizeof(struct ti_adc_softc),
957 };
958
959 static devclass_t ti_adc_devclass;
960
961 DRIVER_MODULE(ti_adc, simplebus, ti_adc_driver, ti_adc_devclass, 0, 0);
962 MODULE_VERSION(ti_adc, 1);
963 MODULE_DEPEND(ti_adc, simplebus, 1, 1, 1);
964 MODULE_DEPEND(ti_adc, ti_sysc, 1, 1, 1);
965 #ifdef EVDEV_SUPPORT
966 MODULE_DEPEND(ti_adc, evdev, 1, 1, 1);
967 #endif
968