1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2013 Thomas Skibo
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 /*
30 * A GPIO driver for Xilinx Zynq-7000.
31 *
32 * The GPIO peripheral on Zynq allows controlling 114 general purpose I/Os.
33 *
34 * Pins 53-0 are sent to the MIO. Any MIO pins not used by a PS peripheral are
35 * available as a GPIO pin. Pins 64-127 are sent to the PL (FPGA) section of
36 * Zynq as EMIO signals.
37 *
38 * The hardware provides a way to use IOs as interrupt sources but the
39 * gpio framework doesn't seem to have hooks for this.
40 *
41 * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual.
42 * (v1.4) November 16, 2012. Xilinx doc UG585. GPIO is covered in
43 * chater 14. Register definitions are in appendix B.19.
44 */
45
46 #include <sys/cdefs.h>
47 #include <sys/param.h>
48 #include <sys/systm.h>
49 #include <sys/conf.h>
50 #include <sys/bus.h>
51 #include <sys/kernel.h>
52 #include <sys/module.h>
53 #include <sys/lock.h>
54 #include <sys/mutex.h>
55 #include <sys/resource.h>
56 #include <sys/rman.h>
57 #include <sys/gpio.h>
58
59 #include <machine/bus.h>
60 #include <machine/resource.h>
61 #include <machine/stdarg.h>
62
63 #include <dev/gpio/gpiobusvar.h>
64 #include <dev/ofw/ofw_bus.h>
65 #include <dev/ofw/ofw_bus_subr.h>
66
67 #include "gpio_if.h"
68
69 #define NUMBANKS 4
70 #define MAXPIN (32*NUMBANKS)
71
72 #define MIO_PIN 0 /* pins 0-53 go to MIO */
73 #define NUM_MIO_PINS 54
74 #define EMIO_PIN 64 /* pins 64-127 go to PL */
75 #define NUM_EMIO_PINS 64
76
77 #define VALID_PIN(u) (((u) >= MIO_PIN && (u) < MIO_PIN + NUM_MIO_PINS) || \
78 ((u) >= EMIO_PIN && (u) < EMIO_PIN + NUM_EMIO_PINS))
79
80 #define ZGPIO_LOCK(sc) mtx_lock(&(sc)->sc_mtx)
81 #define ZGPIO_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx)
82 #define ZGPIO_LOCK_INIT(sc) \
83 mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->dev), \
84 "gpio", MTX_DEF)
85 #define ZGPIO_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx);
86
87 struct zy7_gpio_softc {
88 device_t dev;
89 device_t busdev;
90 struct mtx sc_mtx;
91 struct resource *mem_res; /* Memory resource */
92 };
93
94 #define WR4(sc, off, val) bus_write_4((sc)->mem_res, (off), (val))
95 #define RD4(sc, off) bus_read_4((sc)->mem_res, (off))
96
97 /* Xilinx Zynq-7000 GPIO register definitions:
98 */
99 #define ZY7_GPIO_MASK_DATA_LSW(b) (0x0000+8*(b)) /* maskable wr lo */
100 #define ZY7_GPIO_MASK_DATA_MSW(b) (0x0004+8*(b)) /* maskable wr hi */
101 #define ZY7_GPIO_DATA(b) (0x0040+4*(b)) /* in/out data */
102 #define ZY7_GPIO_DATA_RO(b) (0x0060+4*(b)) /* input data */
103
104 #define ZY7_GPIO_DIRM(b) (0x0204+0x40*(b)) /* direction mode */
105 #define ZY7_GPIO_OEN(b) (0x0208+0x40*(b)) /* output enable */
106 #define ZY7_GPIO_INT_MASK(b) (0x020c+0x40*(b)) /* int mask */
107 #define ZY7_GPIO_INT_EN(b) (0x0210+0x40*(b)) /* int enable */
108 #define ZY7_GPIO_INT_DIS(b) (0x0214+0x40*(b)) /* int disable */
109 #define ZY7_GPIO_INT_STAT(b) (0x0218+0x40*(b)) /* int status */
110 #define ZY7_GPIO_INT_TYPE(b) (0x021c+0x40*(b)) /* int type */
111 #define ZY7_GPIO_INT_POLARITY(b) (0x0220+0x40*(b)) /* int polarity */
112 #define ZY7_GPIO_INT_ANY(b) (0x0224+0x40*(b)) /* any edge */
113
114 static device_t
zy7_gpio_get_bus(device_t dev)115 zy7_gpio_get_bus(device_t dev)
116 {
117 struct zy7_gpio_softc *sc;
118
119 sc = device_get_softc(dev);
120
121 return (sc->busdev);
122 }
123
124 static int
zy7_gpio_pin_max(device_t dev,int * maxpin)125 zy7_gpio_pin_max(device_t dev, int *maxpin)
126 {
127
128 *maxpin = MAXPIN;
129 return (0);
130 }
131
132 /* Get a specific pin's capabilities. */
133 static int
zy7_gpio_pin_getcaps(device_t dev,uint32_t pin,uint32_t * caps)134 zy7_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
135 {
136
137 if (!VALID_PIN(pin))
138 return (EINVAL);
139
140 *caps = (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_TRISTATE);
141
142 return (0);
143 }
144
145 /* Get a specific pin's name. */
146 static int
zy7_gpio_pin_getname(device_t dev,uint32_t pin,char * name)147 zy7_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
148 {
149
150 if (!VALID_PIN(pin))
151 return (EINVAL);
152
153 if (pin < NUM_MIO_PINS) {
154 snprintf(name, GPIOMAXNAME, "MIO_%d", pin);
155 name[GPIOMAXNAME - 1] = '\0';
156 } else {
157 snprintf(name, GPIOMAXNAME, "EMIO_%d", pin - EMIO_PIN);
158 name[GPIOMAXNAME - 1] = '\0';
159 }
160
161 return (0);
162 }
163
164 /* Get a specific pin's current in/out/tri state. */
165 static int
zy7_gpio_pin_getflags(device_t dev,uint32_t pin,uint32_t * flags)166 zy7_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
167 {
168 struct zy7_gpio_softc *sc = device_get_softc(dev);
169
170 if (!VALID_PIN(pin))
171 return (EINVAL);
172
173 ZGPIO_LOCK(sc);
174
175 if ((RD4(sc, ZY7_GPIO_DIRM(pin >> 5)) & (1 << (pin & 31))) != 0) {
176 /* output */
177 if ((RD4(sc, ZY7_GPIO_OEN(pin >> 5)) & (1 << (pin & 31))) == 0)
178 *flags = (GPIO_PIN_OUTPUT | GPIO_PIN_TRISTATE);
179 else
180 *flags = GPIO_PIN_OUTPUT;
181 } else
182 /* input */
183 *flags = GPIO_PIN_INPUT;
184
185 ZGPIO_UNLOCK(sc);
186
187 return (0);
188 }
189
190 /* Set a specific pin's in/out/tri state. */
191 static int
zy7_gpio_pin_setflags(device_t dev,uint32_t pin,uint32_t flags)192 zy7_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
193 {
194 struct zy7_gpio_softc *sc = device_get_softc(dev);
195
196 if (!VALID_PIN(pin))
197 return (EINVAL);
198
199 ZGPIO_LOCK(sc);
200
201 if ((flags & GPIO_PIN_OUTPUT) != 0) {
202 /* Output. Set or reset OEN too. */
203 WR4(sc, ZY7_GPIO_DIRM(pin >> 5),
204 RD4(sc, ZY7_GPIO_DIRM(pin >> 5)) | (1 << (pin & 31)));
205
206 if ((flags & GPIO_PIN_TRISTATE) != 0)
207 WR4(sc, ZY7_GPIO_OEN(pin >> 5),
208 RD4(sc, ZY7_GPIO_OEN(pin >> 5)) &
209 ~(1 << (pin & 31)));
210 else
211 WR4(sc, ZY7_GPIO_OEN(pin >> 5),
212 RD4(sc, ZY7_GPIO_OEN(pin >> 5)) |
213 (1 << (pin & 31)));
214 } else {
215 /* Input. Turn off OEN. */
216 WR4(sc, ZY7_GPIO_DIRM(pin >> 5),
217 RD4(sc, ZY7_GPIO_DIRM(pin >> 5)) & ~(1 << (pin & 31)));
218 WR4(sc, ZY7_GPIO_OEN(pin >> 5),
219 RD4(sc, ZY7_GPIO_OEN(pin >> 5)) & ~(1 << (pin & 31)));
220 }
221
222 ZGPIO_UNLOCK(sc);
223
224 return (0);
225 }
226
227 /* Set a specific output pin's value. */
228 static int
zy7_gpio_pin_set(device_t dev,uint32_t pin,unsigned int value)229 zy7_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
230 {
231 struct zy7_gpio_softc *sc = device_get_softc(dev);
232
233 if (!VALID_PIN(pin) || value > 1)
234 return (EINVAL);
235
236 /* Fancy register tricks allow atomic set or reset. */
237 if ((pin & 16) != 0)
238 WR4(sc, ZY7_GPIO_MASK_DATA_MSW(pin >> 5),
239 (0xffff0000 ^ (0x10000 << (pin & 15))) |
240 (value << (pin & 15)));
241 else
242 WR4(sc, ZY7_GPIO_MASK_DATA_LSW(pin >> 5),
243 (0xffff0000 ^ (0x10000 << (pin & 15))) |
244 (value << (pin & 15)));
245
246 return (0);
247 }
248
249 /* Get a specific pin's input value. */
250 static int
zy7_gpio_pin_get(device_t dev,uint32_t pin,unsigned int * value)251 zy7_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *value)
252 {
253 struct zy7_gpio_softc *sc = device_get_softc(dev);
254
255 if (!VALID_PIN(pin))
256 return (EINVAL);
257
258 *value = (RD4(sc, ZY7_GPIO_DATA_RO(pin >> 5)) >> (pin & 31)) & 1;
259
260 return (0);
261 }
262
263 /* Toggle a pin's output value. */
264 static int
zy7_gpio_pin_toggle(device_t dev,uint32_t pin)265 zy7_gpio_pin_toggle(device_t dev, uint32_t pin)
266 {
267 struct zy7_gpio_softc *sc = device_get_softc(dev);
268
269 if (!VALID_PIN(pin))
270 return (EINVAL);
271
272 ZGPIO_LOCK(sc);
273
274 WR4(sc, ZY7_GPIO_DATA(pin >> 5),
275 RD4(sc, ZY7_GPIO_DATA(pin >> 5)) ^ (1 << (pin & 31)));
276
277 ZGPIO_UNLOCK(sc);
278
279 return (0);
280 }
281
282 static int
zy7_gpio_probe(device_t dev)283 zy7_gpio_probe(device_t dev)
284 {
285
286 if (!ofw_bus_status_okay(dev))
287 return (ENXIO);
288
289 if (!ofw_bus_is_compatible(dev, "xlnx,zy7_gpio"))
290 return (ENXIO);
291
292 device_set_desc(dev, "Zynq-7000 GPIO driver");
293 return (0);
294 }
295
296 static int zy7_gpio_detach(device_t dev);
297
298 static int
zy7_gpio_attach(device_t dev)299 zy7_gpio_attach(device_t dev)
300 {
301 struct zy7_gpio_softc *sc = device_get_softc(dev);
302 int rid;
303
304 sc->dev = dev;
305
306 ZGPIO_LOCK_INIT(sc);
307
308 /* Allocate memory. */
309 rid = 0;
310 sc->mem_res = bus_alloc_resource_any(dev,
311 SYS_RES_MEMORY, &rid, RF_ACTIVE);
312 if (sc->mem_res == NULL) {
313 device_printf(dev, "Can't allocate memory for device");
314 zy7_gpio_detach(dev);
315 return (ENOMEM);
316 }
317
318 sc->busdev = gpiobus_attach_bus(dev);
319 if (sc->busdev == NULL) {
320 zy7_gpio_detach(dev);
321 return (ENOMEM);
322 }
323
324 return (0);
325 }
326
327 static int
zy7_gpio_detach(device_t dev)328 zy7_gpio_detach(device_t dev)
329 {
330 struct zy7_gpio_softc *sc = device_get_softc(dev);
331
332 gpiobus_detach_bus(dev);
333
334 if (sc->mem_res != NULL) {
335 /* Release memory resource. */
336 bus_release_resource(dev, SYS_RES_MEMORY,
337 rman_get_rid(sc->mem_res), sc->mem_res);
338 }
339
340 ZGPIO_LOCK_DESTROY(sc);
341
342 return (0);
343 }
344
345 static device_method_t zy7_gpio_methods[] = {
346 /* device_if */
347 DEVMETHOD(device_probe, zy7_gpio_probe),
348 DEVMETHOD(device_attach, zy7_gpio_attach),
349 DEVMETHOD(device_detach, zy7_gpio_detach),
350
351 /* GPIO protocol */
352 DEVMETHOD(gpio_get_bus, zy7_gpio_get_bus),
353 DEVMETHOD(gpio_pin_max, zy7_gpio_pin_max),
354 DEVMETHOD(gpio_pin_getname, zy7_gpio_pin_getname),
355 DEVMETHOD(gpio_pin_getflags, zy7_gpio_pin_getflags),
356 DEVMETHOD(gpio_pin_getcaps, zy7_gpio_pin_getcaps),
357 DEVMETHOD(gpio_pin_setflags, zy7_gpio_pin_setflags),
358 DEVMETHOD(gpio_pin_get, zy7_gpio_pin_get),
359 DEVMETHOD(gpio_pin_set, zy7_gpio_pin_set),
360 DEVMETHOD(gpio_pin_toggle, zy7_gpio_pin_toggle),
361
362 DEVMETHOD_END
363 };
364
365 static driver_t zy7_gpio_driver = {
366 "gpio",
367 zy7_gpio_methods,
368 sizeof(struct zy7_gpio_softc),
369 };
370 static devclass_t zy7_gpio_devclass;
371
372 DRIVER_MODULE(zy7_gpio, simplebus, zy7_gpio_driver, zy7_gpio_devclass, \
373 NULL, NULL);
374