1 /*-
2 * Copyright (c) 2013 Thomas Skibo. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 */
24
25 #include "opt_platform.h"
26
27 #include <sys/cdefs.h>
28 #include <sys/param.h>
29 #include <sys/systm.h>
30 #include <sys/bus.h>
31 #include <sys/lock.h>
32 #include <sys/mutex.h>
33 #include <sys/smp.h>
34
35 #include <vm/vm.h>
36 #include <vm/pmap.h>
37
38 #include <machine/cpu.h>
39 #include <machine/smp.h>
40 #include <machine/fdt.h>
41 #include <machine/intr.h>
42 #include <machine/platformvar.h>
43
44 #include <arm/xilinx/zy7_machdep.h>
45 #include <arm/xilinx/zy7_reg.h>
46 #include <arm/xilinx/zy7_slcr.h>
47
48 #define ZYNQ7_CPU1_ENTRY 0xfffffff0
49
50 #define SCU_CONTROL_REG 0xf8f00000
51 #define SCU_CONTROL_ENABLE 1
52 #define SCU_CONFIG_REG 0xf8f00004
53 #define SCU_CONFIG_N_CPUS_MASK 3
54
55 #define SLCR_PSS_IDCODE 0xf8000530
56
57 void
zynq7_mp_setmaxid(platform_t plat)58 zynq7_mp_setmaxid(platform_t plat)
59 {
60 bus_space_handle_t slcr_handle;
61 int device_id;
62 bus_space_handle_t scu_handle;
63
64 if (mp_ncpus != 0)
65 return;
66
67 /* Map in SLCR PSS_IDCODE register. */
68 if (bus_space_map(fdtbus_bs_tag, SLCR_PSS_IDCODE, 4, 0,
69 &slcr_handle) != 0)
70 panic("%s: Could not map SLCR IDCODE reg.\n", __func__);
71
72 device_id = bus_space_read_4(fdtbus_bs_tag, slcr_handle, 0) &
73 ZY7_SLCR_PSS_IDCODE_DEVICE_MASK;
74
75 bus_space_unmap(fdtbus_bs_tag, slcr_handle, 4);
76
77 /*
78 * Zynq XC7z0xxS single core chips indicate incorrect number of CPUs in
79 * SCU configuration register.
80 */
81 if (device_id == ZY7_SLCR_PSS_IDCODE_DEVICE_7Z007S ||
82 device_id == ZY7_SLCR_PSS_IDCODE_DEVICE_7Z012S ||
83 device_id == ZY7_SLCR_PSS_IDCODE_DEVICE_7Z014S) {
84 mp_maxid = 0;
85 mp_ncpus = 1;
86 return;
87 }
88
89 /* Map in SCU config register. */
90 if (bus_space_map(fdtbus_bs_tag, SCU_CONFIG_REG, 4, 0,
91 &scu_handle) != 0)
92 panic("zynq7_mp_setmaxid: Could not map SCU config reg.\n");
93
94 mp_maxid = bus_space_read_4(fdtbus_bs_tag, scu_handle, 0) &
95 SCU_CONFIG_N_CPUS_MASK;
96 mp_ncpus = mp_maxid + 1;
97
98 bus_space_unmap(fdtbus_bs_tag, scu_handle, 4);
99 }
100
101 void
zynq7_mp_start_ap(platform_t plat)102 zynq7_mp_start_ap(platform_t plat)
103 {
104 bus_space_handle_t scu_handle;
105 bus_space_handle_t ocm_handle;
106 uint32_t scu_ctrl;
107
108 /* Map in SCU control register. */
109 if (bus_space_map(fdtbus_bs_tag, SCU_CONTROL_REG, 4,
110 0, &scu_handle) != 0)
111 panic("%s: Could not map SCU control reg.\n", __func__);
112
113 /* Set SCU enable bit. */
114 scu_ctrl = bus_space_read_4(fdtbus_bs_tag, scu_handle, 0);
115 scu_ctrl |= SCU_CONTROL_ENABLE;
116 bus_space_write_4(fdtbus_bs_tag, scu_handle, 0, scu_ctrl);
117
118 bus_space_unmap(fdtbus_bs_tag, scu_handle, 4);
119
120 /* Map in magic location to give entry address to CPU1. */
121 if (bus_space_map(fdtbus_bs_tag, ZYNQ7_CPU1_ENTRY, 4,
122 0, &ocm_handle) != 0)
123 panic("%s: Could not map OCM\n", __func__);
124
125 /* Write start address for CPU1. */
126 bus_space_write_4(fdtbus_bs_tag, ocm_handle, 0,
127 pmap_kextract((vm_offset_t)mpentry));
128
129 bus_space_unmap(fdtbus_bs_tag, ocm_handle, 4);
130
131 /*
132 * The SCU is enabled above but I think the second CPU doesn't
133 * turn on filtering until after the wake-up below. I think that's why
134 * things don't work if I don't put these cache ops here. Also, the
135 * magic location, 0xfffffff0, isn't in the SCU's filtering range so it
136 * needs a write-back too.
137 */
138 dcache_wbinv_poc_all();
139
140 /* Wake up CPU1. */
141 dsb();
142 sev();
143 }
144