1 /*-
2 * Copyright (c) 1990 The Regents of the University of California.
3 * Copyright (c) 2014-2016 The FreeBSD Foundation
4 * All rights reserved.
5 *
6 * This code is derived from software contributed to Berkeley by
7 * William Jolitz.
8 *
9 * Portions of this software were developed by Andrew Turner
10 * under sponsorship from the FreeBSD Foundation
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. Neither the name of the University nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * SUCH DAMAGE.
35 *
36 * from: @(#)cpu.h 5.4 (Berkeley) 5/9/91
37 * from: FreeBSD: src/sys/i386/include/cpu.h,v 1.62 2001/06/29
38 */
39
40 #ifndef _MACHINE_CPU_H_
41 #define _MACHINE_CPU_H_
42
43 #if !defined(__ASSEMBLER__)
44 #include <machine/atomic.h>
45 #include <machine/frame.h>
46 #endif
47 #include <machine/armreg.h>
48
49 #define TRAPF_PC(tfp) ((tfp)->tf_elr)
50 #define TRAPF_USERMODE(tfp) (((tfp)->tf_spsr & PSR_M_MASK) == PSR_M_EL0t)
51
52 #define cpu_getstack(td) ((td)->td_frame->tf_sp)
53 #define cpu_setstack(td, sp) ((td)->td_frame->tf_sp = (sp))
54 #define cpu_spinwait() __asm __volatile("yield" ::: "memory")
55 #define cpu_lock_delay() DELAY(1)
56
57 /* Extract CPU affinity levels 0-3 */
58 #define CPU_AFF0(mpidr) (u_int)(((mpidr) >> 0) & 0xff)
59 #define CPU_AFF1(mpidr) (u_int)(((mpidr) >> 8) & 0xff)
60 #define CPU_AFF2(mpidr) (u_int)(((mpidr) >> 16) & 0xff)
61 #define CPU_AFF3(mpidr) (u_int)(((mpidr) >> 32) & 0xff)
62 #define CPU_AFF0_MASK 0xffUL
63 #define CPU_AFF1_MASK 0xff00UL
64 #define CPU_AFF2_MASK 0xff0000UL
65 #define CPU_AFF3_MASK 0xff00000000UL
66 #define CPU_AFF_MASK (CPU_AFF0_MASK | CPU_AFF1_MASK | \
67 CPU_AFF2_MASK| CPU_AFF3_MASK) /* Mask affinity fields in MPIDR_EL1 */
68
69 #ifdef _KERNEL
70
71 #define CPU_IMPL_ARM 0x41
72 #define CPU_IMPL_BROADCOM 0x42
73 #define CPU_IMPL_CAVIUM 0x43
74 #define CPU_IMPL_DEC 0x44
75 #define CPU_IMPL_FUJITSU 0x46
76 #define CPU_IMPL_INFINEON 0x49
77 #define CPU_IMPL_FREESCALE 0x4D
78 #define CPU_IMPL_NVIDIA 0x4E
79 #define CPU_IMPL_APM 0x50
80 #define CPU_IMPL_QUALCOMM 0x51
81 #define CPU_IMPL_MARVELL 0x56
82 #define CPU_IMPL_APPLE 0x61
83 #define CPU_IMPL_INTEL 0x69
84 #define CPU_IMPL_AMPERE 0xC0
85
86 /* ARM Part numbers */
87 #define CPU_PART_FOUNDATION 0xD00
88 #define CPU_PART_CORTEX_A34 0xD02
89 #define CPU_PART_CORTEX_A53 0xD03
90 #define CPU_PART_CORTEX_A35 0xD04
91 #define CPU_PART_CORTEX_A55 0xD05
92 #define CPU_PART_CORTEX_A65 0xD06
93 #define CPU_PART_CORTEX_A57 0xD07
94 #define CPU_PART_CORTEX_A72 0xD08
95 #define CPU_PART_CORTEX_A73 0xD09
96 #define CPU_PART_CORTEX_A75 0xD0A
97 #define CPU_PART_CORTEX_A76 0xD0B
98 #define CPU_PART_NEOVERSE_N1 0xD0C
99 #define CPU_PART_CORTEX_A77 0xD0D
100 #define CPU_PART_CORTEX_A76AE 0xD0E
101 #define CPU_PART_AEM_V8 0xD0F
102 #define CPU_PART_NEOVERSE_V1 0xD40
103 #define CPU_PART_CORTEX_A78 0xD41
104 #define CPU_PART_CORTEX_A65AE 0xD43
105 #define CPU_PART_CORTEX_X1 0xD44
106 #define CPU_PART_CORTEX_A510 0xD46
107 #define CPU_PART_CORTEX_A710 0xD47
108 #define CPU_PART_CORTEX_X2 0xD48
109 #define CPU_PART_NEOVERSE_N2 0xD49
110 #define CPU_PART_NEOVERSE_E1 0xD4A
111 #define CPU_PART_CORTEX_A78C 0xD4B
112 #define CPU_PART_CORTEX_X1C 0xD4C
113 #define CPU_PART_CORTEX_A715 0xD4D
114 #define CPU_PART_CORTEX_X3 0xD4E
115
116 /* Cavium Part numbers */
117 #define CPU_PART_THUNDERX 0x0A1
118 #define CPU_PART_THUNDERX_81XX 0x0A2
119 #define CPU_PART_THUNDERX_83XX 0x0A3
120 #define CPU_PART_THUNDERX2 0x0AF
121
122 #define CPU_REV_THUNDERX_1_0 0x00
123 #define CPU_REV_THUNDERX_1_1 0x01
124
125 #define CPU_REV_THUNDERX2_0 0x00
126
127 /* APM / Ampere Part Number */
128 #define CPU_PART_EMAG8180 0x000
129
130 #define CPU_IMPL(midr) (((midr) >> 24) & 0xff)
131 #define CPU_PART(midr) (((midr) >> 4) & 0xfff)
132 #define CPU_VAR(midr) (((midr) >> 20) & 0xf)
133 #define CPU_ARCH(midr) (((midr) >> 16) & 0xf)
134 #define CPU_REV(midr) (((midr) >> 0) & 0xf)
135
136 #define CPU_IMPL_TO_MIDR(val) (((val) & 0xff) << 24)
137 #define CPU_PART_TO_MIDR(val) (((val) & 0xfff) << 4)
138 #define CPU_VAR_TO_MIDR(val) (((val) & 0xf) << 20)
139 #define CPU_ARCH_TO_MIDR(val) (((val) & 0xf) << 16)
140 #define CPU_REV_TO_MIDR(val) (((val) & 0xf) << 0)
141
142 #define CPU_IMPL_MASK (0xff << 24)
143 #define CPU_PART_MASK (0xfff << 4)
144 #define CPU_VAR_MASK (0xf << 20)
145 #define CPU_ARCH_MASK (0xf << 16)
146 #define CPU_REV_MASK (0xf << 0)
147
148 #define CPU_ID_RAW(impl, part, var, rev) \
149 (CPU_IMPL_TO_MIDR((impl)) | \
150 CPU_PART_TO_MIDR((part)) | CPU_VAR_TO_MIDR((var)) | \
151 CPU_REV_TO_MIDR((rev)))
152
153 #define CPU_MATCH(mask, impl, part, var, rev) \
154 (((mask) & PCPU_GET(midr)) == \
155 ((mask) & CPU_ID_RAW((impl), (part), (var), (rev))))
156
157 #define CPU_MATCH_RAW(mask, devid) \
158 (((mask) & PCPU_GET(midr)) == ((mask) & (devid)))
159
160 /*
161 * Chip-specific errata. This defines are intended to be
162 * booleans used within if statements. When an appropriate
163 * kernel option is disabled, these defines must be defined
164 * as 0 to allow the compiler to remove a dead code thus
165 * produce better optimized kernel image.
166 */
167 /*
168 * Vendor: Cavium
169 * Chip: ThunderX
170 * Revision(s): Pass 1.0, Pass 1.1
171 */
172 #ifdef THUNDERX_PASS_1_1_ERRATA
173 #define CPU_MATCH_ERRATA_CAVIUM_THUNDERX_1_1 \
174 (CPU_MATCH(CPU_IMPL_MASK | CPU_PART_MASK | CPU_REV_MASK, \
175 CPU_IMPL_CAVIUM, CPU_PART_THUNDERX, 0, CPU_REV_THUNDERX_1_0) || \
176 CPU_MATCH(CPU_IMPL_MASK | CPU_PART_MASK | CPU_REV_MASK, \
177 CPU_IMPL_CAVIUM, CPU_PART_THUNDERX, 0, CPU_REV_THUNDERX_1_1))
178 #else
179 #define CPU_MATCH_ERRATA_CAVIUM_THUNDERX_1_1 0
180 #endif
181
182 #if !defined(__ASSEMBLER__)
183 extern char btext[];
184 extern char etext[];
185
186 extern uint64_t __cpu_affinity[];
187
188 void cpu_halt(void) __dead2;
189 void cpu_reset(void) __dead2;
190 void fork_trampoline(void);
191 void identify_cache(uint64_t);
192 void identify_cpu(u_int);
193 void install_cpu_errata(void);
194
195 /* Functions to read the sanitised view of the special registers */
196 void update_special_regs(u_int);
197 bool extract_user_id_field(u_int, u_int, uint8_t *);
198 bool get_kernel_reg(u_int, uint64_t *);
199
200 #define CPU_AFFINITY(cpu) __cpu_affinity[(cpu)]
201 #define CPU_CURRENT_SOCKET \
202 (CPU_AFF2(CPU_AFFINITY(PCPU_GET(cpuid))))
203
204 static __inline uint64_t
get_cyclecount(void)205 get_cyclecount(void)
206 {
207 uint64_t ret;
208
209 ret = READ_SPECIALREG(cntvct_el0);
210
211 return (ret);
212 }
213
214 #define ADDRESS_TRANSLATE_FUNC(stage) \
215 static inline uint64_t \
216 arm64_address_translate_ ##stage (uint64_t addr) \
217 { \
218 uint64_t ret; \
219 \
220 __asm __volatile( \
221 "at " __STRING(stage) ", %1 \n" \
222 "isb \n" \
223 "mrs %0, par_el1" : "=r"(ret) : "r"(addr)); \
224 \
225 return (ret); \
226 }
227
228 ADDRESS_TRANSLATE_FUNC(s1e0r)
229 ADDRESS_TRANSLATE_FUNC(s1e0w)
230 ADDRESS_TRANSLATE_FUNC(s1e1r)
231 ADDRESS_TRANSLATE_FUNC(s1e1w)
232
233 #endif /* !__ASSEMBLER__ */
234 #endif
235
236 #endif /* !_MACHINE_CPU_H_ */
237