1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2018 Emmanuel Vadot <manu@freebsd.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <sys/bus.h>
33 #include <sys/rman.h>
34 #include <sys/kernel.h>
35 #include <sys/module.h>
36 #include <machine/bus.h>
37
38 #include <dev/fdt/simplebus.h>
39
40 #include <dev/ofw/ofw_bus.h>
41 #include <dev/ofw/ofw_bus_subr.h>
42
43 #include <dev/extres/clk/clk.h>
44 #include <dev/extres/clk/clk_div.h>
45 #include <dev/extres/clk/clk_fixed.h>
46 #include <dev/extres/clk/clk_mux.h>
47
48 #include <arm64/rockchip/clk/rk_cru.h>
49
50 #include <dt-bindings/clock/rk3288-cru.h>
51
52 #define CRU_SOFTRST_SIZE 12
53
54 #define CRU_APLL_CON(x) (0x000 + (x) * 0x4)
55 #define CRU_DPLL_CON(x) (0x010 + (x) * 0x4)
56 #define CRU_CPLL_CON(x) (0x020 + (x) * 0x4)
57 #define CRU_GPLL_CON(x) (0x030 + (x) * 0x4)
58 #define CRU_NPLL_CON(x) (0x040 + (x) * 0x4)
59 #define CRU_MODE_CON 0x050
60 #define CRU_CLKSEL_CON(x) (0x060 + (x) * 0x4)
61 #define CRU_CLKGATE_CON(x) (0x160 + (x) * 0x4)
62 #define CRU_GLB_SRST_FST_VALUE 0x1b0
63 #define CRU_GLB_SRST_SND_VALUE 0x1b4
64 #define CRU_SOFTRST_CON(x) (0x1b8 + (x) * 0x4)
65 #define CRU_MISC_CON 0x1e8
66 #define CRU_GLB_CNT_TH 0x1ec
67 #define CRU_GLB_RST_CON 0x1f0
68 #define CRU_GLB_RST_ST 0x1f8
69 #define CRU_SDMMC_CON0 0x200
70 #define CRU_SDMMC_CON1 0x204
71 #define CRU_SDIO0_CON0 0x208
72 #define CRU_SDIO0_CON1 0x20c
73 #define CRU_SDIO1_CON0 0x210
74 #define CRU_SDIO1_CON1 0x214
75 #define CRU_EMMC_CON0 0x218
76 #define CRU_EMMC_CON1 0x21c
77
78 /* GATES */
79 #define GATE(_idx, _clkname, _pname, _o, _s) \
80 { \
81 .id = _idx, \
82 .name = _clkname, \
83 .parent_name = _pname, \
84 .offset = CRU_CLKGATE_CON(_o), \
85 .shift = _s, \
86 }
87
88 static struct rk_cru_gate rk3288_gates[] = {
89 /* CRU_CLKGATE_CON0 */
90 GATE(0, "sclk_acc_efuse", "xin24m", 0, 12),
91 GATE(0, "cpll_aclk_cpu", "cpll", 0, 11),
92 GATE(0, "gpll_aclk_cpu", "gpll", 0, 10),
93 GATE(0, "gpll_ddr", "gpll", 0, 9),
94 GATE(0, "dpll_ddr", "dpll", 0, 8),
95 GATE(0, "aclk_bus_2pmu", "aclk_cpu_pre", 0, 7),
96 GATE(PCLK_CPU, "pclk_cpu", "pclk_cpu_s", 0, 5),
97 GATE(HCLK_CPU, "hclk_cpu", "hclk_cpu_s", 0, 4),
98 GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_pre", 0, 3),
99 GATE(0, "gpll_core", "gpll", 0, 2),
100 GATE(0, "apll_core", "apll", 0, 1),
101
102
103 /* CRU_CLKGATE_CON1 */
104 GATE(0, "uart3_frac", "uart3_frac_s", 1, 15),
105 GATE(0, "uart3_src", "uart3_src_s", 1, 14),
106 GATE(0, "uart2_frac", "uart2_frac_s", 1, 13),
107 GATE(0, "uart2_src", "uart2_src_s", 1, 12),
108 GATE(0, "uart1_frac", "uart1_frac_s", 1, 11),
109 GATE(0, "uart1_src", "uart1_src_s", 1, 10),
110 GATE(0, "uart0_frac", "uart0_frac_s", 1, 9),
111 GATE(0, "uart0_src", "uart0_src_s", 1, 8),
112 GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 1, 5),
113 GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 1, 4),
114 GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 1, 3),
115 GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 1, 2),
116 GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 1, 1),
117 GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 1, 0),
118
119 /* CRU_CLKGATE_CON2 */
120 GATE(0, "uart4_frac", "uart4_frac_s", 2, 13),
121 GATE(0, "uart4_src", "uart4_src_s", 2, 12),
122 GATE(SCLK_SPI2, "sclk_spi2", "sclk_spi2_s", 2, 11),
123 GATE(SCLK_SPI1, "sclk_spi1", "sclk_spi1_s", 2, 10),
124 GATE(SCLK_SPI0, "sclk_spi0", "sclk_spi0_s", 2, 9),
125 GATE(SCLK_SARADC, "sclk_saradc", "sclk_saradc_s", 2, 8),
126 GATE(SCLK_TSADC, "sclk_tsadc", "sclk_tsadc_s", 2, 7),
127 GATE(0, "hsadc_src", "hsadc_src_s", 2, 6),
128 GATE(0, "mac_pll_src", "mac_pll_src_s", 2, 5),
129 GATE(PCLK_PERI, "pclk_peri", "pclk_peri_s", 2, 3),
130 GATE(HCLK_PERI, "hclk_peri", "hclk_peri_s", 2, 2),
131 GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", 2, 1),
132 GATE(0, "aclk_peri_src", "aclk_peri_src_s", 2, 0),
133
134 /* CRU_CLKGATE_CON3 */
135 GATE(SCLK_ISP_JPE, "sclk_isp_jpe", "sclk_isp_jpe_s", 3, 15),
136 GATE(SCLK_ISP, "sclk_isp", "sclk_isp_s", 3, 14),
137 GATE(SCLK_EDP, "sclk_edp", "sclk_edp_s", 3, 13),
138 GATE(SCLK_EDP_24M, "sclk_edp_24m", "sclk_edp_24m_s", 3, 12),
139 GATE(0, "aclk_vdpu", "aclk_vdpu_s", 3, 11),
140 GATE(0, "hclk_vcodec_pre", "hclk_vcodec_pre_s", 3, 10),
141 GATE(0, "aclk_vepu", "aclk_vepu_s", 3, 9),
142 GATE(0, "vip_src", "vip_src_s", 3, 7),
143 /* 6 - Not in TRM, sclk_hsicphy480m in Linux */
144 GATE(0, "aclk_rga_pre", "aclk_rga_pre_s", 3, 5),
145 GATE(SCLK_RGA, "sclk_rga", "sclk_rga_s", 3, 4),
146 GATE(DCLK_VOP1, "dclk_vop1", "dclk_vop1_s", 3, 3),
147 GATE(0, "aclk_vio1", "aclk_vio1_s", 3, 2),
148 GATE(DCLK_VOP0, "dclk_vop0", "dclk_vop0_s", 3, 1),
149 GATE(0, "aclk_vio0", "aclk_vio0_s", 3, 0),
150
151 /* CRU_CLKGATE_CON4 */
152 /* 15 - Test clock generator */
153 GATE(0, "jtag", "ext_jtag", 4, 14),
154 GATE(0, "sclk_ddrphy1", "ddrphy", 4, 13),
155 GATE(0, "sclk_ddrphy0", "ddrphy", 4, 12),
156 GATE(0, "sclk_tspout", "sclk_tspout_s", 4, 11),
157 GATE(0, "sclk_tsp", "sclk_tsp_s", 4, 10),
158 GATE(SCLK_SPDIF8CH, "sclk_spdif_8ch", "spdif_8ch_mux", 4, 9),
159 GATE(0, "spdif_8ch_frac", "spdif_8ch_frac_s", 4, 8),
160 GATE(0, "spdif_8ch_pre", "spdif_8ch_pre_s", 4, 7),
161 GATE(SCLK_SPDIF, "sclk_spdif", "spdif_mux", 4, 6),
162 GATE(0, "spdif_frac", "spdif_frac_s", 4, 5),
163 GATE(0, "spdif_pre", "spdif_pre_s", 4, 4),
164 GATE(SCLK_I2S0, "sclk_i2s0", "i2s_pre", 4, 3),
165 GATE(0, "i2s_frac", "i2s_frac_s", 4, 2),
166 GATE(0, "i2s_src", "i2s_src_s", 4, 1),
167 GATE(SCLK_I2S0_OUT, "i2s0_clkout", "i2s0_clkout_s", 4, 1),
168
169 /* CRU_CLKGATE_CON5 */
170 GATE(SCLK_MIPIDSI_24M, "sclk_mipidsi_24m", "xin24m", 5, 15),
171 GATE(SCLK_USBPHY480M_SRC, "usbphy480m_src", "usbphy480m_src_s", 5, 14),
172 GATE(SCLK_PS2C, "sclk_ps2c", "xin24m", 5, 13),
173 GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m", 5, 12),
174 GATE(SCLK_HDMI_CEC, "sclk_hdmi_cec", "xin32k", 5, 11),
175 GATE(SCLK_PVTM_GPU, "sclk_pvtm_gpu", "xin24m", 5, 10),
176 GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 5, 9),
177 GATE(0, "pclk_pd_pmu", "pclk_pd_pmu_s", 5, 8),
178 GATE(SCLK_GPU, "sclk_gpu", "sclk_gpu_s", 5, 7),
179 GATE(SCLK_NANDC1, "sclk_nandc1", "sclk_nandc1_s", 5, 6),
180 GATE(SCLK_NANDC0, "sclk_nandc0", "sclk_nandc0_s", 5, 5),
181 GATE(SCLK_CRYPTO, "crypto", "crypto_s", 5, 4),
182 GATE(SCLK_MACREF_OUT, "sclk_macref_out", "mac_clk", 5, 3),
183 GATE(SCLK_MACREF, "sclk_macref", "mac_clk", 5, 2),
184 GATE(SCLK_MAC_TX, "sclk_mac_tx", "mac_clk", 5, 1),
185 GATE(SCLK_MAC_RX, "sclk_mac_rx", "mac_clk", 5, 0),
186
187
188 /* CRU_CLKGATE_CON6 */
189 GATE(PCLK_I2C4, "pclk_i2c4", "pclk_peri", 6, 15),
190 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_peri", 6, 14),
191 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_peri", 6, 13),
192 GATE(PCLK_UART4, "pclk_uart4", "pclk_peri", 6, 12),
193 GATE(PCLK_UART3, "pclk_uart3", "pclk_peri", 6, 11),
194 GATE(PCLK_UART1, "pclk_uart1", "pclk_peri", 6, 9),
195 GATE(PCLK_UART0, "pclk_uart0", "pclk_peri", 6, 8),
196 GATE(PCLK_PS2C, "pclk_ps2c", "pclk_peri", 6, 7),
197 GATE(PCLK_SPI2, "pclk_spi2", "pclk_peri", 6, 6),
198 GATE(PCLK_SPI1, "pclk_spi1", "pclk_peri", 6, 5),
199 GATE(PCLK_SPI0, "pclk_spi0", "pclk_peri", 6, 4),
200 GATE(ACLK_DMAC2, "aclk_dmac2", "aclk_peri", 6, 3),
201 GATE(0, "aclk_peri_axi_matrix", "aclk_peri", 6, 2),
202 GATE(0, "pclk_peri_matrix", "pclk_peri", 6, 1),
203 GATE(0, "hclk_peri_matrix", "hclk_peri", 6, 0),
204
205
206 /* CRU_CLKGATE_CON7 */
207 GATE(HCLK_NANDC1, "hclk_nandc1", "hclk_peri", 7, 15),
208 GATE(HCLK_NANDC0, "hclk_nandc0", "hclk_peri", 7, 14),
209 GATE(0, "hclk_mem", "hclk_peri", 7, 13),
210 GATE(0, "hclk_emem", "hclk_peri", 7, 12),
211 GATE(0, "aclk_peri_niu", "aclk_peri", 7, 11),
212 GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", 7, 10),
213 GATE(0, "hclk_usb_peri", "hclk_peri", 7, 9),
214 /* 8 - Not in TRM - hclk_hsic in Linux */
215 GATE(HCLK_USBHOST1, "hclk_host1", "hclk_peri", 7, 7),
216 GATE(HCLK_USBHOST0, "hclk_host0", "hclk_peri", 7, 6),
217 GATE(0, "pmu_hclk_otg0", "hclk_peri", 7, 5),
218 GATE(HCLK_OTG0, "hclk_otg0", "hclk_peri", 7, 4),
219 GATE(PCLK_SIM, "pclk_sim", "pclk_peri", 7, 3),
220 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_peri", 7, 2),
221 GATE(PCLK_SARADC, "pclk_saradc", "pclk_peri", 7, 1),
222 GATE(PCLK_I2C5, "pclk_i2c5", "pclk_peri", 7, 0),
223
224 /* CRU_CLKGATE_CON8 */
225 GATE(ACLK_MMU, "aclk_mmu", "aclk_peri", 8, 12),
226 /* 11 - 9 27m_tsp, hsadc_1_tsp, hsadc_1_tsp */
227 GATE(HCLK_TSP, "hclk_tsp", "hclk_peri", 8, 8),
228 GATE(HCLK_HSADC, "hclk_hsadc", "hclk_peri", 8, 7),
229 GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 8, 6),
230 GATE(HCLK_SDIO1, "hclk_sdio1", "hclk_peri", 8, 5),
231 GATE(HCLK_SDIO0, "hclk_sdio0", "hclk_peri", 8, 4),
232 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 8, 3),
233 GATE(HCLK_GPS, "hclk_gps", "aclk_peri", 8, 2),
234 GATE(PCLK_GMAC, "pclk_gmac", "pclk_peri", 8, 1),
235 GATE(ACLK_GMAC, "aclk_gmac", "aclk_peri", 8, 0),
236
237 /* CRU_CLKGATE_CON9 */
238 GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 9, 1),
239 GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vcodec_pre", 9, 0),
240
241 /* CRU_CLKGATE_CON10 */
242 GATE(PCLK_PUBL0, "pclk_publ0", "pclk_cpu", 10, 15),
243 GATE(PCLK_DDRUPCTL0, "pclk_ddrupctl0", "pclk_cpu", 10, 14),
244 GATE(0, "aclk_strc_sys", "aclk_cpu", 10, 13),
245 GATE(ACLK_DMAC1, "aclk_dmac1", "aclk_cpu", 10, 12),
246 GATE(HCLK_SPDIF8CH, "hclk_spdif_8ch", "hclk_cpu", 10, 11),
247 GATE(HCLK_SPDIF, "hclk_spdif", "hclk_cpu", 10, 10),
248 GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", 10, 9),
249 GATE(HCLK_I2S0, "hclk_i2s0", "hclk_cpu", 10, 8),
250 GATE(0, "sclk_intmem2", "aclk_cpu", 10, 7),
251 GATE(0, "sclk_intmem1", "aclk_cpu", 10, 6),
252 GATE(0, "sclk_intmem0", "aclk_cpu", 10, 5),
253 GATE(0, "aclk_intmem", "aclk_cpu", 10, 4),
254 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_cpu", 10, 3),
255 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_cpu", 10, 2),
256 GATE(PCLK_TIMER, "pclk_timer", "pclk_cpu", 10, 1),
257 GATE(PCLK_PWM, "pclk_pwm", "pclk_cpu", 10, 0),
258
259 /* CRU_CLKGATE_CON11 */
260 GATE(PCLK_RKPWM, "pclk_rkpwm", "pclk_cpu", 11, 11),
261 GATE(PCLK_EFUSE256, "pclk_efuse_256", "pclk_cpu", 11, 10),
262 GATE(PCLK_UART2, "pclk_uart2", "pclk_cpu", 11, 9),
263 GATE(0, "aclk_ccp", "aclk_cpu", 11, 8),
264 GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_cpu", 11, 7),
265 GATE(ACLK_CRYPTO, "aclk_crypto", "aclk_cpu", 11, 6),
266 GATE(0, "nclk_ddrupctl1", "ddrphy", 11, 5),
267 GATE(0, "nclk_ddrupctl0", "ddrphy", 11, 4),
268 GATE(PCLK_TZPC, "pclk_tzpc", "pclk_cpu", 11, 3),
269 GATE(PCLK_EFUSE1024, "pclk_efuse_1024", "pclk_cpu", 11, 2),
270 GATE(PCLK_PUBL1, "pclk_publ1", "pclk_cpu", 11, 1),
271 GATE(PCLK_DDRUPCTL1, "pclk_ddrupctl1", "pclk_cpu", 11, 0),
272
273 /* CRU_CLKGATE_CON12 */
274 GATE(0, "pclk_core_niu", "pclk_dbg_pre", 12, 11),
275 GATE(0, "cs_dbg", "pclk_dbg_pre", 12, 10),
276 GATE(0, "pclk_dbg", "pclk_dbg_pre", 12, 9),
277 GATE(0, "armcore0", "armcore0_s", 12, 8),
278 GATE(0, "armcore1", "armcore1_s", 12, 7),
279 GATE(0, "armcore2", "armcore2_s", 12, 6),
280 GATE(0, "armcore3", "armcore3_s", 12, 5),
281 GATE(0, "l2ram", "l2ram_s", 12, 4),
282 GATE(0, "aclk_core_m0", "aclk_core_m0_s", 12, 3),
283 GATE(0, "aclk_core_mp", "aclk_core_mp_s", 12, 2),
284 GATE(0, "atclk", "atclk_s", 12, 1),
285 GATE(0, "pclk_dbg_pre", "pclk_dbg_pre_s", 12, 0),
286
287 /* CRU_CLKGATE_CON13 */
288 GATE(SCLK_HEVC_CORE, "sclk_hevc_core", "sclk_hevc_core_s", 13, 15),
289 GATE(SCLK_HEVC_CABAC, "sclk_hevc_cabac", "sclk_hevc_cabac_s", 13, 14),
290 GATE(ACLK_HEVC, "aclk_hevc", "aclk_hevc_s", 13, 13),
291 GATE(0, "wii", "wifi_frac_s", 13, 12),
292 GATE(SCLK_LCDC_PWM1, "sclk_lcdc_pwm1", "xin24m", 13, 11),
293 GATE(SCLK_LCDC_PWM0, "sclk_lcdc_pwm0", "xin24m", 13, 10),
294 /* 9 - Not in TRM - hsicphy12m_xin12m in Linux */
295 GATE(0, "c2c_host", "aclk_cpu_src", 13, 8),
296 GATE(SCLK_OTG_ADP, "sclk_otg_adp", "xin32k", 13, 7),
297 GATE(SCLK_OTGPHY2, "sclk_otgphy2", "xin24m", 13, 6),
298 GATE(SCLK_OTGPHY1, "sclk_otgphy1", "xin24m", 13, 5),
299 GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", 13, 4),
300 GATE(SCLK_EMMC, "sclk_emmc", "sclk_emmc_s", 13, 3),
301 GATE(SCLK_SDIO1, "sclk_sdio1", "sclk_sdio1_s", 13, 2),
302 GATE(SCLK_SDIO0, "sclk_sdio0", "sclk_sdio0_s", 13, 1),
303 GATE(SCLK_SDMMC, "sclk_sdmmc", "sclk_sdmmc_s", 13, 0),
304
305 /* CRU_CLKGATE_CON14 */
306 GATE(0, "pclk_alive_niu", "pclk_pd_alive", 14, 12),
307 GATE(PCLK_GRF, "pclk_grf", "pclk_pd_alive", 14, 11),
308 GATE(PCLK_GPIO8, "pclk_gpio8", "pclk_pd_alive", 14, 8),
309 GATE(PCLK_GPIO7, "pclk_gpio7", "pclk_pd_alive", 14, 7),
310 GATE(PCLK_GPIO6, "pclk_gpio6", "pclk_pd_alive", 14, 6),
311 GATE(PCLK_GPIO5, "pclk_gpio5", "pclk_pd_alive", 14, 5),
312 GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_pd_alive", 14, 4),
313 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_pd_alive", 14, 3),
314 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_pd_alive", 14, 2),
315 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_pd_alive", 14, 1),
316
317 /* CRU_CLKGATE_CON15*/
318 GATE(HCLK_VIP, "hclk_vip", "hclk_vio", 15, 15),
319 GATE(ACLK_VIP, "aclk_vip", "aclk_vio0", 15, 14),
320 GATE(ACLK_RGA_NIU, "aclk_rga_niu", "aclk_rga_pre", 15, 13),
321 GATE(ACLK_VIO1_NIU, "aclk_vio1_niu", "aclk_vio1", 15, 12),
322 GATE(ACLK_VIO0_NIU, "aclk_vio0_niu", "aclk_vio0", 15, 11),
323 GATE(HCLK_VIO_NIU, "hclk_vio_niu", "hclk_vio", 15, 10),
324 GATE(HCLK_VIO_AHB_ARBI, "hclk_vio_ahb_arbi", "hclk_vio",15, 9),
325 GATE(HCLK_VOP1, "hclk_vop1", "hclk_vio", 15, 8),
326 GATE(ACLK_VOP1, "aclk_vop1", "aclk_vio1", 15, 7),
327 GATE(HCLK_VOP0, "hclk_vop0", "hclk_vio", 15, 6),
328 GATE(ACLK_VOP0, "aclk_vop0", "aclk_vio0", 15, 5),
329 /* 4 - aclk_lcdc_iep */
330 GATE(HCLK_IEP, "hclk_iep", "hclk_vio", 15, 3),
331 GATE(ACLK_IEP, "aclk_iep", "aclk_vio0", 15, 2),
332 GATE(HCLK_RGA, "hclk_rga", "hclk_vio", 15, 1),
333 GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 15, 0),
334
335 /* CRU_CLKGATE_CON16 */
336 GATE(PCLK_VIO2_H2P, "pclk_vio2_h2p", "hclk_vio", 16, 11),
337 GATE(HCLK_VIO2_H2P, "hclk_vio2_h2p", "hclk_vio", 16, 10),
338 GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "hclk_vio", 16, 9),
339 GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "hclk_vio", 16, 8),
340 GATE(PCLK_LVDS_PHY, "pclk_lvds_phy", "hclk_vio", 16, 7),
341 GATE(PCLK_MIPI_CSI, "pclk_mipi_csi", "hclk_vio", 16, 6),
342 GATE(PCLK_MIPI_DSI1, "pclk_mipi_dsi1", "hclk_vio", 16, 5),
343 GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "hclk_vio", 16, 4),
344 GATE(PCLK_ISP_IN, "pclk_isp_in", "ext_isp", 16, 3),
345 GATE(ACLK_ISP, "aclk_isp", "aclk_vio1", 16, 2),
346 GATE(HCLK_ISP, "hclk_isp", "hclk_vio", 16, 1),
347 GATE(0, "pclk_vip_in", "ext_vip", 16, 0),
348
349 /* CRU_CLKGATE_CON17 */
350 GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pd_pmu", 17, 4),
351 GATE(PCLK_SGRF, "pclk_sgrf", "pclk_pd_pmu", 17, 3),
352 GATE(0, "pclk_pmu_niu", "pclk_pd_pmu", 17, 2),
353 GATE(0, "pclk_intmem1", "pclk_pd_pmu", 17, 1),
354 GATE(PCLK_PMU, "pclk_pmu", "pclk_pd_pmu", 17, 0),
355
356 /* CRU_CLKGATE_CON18 */
357 GATE(ACLK_GPU, "aclk_gpu", "sclk_gpu", 18, 0),
358 };
359
360 /*
361 * PLLs
362 */
363 #define PLL_RATE_BA(_hz, _ref, _fb, _post, _ba) \
364 { \
365 .freq = _hz, \
366 .refdiv = _ref, \
367 .fbdiv = _fb, \
368 .postdiv1 = _post, \
369 .bwadj = _ba, \
370 }
371
372 #define PLL_RATE(_mhz, _ref, _fb, _post) \
373 PLL_RATE_BA(_mhz, _ref, _fb, _post, ((_fb < 2) ? 1 : _fb >> 1))
374
375 static struct rk_clk_pll_rate rk3288_pll_rates[] = {
376 PLL_RATE( 2208000000, 1, 92, 1),
377 PLL_RATE( 2184000000, 1, 91, 1),
378 PLL_RATE( 2160000000, 1, 90, 1),
379 PLL_RATE( 2136000000, 1, 89, 1),
380 PLL_RATE( 2112000000, 1, 88, 1),
381 PLL_RATE( 2088000000, 1, 87, 1),
382 PLL_RATE( 2064000000, 1, 86, 1),
383 PLL_RATE( 2040000000, 1, 85, 1),
384 PLL_RATE( 2016000000, 1, 84, 1),
385 PLL_RATE( 1992000000, 1, 83, 1),
386 PLL_RATE( 1968000000, 1, 82, 1),
387 PLL_RATE( 1944000000, 1, 81, 1),
388 PLL_RATE( 1920000000, 1, 80, 1),
389 PLL_RATE( 1896000000, 1, 79, 1),
390 PLL_RATE( 1872000000, 1, 78, 1),
391 PLL_RATE( 1848000000, 1, 77, 1),
392 PLL_RATE( 1824000000, 1, 76, 1),
393 PLL_RATE( 1800000000, 1, 75, 1),
394 PLL_RATE( 1776000000, 1, 74, 1),
395 PLL_RATE( 1752000000, 1, 73, 1),
396 PLL_RATE( 1728000000, 1, 72, 1),
397 PLL_RATE( 1704000000, 1, 71, 1),
398 PLL_RATE( 1680000000, 1, 70, 1),
399 PLL_RATE( 1656000000, 1, 69, 1),
400 PLL_RATE( 1632000000, 1, 68, 1),
401 PLL_RATE( 1608000000, 1, 67, 1),
402 PLL_RATE( 1560000000, 1, 65, 1),
403 PLL_RATE( 1512000000, 1, 63, 1),
404 PLL_RATE( 1488000000, 1, 62, 1),
405 PLL_RATE( 1464000000, 1, 61, 1),
406 PLL_RATE( 1440000000, 1, 60, 1),
407 PLL_RATE( 1416000000, 1, 59, 1),
408 PLL_RATE( 1392000000, 1, 58, 1),
409 PLL_RATE( 1368000000, 1, 57, 1),
410 PLL_RATE( 1344000000, 1, 56, 1),
411 PLL_RATE( 1320000000, 1, 55, 1),
412 PLL_RATE( 1296000000, 1, 54, 1),
413 PLL_RATE( 1272000000, 1, 53, 1),
414 PLL_RATE( 1248000000, 1, 52, 1),
415 PLL_RATE( 1224000000, 1, 51, 1),
416 PLL_RATE( 1200000000, 1, 50, 1),
417 PLL_RATE( 1188000000, 2, 99, 1),
418 PLL_RATE( 1176000000, 1, 49, 1),
419 PLL_RATE( 1128000000, 1, 47, 1),
420 PLL_RATE( 1104000000, 1, 46, 1),
421 PLL_RATE( 1008000000, 1, 84, 2),
422 PLL_RATE( 912000000, 1, 76, 2),
423 PLL_RATE( 891000000, 8, 594, 2),
424 PLL_RATE( 888000000, 1, 74, 2),
425 PLL_RATE( 816000000, 1, 68, 2),
426 PLL_RATE( 798000000, 2, 133, 2),
427 PLL_RATE( 792000000, 1, 66, 2),
428 PLL_RATE( 768000000, 1, 64, 2),
429 PLL_RATE( 742500000, 8, 495, 2),
430 PLL_RATE( 696000000, 1, 58, 2),
431 PLL_RATE_BA( 621000000, 1, 207, 8, 1),
432 PLL_RATE( 600000000, 1, 50, 2),
433 PLL_RATE_BA( 594000000, 1, 198, 8, 1),
434 PLL_RATE( 552000000, 1, 46, 2),
435 PLL_RATE( 504000000, 1, 84, 4),
436 PLL_RATE( 500000000, 3, 125, 2),
437 PLL_RATE( 456000000, 1, 76, 4),
438 PLL_RATE( 428000000, 1, 107, 6),
439 PLL_RATE( 408000000, 1, 68, 4),
440 PLL_RATE( 400000000, 3, 100, 2),
441 PLL_RATE_BA( 394000000, 1, 197, 12, 1),
442 PLL_RATE( 384000000, 2, 128, 4),
443 PLL_RATE( 360000000, 1, 60, 4),
444 PLL_RATE_BA( 356000000, 1, 178, 12, 1),
445 PLL_RATE_BA( 324000000, 1, 189, 14, 1),
446 PLL_RATE( 312000000, 1, 52, 4),
447 PLL_RATE_BA( 308000000, 1, 154, 12, 1),
448 PLL_RATE_BA( 303000000, 1, 202, 16, 1),
449 PLL_RATE( 300000000, 1, 75, 6),
450 PLL_RATE_BA( 297750000, 2, 397, 16, 1),
451 PLL_RATE_BA( 293250000, 2, 391, 16, 1),
452 PLL_RATE_BA( 292500000, 1, 195, 16, 1),
453 PLL_RATE( 273600000, 1, 114, 10),
454 PLL_RATE_BA( 273000000, 1, 182, 16, 1),
455 PLL_RATE_BA( 270000000, 1, 180, 16, 1),
456 PLL_RATE_BA( 266250000, 2, 355, 16, 1),
457 PLL_RATE_BA( 256500000, 1, 171, 16, 1),
458 PLL_RATE( 252000000, 1, 84, 8),
459 PLL_RATE_BA( 250500000, 1, 167, 16, 1),
460 PLL_RATE_BA( 243428571, 1, 142, 14, 1),
461 PLL_RATE( 238000000, 1, 119, 12),
462 PLL_RATE_BA( 219750000, 2, 293, 16, 1),
463 PLL_RATE_BA( 216000000, 1, 144, 16, 1),
464 PLL_RATE_BA( 213000000, 1, 142, 16, 1),
465 PLL_RATE( 195428571, 1, 114, 14),
466 PLL_RATE( 160000000, 1, 80, 12),
467 PLL_RATE( 157500000, 1, 105, 16),
468 PLL_RATE( 126000000, 1, 84, 16),
469 PLL_RATE( 48000000, 1, 64, 32),
470 {},
471 };
472
473 static struct rk_clk_armclk_rates rk3288_armclk_rates[] = {
474 { 1800000000, 1},
475 { 1704000000, 1},
476 { 1608000000, 1},
477 { 1512000000, 1},
478 { 1416000000, 1},
479 { 1200000000, 1},
480 { 1008000000, 1},
481 { 816000000, 1},
482 { 696000000, 1},
483 { 600000000, 1},
484 { 408000000, 1},
485 { 312000000, 1},
486 { 216000000, 1},
487 { 126000000, 1},
488 };
489
490 /* Standard PLL. */
491 #define PLL(_id, _name, _base, _shift) \
492 { \
493 .type = RK3066_CLK_PLL, \
494 .clk.pll = &(struct rk_clk_pll_def) { \
495 .clkdef.id = _id, \
496 .clkdef.name = _name, \
497 .clkdef.parent_names = pll_src_p, \
498 .clkdef.parent_cnt = nitems(pll_src_p), \
499 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
500 .base_offset = _base, \
501 .mode_reg = CRU_MODE_CON, \
502 .mode_shift = _shift, \
503 .rates = rk3288_pll_rates, \
504 }, \
505 }
506
507 #define ARMDIV(_id, _name, _pn, _r, _o, _ds, _dw, _ms, _mw, _mp, _ap) \
508 { \
509 .type = RK_CLK_ARMCLK, \
510 .clk.armclk = &(struct rk_clk_armclk_def) { \
511 .clkdef.id = _id, \
512 .clkdef.name = _name, \
513 .clkdef.parent_names = _pn, \
514 .clkdef.parent_cnt = nitems(_pn), \
515 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
516 .muxdiv_offset = CRU_CLKSEL_CON(_o), \
517 .mux_shift = _ms, \
518 .mux_width = _mw, \
519 .div_shift = _ds, \
520 .div_width = _dw, \
521 .main_parent = _mp, \
522 .alt_parent = _ap, \
523 .rates = _r, \
524 .nrates = nitems(_r), \
525 }, \
526 }
527
528 #define PLIST(_name) static const char *_name[]
529 PLIST(pll_src_p) = {"xin24m", "xin24m", "xin32k"};
530 PLIST(armclk_p)= {"apll_core", "gpll_core"};
531 PLIST(ddrphy_p) = {"dpll_ddr", "gpll_ddr"};
532 PLIST(aclk_cpu_p) = {"cpll_aclk_cpu", "gpll_aclk_cpu"};
533
534 PLIST(cpll_gpll_p) = {"cpll", "gpll"};
535 PLIST(npll_cpll_gpll_p) = {"npll", "cpll", "gpll"};
536 PLIST(cpll_gpll_npll_p) = {"cpll", "gpll", "npll"};
537 PLIST(cpll_gpll_usb480m_p)= {"cpll", "gpll", "usbphy480m_src"};
538 PLIST(cpll_gpll_usb480m_npll_p) = {"cpll", "gpll", "usbphy480m_src", "npll"};
539
540 PLIST(mmc_p) = {"cpll", "gpll", "xin24m", "xin24m"};
541 PLIST(i2s_pre_p) = {"i2s_src", "i2s_frac", "ext_i2s", "xin12m"};
542 PLIST(i2s_clkout_p) = {"i2s_pre", "xin12m"};
543 PLIST(spdif_p) = {"spdif_pre", "spdif_frac", "xin12m"};
544 PLIST(spdif_8ch_p) = {"spdif_8ch_pre", "spdif_8ch_frac", "xin12m"};
545 PLIST(uart0_p) = {"uart0_src", "uart0_frac", "xin24m"};
546 PLIST(uart1_p) = {"uart1_src", "uart1_frac", "xin24m"};
547 PLIST(uart2_p) = {"uart2_src", "uart2_frac", "xin24m"};
548 PLIST(uart3_p) = {"uart3_src", "uart3_frac", "xin24m"};
549 PLIST(uart4_p) = {"uart4_src", "uart4_frac", "xin24m"};
550 PLIST(vip_out_p) = {"vip_src", "xin24m"};
551 PLIST(mac_p) = {"mac_pll_src", "ext_gmac"};
552 PLIST(hsadcout_p) = {"hsadc_src", "ext_hsadc"};
553 PLIST(edp_24m_p) = {"ext_edp_24m", "xin24m"};
554 PLIST(tspout_p) = {"cpll", "gpll", "npll", "xin27m"};
555 PLIST(wifi_p) = {"cpll", "gpll"};
556 PLIST(usbphy480m_p) = {"sclk_otgphy1_480m", "sclk_otgphy2_480m", "sclk_otgphy0_480m"};
557
558 /* PLIST(aclk_vcodec_pre_p) = {"aclk_vepu", "aclk_vdpu"}; */
559
560
561 static struct rk_clk rk3288_clks[] = {
562 /* External clocks */
563 LINK("xin24m"),
564 FRATE(0, "xin32k", 32000),
565 FRATE(0, "xin27m", 27000000),
566 FRATE(0, "ext_hsadc", 0),
567 FRATE(0, "ext_jtag", 0),
568 FRATE(0, "ext_isp", 0),
569 FRATE(0, "ext_vip", 0),
570 FRATE(0, "ext_i2s", 0),
571 FRATE(0, "ext_edp_24m", 0),
572
573 FRATE(0, "sclk_otgphy0_480m", 0),
574 FRATE(0, "sclk_otgphy1_480m", 0),
575 FRATE(0, "sclk_otgphy2_480m", 0),
576
577 FRATE(0, "aclk_vcodec_pre", 0),
578
579 /* Fixed dividers */
580 FFACT(0, "xin12m", "xin24m", 1, 2),
581 FFACT(0, "hclk_vcodec_pre_s", "aclk_vcodec_pre", 1, 4),
582
583 PLL(PLL_APLL, "apll", CRU_APLL_CON(0), 0),
584 PLL(PLL_DPLL, "dpll", CRU_DPLL_CON(0), 4),
585 PLL(PLL_CPLL, "cpll", CRU_CPLL_CON(0), 8),
586 PLL(PLL_GPLL, "gpll", CRU_GPLL_CON(0), 12),
587 PLL(PLL_NPLL, "npll", CRU_NPLL_CON(0), 14),
588
589 /* CRU_CLKSEL0_CON */
590 ARMDIV(ARMCLK, "armclk", armclk_p, rk3288_armclk_rates,
591 0, 8, 5, 15, 1, 0, 1),
592 CDIV(0, "aclk_core_mp_s", "armclk", 0,
593 0, 4, 4),
594 CDIV(0, "aclk_core_m0_s", "armclk", 0,
595 0, 0, 4),
596
597 /* CRU_CLKSEL1_CON */
598 CDIV(0, "pclk_cpu_s", "aclk_cpu_pre", 0,
599 1, 12, 3),
600 CDIV(0, "hclk_cpu_s", "aclk_cpu_pre", RK_CLK_COMPOSITE_DIV_EXP,
601 1, 8, 2),
602 COMP(0, "aclk_cpu_src", aclk_cpu_p, 0,
603 1, 3, 5, 15, 1),
604 CDIV(0, "aclk_cpu_pre", "aclk_cpu_src", 0,
605 1, 0, 3),
606
607 /* CRU_CLKSEL2_CON */
608 /* 12:8 testout_div */
609 CDIV(0, "sclk_tsadc_s", "xin32k", 0,
610 2, 0, 6),
611
612 /* CRU_CLKSEL3_CON */
613 MUX(SCLK_UART4, "sclk_uart4", uart4_p, 0,
614 3, 8, 2),
615 CDIV(0, "uart4_src_s", "uart_src", 0,
616 3, 0, 7),
617
618 /* CRU_CLKSEL4_CON */
619 MUX(0, "i2s_pre", i2s_pre_p, 0,
620 4, 8, 2),
621 MUX(0, "i2s0_clkout_s", i2s_clkout_p, 0,
622 4, 12, 1),
623 COMP(0, "i2s_src_s", cpll_gpll_p, 0,
624 4, 0, 7, 15, 1),
625
626 /* CRU_CLKSEL5_CON */
627 MUX(0, "spdif_src", cpll_gpll_p, 0,
628 5, 15, 1),
629 MUX(0, "spdif_mux", spdif_p, 0,
630 5, 8, 2),
631 CDIV(0, "spdif_pre_s", "spdif_src", 0,
632 5, 0, 7),
633
634 /* CRU_CLKSEL6_CON */
635 COMP(0, "sclk_isp_jpe_s", cpll_gpll_npll_p, 0,
636 6, 8, 6, 14, 2),
637 COMP(0, "sclk_isp_s", cpll_gpll_npll_p, 0,
638 6, 0, 6, 6, 2),
639
640 /* CRU_CLKSEL7_CON */
641 FRACT(0, "uart4_frac_s", "uart4_src", 0,
642 7),
643
644 /* CRU_CLKSEL8_CON */
645 FRACT(0, "i2s_frac_s", "i2s_src", 0,
646 8),
647
648 /* CRU_CLKSEL9_CON */
649 FRACT(0, "spdif_frac_s", "spdif_src", 0,
650 9),
651
652 /* CRU_CLKSEL10_CON */
653 CDIV(0, "pclk_peri_s", "aclk_peri_src", RK_CLK_COMPOSITE_DIV_EXP,
654 10, 12, 2),
655 CDIV(0, "hclk_peri_s", "aclk_peri_src", RK_CLK_COMPOSITE_DIV_EXP,
656 10, 8, 2),
657 COMP(0, "aclk_peri_src_s", cpll_gpll_p, 0,
658 10, 0, 5, 15, 1),
659
660 /* CRU_CLKSEL11_CON */
661 COMP(0, "sclk_sdmmc_s", mmc_p, 0,
662 11, 0, 6, 6, 2),
663
664 /* CRU_CLKSEL12_CON */
665 COMP(0, "sclk_emmc_s", mmc_p, 0,
666 12, 8, 6, 14, 2),
667 COMP(0, "sclk_sdio0_s", mmc_p, 0,
668 12, 0, 6, 6, 2),
669
670 /* CRU_CLKSEL13_CON */
671 MUX(0, "uart_src", cpll_gpll_p, 0,
672 13, 15, 1),
673 MUX(0, "usbphy480m_src_s", usbphy480m_p, 0,
674 13, 11, 2),
675 MUX(SCLK_UART0, "sclk_uart0", uart0_p, 0,
676 13, 8, 2),
677 COMP(0, "uart0_src_s", cpll_gpll_usb480m_npll_p, 0,
678 13, 0, 7, 13, 2),
679
680 /* CRU_CLKSEL14_CON */
681 MUX(SCLK_UART1, "sclk_uart1", uart1_p, 0,
682 14, 8, 2),
683 CDIV(0, "uart1_src_s", "uart_src", 0,
684 14, 0, 7),
685
686
687 /* CRU_CLKSEL15_CON */
688 MUX(SCLK_UART2, "sclk_uart2", uart2_p, 0,
689 15, 8, 2),
690 CDIV(0, "uart2_src_s", "uart_src", 0,
691 15, 0, 7),
692
693 /* CRU_CLKSEL16_CON */
694 MUX(SCLK_UART3, "sclk_uart3", uart3_p, 0,
695 16, 8, 2),
696 CDIV(0, "uart3_src_s", "uart_src", 0,
697 16, 0, 7),
698
699 /* CRU_CLKSEL17_CON */
700 FRACT(0, "uart0_frac_s", "uart0_src", 0,
701 17),
702
703 /* CRU_CLKSEL18_CON */
704 FRACT(0, "uart1_frac_s", "uart1_src", 0,
705 18),
706
707 /* CRU_CLKSEL19_CON */
708 FRACT(0, "uart2_frac_s", "uart2_src", 0,
709 19),
710
711 /* CRU_CLKSEL20_CON */
712 FRACT(0, "uart3_frac_s", "uart3_src", 0,
713 20),
714
715 /* CRU_CLKSEL21_CON */
716 COMP(0, "mac_pll_src_s", npll_cpll_gpll_p, 0,
717 21, 8, 5, 0, 2),
718 MUX(SCLK_MAC, "mac_clk", mac_p, 0,
719 21, 4, 1),
720
721 /* CRU_CLKSEL22_CON */
722 MUX(0, "sclk_hsadc_out", hsadcout_p, 0,
723 22, 4, 1),
724 COMP(0, "hsadc_src_s", cpll_gpll_p, 0,
725 22, 8, 8, 0, 1),
726 MUX(0, "wifi_src", wifi_p, 0,
727 22, 1, 1),
728 /* 7 - inverter "sclk_hsadc", "sclk_hsadc_out" */
729
730 /* CRU_CLKSEL23_CON */
731 FRACT(0, "wifi_frac_s", "wifi_src", 0,
732 23),
733
734 /* CRU_CLKSEL24_CON */
735 CDIV(0, "sclk_saradc_s", "xin24m", 0,
736 24, 8, 8),
737
738 /* CRU_CLKSEL25_CON */
739 COMP(0, "sclk_spi1_s", cpll_gpll_p, 0,
740 25, 8, 7, 15, 1),
741 COMP(0, "sclk_spi0_s", cpll_gpll_p, 0,
742 25, 0, 7, 7, 1),
743
744 /* CRU_CLKSEL26_CON */
745 COMP(SCLK_VIP_OUT, "sclk_vip_out", vip_out_p, 0,
746 26, 9, 5, 15, 1),
747 MUX(0, "vip_src_s", cpll_gpll_p, 0,
748 26, 8, 1),
749 CDIV(0, "crypto_s", "aclk_cpu_pre", 0,
750 26, 6, 2),
751 COMP(0, "ddrphy", ddrphy_p, RK_CLK_COMPOSITE_DIV_EXP,
752 26, 0, 2, 2, 1),
753
754 /* CRU_CLKSEL27_CON */
755 COMP(0, "dclk_vop0_s", cpll_gpll_npll_p, 0,
756 27, 8, 8, 0, 2),
757
758 MUX(0, "sclk_edp_24m_s", edp_24m_p, 0,
759 28, 15, 1),
760 CDIV(0, "hclk_vio", "aclk_vio0", 0,
761 28, 8, 5),
762 COMP(0, "sclk_edp_s", cpll_gpll_npll_p, 0,
763 28, 0, 6, 6, 2),
764
765 /* CRU_CLKSEL29_CON */
766 COMP(0, "dclk_vop1_s", cpll_gpll_npll_p, 0,
767 29, 8, 8, 6, 2),
768 /* 4 - inverter "pclk_vip" "pclk_vip_in" */
769 /* 3 - inverter "pclk_isp", "pclk_isp_in" */
770
771 /* CRU_CLKSEL30_CON */
772 COMP(0, "sclk_rga_s", cpll_gpll_usb480m_p, 0,
773 30, 8, 5, 14, 2),
774 COMP(0, "aclk_rga_pre_s", cpll_gpll_usb480m_p, 0,
775 30, 0, 5, 6, 2),
776
777 /* CRU_CLKSEL31_CON */
778 COMP(0, "aclk_vio1_s", cpll_gpll_usb480m_p, 0,
779 31, 8, 5, 14, 2),
780 COMP(0, "aclk_vio0_s", cpll_gpll_usb480m_p, 0,
781 31, 0, 5, 6, 2),
782
783 /* CRU_CLKSEL32_CON */
784 COMP(0, "aclk_vdpu_s", cpll_gpll_usb480m_p, 0,
785 32, 8, 5, 14, 2),
786 COMP(0, "aclk_vepu_s", cpll_gpll_usb480m_p, 0,
787 32, 0, 5, 6, 2),
788
789 /* CRU_CLKSEL33_CON */
790 CDIV(0, "pclk_pd_alive", "gpll", 0,
791 33, 8, 5),
792 CDIV(0, "pclk_pd_pmu_s", "gpll", 0,
793 33, 0, 5),
794
795 /* CRU_CLKSEL34_CON */
796 COMP(0, "sclk_sdio1_s", mmc_p, 0,
797 34, 8, 6, 14, 2),
798 COMP(0, "sclk_gpu_s", cpll_gpll_usb480m_npll_p, 0,
799 34, 0, 5, 6, 2),
800
801 /* CRU_CLKSEL35_CON */
802 COMP(0, "sclk_tspout_s", tspout_p, 0,
803 35, 8, 5, 14, 2),
804 COMP(0, "sclk_tsp_s", cpll_gpll_npll_p, 0,
805 35, 0, 5, 6, 2),
806
807 /* CRU_CLKSEL36_CON */
808 CDIV(0, "armcore3_s", "armclk", 0,
809 36, 12, 3),
810 CDIV(0, "armcore2_s", "armclk", 0,
811 36, 8, 3),
812 CDIV(0, "armcore1_s", "armclk", 0,
813 36, 4, 3),
814 CDIV(0, "armcore0_s", "armclk", 0,
815 36, 0, 3),
816
817 /* CRU_CLKSEL37_CON */
818 CDIV(0, "pclk_dbg_pre_s", "armclk", 0,
819 37, 9, 5),
820 CDIV(0, "atclk_s", "armclk", 0,
821 37, 4, 5),
822 CDIV(0, "l2ram_s", "armclk", 0,
823 37, 0, 3),
824
825 /* CRU_CLKSEL38_CON */
826 COMP(0, "sclk_nandc1_s", cpll_gpll_p, 0,
827 38, 8, 5, 15, 1),
828 COMP(0, "sclk_nandc0_s", cpll_gpll_p, 0,
829 38, 0, 5, 7, 1),
830
831 /* CRU_CLKSEL39_CON */
832 COMP(0, "aclk_hevc_s", cpll_gpll_npll_p, 0,
833 39, 8, 5, 14, 2),
834 COMP(0, "sclk_spi2_s", cpll_gpll_p, 0,
835 39, 0, 7, 7, 1),
836
837 /* CRU_CLKSEL40_CON */
838 CDIV(HCLK_HEVC, "hclk_hevc", "aclk_hevc", 0,
839 40, 12, 2),
840 MUX(0, "spdif_8ch_mux", spdif_8ch_p, 0,
841 40, 8, 2),
842 CDIV(0, "spdif_8ch_pre_s", "spdif_src", 0,
843 40, 0, 7),
844
845 /* CRU_CLKSEL41_CON */
846 FRACT(0, "spdif_8ch_frac_s", "spdif_8ch_pre", 0,
847 41),
848
849 /* CRU_CLKSEL42_CON */
850 COMP(0, "sclk_hevc_core_s", cpll_gpll_npll_p, 0,
851 42, 8, 5, 14, 2),
852 COMP(0, "sclk_hevc_cabac_s", cpll_gpll_npll_p, 0,
853 42, 0, 5, 6, 2),
854 /*
855 * not yet implemented MMC clocks
856 * id name src reg
857 * SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RK3288_SDMMC_CON0
858 * SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3288_SDMMC_CON1,
859
860 * SCLK_SDIO0_DRV, "sdio0_drv", "sclk_sdio0", RK3288_SDIO0_CON0, 1),
861 * SCLK_SDIO0_SAMPLE, "sdio0_sample", "sclk_sdio0", RK3288_SDIO0_CON1, 0),
862
863 * SCLK_SDIO1_DRV, "sdio1_drv", "sclk_sdio1", RK3288_SDIO1_CON0, 1),
864 * SCLK_SDIO1_SAMPLE, "sdio1_sample", "sclk_sdio1", RK3288_SDIO1_CON1, 0),
865
866 * SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc", RK3288_EMMC_CON0, 1),
867 * SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RK3288_EMMC_CON1, 0),
868 *
869 * and GFR based mux for "aclk_vcodec_pre"
870 */
871
872 };
873
874 static int
rk3288_cru_probe(device_t dev)875 rk3288_cru_probe(device_t dev)
876 {
877
878 if (!ofw_bus_status_okay(dev))
879 return (ENXIO);
880
881 if (ofw_bus_is_compatible(dev, "rockchip,rk3288-cru")) {
882 device_set_desc(dev, "Rockchip RK3288 Clock and Reset Unit");
883 return (BUS_PROBE_DEFAULT);
884 }
885
886 return (ENXIO);
887 }
888
889 static int
rk3288_cru_attach(device_t dev)890 rk3288_cru_attach(device_t dev)
891 {
892 struct rk_cru_softc *sc;
893
894 sc = device_get_softc(dev);
895 sc->dev = dev;
896
897 sc->gates = rk3288_gates;
898 sc->ngates = nitems(rk3288_gates);
899
900 sc->clks = rk3288_clks;
901 sc->nclks = nitems(rk3288_clks);
902
903 sc->reset_num = CRU_SOFTRST_SIZE * 16;
904 sc->reset_offset = CRU_SOFTRST_CON(0);
905
906 return (rk_cru_attach(dev));
907 }
908
909 static device_method_t rk3288_cru_methods[] = {
910 /* Device interface */
911 DEVMETHOD(device_probe, rk3288_cru_probe),
912 DEVMETHOD(device_attach, rk3288_cru_attach),
913
914 DEVMETHOD_END
915 };
916
917 static devclass_t rk3288_cru_devclass;
918
919 DEFINE_CLASS_1(rk3288_cru, rk3288_cru_driver, rk3288_cru_methods,
920 sizeof(struct rk_cru_softc), rk_cru_driver);
921
922 EARLY_DRIVER_MODULE(rk3288_cru, simplebus, rk3288_cru_driver,
923 rk3288_cru_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE + 1);
924