1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2018 Emmanuel Vadot <manu@freebsd.org>
5 * Copyright (c) 2018 Greg V <greg@unrelenting.technology>
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <sys/bus.h>
33 #include <sys/rman.h>
34 #include <sys/kernel.h>
35 #include <sys/module.h>
36 #include <machine/bus.h>
37
38 #include <dev/fdt/simplebus.h>
39
40 #include <dev/ofw/ofw_bus.h>
41 #include <dev/ofw/ofw_bus_subr.h>
42
43 #include <dev/extres/clk/clk_div.h>
44 #include <dev/extres/clk/clk_fixed.h>
45 #include <dev/extres/clk/clk_mux.h>
46
47 #include <arm64/rockchip/clk/rk_cru.h>
48
49 #include <arm64/rockchip/clk/rk3399_cru_dt.h>
50
51 #define CRU_CLKSEL_CON(x) (0x100 + (x) * 0x4)
52 #define CRU_CLKGATE_CON(x) (0x300 + (x) * 0x4)
53
54 /* GATES */
55
56 static struct rk_cru_gate rk3399_gates[] = {
57 /* CRU_CLKGATE_CON0 */
58 /* 15-8 unused */
59 GATE(SCLK_PVTM_CORE_L, "clk_pvtm_core_l", "xin24m", 0, 7),
60 GATE(0, "pclk_dbg_core_l", "pclk_dbg_core_l_c", 0, 6),
61 GATE(0, "atclk_core_l", "atclk_core_l_c", 0, 5),
62 GATE(0, "aclkm_core_l", "aclkm_core_l_c", 0, 4),
63 GATE(0, "clk_core_l_gpll_src", "gpll", 0, 3),
64 GATE(0, "clk_core_l_dpll_src", "dpll", 0, 2),
65 GATE(0, "clk_core_l_bpll_src", "bpll", 0, 1),
66 GATE(0, "clk_core_l_lpll_src", "lpll", 0, 0),
67
68 /* CRU_CLKGATE_CON1 */
69 /* 15 - 8 unused */
70 GATE(SCLK_PVTM_CORE_B, "clk_pvtm_core_b", "xin24m", 1, 7),
71 GATE(0, "pclk_dbg_core_b","pclk_dbg_core_b_c", 1, 6),
72 GATE(0, "atclk_core_b", "atclk_core_b_c", 1, 5),
73 GATE(0, "aclkm_core_b", "aclkm_core_b_c", 1, 4),
74 GATE(0, "clk_core_b_gpll_src", "gpll", 1, 3),
75 GATE(0, "clk_core_b_dpll_src", "dpll", 1, 2),
76 GATE(0, "clk_core_b_bpll_src", "bpll", 1, 1),
77 GATE(0, "clk_core_b_lpll_src", "lpll", 1, 0),
78
79 /* CRU_CLKGATE_CON2 */
80 /* 15 - 11 unused */
81 GATE(0, "npll_cs", "npll", 2, 10),
82 GATE(0, "gpll_cs", "gpll", 2, 9),
83 GATE(0, "cpll_cs", "cpll", 2, 8),
84 GATE(SCLK_CCI_TRACE, "clk_cci_trace", "clk_cci_trace_c", 2, 7),
85 GATE(0, "gpll_cci_trace", "gpll", 2, 6),
86 GATE(0, "cpll_cci_trace", "cpll", 2, 5),
87 GATE(0, "aclk_cci_pre", "aclk_cci_pre_c", 2, 4),
88 GATE(0, "vpll_aclk_cci_src", "vpll", 2, 3),
89 GATE(0, "npll_aclk_cci_src", "npll", 2, 2),
90 GATE(0, "gpll_aclk_cci_src", "gpll", 2, 1),
91 GATE(0, "cpll_aclk_cci_src", "cpll", 2, 0),
92
93 /* CRU_CLKGATE_CON3 */
94 /* 15 - 8 unused */
95 GATE(0, "aclk_center", "aclk_center_c", 3, 7),
96 /* 6 unused */
97 /* 5 unused */
98 GATE(PCLK_DDR, "pclk_ddr", "pclk_ddr_c", 3, 4),
99 GATE(0, "clk_ddrc_gpll_src", "gpll", 3, 3),
100 GATE(0, "clk_ddrc_dpll_src", "dpll", 3, 2),
101 GATE(0, "clk_ddrc_bpll_src", "bpll", 3, 1),
102 GATE(0, "clk_ddrc_lpll_src", "lpll", 3, 0),
103
104 /* CRU_CLKGATE_CON4 */
105 /* 15 - 12 unused */
106 GATE(SCLK_PVTM_DDR, "clk_pvtm_ddr", "xin24m", 4, 11),
107 GATE(0, "clk_rga_core", "clk_rga_core_c", 4, 10),
108 GATE(0, "hclk_rga_pre", "hclk_rga_pre_c", 4, 9),
109 GATE(0, "aclk_rga_pre", "aclk_rga_pre_c", 4, 8),
110 GATE(0, "hclk_iep_pre", "hclk_iep_pre_c", 4, 7),
111 GATE(0, "aclk_iep_pre", "aclk_iep_pre_c", 4, 6),
112 GATE(SCLK_VDU_CA, "clk_vdu_ca", "clk_vdu_ca_c", 4, 5),
113 GATE(SCLK_VDU_CORE, "clk_vdu_core", "clk_vdu_core_c", 4, 4),
114 GATE(0, "hclk_vdu_pre", "hclk_vdu_pre_c", 4, 3),
115 GATE(0, "aclk_vdu_pre", "aclk_vdu_pre_c", 4, 2),
116 GATE(0, "hclk_vcodec_pre", "hclk_vcodec_pre_c", 4, 1),
117 GATE(0, "aclk_vcodec_pre", "aclk_vcodec_pre_c", 4, 0),
118
119 /* CRU_CLKGATE_CON5 */
120 /* 15 - 10 unused */
121 GATE(SCLK_MAC_TX, "clk_rmii_tx", "clk_rmii_src", 5, 9),
122 GATE(SCLK_MAC_RX, "clk_rmii_rx", "clk_rmii_src", 5, 8),
123 GATE(SCLK_MACREF, "clk_mac_ref", "clk_rmii_src", 5, 7),
124 GATE(SCLK_MACREF_OUT, "clk_mac_refout", "clk_rmii_src", 5, 6),
125 GATE(SCLK_MAC, "clk_gmac", "clk_gmac_c", 5, 5),
126 GATE(PCLK_PERIHP, "pclk_perihp", "pclk_perihp_c", 5, 4),
127 GATE(HCLK_PERIHP, "hclk_perihp", "hclk_perihp_c", 5, 3),
128 GATE(ACLK_PERIHP, "aclk_perihp", "aclk_perihp_c", 5, 2),
129 GATE(0, "cpll_aclk_perihp_src", "cpll", 5, 1),
130 GATE(0, "gpll_aclk_perihp_src", "gpll", 5, 0),
131
132 /* CRU_CLKGATE_CON6 */
133 /* 15 unused */
134 GATE(SCLK_EMMC, "clk_emmc", "clk_emmc_c", 6, 14),
135 GATE(0, "cpll_aclk_emmc_src", "cpll", 6, 13),
136 GATE(0, "gpll_aclk_emmc_src", "gpll", 6, 12),
137 GATE(0, "pclk_gmac_pre", "pclk_gmac_pre_c", 6, 11),
138 GATE(0, "aclk_gmac_pre", "aclk_gmac_pre_c", 6, 10),
139 GATE(0, "cpll_aclk_gmac_src", "cpll", 6, 9),
140 GATE(0, "gpll_aclk_gmac_src", "gpll", 6, 8),
141 /* 7 unused */
142 GATE(SCLK_USB2PHY1_REF, "clk_usb2phy1_ref", "xin24m", 6, 6),
143 GATE(SCLK_USB2PHY0_REF, "clk_usb2phy0_ref", "xin24m", 6, 5),
144 GATE(SCLK_HSICPHY, "clk_hsicphy", "clk_hsicphy_c", 6, 4),
145 GATE(0, "clk_pcie_core_cru", "clk_pcie_core_cru_c", 6, 3),
146 GATE(SCLK_PCIE_PM, "clk_pcie_pm", "clk_pcie_pm_c", 6, 2),
147 GATE(SCLK_SDMMC, "clk_sdmmc", "clk_sdmmc_c", 6, 1),
148 GATE(SCLK_SDIO, "clk_sdio", "clk_sdio_c", 6, 0),
149
150 /* CRU_CLKGATE_CON7 */
151 /* 15 - 10 unused */
152 GATE(FCLK_CM0S, "fclk_cm0s", "fclk_cm0s_c", 7, 9),
153 GATE(SCLK_CRYPTO1, "clk_crypto1", "clk_crypto1_c", 7, 8),
154 GATE(SCLK_CRYPTO0, "clk_crypto0", "clk_crypto0_c", 7, 7),
155 GATE(0, "cpll_fclk_cm0s_src", "cpll", 7, 6),
156 GATE(0, "gpll_fclk_cm0s_src", "gpll", 7, 5),
157 GATE(PCLK_PERILP0, "pclk_perilp0", "pclk_perilp0_c", 7, 4),
158 GATE(HCLK_PERILP0, "hclk_perilp0", "hclk_perilp0_c", 7, 3),
159 GATE(ACLK_PERILP0, "aclk_perilp0", "aclk_perilp0_c", 7, 2),
160 GATE(0, "cpll_aclk_perilp0_src", "cpll", 7, 1),
161 GATE(0, "gpll_aclk_perilp0_src", "gpll", 7, 0),
162
163 /* CRU_CLKGATE_CON8 */
164 GATE(SCLK_SPDIF_8CH, "clk_spdif", "clk_spdif_mux", 8, 15),
165 GATE(0, "clk_spdif_frac", "clk_spdif_frac_c", 8, 14),
166 GATE(0, "clk_spdif_div", "clk_spdif_div_c", 8, 13),
167 GATE(SCLK_I2S_8CH_OUT, "clk_i2sout", "clk_i2sout_c", 8, 12),
168 GATE(SCLK_I2S2_8CH, "clk_i2s2", "clk_i2s2_mux", 8, 11),
169 GATE(0, "clk_i2s2_frac", "clk_i2s2_frac_c", 8, 10),
170 GATE(0, "clk_i2s2_div", "clk_i2s2_div_c", 8, 9),
171 GATE(SCLK_I2S1_8CH, "clk_i2s1", "clk_i2s1_mux", 8, 8),
172 GATE(0, "clk_i2s1_frac", "clk_i2s1_frac_c", 8, 7),
173 GATE(0, "clk_i2s1_div", "clk_i2s1_div_c", 8, 6),
174 GATE(SCLK_I2S0_8CH, "clk_i2s0", "clk_i2s0_mux", 8, 5),
175 GATE(0, "clk_i2s0_frac","clk_i2s0_frac_c", 8, 4),
176 GATE(0, "clk_i2s0_div","clk_i2s0_div_c", 8, 3),
177 GATE(PCLK_PERILP1, "pclk_perilp1", "pclk_perilp1_c", 8, 2),
178 GATE(HCLK_PERILP1, "cpll_hclk_perilp1_src", "cpll", 8, 1),
179 GATE(0, "gpll_hclk_perilp1_src", "gpll", 8, 0),
180
181 /* CRU_CLKGATE_CON9 */
182 GATE(SCLK_SPI4, "clk_spi4", "clk_spi4_c", 9, 15),
183 GATE(SCLK_SPI2, "clk_spi2", "clk_spi2_c", 9, 14),
184 GATE(SCLK_SPI1, "clk_spi1", "clk_spi1_c", 9, 13),
185 GATE(SCLK_SPI0, "clk_spi0", "clk_spi0_c", 9, 12),
186 GATE(SCLK_SARADC, "clk_saradc", "clk_saradc_c", 9, 11),
187 GATE(SCLK_TSADC, "clk_tsadc", "clk_tsadc_c", 9, 10),
188 /* 9 - 8 unused */
189 GATE(0, "clk_uart3_frac", "clk_uart3_frac_c", 9, 7),
190 GATE(0, "clk_uart3_div", "clk_uart3_div_c", 9, 6),
191 GATE(0, "clk_uart2_frac", "clk_uart2_frac_c", 9, 5),
192 GATE(0, "clk_uart2_div", "clk_uart2_div_c", 9, 4),
193 GATE(0, "clk_uart1_frac", "clk_uart1_frac_c", 9, 3),
194 GATE(0, "clk_uart1_div", "clk_uart1_div_c", 9, 2),
195 GATE(0, "clk_uart0_frac", "clk_uart0_frac_c", 9, 1),
196 GATE(0, "clk_uart0_div", "clk_uart0_div_c", 9, 0),
197
198 /* CRU_CLKGATE_CON10 */
199 GATE(SCLK_VOP1_PWM, "clk_vop1_pwm", "clk_vop1_pwm_c", 10, 15),
200 GATE(SCLK_VOP0_PWM, "clk_vop0_pwm", "clk_vop0_pwm_c", 10, 14),
201 GATE(DCLK_VOP0_DIV, "dclk_vop0_div", "dclk_vop0_div_c", 10, 12),
202 GATE(DCLK_VOP1_DIV, "dclk_vop1_div", "dclk_vop1_div_c", 10, 13),
203 GATE(0, "hclk_vop1_pre", "hclk_vop1_pre_c", 10, 11),
204 GATE(ACLK_VOP1_PRE, "aclk_vop1_pre", "aclk_vop1_pre_c", 10, 10),
205 GATE(0, "hclk_vop0_pre", "hclk_vop0_pre_c", 10, 9),
206 GATE(ACLK_VOP0_PRE, "aclk_vop0_pre", "aclk_vop0_pre_c", 10, 8),
207 GATE(0, "clk_cifout_src", "clk_cifout_src_c", 10, 7),
208 GATE(SCLK_SPDIF_REC_DPTX, "clk_spdif_rec_dptx", "clk_spdif_rec_dptx_c", 10, 6),
209 GATE(SCLK_I2C7, "clk_i2c7", "clk_i2c7_c", 10, 5),
210 GATE(SCLK_I2C3, "clk_i2c3", "clk_i2c3_c", 10, 4),
211 GATE(SCLK_I2C6, "clk_i2c6", "clk_i2c6_c", 10, 3),
212 GATE(SCLK_I2C2, "clk_i2c2", "clk_i2c2_c", 10, 2),
213 GATE(SCLK_I2C5, "clk_i2c5", "clk_i2c5_c", 10, 1),
214 GATE(SCLK_I2C1, "clk_i2c1", "clk_i2c1_c", 10, 0),
215
216 /* CRU_CLKGATE_CON11 */
217 GATE(SCLK_MIPIDPHY_CFG, "clk_mipidphy_cfg", "xin24m", 11, 15),
218 GATE(SCLK_MIPIDPHY_REF, "clk_mipidphy_ref", "xin24m", 11, 14),
219 /* 13-12 unused */
220 GATE(PCLK_EDP, "pclk_edp", "pclk_edp_c", 11, 11),
221 GATE(PCLK_HDCP, "pclk_hdcp", "pclk_hdcp_c", 11, 10),
222 /* 9 unuwsed */
223 GATE(SCLK_DP_CORE, "clk_dp_core", "clk_dp_core_c", 11, 8),
224 GATE(SCLK_HDMI_CEC, "clk_hdmi_cec", "clk_hdmi_cec_c", 11, 7),
225 GATE(SCLK_HDMI_SFR, "clk_hdmi_sfr", "xin24m", 11, 6),
226 GATE(SCLK_ISP1, "clk_isp1", "clk_isp1_c", 11, 5),
227 GATE(SCLK_ISP0, "clk_isp0", "clk_isp0_c", 11, 4),
228 GATE(HCLK_HDCP, "hclk_hdcp", "hclk_hdcp_c", 11, 3),
229 GATE(ACLK_HDCP, "aclk_hdcp", "aclk_hdcp_c", 11, 2),
230 GATE(PCLK_VIO, "pclk_vio", "pclk_vio_c", 11, 1),
231 GATE(ACLK_VIO, "aclk_vio", "aclk_vio_c", 11, 0),
232
233 /* CRU_CLKGATE_CON12 */
234 /* 15 - 14 unused */
235 GATE(HCLK_SD, "hclk_sd", "hclk_sd_c", 12, 13),
236 GATE(ACLK_GIC_PRE, "aclk_gic_pre", "aclk_gic_pre_c", 12, 12),
237 GATE(HCLK_ISP1, "hclk_isp1", "hclk_isp1_c", 12, 11),
238 GATE(ACLK_ISP1, "aclk_isp1", "aclk_isp1_c", 12, 10),
239 GATE(HCLK_ISP0, "hclk_isp0", "hclk_isp0_c", 12, 9),
240 GATE(ACLK_ISP0, "aclk_isp0", "aclk_isp0_c", 12, 8),
241 /* 7 unused */
242 GATE(SCLK_PCIEPHY_REF100M, "clk_pciephy_ref100m", "clk_pciephy_ref100m_c", 12, 6),
243 /* 5 unused */
244 GATE(SCLK_USB3OTG1_SUSPEND, "clk_usb3otg1_suspend", "clk_usb3otg1_suspend_c", 12, 4),
245 GATE(SCLK_USB3OTG0_SUSPEND, "clk_usb3otg0_suspend", "clk_usb3otg0_suspend_c", 12, 3),
246 GATE(SCLK_USB3OTG1_REF, "clk_usb3otg1_ref", "xin24m", 12, 2),
247 GATE(SCLK_USB3OTG0_REF, "clk_usb3otg0_ref", "xin24m", 12, 1),
248 GATE(ACLK_USB3, "aclk_usb3", "aclk_usb3_c", 12, 0),
249
250 /* CRU_CLKGATE_CON13 */
251 GATE(SCLK_TESTCLKOUT2, "clk_testout2", "clk_testout2_c", 13, 15),
252 GATE(SCLK_TESTCLKOUT1, "clk_testout1", "clk_testout1_c", 13, 14),
253 GATE(SCLK_SPI5, "clk_spi5", "clk_spi5_c", 13, 13),
254 GATE(0, "clk_usbphy0_480m_src", "clk_usbphy0_480m", 13, 12),
255 GATE(0, "clk_usbphy1_480m_src", "clk_usbphy1_480m", 13, 12),
256 GATE(0, "clk_test", "clk_test_c", 13, 11),
257 /* 10 unused */
258 GATE(0, "clk_test_frac", "clk_test_frac_c", 13, 9),
259 /* 8 unused */
260 GATE(SCLK_UPHY1_TCPDCORE, "clk_uphy1_tcpdcore", "clk_uphy1_tcpdcore_c", 13, 7),
261 GATE(SCLK_UPHY1_TCPDPHY_REF, "clk_uphy1_tcpdphy_ref", "clk_uphy1_tcpdphy_ref_c", 13, 6),
262 GATE(SCLK_UPHY0_TCPDCORE, "clk_uphy0_tcpdcore", "clk_uphy0_tcpdcore_c", 13, 5),
263 GATE(SCLK_UPHY0_TCPDPHY_REF, "clk_uphy0_tcpdphy_ref", "clk_uphy0_tcpdphy_ref_c", 13, 4),
264 /* 3 - 2 unused */
265 GATE(SCLK_PVTM_GPU, "aclk_pvtm_gpu", "xin24m", 13, 1),
266 GATE(0, "aclk_gpu_pre", "aclk_gpu_pre_c", 13, 0),
267
268 /* CRU_CLKGATE_CON14 */
269 /* 15 - 14 unused */
270 GATE(ACLK_PERF_CORE_L, "aclk_perf_core_l", "aclkm_core_l", 14, 13),
271 GATE(ACLK_CORE_ADB400_CORE_L_2_CCI500, "aclk_core_adb400_core_l_2_cci500", "aclkm_core_l", 14, 12),
272 GATE(ACLK_GIC_ADB400_CORE_L_2_GIC, "aclk_core_adb400_core_l_2_gic", "armclkl", 14, 11),
273 GATE(ACLK_GIC_ADB400_GIC_2_CORE_L, "aclk_core_adb400_gic_2_core_l", "armclkl", 14, 10),
274 GATE(0, "clk_dbg_pd_core_l", "armclkl", 14, 9),
275 /* 8 - 7 unused */
276 GATE(ACLK_PERF_CORE_B, "aclk_perf_core_b", "aclkm_core_b", 14, 6),
277 GATE(ACLK_CORE_ADB400_CORE_B_2_CCI500, "aclk_core_adb400_core_b_2_cci500", "aclkm_core_b", 14, 5),
278 GATE(ACLK_GIC_ADB400_CORE_B_2_GIC, "aclk_core_adb400_core_b_2_gic", "armclkb", 14, 4),
279 GATE(ACLK_GIC_ADB400_GIC_2_CORE_B, "aclk_core_adb400_gic_2_core_b", "armclkb", 14, 3),
280 GATE(0, "pclk_dbg_cxcs_pd_core_b", "pclk_dbg_core_b", 14, 2),
281 GATE(0, "clk_dbg_pd_core_b", "armclkb", 14, 1),
282 /* 0 unused */
283
284 /* CRU_CLKGATE_CON15 */
285 /* 15 - 8 unused */
286 GATE(ACLK_CCI_GRF, "aclk_cci_grf", "aclk_cci_pre", 15, 7),
287 GATE(0, "clk_dbg_noc", "clk_cs", 15, 6),
288 GATE(0, "clk_dbg_cxcs", "clk_cs", 15, 5),
289 GATE(ACLK_CCI_NOC1, "aclk_cci_noc1", "aclk_cci_pre", 15, 4),
290 GATE(ACLK_CCI_NOC0, "aclk_cci_noc0", "aclk_cci_pre", 15, 3),
291 GATE(ACLK_CCI, "aclk_cci", "aclk_cci_pre", 15, 2),
292 GATE(ACLK_ADB400M_PD_CORE_B, "aclk_adb400m_pd_core_b", "aclk_cci_pre", 15, 1),
293 GATE(ACLK_ADB400M_PD_CORE_L, "aclk_adb400m_pd_core_l", "aclk_cci_pre", 15, 0),
294
295 /* CRU_CLKGATE_CON16 */
296 /* 15 - 12 unused */
297 GATE(HCLK_RGA_NOC, "hclk_rga_noc", "hclk_rga_pre", 16, 11),
298 GATE(HCLK_RGA, "hclk_rga", "hclk_rga_pre", 16, 10),
299 GATE(ACLK_RGA_NOC, "aclk_rga_noc", "aclk_rga_pre", 16, 9),
300 GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 16, 8),
301 /* 7 - 4 unused */
302 GATE(HCLK_IEP_NOC, "hclk_iep_noc", "hclk_iep_pre", 16, 3),
303 GATE(HCLK_IEP, "hclk_iep", "hclk_iep_pre", 16, 2),
304 GATE(ACLK_IEP_NOC, "aclk_iep_noc", "aclk_iep_pre", 16, 1),
305 GATE(ACLK_IEP, "aclk_iep", "aclk_iep_pre", 16, 0),
306
307 /* CRU_CLKGATE_CON17 */
308 /* 15 - 12 unused */
309 GATE(HCLK_VDU_NOC, "hclk_vdu_noc", "hclk_vdu_pre", 17, 11),
310 GATE(HCLK_VDU, "hclk_vdu", "hclk_vdu_pre", 17, 10),
311 GATE(ACLK_VDU_NOC, "aclk_vdu_noc", "aclk_vdu_pre", 17, 9),
312 GATE(ACLK_VDU, "aclk_vdu", "aclk_vdu_pre", 17, 8),
313 GATE(0, "hclk_vcodec_noc", "hclk_vcodec_pre", 17, 3),
314 GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 17, 2),
315 GATE(0, "aclk_vcodec_noc", "aclk_vcodec_pre", 17, 1),
316 GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vcodec_pre", 17, 0),
317
318 /* CRU_CLKGATE_CON18 */
319 GATE(PCLK_CIC, "pclk_cic", "pclk_ddr", 18, 15),
320 GATE(0, "clk_ddr_mon_timer", "xin24m", 18, 14),
321 GATE(0, "clk_ddr_mon", "clk_ddrc_div2", 18, 13),
322 GATE(PCLK_DDR_MON, "pclk_ddr_mon", "pclk_ddr", 18, 12),
323 GATE(0, "clk_ddr_cic", "clk_ddrc_div2", 18, 11),
324 GATE(PCLK_CENTER_MAIN_NOC, "pclk_center_main_noc", "pclk_ddr", 18, 10),
325 GATE(0, "clk_ddrcfg_msch1", "clk_ddrc_div2", 18, 9),
326 GATE(0, "clk_ddrphy1", "clk_ddrc_div2", 18, 8),
327 GATE(0, "clk_ddrphy_ctrl1", "clk_ddrc_div2", 18, 7),
328 GATE(0, "clk_ddrc1", "clk_ddrc_div2", 18, 6),
329 GATE(0, "clk_ddr1_msch", "clk_ddrc_div2", 18, 5),
330 GATE(0, "clk_ddrcfg_msch0", "clk_ddrc_div2", 18, 4),
331 GATE(0, "clk_ddrphy0", "clk_ddrc_div2", 18, 3),
332 GATE(0, "clk_ddrphy_ctrl0", "clk_ddrc_div2", 18, 2),
333 GATE(0, "clk_ddrc0", "clk_ddrc_div2", 18, 1),
334
335 /* CRU_CLKGATE_CON19 */
336 /* 15 - 3 unused */
337 GATE(PCLK_DDR_SGRF, "pclk_ddr_sgrf", "pclk_ddr", 19, 2),
338 GATE(ACLK_CENTER_PERI_NOC, "aclk_center_peri_noc", "aclk_center", 19, 1),
339 GATE(ACLK_CENTER_MAIN_NOC, "aclk_center_main_noc", "aclk_center", 19, 0),
340
341 /* CRU_CLKGATE_CON20 */
342 GATE(0, "hclk_ahb1tom", "hclk_perihp", 20, 15),
343 GATE(0, "pclk_perihp_noc", "pclk_perihp", 20, 14),
344 GATE(0, "hclk_perihp_noc", "hclk_perihp", 20, 13),
345 GATE(0, "aclk_perihp_noc", "aclk_perihp", 20, 12),
346 GATE(PCLK_PCIE, "pclk_pcie", "pclk_perihp", 20, 11),
347 GATE(ACLK_PCIE, "aclk_pcie", "aclk_perihp", 20, 10),
348 GATE(HCLK_HSIC, "hclk_hsic", "hclk_perihp", 20, 9),
349 GATE(HCLK_HOST1_ARB, "hclk_host1_arb", "hclk_perihp", 20, 8),
350 GATE(HCLK_HOST1, "hclk_host1", "hclk_perihp", 20, 7),
351 GATE(HCLK_HOST0_ARB, "hclk_host0_arb", "hclk_perihp", 20, 6),
352 GATE(HCLK_HOST0, "hclk_host0", "hclk_perihp", 20, 5),
353 GATE(PCLK_PERIHP_GRF, "pclk_perihp_grf", "pclk_perihp", 20, 4),
354 GATE(ACLK_PERF_PCIE, "aclk_perf_pcie", "aclk_perihp", 20, 2),
355 /* 1 - 0 unused */
356
357 /* CRU_CLKGATE_CON21 */
358 /* 15 - 10 unused */
359 GATE(PCLK_UPHY1_TCPD_G, "pclk_uphy1_tcpd_g", "pclk_alive", 21, 9),
360 GATE(PCLK_UPHY1_TCPHY_G, "pclk_uphy1_tcphy_g", "pclk_alive", 21, 8),
361 /* 7 unused */
362 GATE(PCLK_UPHY0_TCPD_G, "pclk_uphy0_tcpd_g", "pclk_alive", 21, 6),
363 GATE(PCLK_UPHY0_TCPHY_G, "pclk_uphy0_tcphy_g", "pclk_alive", 21, 5),
364 GATE(PCLK_USBPHY_MUX_G, "pclk_usbphy_mux_g", "pclk_alive", 21, 4),
365 GATE(SCLK_DPHY_RX0_CFG, "clk_dphy_rx0_cfg", "clk_mipidphy_cfg", 21, 3),
366 GATE(SCLK_DPHY_TX1RX1_CFG, "clk_dphy_tx1rx1_cfg", "clk_mipidphy_cfg", 21, 2),
367 GATE(SCLK_DPHY_TX0_CFG, "clk_dphy_tx0_cfg", "clk_mipidphy_cfg", 21, 1),
368 GATE(SCLK_DPHY_PLL, "clk_dphy_pll", "clk_mipidphy_ref", 21, 0),
369
370 /* CRU_CLKGATE_CON22 */
371 GATE(PCLK_EFUSE1024S, "pclk_efuse1024s", "pclk_perilp1", 22, 15),
372 GATE(PCLK_EFUSE1024NS, "pclk_efuse1024ns", "pclk_perilp1", 22, 14),
373 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_perilp1", 22, 13),
374 GATE(PCLK_SARADC, "pclk_saradc", "pclk_perilp1", 22, 12),
375 GATE(PCLK_MAILBOX0, "pclk_mailbox0", "pclk_perilp1", 22, 11),
376 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_perilp1", 22, 10),
377 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_perilp1", 22, 9),
378 GATE(PCLK_I2C6, "pclk_i2c6", "pclk_perilp1", 22, 8),
379 GATE(PCLK_I2C5, "pclk_i2c5", "pclk_perilp1", 22, 7),
380 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_perilp1", 22, 6),
381 GATE(PCLK_I2C7, "pclk_i2c7", "pclk_perilp1", 22, 5),
382 GATE(PCLK_UART3, "pclk_uart3", "pclk_perilp1", 22, 3),
383 GATE(PCLK_UART2, "pclk_uart2", "pclk_perilp1", 22, 2),
384 GATE(PCLK_UART1, "pclk_uart1", "pclk_perilp1", 22, 1),
385 GATE(PCLK_UART0, "pclk_uart0", "pclk_perilp1", 22, 0),
386
387 /* CRU_CLKGATE_CON23 */
388 /* 15 - 14 unused */
389 GATE(PCLK_SPI4, "pclk_spi4", "pclk_perilp1", 23, 13),
390 GATE(PCLK_SPI2, "pclk_spi2", "pclk_perilp1", 23, 12),
391 GATE(PCLK_SPI1, "pclk_spi1", "pclk_perilp1", 23, 11),
392 GATE(PCLK_SPI0, "pclk_spi0", "pclk_perilp1", 23, 10),
393 GATE(PCLK_DCF, "pclk_dcf", "pclk_perilp0", 23, 9),
394 GATE(ACLK_DCF, "aclk_dcf", "aclk_perilp0", 23, 8),
395 GATE(SCLK_INTMEM5, "clk_intmem5", "aclk_perilp0", 23, 7),
396 GATE(SCLK_INTMEM4, "clk_intmem4", "aclk_perilp0", 23, 6),
397 GATE(SCLK_INTMEM3, "clk_intmem3", "aclk_perilp0", 23, 5),
398 GATE(SCLK_INTMEM2, "clk_intmem2", "aclk_perilp0", 23, 4),
399 GATE(SCLK_INTMEM1, "clk_intmem1", "aclk_perilp0", 23, 3),
400 GATE(SCLK_INTMEM0, "clk_intmem0", "aclk_perilp0", 23, 2),
401 GATE(ACLK_TZMA, "aclk_tzma", "aclk_perilp0", 23, 1),
402 GATE(ACLK_INTMEM, "aclk_intmem", "aclk_perilp0", 23, 0),
403
404 /* CRU_CLKGATE_CON24 */
405 GATE(HCLK_S_CRYPTO1, "hclk_s_crypto1", "hclk_perilp0", 24, 15),
406 GATE(HCLK_M_CRYPTO1, "hclk_m_crypto1", "hclk_perilp0", 24, 14),
407 GATE(PCLK_PERIHP_GRF, "pclk_perilp_sgrf", "pclk_perilp1", 24, 13),
408 GATE(SCLK_M0_PERILP_DEC, "clk_m0_perilp_dec", "fclk_cm0s", 24, 11),
409 GATE(DCLK_M0_PERILP, "dclk_m0_perilp", "fclk_cm0s", 24, 10),
410 GATE(HCLK_M0_PERILP, "hclk_m0_perilp", "fclk_cm0s", 24, 9),
411 GATE(SCLK_M0_PERILP, "sclk_m0_perilp", "fclk_cm0s", 24, 8),
412 /* 7 - unused */
413 GATE(HCLK_S_CRYPTO0, "hclk_s_crypto0", "hclk_perilp0", 24, 6),
414 GATE(HCLK_M_CRYPTO0, "hclk_m_crypto0", "hclk_perilp0", 24, 5),
415 GATE(HCLK_ROM, "hclk_rom", "hclk_perilp0", 24, 4),
416 /* 3 - 0 unused */
417
418 /* CRU_CLKGATE_CON25 */
419 /* 15 - 13 unused */
420 GATE(0, "hclk_sdio_noc", "hclk_perilp1", 25, 12),
421 GATE(HCLK_M0_PERILP_NOC, "hclk_m0_perilp_noc", "fclk_cm0s", 25, 11),
422 GATE(0, "pclk_perilp1_noc", "pclk_perilp1", 25, 10),
423 GATE(0, "hclk_perilp1_noc", "hclk_perilp1", 25, 9),
424 GATE(HCLK_PERILP0_NOC, "hclk_perilp0_noc", "hclk_perilp0", 25, 8),
425 GATE(ACLK_PERILP0_NOC, "aclk_perilp0_noc", "aclk_perilp0", 25, 7),
426 GATE(ACLK_DMAC1_PERILP, "aclk_dmac1_perilp", "aclk_perilp0", 25, 6),
427 GATE(ACLK_DMAC0_PERILP, "aclk_dmac0_perilp", "aclk_perilp0", 25, 5),
428 /* 4 - 0 unused */
429
430 /* CRU_CLKGATE_CON26 */
431 /* 15 - 12 unused */
432 GATE(SCLK_TIMER11, "clk_timer11", "xin24m", 26, 11),
433 GATE(SCLK_TIMER10, "clk_timer10", "xin24m", 26, 10),
434 GATE(SCLK_TIMER09, "clk_timer09", "xin24m", 26, 9),
435 GATE(SCLK_TIMER08, "clk_timer08", "xin24m", 26, 8),
436 GATE(SCLK_TIMER07, "clk_timer07", "xin24m", 26, 7),
437 GATE(SCLK_TIMER06, "clk_timer06", "xin24m", 26, 6),
438 GATE(SCLK_TIMER05, "clk_timer05", "xin24m", 26, 5),
439 GATE(SCLK_TIMER04, "clk_timer04", "xin24m", 26, 4),
440 GATE(SCLK_TIMER03, "clk_timer03", "xin24m", 26, 3),
441 GATE(SCLK_TIMER02, "clk_timer02", "xin24m", 26, 2),
442 GATE(SCLK_TIMER01, "clk_timer01", "xin24m", 26, 1),
443 GATE(SCLK_TIMER00, "clk_timer00", "xin24m", 26, 0),
444
445 /* CRU_CLKGATE_CON27 */
446 /* 15 - 9 unused */
447 GATE(ACLK_ISP1_WRAPPER, "aclk_isp1_wrapper", "hclk_isp1", 27, 8),
448 GATE(HCLK_ISP1_WRAPPER, "hclk_isp1_wrapper", "aclk_isp0", 27, 7),
449 GATE(PCLK_ISP1_WRAPPER, "pclkin_isp1_wrapper", "pclkin_cif", 27, 6),
450 GATE(ACLK_ISP0_WRAPPER, "aclk_isp0_wrapper", "aclk_isp0", 27, 5),
451 GATE(HCLK_ISP0_WRAPPER, "hclk_isp0_wrapper", "hclk_isp0", 27, 4),
452 GATE(ACLK_ISP1_NOC, "aclk_isp1_noc", "aclk_isp1", 27, 3),
453 GATE(HCLK_ISP1_NOC, "hclk_isp1_noc", "hclk_isp1", 27, 2),
454 GATE(ACLK_ISP0_NOC, "aclk_isp0_noc", "aclk_isp0", 27, 1),
455 GATE(HCLK_ISP0_NOC, "hclk_isp0_noc", "hclk_isp0", 27, 0),
456
457 /* CRU_CLKGATE_CON28 */
458 /* 15 - 8 unused */
459 GATE(ACLK_VOP1, "aclk_vop1", "aclk_vop1_pre", 28, 7),
460 GATE(HCLK_VOP1, "hclk_vop1", "hclk_vop1_pre", 28, 6),
461 GATE(ACLK_VOP1_NOC, "aclk_vop1_noc", "aclk_vop1_pre", 28, 5),
462 GATE(HCLK_VOP1_NOC, "hclk_vop1_noc", "hclk_vop1_pre", 28, 4),
463 GATE(ACLK_VOP0, "aclk_vop0", "aclk_vop0_pre", 28, 3),
464 GATE(HCLK_VOP0, "hclk_vop0", "hclk_vop0_pre", 28, 2),
465 GATE(ACLK_VOP0_NOC, "aclk_vop0_noc", "aclk_vop0_pre", 28, 1),
466 GATE(HCLK_VOP0_NOC, "hclk_vop0_noc", "hclk_vop0_pre", 28, 0),
467
468 /* CRU_CLKGATE_CON29 */
469 /* 15 - 13 unused */
470 GATE(PCLK_VIO_GRF, "pclk_vio_grf", "pclk_vio", 29, 12),
471 GATE(PCLK_GASKET, "pclk_gasket", "pclk_hdcp", 29, 11),
472 GATE(ACLK_HDCP22, "aclk_hdcp22", "aclk_hdcp", 29, 10),
473 GATE(HCLK_HDCP22, "hclk_hdcp22", "hclk_hdcp", 29, 9),
474 GATE(PCLK_HDCP22, "pclk_hdcp22", "pclk_hdcp", 29, 8),
475 GATE(PCLK_DP_CTRL, "pclk_dp_ctrl", "pclk_hdcp", 29, 7),
476 GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "pclk_hdcp", 29, 6),
477 GATE(HCLK_HDCP_NOC, "hclk_hdcp_noc", "hclk_hdcp", 29, 5),
478 GATE(ACLK_HDCP_NOC, "aclk_hdcp_noc", "aclk_hdcp", 29, 4),
479 GATE(PCLK_HDCP_NOC, "pclk_hdcp_noc", "pclk_hdcp", 29, 3),
480 GATE(PCLK_MIPI_DSI1, "pclk_mipi_dsi1", "pclk_vio", 29, 2),
481 GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "pclk_vio", 29, 1),
482 GATE(ACLK_VIO_NOC, "aclk_vio_noc", "aclk_vio", 29, 0),
483
484 /* CRU_CLKGATE_CON30 */
485 /* 15 - 12 unused */
486 GATE(ACLK_GPU_GRF, "aclk_gpu_grf", "aclk_gpu_pre", 30, 11),
487 GATE(ACLK_PERF_GPU, "aclk_perf_gpu", "aclk_gpu_pre", 30, 10),
488 /* 9 unused */
489 GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", 30, 8),
490 /* 7 - 5 unused */
491 GATE(ACLK_USB3_GRF, "aclk_usb3_grf", "aclk_usb3", 30, 4),
492 GATE(ACLK_USB3_RKSOC_AXI_PERF, "aclk_usb3_rksoc_axi_perf", "aclk_usb3", 30, 3),
493 GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_usb3", 30, 2),
494 GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb3", 30, 1),
495 GATE(ACLK_USB3_NOC, "aclk_usb3_noc", "aclk_usb3", 30, 0),
496
497 /* CRU_CLKGATE_CON31 */
498 /* 15 - 11 unused */
499 GATE(PCLK_SGRF, "pclk_sgrf", "pclk_alive", 31, 10),
500 GATE(PCLK_PMU_INTR_ARB, "pclk_pmu_intr_arb", "pclk_alive", 31, 9),
501 GATE(PCLK_HSICPHY, "pclk_hsicphy", "pclk_perihp", 31, 8),
502 GATE(PCLK_TIMER1, "pclk_timer1", "pclk_alive", 31, 7),
503 GATE(PCLK_TIMER0, "pclk_timer0", "pclk_alive", 31, 6),
504 GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_alive", 31, 5),
505 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_alive", 31, 4),
506 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_alive", 31, 3),
507 GATE(PCLK_INTR_ARB, "pclk_intr_arb", "pclk_alive", 31, 2),
508 GATE(PCLK_GRF, "pclk_grf", "pclk_alive", 31, 1),
509 /* 0 unused */
510
511 /* CRU_CLKGATE_CON32 */
512 /* 15 - 14 unused */
513 GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "pclk_edp", 32, 13),
514 GATE(PCLK_EDP_NOC, "pclk_edp_noc", "pclk_edp", 32, 12),
515 /* 11 unused */
516 GATE(ACLK_EMMC_GRF, "aclk_emmcgrf", "aclk_emmc", 32, 10),
517 GATE(ACLK_EMMC_NOC, "aclk_emmc_noc", "aclk_emmc", 32, 9),
518 GATE(ACLK_EMMC_CORE, "aclk_emmccore", "aclk_emmc", 32, 8),
519 /* 7 - 5 unused */
520 GATE(ACLK_PERF_GMAC, "aclk_perf_gmac", "aclk_gmac_pre", 32, 4),
521 GATE(PCLK_GMAC_NOC, "pclk_gmac_noc", "pclk_gmac_pre", 32, 3),
522 GATE(PCLK_GMAC, "pclk_gmac", "pclk_gmac_pre", 32, 2),
523 GATE(ACLK_GMAC_NOC, "aclk_gmac_noc", "aclk_gmac_pre", 32, 1),
524 GATE(ACLK_GMAC, "aclk_gmac", "aclk_gmac_pre", 32, 0),
525
526 /* CRU_CLKGATE_CON33 */
527 /* 15 - 10 unused */
528 GATE(0, "hclk_sdmmc_noc", "hclk_sd", 33, 9),
529 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sd", 33, 8),
530 GATE(ACLK_GIC_ADB400_GIC_2_CORE_B, "aclk_gic_adb400_gic_2_core_b", "aclk_gic_pre", 33, 5),
531 GATE(ACLK_GIC_ADB400_GIC_2_CORE_L, "aclk_gic_adb400_gic_2_core_l", "aclk_gic_pre", 33, 4),
532 GATE(ACLK_GIC_ADB400_CORE_B_2_GIC, "aclk_gic_adb400_core_b_2_gic", "aclk_gic_pre", 33, 3),
533 GATE(ACLK_GIC_ADB400_CORE_L_2_GIC, "aclk_gic_adb400_core_l_2_gic", "aclk_gic_pre", 33, 2),
534 GATE(ACLK_GIC_NOC, "aclk_gic_noc", "aclk_gic_pre", 33, 1),
535 GATE(ACLK_GIC, "aclk_gic", "aclk_gic_pre", 33, 0),
536
537 /* CRU_CLKGATE_CON34 */
538 /* 15 - 7 unused */
539 GATE(0, "hclk_sdioaudio_noc", "hclk_perilp1", 34, 6),
540 GATE(PCLK_SPI5, "pclk_spi5", "hclk_perilp1", 34, 5),
541 GATE(HCLK_SDIO, "hclk_sdio", "hclk_perilp1", 34, 4),
542 GATE(HCLK_SPDIF, "hclk_spdif", "hclk_perilp1", 34, 3),
543 GATE(HCLK_I2S2_8CH, "hclk_i2s2", "hclk_perilp1", 34, 2),
544 GATE(HCLK_I2S1_8CH, "hclk_i2s1", "hclk_perilp1", 34, 1),
545 GATE(HCLK_I2S0_8CH, "hclk_i2s0", "hclk_perilp1", 34, 0),
546 };
547
548 #define PLL_RATE(_hz, _ref, _fb, _post1, _post2, _dspd) \
549 { \
550 .freq = _hz, \
551 .refdiv = _ref, \
552 .fbdiv = _fb, \
553 .postdiv1 = _post1, \
554 .postdiv2 = _post2, \
555 .dsmpd = _dspd, \
556 }
557
558 static struct rk_clk_pll_rate rk3399_pll_rates[] = {
559 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
560 PLL_RATE(2208000000, 1, 92, 1, 1, 1),
561 PLL_RATE(2184000000, 1, 91, 1, 1, 1),
562 PLL_RATE(2160000000, 1, 90, 1, 1, 1),
563 PLL_RATE(2136000000, 1, 89, 1, 1, 1),
564 PLL_RATE(2112000000, 1, 88, 1, 1, 1),
565 PLL_RATE(2088000000, 1, 87, 1, 1, 1),
566 PLL_RATE(2064000000, 1, 86, 1, 1, 1),
567 PLL_RATE(2040000000, 1, 85, 1, 1, 1),
568 PLL_RATE(2016000000, 1, 84, 1, 1, 1),
569 PLL_RATE(1992000000, 1, 83, 1, 1, 1),
570 PLL_RATE(1968000000, 1, 82, 1, 1, 1),
571 PLL_RATE(1944000000, 1, 81, 1, 1, 1),
572 PLL_RATE(1920000000, 1, 80, 1, 1, 1),
573 PLL_RATE(1896000000, 1, 79, 1, 1, 1),
574 PLL_RATE(1872000000, 1, 78, 1, 1, 1),
575 PLL_RATE(1848000000, 1, 77, 1, 1, 1),
576 PLL_RATE(1824000000, 1, 76, 1, 1, 1),
577 PLL_RATE(1800000000, 1, 75, 1, 1, 1),
578 PLL_RATE(1776000000, 1, 74, 1, 1, 1),
579 PLL_RATE(1752000000, 1, 73, 1, 1, 1),
580 PLL_RATE(1728000000, 1, 72, 1, 1, 1),
581 PLL_RATE(1704000000, 1, 71, 1, 1, 1),
582 PLL_RATE(1680000000, 1, 70, 1, 1, 1),
583 PLL_RATE(1656000000, 1, 69, 1, 1, 1),
584 PLL_RATE(1632000000, 1, 68, 1, 1, 1),
585 PLL_RATE(1608000000, 1, 67, 1, 1, 1),
586 PLL_RATE(1600000000, 3, 200, 1, 1, 1),
587 PLL_RATE(1584000000, 1, 66, 1, 1, 1),
588 PLL_RATE(1560000000, 1, 65, 1, 1, 1),
589 PLL_RATE(1536000000, 1, 64, 1, 1, 1),
590 PLL_RATE(1512000000, 1, 63, 1, 1, 1),
591 PLL_RATE(1488000000, 1, 62, 1, 1, 1),
592 PLL_RATE(1464000000, 1, 61, 1, 1, 1),
593 PLL_RATE(1440000000, 1, 60, 1, 1, 1),
594 PLL_RATE(1416000000, 1, 59, 1, 1, 1),
595 PLL_RATE(1392000000, 1, 58, 1, 1, 1),
596 PLL_RATE(1368000000, 1, 57, 1, 1, 1),
597 PLL_RATE(1344000000, 1, 56, 1, 1, 1),
598 PLL_RATE(1320000000, 1, 55, 1, 1, 1),
599 PLL_RATE(1296000000, 1, 54, 1, 1, 1),
600 PLL_RATE(1272000000, 1, 53, 1, 1, 1),
601 PLL_RATE(1248000000, 1, 52, 1, 1, 1),
602 PLL_RATE(1200000000, 1, 50, 1, 1, 1),
603 PLL_RATE(1188000000, 2, 99, 1, 1, 1),
604 PLL_RATE(1104000000, 1, 46, 1, 1, 1),
605 PLL_RATE(1100000000, 12, 550, 1, 1, 1),
606 PLL_RATE(1008000000, 1, 84, 2, 1, 1),
607 PLL_RATE(1000000000, 1, 125, 3, 1, 1),
608 PLL_RATE( 984000000, 1, 82, 2, 1, 1),
609 PLL_RATE( 960000000, 1, 80, 2, 1, 1),
610 PLL_RATE( 936000000, 1, 78, 2, 1, 1),
611 PLL_RATE( 912000000, 1, 76, 2, 1, 1),
612 PLL_RATE( 900000000, 4, 300, 2, 1, 1),
613 PLL_RATE( 888000000, 1, 74, 2, 1, 1),
614 PLL_RATE( 864000000, 1, 72, 2, 1, 1),
615 PLL_RATE( 840000000, 1, 70, 2, 1, 1),
616 PLL_RATE( 816000000, 1, 68, 2, 1, 1),
617 PLL_RATE( 800000000, 1, 100, 3, 1, 1),
618 PLL_RATE( 700000000, 6, 350, 2, 1, 1),
619 PLL_RATE( 696000000, 1, 58, 2, 1, 1),
620 PLL_RATE( 676000000, 3, 169, 2, 1, 1),
621 PLL_RATE( 600000000, 1, 75, 3, 1, 1),
622 PLL_RATE( 594000000, 1, 99, 4, 1, 1),
623 PLL_RATE( 533250000, 8, 711, 4, 1, 1),
624 PLL_RATE( 504000000, 1, 63, 3, 1, 1),
625 PLL_RATE( 500000000, 6, 250, 2, 1, 1),
626 PLL_RATE( 408000000, 1, 68, 2, 2, 1),
627 PLL_RATE( 312000000, 1, 52, 2, 2, 1),
628 PLL_RATE( 297000000, 1, 99, 4, 2, 1),
629 PLL_RATE( 216000000, 1, 72, 4, 2, 1),
630 PLL_RATE( 148500000, 1, 99, 4, 4, 1),
631 PLL_RATE( 106500000, 1, 71, 4, 4, 1),
632 PLL_RATE( 96000000, 1, 64, 4, 4, 1),
633 PLL_RATE( 74250000, 2, 99, 4, 4, 1),
634 PLL_RATE( 65000000, 1, 65, 6, 4, 1),
635 PLL_RATE( 54000000, 1, 54, 6, 4, 1),
636 PLL_RATE( 27000000, 1, 27, 6, 4, 1),
637 {},
638 };
639
640 static struct rk_clk_armclk_rates rk3399_cpu_l_rates[] = {
641 {1800000000, 1},
642 {1704000000, 1},
643 {1608000000, 1},
644 {1512000000, 1},
645 {1488000000, 1},
646 {1416000000, 1},
647 {1200000000, 1},
648 {1008000000, 1},
649 { 816000000, 1},
650 { 696000000, 1},
651 { 600000000, 1},
652 { 408000000, 1},
653 { 312000000, 1},
654 { 216000000, 1},
655 { 96000000, 1},
656 };
657
658 static struct rk_clk_armclk_rates rk3399_cpu_b_rates[] = {
659 {2208000000, 1},
660 {2184000000, 1},
661 {2088000000, 1},
662 {2040000000, 1},
663 {2016000000, 1},
664 {1992000000, 1},
665 {1896000000, 1},
666 {1800000000, 1},
667 {1704000000, 1},
668 {1608000000, 1},
669 {1512000000, 1},
670 {1488000000, 1},
671 {1416000000, 1},
672 {1200000000, 1},
673 {1008000000, 1},
674 { 816000000, 1},
675 { 696000000, 1},
676 { 600000000, 1},
677 { 408000000, 1},
678 { 312000000, 1},
679 { 216000000, 1},
680 { 96000000, 1},
681 };
682
683 /* Standard PLL. */
684 #define PLL(_id, _name, _base) \
685 { \
686 .type = RK3399_CLK_PLL, \
687 .clk.pll = &(struct rk_clk_pll_def) { \
688 .clkdef.id = _id, \
689 .clkdef.name = _name, \
690 .clkdef.parent_names = pll_src_p, \
691 .clkdef.parent_cnt = nitems(pll_src_p), \
692 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
693 .base_offset = _base, \
694 .rates = rk3399_pll_rates, \
695 }, \
696 }
697
698 #define PLIST(_name) static const char *_name[]
699 PLIST(pll_src_p) = {"xin24m", "xin32k"};
700
701 PLIST(armclkl_p) = {"clk_core_l_lpll_src", "clk_core_l_bpll_src",
702 "clk_core_l_dpll_src", "clk_core_l_gpll_src"};
703 PLIST(armclkb_p) = {"clk_core_b_lpll_src", "clk_core_b_bpll_src",
704 "clk_core_b_dpll_src", "clk_core_b_gpll_src"};
705 PLIST(ddrclk_p) = {"clk_ddrc_lpll_src", "clk_ddrc_bpll_src",
706 "clk_ddrc_dpll_src", "clk_ddrc_gpll_src"};
707 PLIST(pll_src_cpll_gpll_p) = {"cpll", "gpll"};
708 PLIST(pll_src_cpll_gpll_ppll_p) = {"cpll", "gpll", "ppll"};
709 PLIST(pll_src_cpll_gpll_upll_p) = {"cpll", "gpll", "upll"};
710 PLIST(pll_src_npll_cpll_gpll_p) = {"npll", "cpll", "gpll"};
711 PLIST(pll_src_cpll_gpll_npll_npll_p) = {"cpll", "gpll", "npll", "npll"};
712 PLIST(pll_src_cpll_gpll_npll_ppll_p) = {"cpll", "gpll", "npll", "ppll" };
713 PLIST(pll_src_cpll_gpll_npll_24m_p) = {"cpll", "gpll", "npll", "xin24m" };
714 PLIST(pll_src_cpll_gpll_npll_usbphy480m_p)= {"cpll", "gpll", "npll", "clk_usbphy_480m" };
715 PLIST(pll_src_ppll_cpll_gpll_npll_upll_p) = { "ppll", "cpll", "gpll", "npll", "upll" };
716 PLIST(pll_src_cpll_gpll_npll_upll_24m_p)= { "cpll", "gpll", "npll", "upll", "xin24m" };
717 PLIST(pll_src_cpll_gpll_npll_ppll_upll_24m_p) = { "cpll", "gpll", "npll", "ppll", "upll", "xin24m" };
718 PLIST(pll_src_vpll_cpll_gpll_gpll_p) = {"vpll", "cpll", "gpll", "gpll"};
719 PLIST(pll_src_vpll_cpll_gpll_npll_p) = {"vpll", "cpll", "gpll", "npll"};
720
721 PLIST(aclk_cci_p) = {"cpll_aclk_cci_src", "gpll_aclk_cci_src",
722 "npll_aclk_cci_src", "vpll_aclk_cci_src"};
723 PLIST(cci_trace_p) = {"cpll_cci_trace","gpll_cci_trace"};
724 PLIST(cs_p)= {"cpll_cs", "gpll_cs", "npll_cs","npll_cs"};
725 PLIST(aclk_perihp_p)= {"cpll_aclk_perihp_src", "gpll_aclk_perihp_src" };
726 PLIST(dclk_vop0_p) = {"dclk_vop0_div", "dclk_vop0_frac"};
727 PLIST(dclk_vop1_p)= {"dclk_vop1_div", "dclk_vop1_frac"};
728
729 PLIST(clk_cif_p) = {"clk_cifout_src", "xin24m"};
730
731 PLIST(pll_src_24m_usbphy480m_p) = { "xin24m", "clk_usbphy_480m"};
732 PLIST(pll_src_24m_pciephy_p) = { "xin24m", "clk_pciephy_ref100m"};
733 PLIST(pll_src_24m_32k_cpll_gpll_p)= {"xin24m", "xin32k", "cpll", "gpll"};
734 PLIST(pciecore_cru_phy_p) = {"clk_pcie_core_cru", "clk_pcie_core_phy"};
735
736 PLIST(aclk_emmc_p) = { "cpll_aclk_emmc_src", "gpll_aclk_emmc_src"};
737
738 PLIST(aclk_perilp0_p) = { "cpll_aclk_perilp0_src",
739 "gpll_aclk_perilp0_src" };
740
741 PLIST(fclk_cm0s_p) = { "cpll_fclk_cm0s_src",
742 "gpll_fclk_cm0s_src" };
743
744 PLIST(hclk_perilp1_p) = { "cpll_hclk_perilp1_src",
745 "gpll_hclk_perilp1_src" };
746
747 PLIST(clk_testout1_p) = { "clk_testout1_pll_src", "xin24m" };
748 PLIST(clk_testout2_p) = { "clk_testout2_pll_src", "xin24m" };
749
750 PLIST(usbphy_480m_p) = { "clk_usbphy0_480m_src",
751 "clk_usbphy1_480m_src" };
752 PLIST(aclk_gmac_p) = { "cpll_aclk_gmac_src",
753 "gpll_aclk_gmac_src" };
754 PLIST(rmii_p) = { "clk_gmac", "clkin_gmac" };
755 PLIST(spdif_p) = { "clk_spdif_div", "clk_spdif_frac",
756 "clkin_i2s", "xin12m" };
757 PLIST(i2s0_p) = { "clk_i2s0_div", "clk_i2s0_frac",
758 "clkin_i2s", "xin12m" };
759 PLIST(i2s1_p) = { "clk_i2s1_div", "clk_i2s1_frac",
760 "clkin_i2s", "xin12m" };
761 PLIST(i2s2_p) = { "clk_i2s2_div", "clk_i2s2_frac",
762 "clkin_i2s", "xin12m" };
763 PLIST(i2sch_p) = {"clk_i2s0", "clk_i2s1", "clk_i2s2"};
764 PLIST(i2sout_p) = {"clk_i2sout_src", "xin12m"};
765
766 PLIST(uart0_p)= {"clk_uart0_div", "clk_uart0_frac", "xin24m"};
767 PLIST(uart1_p)= {"clk_uart1_div", "clk_uart1_frac", "xin24m"};
768 PLIST(uart2_p)= {"clk_uart2_div", "clk_uart2_frac", "xin24m"};
769 PLIST(uart3_p)= {"clk_uart3_div", "clk_uart3_frac", "xin24m"};
770
771 static struct rk_clk rk3399_clks[] = {
772 /* External clocks */
773 LINK("xin24m"),
774 FRATE(0, "xin32k", 32768),
775 FFACT(0, "xin12m", "xin24m", 1, 2),
776 FRATE(0, "clkin_i2s", 0),
777 FRATE(0, "pclkin_cif", 0),
778 LINK("clk_usbphy0_480m"),
779 LINK("clk_usbphy1_480m"),
780 LINK("clkin_gmac"),
781 FRATE(0, "clk_pcie_core_phy", 0),
782 FFACT(0, "clk_ddrc_div2", "clk_ddrc", 1, 2),
783
784 /* PLLs */
785 PLL(PLL_APLLL, "lpll", 0x00),
786 PLL(PLL_APLLB, "bpll", 0x20),
787 PLL(PLL_DPLL, "dpll", 0x40),
788 PLL(PLL_CPLL, "cpll", 0x60),
789 PLL(PLL_GPLL, "gpll", 0x80),
790 PLL(PLL_NPLL, "npll", 0xA0),
791 PLL(PLL_VPLL, "vpll", 0xC0),
792
793 /* CRU_CLKSEL_CON0 */
794 CDIV(0, "aclkm_core_l_c", "armclkl", 0,
795 0, 8, 5),
796 ARMDIV(ARMCLKL, "armclkl", armclkl_p, rk3399_cpu_l_rates,
797 0, 0, 5, 6, 2, 0, 3),
798 /* CRU_CLKSEL_CON1 */
799 CDIV(0, "pclk_dbg_core_l_c", "armclkl", 0,
800 1, 8, 5),
801 CDIV(0, "atclk_core_l_c", "armclkl", 0,
802 1, 0, 5),
803
804 /* CRU_CLKSEL_CON2 */
805 CDIV(0, "aclkm_core_b_c", "armclkb", 0,
806 2, 8, 5),
807 ARMDIV(ARMCLKB, "armclkb", armclkb_p, rk3399_cpu_b_rates,
808 2, 0, 5, 6, 2, 1, 3),
809
810 /* CRU_CLKSEL_CON3 */
811 CDIV(0, "pclken_dbg_core_b", "pclk_dbg_core_b", 0,
812 3, 13, 2),
813 CDIV(0, "pclk_dbg_core_b_c", "armclkb", 0,
814 3, 8, 5),
815 CDIV(0, "atclk_core_b_c", "armclkb", 0,
816 3, 0, 5),
817
818 /* CRU_CLKSEL_CON4 */
819 COMP(0, "clk_cs", cs_p, 0,
820 4, 0, 5, 6, 2),
821
822 /* CRU_CLKSEL_CON5 */
823 COMP(0, "clk_cci_trace_c", cci_trace_p, 0,
824 5, 8, 5, 15, 1),
825 COMP(0, "aclk_cci_pre_c", aclk_cci_p, 0,
826 5, 0, 5, 6, 2),
827
828 /* CRU_CLKSEL_CON6 */
829 COMP(0, "pclk_ddr_c", pll_src_cpll_gpll_p, 0,
830 6, 8, 5, 15, 1),
831 COMP(SCLK_DDRC, "clk_ddrc", ddrclk_p, 0,
832 6, 0, 3, 4, 2),
833
834 /* CRU_CLKSEL_CON7 */
835 CDIV(0, "hclk_vcodec_pre_c", "aclk_vcodec_pre", 0,
836 7, 8, 5),
837 COMP(0, "aclk_vcodec_pre_c", pll_src_cpll_gpll_npll_ppll_p, 0,
838 7, 0, 5, 6, 2),
839
840 /* CRU_CLKSEL_CON8 */
841 CDIV(0, "hclk_vdu_pre_c", "aclk_vdu_pre", 0,
842 8, 8, 5),
843 COMP(0, "aclk_vdu_pre_c", pll_src_cpll_gpll_npll_ppll_p, 0,
844 8, 0, 5, 6, 2),
845
846 /* CRU_CLKSEL_CON9 */
847 COMP(0, "clk_vdu_ca_c", pll_src_cpll_gpll_npll_npll_p, 0,
848 9, 8, 5, 14, 2),
849 COMP(0, "clk_vdu_core_c", pll_src_cpll_gpll_npll_npll_p, 0,
850 9, 0, 5, 6, 2),
851
852 /* CRU_CLKSEL_CON10 */
853 CDIV(0, "hclk_iep_pre_c", "aclk_iep_pre", 0,
854 10, 8, 5),
855 COMP(0, "aclk_iep_pre_c", pll_src_cpll_gpll_npll_ppll_p, 0,
856 10, 0, 5, 6, 2),
857
858 /* CRU_CLKSEL_CON11 */
859 CDIV(0, "hclk_rga_pre_c", "aclk_rga_pre", 0,
860 11, 8, 5),
861 COMP(0, "aclk_rga_pre_c", pll_src_cpll_gpll_npll_ppll_p, 0,
862 11, 0, 5, 6, 2),
863
864 /* CRU_CLKSEL_CON12 */
865 COMP(0, "aclk_center_c", pll_src_cpll_gpll_npll_npll_p, 0,
866 12, 8, 5, 14, 2),
867 COMP(SCLK_RGA_CORE, "clk_rga_core_c", pll_src_cpll_gpll_npll_ppll_p, 0,
868 12, 0, 5, 6, 2),
869
870 /* CRU_CLKSEL_CON13 */
871 COMP(0, "hclk_sd_c", pll_src_cpll_gpll_p, 0,
872 13, 8, 5, 15, 1),
873 COMP(0, "aclk_gpu_pre_c", pll_src_ppll_cpll_gpll_npll_upll_p, 0,
874 13, 0, 5, 5, 3),
875
876 /* CRU_CLKSEL_CON14 */
877 MUX(0, "upll", pll_src_24m_usbphy480m_p, 0,
878 14, 15, 1),
879 CDIV(0, "pclk_perihp_c", "aclk_perihp", 0,
880 14, 12, 2),
881 CDIV(0, "hclk_perihp_c", "aclk_perihp", 0,
882 14, 8, 2),
883 MUX(0, "clk_usbphy_480m", usbphy_480m_p, 0,
884 14, 6, 1),
885 COMP(0, "aclk_perihp_c", aclk_perihp_p, 0,
886 14, 0, 5, 7, 1),
887
888 /* CRU_CLKSEL_CON15 */
889 COMP(0, "clk_sdio_c", pll_src_cpll_gpll_npll_ppll_upll_24m_p, 0,
890 15, 0, 7, 8, 3),
891
892 /* CRU_CLKSEL_CON16 */
893 COMP(0, "clk_sdmmc_c", pll_src_cpll_gpll_npll_ppll_upll_24m_p, 0,
894 16, 0, 7, 8, 3),
895
896 /* CRU_CLKSEL_CON17 */
897 COMP(0, "clk_pcie_pm_c", pll_src_cpll_gpll_npll_24m_p, 0,
898 17, 0, 7, 8, 3),
899
900 /* CRU_CLKSEL_CON18 */
901 CDIV(0, "clk_pciephy_ref100m_c", "npll", 0,
902 18, 11, 5),
903 MUX(SCLK_PCIEPHY_REF, "clk_pciephy_ref", pll_src_24m_pciephy_p, 0,
904 18, 10, 1),
905 MUX(SCLK_PCIE_CORE, "clk_pcie_core", pciecore_cru_phy_p, 0,
906 18, 7, 1),
907 COMP(0, "clk_pcie_core_cru_c", pll_src_cpll_gpll_npll_npll_p, 0,
908 18, 0, 7, 8, 2),
909
910 /* CRU_CLKSEL_CON19 */
911 CDIV(0, "pclk_gmac_pre_c", "aclk_gmac_pre", 0,
912 19, 8, 3),
913 MUX(SCLK_RMII_SRC, "clk_rmii_src",rmii_p, 0,
914 19, 4, 1),
915 MUX(SCLK_HSICPHY, "clk_hsicphy_c", pll_src_cpll_gpll_npll_usbphy480m_p, 0,
916 19, 0, 2),
917
918 /* CRU_CLKSEL_CON20 */
919 COMP(0, "clk_gmac_c", pll_src_cpll_gpll_npll_npll_p, 0,
920 20, 8, 5, 14, 2),
921 COMP(0, "aclk_gmac_pre_c", aclk_gmac_p, 0,
922 20, 0, 5, 7, 1),
923
924 /* CRU_CLKSEL_CON21 */
925 COMP(ACLK_EMMC, "aclk_emmc", aclk_emmc_p, 0,
926 21, 0, 5, 7, 1),
927
928 /* CRU_CLKSEL_CON22 */
929 COMP(0, "clk_emmc_c", pll_src_cpll_gpll_npll_upll_24m_p, 0,
930 22, 0, 7, 8, 3),
931
932 /* CRU_CLKSEL_CON23 */
933 CDIV(0, "pclk_perilp0_c", "aclk_perilp0", 0,
934 23, 12, 3),
935 CDIV(0, "hclk_perilp0_c", "aclk_perilp0", 0,
936 23, 8, 2),
937 COMP(0, "aclk_perilp0_c", aclk_perilp0_p, 0,
938 23, 0, 5, 7, 1),
939
940 /* CRU_CLKSEL_CON24 */
941 COMP(0, "fclk_cm0s_c", fclk_cm0s_p, 0,
942 24, 8, 5, 15, 1),
943 COMP(0, "clk_crypto0_c", pll_src_cpll_gpll_ppll_p, 0,
944 24, 0, 5, 6, 2),
945
946 /* CRU_CLKSEL_CON25 */
947 CDIV(0, "pclk_perilp1_c", "hclk_perilp1", 0,
948 25, 8, 3),
949 COMP(HCLK_PERILP1, "hclk_perilp1", hclk_perilp1_p, 0,
950 25, 0, 5, 7, 1),
951
952 /* CRU_CLKSEL_CON26 */
953 CDIV(0, "clk_saradc_c", "xin24m", 0,
954 26, 8, 8),
955 COMP(0, "clk_crypto1_c", pll_src_cpll_gpll_ppll_p, 0,
956 26, 0, 5, 6, 2),
957
958 /* CRU_CLKSEL_CON27 */
959 COMP(0, "clk_tsadc_c", pll_src_p, 0,
960 27, 0, 10, 15, 1),
961
962 /* CRU_CLKSEL_CON28 */
963 MUX(0, "clk_i2s0_mux", i2s0_p, RK_CLK_MUX_REPARENT,
964 28, 8, 2),
965 COMP(0, "clk_i2s0_div_c", pll_src_cpll_gpll_p, 0,
966 28, 0, 7, 7, 1),
967
968 /* CRU_CLKSEL_CON29 */
969 MUX(0, "clk_i2s1_mux", i2s1_p, RK_CLK_MUX_REPARENT,
970 29, 8, 2),
971 COMP(0, "clk_i2s1_div_c", pll_src_cpll_gpll_p, 0,
972 29, 0, 7, 7, 1),
973
974 /* CRU_CLKSEL_CON30 */
975 MUX(0, "clk_i2s2_mux", i2s2_p, RK_CLK_MUX_REPARENT,
976 30, 8, 2),
977 COMP(0, "clk_i2s2_div_c", pll_src_cpll_gpll_p, 0,
978 30, 0, 7, 7, 1),
979
980 /* CRU_CLKSEL_CON31 */
981 MUX(0, "clk_i2sout_c", i2sout_p, 0,
982 31, 2, 1),
983 MUX(0, "clk_i2sout_src", i2sch_p, 0,
984 31, 0, 2),
985
986 /* CRU_CLKSEL_CON32 */
987 COMP(0, "clk_spdif_rec_dptx_c", pll_src_cpll_gpll_p, 0,
988 32, 8, 5, 15, 1),
989 MUX(0, "clk_spdif_mux", spdif_p, 0,
990 32, 13, 2),
991 COMP(0, "clk_spdif_div_c", pll_src_cpll_gpll_p, 0,
992 32, 0, 7, 7, 1),
993
994 /* CRU_CLKSEL_CON33 */
995 MUX(0, "clk_uart_src", pll_src_cpll_gpll_p, 0,
996 33, 15, 1),
997 MUX(0, "clk_uart0_src", pll_src_cpll_gpll_upll_p, 0,
998 33, 12, 2),
999 MUX(SCLK_UART0, "clk_uart0", uart0_p, 0,
1000 33, 8, 2),
1001 CDIV(0, "clk_uart0_div_c", "clk_uart0_src", 0,
1002 33, 0, 7),
1003
1004 /* CRU_CLKSEL_CON34 */
1005 MUX(SCLK_UART1, "clk_uart1", uart1_p, 0,
1006 34, 8, 2),
1007 CDIV(0, "clk_uart1_div_c", "clk_uart_src", 0,
1008 34, 0, 7),
1009
1010 /* CRU_CLKSEL_CON35 */
1011 MUX(SCLK_UART2, "clk_uart2", uart2_p, 0,
1012 35, 8, 2),
1013 CDIV(0, "clk_uart2_div_c", "clk_uart_src", 0,
1014 35, 0, 7),
1015
1016 /* CRU_CLKSEL_CON36 */
1017 MUX(SCLK_UART3, "clk_uart3", uart3_p, 0,
1018 36, 8, 2),
1019 CDIV(0, "clk_uart3_div_c", "clk_uart_src", 0,
1020 36, 0, 7),
1021
1022 /* CRU_CLKSEL_CON37 */
1023 /* unused */
1024
1025 /* CRU_CLKSEL_CON38 */
1026 MUX(0, "clk_testout2_pll_src", pll_src_cpll_gpll_npll_npll_p, 0,
1027 38, 14, 2),
1028 COMP(0, "clk_testout2_c", clk_testout2_p, 0,
1029 38, 8, 5, 13, 1),
1030 MUX(0, "clk_testout1_pll_src", pll_src_cpll_gpll_npll_npll_p, 0,
1031 38, 6, 2),
1032 COMP(0, "clk_testout1_c", clk_testout1_p, 0,
1033 38, 0, 5, 5, 1),
1034
1035 /* CRU_CLKSEL_CON39 */
1036 COMP(0, "aclk_usb3_c", pll_src_cpll_gpll_npll_npll_p, 0,
1037 39, 0, 5, 6, 2),
1038
1039 /* CRU_CLKSEL_CON40 */
1040 COMP(0, "clk_usb3otg0_suspend_c", pll_src_p, 0,
1041 40, 0, 10, 15, 1),
1042
1043 /* CRU_CLKSEL_CON41 */
1044 COMP(0, "clk_usb3otg1_suspend_c", pll_src_p, 0,
1045 41, 0, 10, 15, 1),
1046
1047 /* CRU_CLKSEL_CON42 */
1048 COMP(0, "aclk_hdcp_c", pll_src_cpll_gpll_ppll_p, 0,
1049 42, 8, 5, 14, 2),
1050 COMP(0, "aclk_vio_c", pll_src_cpll_gpll_ppll_p, 0,
1051 42, 0, 5, 6, 2),
1052
1053 /* CRU_CLKSEL_CON43 */
1054 CDIV(0, "pclk_hdcp_c", "aclk_hdcp", 0,
1055 43, 10, 5),
1056 CDIV(0, "hclk_hdcp_c", "aclk_hdcp", 0,
1057 43, 5, 5),
1058 CDIV(0, "pclk_vio_c", "aclk_vio", 0,
1059 43, 0, 5),
1060
1061 /* CRU_CLKSEL_CON44 */
1062 COMP(0, "pclk_edp_c", pll_src_cpll_gpll_p, 0,
1063 44, 8, 6, 15, 1),
1064
1065 /* CRU_CLKSEL_CON45 - XXX clocks in mux are reversed in TRM !!!*/
1066 COMP(0, "clk_hdmi_cec_c", pll_src_p, 0,
1067 45, 0, 10, 15, 1),
1068
1069 /* CRU_CLKSEL_CON46 */
1070 COMP(0, "clk_dp_core_c", pll_src_npll_cpll_gpll_p, 0,
1071 46, 0, 5, 6, 2),
1072
1073 /* CRU_CLKSEL_CON47 */
1074 CDIV(0, "hclk_vop0_pre_c", "aclk_vop0_pre_c", 0,
1075 47, 8, 5),
1076 COMP(0, "aclk_vop0_pre_c", pll_src_vpll_cpll_gpll_npll_p, 0,
1077 47, 0, 5, 6, 2),
1078
1079 /* CRU_CLKSEL_CON48 */
1080 CDIV(0, "hclk_vop1_pre_c", "aclk_vop1_pre", 0,
1081 48, 8, 5),
1082 COMP(0, "aclk_vop1_pre_c", pll_src_vpll_cpll_gpll_npll_p, 0,
1083 48, 0, 5, 6, 2),
1084
1085 /* CRU_CLKSEL_CON49 */
1086 MUX(DCLK_VOP0, "dclk_vop0", dclk_vop0_p, 0,
1087 49, 11, 1),
1088 COMP(0, "dclk_vop0_div_c", pll_src_vpll_cpll_gpll_gpll_p, 0,
1089 49, 0, 8, 8, 2),
1090
1091 /* CRU_CLKSEL_CON50 */
1092 MUX(DCLK_VOP1, "dclk_vop1", dclk_vop1_p, 0,
1093 50, 11, 1),
1094 COMP(0, "dclk_vop1_div_c", pll_src_vpll_cpll_gpll_gpll_p, 0,
1095 50, 0, 8, 8, 2),
1096
1097 /* CRU_CLKSEL_CON51 */
1098 COMP(0, "clk_vop0_pwm_c", pll_src_vpll_cpll_gpll_gpll_p, 0,
1099 51, 0, 5, 6, 2),
1100
1101 /* CRU_CLKSEL_CON52 */
1102 COMP(0, "clk_vop1_pwm_c", pll_src_vpll_cpll_gpll_gpll_p, 0,
1103 52, 0, 5, 6, 2),
1104
1105 /* CRU_CLKSEL_CON53 */
1106 CDIV(0, "hclk_isp0_c", "aclk_isp0", 0,
1107 53, 8, 5),
1108 COMP(0, "aclk_isp0_c", pll_src_cpll_gpll_ppll_p, 0,
1109 53, 0, 5, 6, 2),
1110
1111 /* CRU_CLKSEL_CON54 */
1112 CDIV(0, "hclk_isp1_c", "aclk_isp1", 0,
1113 54, 8, 5),
1114 COMP(0, "aclk_isp1_c", pll_src_cpll_gpll_ppll_p, 0,
1115 54, 0, 5, 6, 2),
1116
1117 /* CRU_CLKSEL_CON55 */
1118 COMP(0, "clk_isp1_c", pll_src_cpll_gpll_npll_npll_p, 0,
1119 55, 8, 5, 14, 2),
1120 COMP(0, "clk_isp0_c", pll_src_cpll_gpll_npll_npll_p, 0,
1121 55, 0, 5, 6, 2),
1122
1123 /* CRU_CLKSEL_CON56 */
1124 COMP(0, "aclk_gic_pre_c", pll_src_cpll_gpll_p, 0,
1125 56, 8, 5, 15, 1),
1126 MUX(0, "clk_cifout_src_c", pll_src_cpll_gpll_npll_npll_p, 0,
1127 56, 6, 2),
1128 COMP(SCLK_CIF_OUT, "clk_cifout", clk_cif_p, 0,
1129 56, 0, 5, 5, 1),
1130
1131 /* CRU_CLKSEL_CON57 */
1132 CDIV(0, "clk_test_24m", "xin24m", 0,
1133 57, 6, 10),
1134 CDIV(PCLK_ALIVE, "pclk_alive", "gpll", 0,
1135 57, 0, 5),
1136
1137 /* CRU_CLKSEL_CON58 */
1138 COMP(0, "clk_spi5_c", pll_src_cpll_gpll_p, 0,
1139 58, 8, 7, 15, 1),
1140 MUX(0, "clk_test_pre", pll_src_cpll_gpll_p, 0,
1141 58, 7, 1),
1142 CDIV(0, "clk_test_c", "clk_test_pre", 0,
1143 58, 0, 5),
1144
1145 /* CRU_CLKSEL_CON59 */
1146 COMP(0, "clk_spi1_c", pll_src_cpll_gpll_p, 0,
1147 59, 8, 7, 15, 1),
1148 COMP(0, "clk_spi0_c", pll_src_cpll_gpll_p, 0,
1149 59, 0, 7, 7, 1),
1150
1151 /* CRU_CLKSEL_CON60 */
1152 COMP(0, "clk_spi4_c", pll_src_cpll_gpll_p, 0,
1153 60, 8, 7, 15, 1),
1154 COMP(0, "clk_spi2_c", pll_src_cpll_gpll_p, 0,
1155 60, 0, 7, 7, 1),
1156
1157 /* CRU_CLKSEL_CON61 */
1158 COMP(0, "clk_i2c5_c", pll_src_cpll_gpll_p, 0,
1159 61, 8, 7, 15, 1),
1160 COMP(0, "clk_i2c1_c", pll_src_cpll_gpll_p, 0,
1161 61, 0, 7, 7, 1),
1162
1163 /* CRU_CLKSEL_CON62 */
1164 COMP(0, "clk_i2c6_c", pll_src_cpll_gpll_p, 0,
1165 62, 8, 7, 15, 1),
1166 COMP(0, "clk_i2c2_c", pll_src_cpll_gpll_p, 0,
1167 62, 0, 7, 7, 1),
1168
1169 /* CRU_CLKSEL_CON63 */
1170 COMP(0, "clk_i2c7_c", pll_src_cpll_gpll_p, 0,
1171 63, 8, 7, 15, 1),
1172 COMP(0, "clk_i2c3_c", pll_src_cpll_gpll_p, 0,
1173 63, 0, 7, 7, 1),
1174
1175 /* CRU_CLKSEL_CON64 */
1176 COMP(0, "clk_uphy0_tcpdphy_ref_c", pll_src_p, 0,
1177 64, 8, 5, 15, 1),
1178 COMP(0, "clk_uphy0_tcpdcore_c", pll_src_24m_32k_cpll_gpll_p, 0,
1179 64, 0, 5, 6, 2),
1180
1181 /* CRU_CLKSEL_CON65 */
1182 COMP(0, "clk_uphy1_tcpdphy_ref_c", pll_src_p, 0,
1183 65, 8, 5, 15, 1),
1184 COMP(0, "clk_uphy1_tcpdcore_c", pll_src_24m_32k_cpll_gpll_p, 0,
1185 65, 0, 5, 6, 2),
1186
1187 /* CRU_CLKSEL_CON99 - 107 */
1188 FRACT(0, "clk_spdif_frac_c", "clk_spdif_div", 0,
1189 99),
1190 FRACT(0, "clk_i2s0_frac_c", "clk_i2s0_div", 0,
1191 96),
1192 FRACT(0, "clk_i2s1_frac_c", "clk_i2s1_div", 0,
1193 97),
1194 FRACT(0, "clk_i2s2_frac_c", "clk_i2s2_div", 0,
1195 98),
1196 FRACT(0, "clk_uart0_frac_c", "clk_uart0_div", 0,
1197 100),
1198 FRACT(0, "clk_uart1_frac_c", "clk_uart1_div", 0,
1199 101),
1200 FRACT(0, "clk_uart2_frac_c", "clk_uart2_div", 0,
1201 102),
1202 FRACT(0, "clk_uart3_frac_c", "clk_uart3_div", 0,
1203 103),
1204 FRACT(0, "clk_test_frac_c", "clk_test_pre", 0,
1205 105),
1206 FRACT(DCLK_VOP0_FRAC, "dclk_vop0_frac", "dclk_vop0_div", 0,
1207 106),
1208 FRACT(DCLK_VOP1_FRAC, "dclk_vop1_frac", "dclk_vop1_div", 0,
1209 107),
1210
1211 /*
1212 * This clock is controlled in the secure world
1213 */
1214 FFACT(PCLK_WDT, "pclk_wdt", "pclk_alive", 1, 1),
1215
1216 /* Not yet implemented yet
1217 * MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc", RK3399_SDMMC_CON0, 1),
1218 * MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc", RK3399_SDMMC_CON1, 1),
1219 * MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio", RK3399_SDIO_CON0, 1),
1220 * MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio", RK3399_SDIO_CON1, 1),
1221 */
1222
1223 };
1224
1225 static int
rk3399_cru_probe(device_t dev)1226 rk3399_cru_probe(device_t dev)
1227 {
1228
1229 if (!ofw_bus_status_okay(dev))
1230 return (ENXIO);
1231
1232 if (ofw_bus_is_compatible(dev, "rockchip,rk3399-cru")) {
1233 device_set_desc(dev, "Rockchip RK3399 Clock and Reset Unit");
1234 return (BUS_PROBE_DEFAULT);
1235 }
1236
1237 return (ENXIO);
1238 }
1239
1240 static int
rk3399_cru_attach(device_t dev)1241 rk3399_cru_attach(device_t dev)
1242 {
1243 struct rk_cru_softc *sc;
1244
1245 sc = device_get_softc(dev);
1246 sc->dev = dev;
1247
1248 sc->gates = rk3399_gates;
1249 sc->ngates = nitems(rk3399_gates);
1250
1251 sc->clks = rk3399_clks;
1252 sc->nclks = nitems(rk3399_clks);
1253
1254 sc->reset_offset = 0x400;
1255 sc->reset_num = 335;
1256
1257 return (rk_cru_attach(dev));
1258 }
1259
1260 static device_method_t rk3399_cru_methods[] = {
1261 /* Device interface */
1262 DEVMETHOD(device_probe, rk3399_cru_probe),
1263 DEVMETHOD(device_attach, rk3399_cru_attach),
1264
1265 DEVMETHOD_END
1266 };
1267
1268 static devclass_t rk3399_cru_devclass;
1269
1270 DEFINE_CLASS_1(rk3399_cru, rk3399_cru_driver, rk3399_cru_methods,
1271 sizeof(struct rk_cru_softc), rk_cru_driver);
1272
1273 EARLY_DRIVER_MODULE(rk3399_cru, simplebus, rk3399_cru_driver,
1274 rk3399_cru_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);
1275