1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2018 Emmanuel Vadot <manu@FreeBSD.org>
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 */
28
29 #include <sys/cdefs.h>
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <sys/bus.h>
33
34 #include <sys/kernel.h>
35 #include <sys/module.h>
36 #include <sys/rman.h>
37 #include <sys/lock.h>
38 #include <sys/mutex.h>
39 #include <sys/gpio.h>
40
41 #include <machine/bus.h>
42 #include <machine/resource.h>
43 #include <machine/intr.h>
44
45 #include <dev/gpio/gpiobusvar.h>
46 #include <dev/ofw/ofw_bus.h>
47 #include <dev/ofw/ofw_bus_subr.h>
48 #include <dev/extres/clk/clk.h>
49
50 #include "gpio_if.h"
51
52 #include "fdt_pinctrl_if.h"
53
54 #define RK_GPIO_SWPORTA_DR 0x00 /* Data register */
55 #define RK_GPIO_SWPORTA_DDR 0x04 /* Data direction register */
56
57 #define RK_GPIO_INTEN 0x30 /* Interrupt enable register */
58 #define RK_GPIO_INTMASK 0x34 /* Interrupt mask register */
59 #define RK_GPIO_INTTYPE_LEVEL 0x38 /* Interrupt level register */
60 #define RK_GPIO_INT_POLARITY 0x3C /* Interrupt polarity register */
61 #define RK_GPIO_INT_STATUS 0x40 /* Interrupt status register */
62 #define RK_GPIO_INT_RAWSTATUS 0x44 /* Raw Interrupt status register */
63
64 #define RK_GPIO_DEBOUNCE 0x48 /* Debounce enable register */
65
66 #define RK_GPIO_PORTA_EOI 0x4C /* Clear interrupt register */
67 #define RK_GPIO_EXT_PORTA 0x50 /* External port register */
68
69 #define RK_GPIO_LS_SYNC 0x60 /* Level sensitive syncronization enable register */
70
71 #define RK_GPIO_DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \
72 GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN)
73
74 #define GPIO_FLAGS_PINCTRL (GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN)
75 #define RK_GPIO_MAX_PINS 32
76
77 struct pin_cached {
78 uint8_t is_gpio;
79 uint32_t flags;
80 };
81
82 struct rk_gpio_softc {
83 device_t sc_dev;
84 device_t sc_busdev;
85 struct mtx sc_mtx;
86 struct resource *sc_res[2];
87 bus_space_tag_t sc_bst;
88 bus_space_handle_t sc_bsh;
89 clk_t clk;
90 device_t pinctrl;
91 uint32_t swporta;
92 uint32_t swporta_ddr;
93 struct pin_cached pin_cached[RK_GPIO_MAX_PINS];
94 };
95
96 static struct ofw_compat_data compat_data[] = {
97 {"rockchip,gpio-bank", 1},
98 {NULL, 0}
99 };
100
101 static struct resource_spec rk_gpio_spec[] = {
102 { SYS_RES_MEMORY, 0, RF_ACTIVE },
103 { SYS_RES_IRQ, 0, RF_ACTIVE },
104 { -1, 0 }
105 };
106
107 static int rk_gpio_detach(device_t dev);
108
109 #define RK_GPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx)
110 #define RK_GPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx)
111 #define RK_GPIO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
112
113 #define RK_GPIO_WRITE(_sc, _off, _val) \
114 bus_space_write_4(_sc->sc_bst, _sc->sc_bsh, _off, _val)
115 #define RK_GPIO_READ(_sc, _off) \
116 bus_space_read_4(_sc->sc_bst, _sc->sc_bsh, _off)
117
118 static int
rk_gpio_probe(device_t dev)119 rk_gpio_probe(device_t dev)
120 {
121
122 if (!ofw_bus_status_okay(dev))
123 return (ENXIO);
124
125 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
126 return (ENXIO);
127
128 device_set_desc(dev, "RockChip GPIO Bank controller");
129 return (BUS_PROBE_DEFAULT);
130 }
131
132 static int
rk_gpio_attach(device_t dev)133 rk_gpio_attach(device_t dev)
134 {
135 struct rk_gpio_softc *sc;
136 phandle_t node;
137 int err, i;
138
139 sc = device_get_softc(dev);
140 sc->sc_dev = dev;
141 sc->pinctrl = device_get_parent(dev);
142
143 node = ofw_bus_get_node(sc->sc_dev);
144 if (!OF_hasprop(node, "gpio-controller"))
145 return (ENXIO);
146
147 mtx_init(&sc->sc_mtx, "rk gpio", "gpio", MTX_SPIN);
148
149 if (bus_alloc_resources(dev, rk_gpio_spec, sc->sc_res)) {
150 device_printf(dev, "could not allocate resources\n");
151 bus_release_resources(dev, rk_gpio_spec, sc->sc_res);
152 mtx_destroy(&sc->sc_mtx);
153 return (ENXIO);
154 }
155
156 sc->sc_bst = rman_get_bustag(sc->sc_res[0]);
157 sc->sc_bsh = rman_get_bushandle(sc->sc_res[0]);
158
159 if (clk_get_by_ofw_index(dev, 0, 0, &sc->clk) != 0) {
160 device_printf(dev, "Cannot get clock\n");
161 rk_gpio_detach(dev);
162 return (ENXIO);
163 }
164 err = clk_enable(sc->clk);
165 if (err != 0) {
166 device_printf(dev, "Could not enable clock %s\n",
167 clk_get_name(sc->clk));
168 rk_gpio_detach(dev);
169 return (ENXIO);
170 }
171
172 sc->sc_busdev = gpiobus_attach_bus(dev);
173 if (sc->sc_busdev == NULL) {
174 rk_gpio_detach(dev);
175 return (ENXIO);
176 }
177
178 /* Set the cached value to unknown */
179 for (i = 0; i < RK_GPIO_MAX_PINS; i++)
180 sc->pin_cached[i].is_gpio = 2;
181
182 RK_GPIO_LOCK(sc);
183 sc->swporta = RK_GPIO_READ(sc, RK_GPIO_SWPORTA_DR);
184 sc->swporta_ddr = RK_GPIO_READ(sc, RK_GPIO_SWPORTA_DDR);
185 RK_GPIO_UNLOCK(sc);
186
187 return (0);
188 }
189
190 static int
rk_gpio_detach(device_t dev)191 rk_gpio_detach(device_t dev)
192 {
193 struct rk_gpio_softc *sc;
194
195 sc = device_get_softc(dev);
196
197 if (sc->sc_busdev)
198 gpiobus_detach_bus(dev);
199 bus_release_resources(dev, rk_gpio_spec, sc->sc_res);
200 mtx_destroy(&sc->sc_mtx);
201 clk_disable(sc->clk);
202
203 return(0);
204 }
205
206 static device_t
rk_gpio_get_bus(device_t dev)207 rk_gpio_get_bus(device_t dev)
208 {
209 struct rk_gpio_softc *sc;
210
211 sc = device_get_softc(dev);
212
213 return (sc->sc_busdev);
214 }
215
216 static int
rk_gpio_pin_max(device_t dev,int * maxpin)217 rk_gpio_pin_max(device_t dev, int *maxpin)
218 {
219
220 /* Each bank have always 32 pins */
221 /* XXX not true*/
222 *maxpin = 31;
223 return (0);
224 }
225
226 static int
rk_gpio_pin_getname(device_t dev,uint32_t pin,char * name)227 rk_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
228 {
229 struct rk_gpio_softc *sc;
230 uint32_t bank;
231
232 sc = device_get_softc(dev);
233
234 if (pin >= 32)
235 return (EINVAL);
236
237 bank = pin / 8;
238 pin = pin - (bank * 8);
239 RK_GPIO_LOCK(sc);
240 snprintf(name, GPIOMAXNAME, "P%c%d", bank + 'A', pin);
241 RK_GPIO_UNLOCK(sc);
242
243 return (0);
244 }
245
246 static int
rk_gpio_pin_getflags(device_t dev,uint32_t pin,uint32_t * flags)247 rk_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
248 {
249 struct rk_gpio_softc *sc;
250 int rv;
251
252 sc = device_get_softc(dev);
253
254 if (__predict_false(sc->pin_cached[pin].is_gpio != 1)) {
255 rv = FDT_PINCTRL_IS_GPIO(sc->pinctrl, dev, pin, (bool *)&sc->pin_cached[pin].is_gpio);
256 if (rv != 0)
257 return (rv);
258 if (sc->pin_cached[pin].is_gpio == 0)
259 return (EINVAL);
260 }
261
262 *flags = 0;
263 rv = FDT_PINCTRL_GET_FLAGS(sc->pinctrl, dev, pin, flags);
264 if (rv != 0)
265 return (rv);
266 sc->pin_cached[pin].flags = *flags;
267
268 if (sc->swporta_ddr & (1 << pin))
269 *flags |= GPIO_PIN_OUTPUT;
270 else
271 *flags |= GPIO_PIN_INPUT;
272
273 return (0);
274 }
275
276 static int
rk_gpio_pin_getcaps(device_t dev,uint32_t pin,uint32_t * caps)277 rk_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
278 {
279
280 *caps = RK_GPIO_DEFAULT_CAPS;
281 return (0);
282 }
283
284 static int
rk_gpio_pin_setflags(device_t dev,uint32_t pin,uint32_t flags)285 rk_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
286 {
287 struct rk_gpio_softc *sc;
288 int rv;
289
290 sc = device_get_softc(dev);
291
292 if (__predict_false(sc->pin_cached[pin].is_gpio != 1)) {
293 rv = FDT_PINCTRL_IS_GPIO(sc->pinctrl, dev, pin, (bool *)&sc->pin_cached[pin].is_gpio);
294 if (rv != 0)
295 return (rv);
296 if (sc->pin_cached[pin].is_gpio == 0)
297 return (EINVAL);
298 }
299
300 if (__predict_false((flags & GPIO_PIN_INPUT) && ((flags & GPIO_FLAGS_PINCTRL) != sc->pin_cached[pin].flags))) {
301 rv = FDT_PINCTRL_SET_FLAGS(sc->pinctrl, dev, pin, flags);
302 sc->pin_cached[pin].flags = flags & GPIO_FLAGS_PINCTRL;
303 if (rv != 0)
304 return (rv);
305 }
306
307 RK_GPIO_LOCK(sc);
308 if (flags & GPIO_PIN_INPUT)
309 sc->swporta_ddr &= ~(1 << pin);
310 else if (flags & GPIO_PIN_OUTPUT)
311 sc->swporta_ddr |= (1 << pin);
312
313 RK_GPIO_WRITE(sc, RK_GPIO_SWPORTA_DDR, sc->swporta_ddr);
314 RK_GPIO_UNLOCK(sc);
315
316 return (0);
317 }
318
319 static int
rk_gpio_pin_get(device_t dev,uint32_t pin,unsigned int * val)320 rk_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
321 {
322 struct rk_gpio_softc *sc;
323 uint32_t reg;
324
325 sc = device_get_softc(dev);
326
327 RK_GPIO_LOCK(sc);
328 reg = RK_GPIO_READ(sc, RK_GPIO_EXT_PORTA);
329 RK_GPIO_UNLOCK(sc);
330
331 *val = reg & (1 << pin) ? 1 : 0;
332
333 return (0);
334 }
335
336 static int
rk_gpio_pin_set(device_t dev,uint32_t pin,unsigned int value)337 rk_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
338 {
339 struct rk_gpio_softc *sc;
340
341 sc = device_get_softc(dev);
342
343 RK_GPIO_LOCK(sc);
344 if (value)
345 sc->swporta |= (1 << pin);
346 else
347 sc->swporta &= ~(1 << pin);
348 RK_GPIO_WRITE(sc, RK_GPIO_SWPORTA_DR, sc->swporta);
349 RK_GPIO_UNLOCK(sc);
350
351 return (0);
352 }
353
354 static int
rk_gpio_pin_toggle(device_t dev,uint32_t pin)355 rk_gpio_pin_toggle(device_t dev, uint32_t pin)
356 {
357 struct rk_gpio_softc *sc;
358
359 sc = device_get_softc(dev);
360
361 RK_GPIO_LOCK(sc);
362 if (sc->swporta & (1 << pin))
363 sc->swporta &= ~(1 << pin);
364 else
365 sc->swporta |= (1 << pin);
366 RK_GPIO_WRITE(sc, RK_GPIO_SWPORTA_DR, sc->swporta);
367 RK_GPIO_UNLOCK(sc);
368
369 return (0);
370 }
371
372 static int
rk_gpio_pin_access_32(device_t dev,uint32_t first_pin,uint32_t clear_pins,uint32_t change_pins,uint32_t * orig_pins)373 rk_gpio_pin_access_32(device_t dev, uint32_t first_pin, uint32_t clear_pins,
374 uint32_t change_pins, uint32_t *orig_pins)
375 {
376 struct rk_gpio_softc *sc;
377 uint32_t reg;
378
379 sc = device_get_softc(dev);
380
381 RK_GPIO_LOCK(sc);
382 reg = RK_GPIO_READ(sc, RK_GPIO_SWPORTA_DR);
383 if (orig_pins)
384 *orig_pins = reg;
385 sc->swporta = reg;
386
387 if ((clear_pins | change_pins) != 0) {
388 reg = (reg & ~clear_pins) ^ change_pins;
389 RK_GPIO_WRITE(sc, RK_GPIO_SWPORTA_DR, reg);
390 }
391 RK_GPIO_UNLOCK(sc);
392
393 return (0);
394 }
395
396 static int
rk_gpio_pin_config_32(device_t dev,uint32_t first_pin,uint32_t num_pins,uint32_t * pin_flags)397 rk_gpio_pin_config_32(device_t dev, uint32_t first_pin, uint32_t num_pins,
398 uint32_t *pin_flags)
399 {
400 struct rk_gpio_softc *sc;
401 uint32_t reg, set, mask, flags;
402 int i;
403
404 sc = device_get_softc(dev);
405
406 if (first_pin != 0 || num_pins > 32)
407 return (EINVAL);
408
409 set = 0;
410 mask = 0;
411 for (i = 0; i < num_pins; i++) {
412 mask = (mask << 1) | 1;
413 flags = pin_flags[i];
414 if (flags & GPIO_PIN_INPUT) {
415 set &= ~(1 << i);
416 } else if (flags & GPIO_PIN_OUTPUT) {
417 set |= (1 << i);
418 }
419 }
420
421 RK_GPIO_LOCK(sc);
422 reg = RK_GPIO_READ(sc, RK_GPIO_SWPORTA_DDR);
423 reg &= ~mask;
424 reg |= set;
425 RK_GPIO_WRITE(sc, RK_GPIO_SWPORTA_DDR, reg);
426 sc->swporta_ddr = reg;
427 RK_GPIO_UNLOCK(sc);
428
429 return (0);
430 }
431
432 static int
rk_gpio_map_gpios(device_t bus,phandle_t dev,phandle_t gparent,int gcells,pcell_t * gpios,uint32_t * pin,uint32_t * flags)433 rk_gpio_map_gpios(device_t bus, phandle_t dev, phandle_t gparent, int gcells,
434 pcell_t *gpios, uint32_t *pin, uint32_t *flags)
435 {
436
437 /* The gpios are mapped as <pin flags> */
438 *pin = gpios[0];
439 *flags = gpios[1];
440 return (0);
441 }
442
443 static phandle_t
rk_gpio_get_node(device_t bus,device_t dev)444 rk_gpio_get_node(device_t bus, device_t dev)
445 {
446
447 /* We only have one child, the GPIO bus, which needs our own node. */
448 return (ofw_bus_get_node(bus));
449 }
450
451 static device_method_t rk_gpio_methods[] = {
452 /* Device interface */
453 DEVMETHOD(device_probe, rk_gpio_probe),
454 DEVMETHOD(device_attach, rk_gpio_attach),
455 DEVMETHOD(device_detach, rk_gpio_detach),
456
457 /* GPIO protocol */
458 DEVMETHOD(gpio_get_bus, rk_gpio_get_bus),
459 DEVMETHOD(gpio_pin_max, rk_gpio_pin_max),
460 DEVMETHOD(gpio_pin_getname, rk_gpio_pin_getname),
461 DEVMETHOD(gpio_pin_getflags, rk_gpio_pin_getflags),
462 DEVMETHOD(gpio_pin_getcaps, rk_gpio_pin_getcaps),
463 DEVMETHOD(gpio_pin_setflags, rk_gpio_pin_setflags),
464 DEVMETHOD(gpio_pin_get, rk_gpio_pin_get),
465 DEVMETHOD(gpio_pin_set, rk_gpio_pin_set),
466 DEVMETHOD(gpio_pin_toggle, rk_gpio_pin_toggle),
467 DEVMETHOD(gpio_pin_access_32, rk_gpio_pin_access_32),
468 DEVMETHOD(gpio_pin_config_32, rk_gpio_pin_config_32),
469 DEVMETHOD(gpio_map_gpios, rk_gpio_map_gpios),
470
471 /* ofw_bus interface */
472 DEVMETHOD(ofw_bus_get_node, rk_gpio_get_node),
473
474 DEVMETHOD_END
475 };
476
477 static driver_t rk_gpio_driver = {
478 "gpio",
479 rk_gpio_methods,
480 sizeof(struct rk_gpio_softc),
481 };
482
483 static devclass_t rk_gpio_devclass;
484
485 /*
486 * GPIO driver is always a child of rk_pinctrl driver and should be probed
487 * and attached within rk_pinctrl_attach function. Due to this, bus pass order
488 * must be same as bus pass order of rk_pinctrl driver.
489 */
490 EARLY_DRIVER_MODULE(rk_gpio, simplebus, rk_gpio_driver,
491 rk_gpio_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE);
492