1 /*
2 ********************************************************************************
3 ** OS : FreeBSD
4 ** FILE NAME : arcmsr.c
5 ** BY : Erich Chen, Ching Huang
6 ** Description: SCSI RAID Device Driver for
7 ** ARECA (ARC11XX/ARC12XX/ARC13XX/ARC16XX/ARC188x)
8 ** SATA/SAS RAID HOST Adapter
9 ********************************************************************************
10 ********************************************************************************
11 **
12 ** SPDX-License-Identifier: BSD-3-Clause
13 **
14 ** Copyright (C) 2002 - 2012, Areca Technology Corporation All rights reserved.
15 **
16 ** Redistribution and use in source and binary forms, with or without
17 ** modification, are permitted provided that the following conditions
18 ** are met:
19 ** 1. Redistributions of source code must retain the above copyright
20 ** notice, this list of conditions and the following disclaimer.
21 ** 2. Redistributions in binary form must reproduce the above copyright
22 ** notice, this list of conditions and the following disclaimer in the
23 ** documentation and/or other materials provided with the distribution.
24 ** 3. The name of the author may not be used to endorse or promote products
25 ** derived from this software without specific prior written permission.
26 **
27 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
28 ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
29 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
30 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
31 ** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT
32 ** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33 ** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY
34 ** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35 **(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF
36 ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 ********************************************************************************
38 ** History
39 **
40 ** REV# DATE NAME DESCRIPTION
41 ** 1.00.00.00 03/31/2004 Erich Chen First release
42 ** 1.20.00.02 11/29/2004 Erich Chen bug fix with arcmsr_bus_reset when PHY error
43 ** 1.20.00.03 04/19/2005 Erich Chen add SATA 24 Ports adapter type support
44 ** clean unused function
45 ** 1.20.00.12 09/12/2005 Erich Chen bug fix with abort command handling,
46 ** firmware version check
47 ** and firmware update notify for hardware bug fix
48 ** handling if none zero high part physical address
49 ** of srb resource
50 ** 1.20.00.13 08/18/2006 Erich Chen remove pending srb and report busy
51 ** add iop message xfer
52 ** with scsi pass-through command
53 ** add new device id of sas raid adapters
54 ** code fit for SPARC64 & PPC
55 ** 1.20.00.14 02/05/2007 Erich Chen bug fix for incorrect ccb_h.status report
56 ** and cause g_vfs_done() read write error
57 ** 1.20.00.15 10/10/2007 Erich Chen support new RAID adapter type ARC120x
58 ** 1.20.00.16 10/10/2009 Erich Chen Bug fix for RAID adapter type ARC120x
59 ** bus_dmamem_alloc() with BUS_DMA_ZERO
60 ** 1.20.00.17 07/15/2010 Ching Huang Added support ARC1880
61 ** report CAM_DEV_NOT_THERE instead of CAM_SEL_TIMEOUT when device failed,
62 ** prevent cam_periph_error removing all LUN devices of one Target id
63 ** for any one LUN device failed
64 ** 1.20.00.18 10/14/2010 Ching Huang Fixed "inquiry data fails comparion at DV1 step"
65 ** 10/25/2010 Ching Huang Fixed bad range input in bus_alloc_resource for ADAPTER_TYPE_B
66 ** 1.20.00.19 11/11/2010 Ching Huang Fixed arcmsr driver prevent arcsas support for Areca SAS HBA ARC13x0
67 ** 1.20.00.20 12/08/2010 Ching Huang Avoid calling atomic_set_int function
68 ** 1.20.00.21 02/08/2011 Ching Huang Implement I/O request timeout
69 ** 02/14/2011 Ching Huang Modified pktRequestCount
70 ** 1.20.00.21 03/03/2011 Ching Huang if a command timeout, then wait its ccb back before free it
71 ** 1.20.00.22 07/04/2011 Ching Huang Fixed multiple MTX panic
72 ** 1.20.00.23 10/28/2011 Ching Huang Added TIMEOUT_DELAY in case of too many HDDs need to start
73 ** 1.20.00.23 11/08/2011 Ching Huang Added report device transfer speed
74 ** 1.20.00.23 01/30/2012 Ching Huang Fixed Request requeued and Retrying command
75 ** 1.20.00.24 06/11/2012 Ching Huang Fixed return sense data condition
76 ** 1.20.00.25 08/17/2012 Ching Huang Fixed hotplug device no function on type A adapter
77 ** 1.20.00.26 12/14/2012 Ching Huang Added support ARC1214,1224,1264,1284
78 ** 1.20.00.27 05/06/2013 Ching Huang Fixed out standing cmd full on ARC-12x4
79 ** 1.20.00.28 09/13/2013 Ching Huang Removed recursive mutex in arcmsr_abort_dr_ccbs
80 ** 1.20.00.29 12/18/2013 Ching Huang Change simq allocation number, support ARC1883
81 ** 1.30.00.00 11/30/2015 Ching Huang Added support ARC1203
82 ** 1.40.00.00 07/11/2017 Ching Huang Added support ARC1884
83 ** 1.40.00.01 10/30/2017 Ching Huang Fixed release memory resource
84 ** 1.50.00.00 09/30/2020 Ching Huang Added support ARC-1886, NVMe/SAS/SATA controller
85 ** 1.50.00.01 02/26/2021 Ching Huang Fixed no action of hot plugging device on type_F adapter
86 ** 1.50.00.02 04/16/2021 Ching Huang Fixed scsi command timeout on ARC-1886 when
87 ** scatter-gather count large than some number
88 ** 1.50.00.03 05/04/2021 Ching Huang Fixed doorbell status arrived late on ARC-1886
89 ** 1.50.00.04 12/08/2021 Ching Huang Fixed boot up hung under ARC-1886 with no volume created
90 ** 1.50.00.05 03/23/2023 Ching Huang Fixed reading buffer empty length error
91 ******************************************************************************************
92 */
93
94 #include <sys/cdefs.h>
95 #if 0
96 #define ARCMSR_DEBUG1 1
97 #endif
98 #include <sys/param.h>
99 #include <sys/systm.h>
100 #include <sys/malloc.h>
101 #include <sys/kernel.h>
102 #include <sys/bus.h>
103 #include <sys/queue.h>
104 #include <sys/stat.h>
105 #include <sys/devicestat.h>
106 #include <sys/kthread.h>
107 #include <sys/module.h>
108 #include <sys/proc.h>
109 #include <sys/lock.h>
110 #include <sys/sysctl.h>
111 #include <sys/poll.h>
112 #include <sys/ioccom.h>
113 #include <vm/vm.h>
114 #include <vm/vm_param.h>
115 #include <vm/pmap.h>
116
117 #include <isa/rtc.h>
118
119 #include <machine/bus.h>
120 #include <machine/resource.h>
121 #include <machine/atomic.h>
122 #include <sys/conf.h>
123 #include <sys/rman.h>
124
125 #include <cam/cam.h>
126 #include <cam/cam_ccb.h>
127 #include <cam/cam_sim.h>
128 #include <cam/cam_periph.h>
129 #include <cam/cam_xpt_periph.h>
130 #include <cam/cam_xpt_sim.h>
131 #include <cam/cam_debug.h>
132 #include <cam/scsi/scsi_all.h>
133 #include <cam/scsi/scsi_message.h>
134 /*
135 **************************************************************************
136 **************************************************************************
137 */
138 #include <sys/selinfo.h>
139 #include <sys/mutex.h>
140 #include <sys/endian.h>
141 #include <dev/pci/pcivar.h>
142 #include <dev/pci/pcireg.h>
143
144 #define arcmsr_callout_init(a) callout_init(a, /*mpsafe*/1);
145
146 #define ARCMSR_DRIVER_VERSION "arcmsr version 1.50.00.05 2023-03-23"
147 #include <dev/arcmsr/arcmsr.h>
148 /*
149 **************************************************************************
150 **************************************************************************
151 */
152 static void arcmsr_free_srb(struct CommandControlBlock *srb);
153 static struct CommandControlBlock *arcmsr_get_freesrb(struct AdapterControlBlock *acb);
154 static u_int8_t arcmsr_seek_cmd2abort(union ccb *abortccb);
155 static int arcmsr_probe(device_t dev);
156 static int arcmsr_attach(device_t dev);
157 static int arcmsr_detach(device_t dev);
158 static u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_cmd, caddr_t arg);
159 static void arcmsr_iop_parking(struct AdapterControlBlock *acb);
160 static int arcmsr_shutdown(device_t dev);
161 static void arcmsr_interrupt(struct AdapterControlBlock *acb);
162 static void arcmsr_polling_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb);
163 static void arcmsr_free_resource(struct AdapterControlBlock *acb);
164 static void arcmsr_bus_reset(struct AdapterControlBlock *acb);
165 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb);
166 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb);
167 static void arcmsr_iop_init(struct AdapterControlBlock *acb);
168 static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb);
169 static u_int32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb, struct QBUFFER *prbuffer);
170 static void arcmsr_Write_data_2iop_wqbuffer(struct AdapterControlBlock *acb);
171 static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb);
172 static void arcmsr_srb_complete(struct CommandControlBlock *srb, int stand_flag);
173 static void arcmsr_iop_reset(struct AdapterControlBlock *acb);
174 static void arcmsr_report_sense_info(struct CommandControlBlock *srb);
175 static void arcmsr_build_srb(struct CommandControlBlock *srb, bus_dma_segment_t *dm_segs, u_int32_t nseg);
176 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb *pccb);
177 static int arcmsr_resume(device_t dev);
178 static int arcmsr_suspend(device_t dev);
179 static void arcmsr_rescanLun_cb(struct cam_periph *periph, union ccb *ccb);
180 static void arcmsr_polling_devmap(void *arg);
181 static void arcmsr_srb_timeout(void *arg);
182 static void arcmsr_hbd_postqueue_isr(struct AdapterControlBlock *acb);
183 static void arcmsr_hbe_postqueue_isr(struct AdapterControlBlock *acb);
184 static void arcmsr_hbf_postqueue_isr(struct AdapterControlBlock *acb);
185 static void arcmsr_teardown_intr(device_t dev, struct AdapterControlBlock *acb);
186 #ifdef ARCMSR_DEBUG1
187 static void arcmsr_dump_data(struct AdapterControlBlock *acb);
188 #endif
189 /*
190 **************************************************************************
191 **************************************************************************
192 */
UDELAY(u_int32_t us)193 static void UDELAY(u_int32_t us) { DELAY(us); }
194 /*
195 **************************************************************************
196 **************************************************************************
197 */
198 static bus_dmamap_callback_t arcmsr_map_free_srb;
199 static bus_dmamap_callback_t arcmsr_execute_srb;
200 /*
201 **************************************************************************
202 **************************************************************************
203 */
204 static d_open_t arcmsr_open;
205 static d_close_t arcmsr_close;
206 static d_ioctl_t arcmsr_ioctl;
207
208 static device_method_t arcmsr_methods[]={
209 DEVMETHOD(device_probe, arcmsr_probe),
210 DEVMETHOD(device_attach, arcmsr_attach),
211 DEVMETHOD(device_detach, arcmsr_detach),
212 DEVMETHOD(device_shutdown, arcmsr_shutdown),
213 DEVMETHOD(device_suspend, arcmsr_suspend),
214 DEVMETHOD(device_resume, arcmsr_resume),
215 DEVMETHOD_END
216 };
217
218 static driver_t arcmsr_driver={
219 "arcmsr", arcmsr_methods, sizeof(struct AdapterControlBlock)
220 };
221
222 static devclass_t arcmsr_devclass;
223 DRIVER_MODULE(arcmsr, pci, arcmsr_driver, arcmsr_devclass, 0, 0);
224 MODULE_DEPEND(arcmsr, pci, 1, 1, 1);
225 MODULE_DEPEND(arcmsr, cam, 1, 1, 1);
226 #ifndef BUS_DMA_COHERENT
227 #define BUS_DMA_COHERENT 0x04 /* hint: map memory in a coherent way */
228 #endif
229 static struct cdevsw arcmsr_cdevsw={
230 .d_version = D_VERSION,
231 .d_open = arcmsr_open, /* open */
232 .d_close = arcmsr_close, /* close */
233 .d_ioctl = arcmsr_ioctl, /* ioctl */
234 .d_name = "arcmsr", /* name */
235 };
236 /*
237 **************************************************************************
238 **************************************************************************
239 */
arcmsr_open(struct cdev * dev,int flags,int fmt,struct thread * proc)240 static int arcmsr_open(struct cdev *dev, int flags, int fmt, struct thread *proc)
241 {
242 return (0);
243 }
244 /*
245 **************************************************************************
246 **************************************************************************
247 */
arcmsr_close(struct cdev * dev,int flags,int fmt,struct thread * proc)248 static int arcmsr_close(struct cdev *dev, int flags, int fmt, struct thread *proc)
249 {
250 return 0;
251 }
252 /*
253 **************************************************************************
254 **************************************************************************
255 */
arcmsr_ioctl(struct cdev * dev,u_long ioctl_cmd,caddr_t arg,int flags,struct thread * proc)256 static int arcmsr_ioctl(struct cdev *dev, u_long ioctl_cmd, caddr_t arg, int flags, struct thread *proc)
257 {
258 struct AdapterControlBlock *acb = dev->si_drv1;
259
260 return (arcmsr_iop_ioctlcmd(acb, ioctl_cmd, arg));
261 }
262 /*
263 **********************************************************************
264 **********************************************************************
265 */
arcmsr_disable_allintr(struct AdapterControlBlock * acb)266 static u_int32_t arcmsr_disable_allintr( struct AdapterControlBlock *acb)
267 {
268 u_int32_t intmask_org = 0;
269
270 switch (acb->adapter_type) {
271 case ACB_ADAPTER_TYPE_A: {
272 /* disable all outbound interrupt */
273 intmask_org = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intmask); /* disable outbound message0 int */
274 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intmask, intmask_org|ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE);
275 }
276 break;
277 case ACB_ADAPTER_TYPE_B: {
278 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
279 /* disable all outbound interrupt */
280 intmask_org = READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell_mask)
281 & (~ARCMSR_IOP2DRV_MESSAGE_CMD_DONE); /* disable outbound message0 int */
282 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell_mask, 0); /* disable all interrupt */
283 }
284 break;
285 case ACB_ADAPTER_TYPE_C: {
286 /* disable all outbound interrupt */
287 intmask_org = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_mask); /* disable outbound message0 int */
288 CHIP_REG_WRITE32(HBC_MessageUnit, 0, host_int_mask, intmask_org|ARCMSR_HBCMU_ALL_INTMASKENABLE);
289 }
290 break;
291 case ACB_ADAPTER_TYPE_D: {
292 /* disable all outbound interrupt */
293 intmask_org = CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable); /* disable outbound message0 int */
294 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, ARCMSR_HBDMU_ALL_INT_DISABLE);
295 }
296 break;
297 case ACB_ADAPTER_TYPE_E:
298 case ACB_ADAPTER_TYPE_F: {
299 /* disable all outbound interrupt */
300 intmask_org = CHIP_REG_READ32(HBE_MessageUnit, 0, host_int_mask); /* disable outbound message0 int */
301 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_mask, intmask_org | ARCMSR_HBEMU_ALL_INTMASKENABLE);
302 }
303 break;
304 }
305 return (intmask_org);
306 }
307 /*
308 **********************************************************************
309 **********************************************************************
310 */
arcmsr_enable_allintr(struct AdapterControlBlock * acb,u_int32_t intmask_org)311 static void arcmsr_enable_allintr( struct AdapterControlBlock *acb, u_int32_t intmask_org)
312 {
313 u_int32_t mask;
314
315 switch (acb->adapter_type) {
316 case ACB_ADAPTER_TYPE_A: {
317 /* enable outbound Post Queue, outbound doorbell Interrupt */
318 mask = ~(ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE|ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE|ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE);
319 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intmask, intmask_org & mask);
320 acb->outbound_int_enable = ~(intmask_org & mask) & 0x000000ff;
321 }
322 break;
323 case ACB_ADAPTER_TYPE_B: {
324 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
325 /* enable ARCMSR_IOP2DRV_MESSAGE_CMD_DONE */
326 mask = (ARCMSR_IOP2DRV_DATA_WRITE_OK|ARCMSR_IOP2DRV_DATA_READ_OK|ARCMSR_IOP2DRV_CDB_DONE|ARCMSR_IOP2DRV_MESSAGE_CMD_DONE);
327 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell_mask, intmask_org | mask); /*1=interrupt enable, 0=interrupt disable*/
328 acb->outbound_int_enable = (intmask_org | mask) & 0x0000000f;
329 }
330 break;
331 case ACB_ADAPTER_TYPE_C: {
332 /* enable outbound Post Queue, outbound doorbell Interrupt */
333 mask = ~(ARCMSR_HBCMU_UTILITY_A_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK);
334 CHIP_REG_WRITE32(HBC_MessageUnit, 0, host_int_mask, intmask_org & mask);
335 acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f;
336 }
337 break;
338 case ACB_ADAPTER_TYPE_D: {
339 /* enable outbound Post Queue, outbound doorbell Interrupt */
340 mask = ARCMSR_HBDMU_ALL_INT_ENABLE;
341 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, intmask_org | mask);
342 CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable);
343 acb->outbound_int_enable = mask;
344 }
345 break;
346 case ACB_ADAPTER_TYPE_E:
347 case ACB_ADAPTER_TYPE_F: {
348 /* enable outbound Post Queue, outbound doorbell Interrupt */
349 mask = ~(ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR | ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR);
350 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_mask, intmask_org & mask);
351 acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f;
352 }
353 break;
354 }
355 }
356 /*
357 **********************************************************************
358 **********************************************************************
359 */
arcmsr_hba_wait_msgint_ready(struct AdapterControlBlock * acb)360 static u_int8_t arcmsr_hba_wait_msgint_ready(struct AdapterControlBlock *acb)
361 {
362 u_int32_t Index;
363 u_int8_t Retries = 0x00;
364
365 do {
366 for(Index=0; Index < 100; Index++) {
367 if(CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) {
368 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, ARCMSR_MU_OUTBOUND_MESSAGE0_INT);/*clear interrupt*/
369 return TRUE;
370 }
371 UDELAY(10000);
372 }/*max 1 seconds*/
373 }while(Retries++ < 20);/*max 20 sec*/
374 return (FALSE);
375 }
376 /*
377 **********************************************************************
378 **********************************************************************
379 */
arcmsr_hbb_wait_msgint_ready(struct AdapterControlBlock * acb)380 static u_int8_t arcmsr_hbb_wait_msgint_ready(struct AdapterControlBlock *acb)
381 {
382 u_int32_t Index;
383 u_int8_t Retries = 0x00;
384 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
385
386 do {
387 for(Index=0; Index < 100; Index++) {
388 if(READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell) & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) {
389 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN);/*clear interrupt*/
390 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT);
391 return TRUE;
392 }
393 UDELAY(10000);
394 }/*max 1 seconds*/
395 }while(Retries++ < 20);/*max 20 sec*/
396 return (FALSE);
397 }
398 /*
399 **********************************************************************
400 **********************************************************************
401 */
arcmsr_hbc_wait_msgint_ready(struct AdapterControlBlock * acb)402 static u_int8_t arcmsr_hbc_wait_msgint_ready(struct AdapterControlBlock *acb)
403 {
404 u_int32_t Index;
405 u_int8_t Retries = 0x00;
406
407 do {
408 for(Index=0; Index < 100; Index++) {
409 if(CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
410 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR);/*clear interrupt*/
411 return TRUE;
412 }
413 UDELAY(10000);
414 }/*max 1 seconds*/
415 }while(Retries++ < 20);/*max 20 sec*/
416 return (FALSE);
417 }
418 /*
419 **********************************************************************
420 **********************************************************************
421 */
arcmsr_hbd_wait_msgint_ready(struct AdapterControlBlock * acb)422 static u_int8_t arcmsr_hbd_wait_msgint_ready(struct AdapterControlBlock *acb)
423 {
424 u_int32_t Index;
425 u_int8_t Retries = 0x00;
426
427 do {
428 for(Index=0; Index < 100; Index++) {
429 if(CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) {
430 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR);/*clear interrupt*/
431 return TRUE;
432 }
433 UDELAY(10000);
434 }/*max 1 seconds*/
435 }while(Retries++ < 20);/*max 20 sec*/
436 return (FALSE);
437 }
438 /*
439 **********************************************************************
440 **********************************************************************
441 */
arcmsr_hbe_wait_msgint_ready(struct AdapterControlBlock * acb)442 static u_int8_t arcmsr_hbe_wait_msgint_ready(struct AdapterControlBlock *acb)
443 {
444 u_int32_t Index, read_doorbell;
445 u_int8_t Retries = 0x00;
446
447 do {
448 for(Index=0; Index < 100; Index++) {
449 read_doorbell = CHIP_REG_READ32(HBE_MessageUnit, 0, iobound_doorbell);
450 if((read_doorbell ^ acb->in_doorbell) & ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE) {
451 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0);/*clear interrupt*/
452 acb->in_doorbell = read_doorbell;
453 return TRUE;
454 }
455 UDELAY(10000);
456 }/*max 1 seconds*/
457 }while(Retries++ < 20);/*max 20 sec*/
458 return (FALSE);
459 }
460 /*
461 ************************************************************************
462 ************************************************************************
463 */
arcmsr_flush_hba_cache(struct AdapterControlBlock * acb)464 static void arcmsr_flush_hba_cache(struct AdapterControlBlock *acb)
465 {
466 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */
467
468 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE);
469 do {
470 if(arcmsr_hba_wait_msgint_ready(acb)) {
471 break;
472 } else {
473 retry_count--;
474 }
475 }while(retry_count != 0);
476 }
477 /*
478 ************************************************************************
479 ************************************************************************
480 */
arcmsr_flush_hbb_cache(struct AdapterControlBlock * acb)481 static void arcmsr_flush_hbb_cache(struct AdapterControlBlock *acb)
482 {
483 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */
484 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
485
486 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_FLUSH_CACHE);
487 do {
488 if(arcmsr_hbb_wait_msgint_ready(acb)) {
489 break;
490 } else {
491 retry_count--;
492 }
493 }while(retry_count != 0);
494 }
495 /*
496 ************************************************************************
497 ************************************************************************
498 */
arcmsr_flush_hbc_cache(struct AdapterControlBlock * acb)499 static void arcmsr_flush_hbc_cache(struct AdapterControlBlock *acb)
500 {
501 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */
502
503 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE);
504 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
505 do {
506 if(arcmsr_hbc_wait_msgint_ready(acb)) {
507 break;
508 } else {
509 retry_count--;
510 }
511 }while(retry_count != 0);
512 }
513 /*
514 ************************************************************************
515 ************************************************************************
516 */
arcmsr_flush_hbd_cache(struct AdapterControlBlock * acb)517 static void arcmsr_flush_hbd_cache(struct AdapterControlBlock *acb)
518 {
519 int retry_count = 30; /* enlarge wait flush adapter cache time: 10 minute */
520
521 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE);
522 do {
523 if(arcmsr_hbd_wait_msgint_ready(acb)) {
524 break;
525 } else {
526 retry_count--;
527 }
528 }while(retry_count != 0);
529 }
530 /*
531 ************************************************************************
532 ************************************************************************
533 */
arcmsr_flush_hbe_cache(struct AdapterControlBlock * acb)534 static void arcmsr_flush_hbe_cache(struct AdapterControlBlock *acb)
535 {
536 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */
537
538 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE);
539 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
540 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
541 do {
542 if(arcmsr_hbe_wait_msgint_ready(acb)) {
543 break;
544 } else {
545 retry_count--;
546 }
547 }while(retry_count != 0);
548 }
549 /*
550 ************************************************************************
551 ************************************************************************
552 */
arcmsr_flush_adapter_cache(struct AdapterControlBlock * acb)553 static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb)
554 {
555 switch (acb->adapter_type) {
556 case ACB_ADAPTER_TYPE_A: {
557 arcmsr_flush_hba_cache(acb);
558 }
559 break;
560 case ACB_ADAPTER_TYPE_B: {
561 arcmsr_flush_hbb_cache(acb);
562 }
563 break;
564 case ACB_ADAPTER_TYPE_C: {
565 arcmsr_flush_hbc_cache(acb);
566 }
567 break;
568 case ACB_ADAPTER_TYPE_D: {
569 arcmsr_flush_hbd_cache(acb);
570 }
571 break;
572 case ACB_ADAPTER_TYPE_E:
573 case ACB_ADAPTER_TYPE_F: {
574 arcmsr_flush_hbe_cache(acb);
575 }
576 break;
577 }
578 }
579 /*
580 *******************************************************************************
581 *******************************************************************************
582 */
arcmsr_suspend(device_t dev)583 static int arcmsr_suspend(device_t dev)
584 {
585 struct AdapterControlBlock *acb = device_get_softc(dev);
586
587 /* flush controller */
588 arcmsr_iop_parking(acb);
589 /* disable all outbound interrupt */
590 arcmsr_disable_allintr(acb);
591 return(0);
592 }
593 /*
594 *******************************************************************************
595 *******************************************************************************
596 */
arcmsr_resume(device_t dev)597 static int arcmsr_resume(device_t dev)
598 {
599 struct AdapterControlBlock *acb = device_get_softc(dev);
600
601 arcmsr_iop_init(acb);
602 return(0);
603 }
604 /*
605 *********************************************************************************
606 *********************************************************************************
607 */
arcmsr_async(void * cb_arg,u_int32_t code,struct cam_path * path,void * arg)608 static void arcmsr_async(void *cb_arg, u_int32_t code, struct cam_path *path, void *arg)
609 {
610 struct AdapterControlBlock *acb;
611 u_int8_t target_id, target_lun;
612 struct cam_sim *sim;
613
614 sim = (struct cam_sim *) cb_arg;
615 acb =(struct AdapterControlBlock *) cam_sim_softc(sim);
616 switch (code) {
617 case AC_LOST_DEVICE:
618 target_id = xpt_path_target_id(path);
619 target_lun = xpt_path_lun_id(path);
620 if((target_id > ARCMSR_MAX_TARGETID) || (target_lun > ARCMSR_MAX_TARGETLUN)) {
621 break;
622 }
623 // printf("%s:scsi id=%d lun=%d device lost \n", device_get_name(acb->pci_dev), target_id, target_lun);
624 break;
625 default:
626 break;
627 }
628 }
629 /*
630 **********************************************************************
631 **********************************************************************
632 */
arcmsr_report_sense_info(struct CommandControlBlock * srb)633 static void arcmsr_report_sense_info(struct CommandControlBlock *srb)
634 {
635 union ccb *pccb = srb->pccb;
636
637 pccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR;
638 pccb->csio.scsi_status = SCSI_STATUS_CHECK_COND;
639 if(pccb->csio.sense_len) {
640 memset(&pccb->csio.sense_data, 0, sizeof(pccb->csio.sense_data));
641 memcpy(&pccb->csio.sense_data, srb->arcmsr_cdb.SenseData,
642 get_min(sizeof(struct SENSE_DATA), sizeof(pccb->csio.sense_data)));
643 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70); /* Valid,ErrorCode */
644 pccb->ccb_h.status |= CAM_AUTOSNS_VALID;
645 }
646 }
647 /*
648 *********************************************************************
649 *********************************************************************
650 */
arcmsr_abort_hba_allcmd(struct AdapterControlBlock * acb)651 static void arcmsr_abort_hba_allcmd(struct AdapterControlBlock *acb)
652 {
653 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD);
654 if(!arcmsr_hba_wait_msgint_ready(acb)) {
655 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit);
656 }
657 }
658 /*
659 *********************************************************************
660 *********************************************************************
661 */
arcmsr_abort_hbb_allcmd(struct AdapterControlBlock * acb)662 static void arcmsr_abort_hbb_allcmd(struct AdapterControlBlock *acb)
663 {
664 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
665 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_ABORT_CMD);
666 if(!arcmsr_hbb_wait_msgint_ready(acb)) {
667 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit);
668 }
669 }
670 /*
671 *********************************************************************
672 *********************************************************************
673 */
arcmsr_abort_hbc_allcmd(struct AdapterControlBlock * acb)674 static void arcmsr_abort_hbc_allcmd(struct AdapterControlBlock *acb)
675 {
676 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD);
677 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
678 if(!arcmsr_hbc_wait_msgint_ready(acb)) {
679 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit);
680 }
681 }
682 /*
683 *********************************************************************
684 *********************************************************************
685 */
arcmsr_abort_hbd_allcmd(struct AdapterControlBlock * acb)686 static void arcmsr_abort_hbd_allcmd(struct AdapterControlBlock *acb)
687 {
688 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD);
689 if(!arcmsr_hbd_wait_msgint_ready(acb)) {
690 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit);
691 }
692 }
693 /*
694 *********************************************************************
695 *********************************************************************
696 */
arcmsr_abort_hbe_allcmd(struct AdapterControlBlock * acb)697 static void arcmsr_abort_hbe_allcmd(struct AdapterControlBlock *acb)
698 {
699 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD);
700 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
701 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
702 if(!arcmsr_hbe_wait_msgint_ready(acb)) {
703 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit);
704 }
705 }
706 /*
707 *********************************************************************
708 *********************************************************************
709 */
arcmsr_abort_allcmd(struct AdapterControlBlock * acb)710 static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb)
711 {
712 switch (acb->adapter_type) {
713 case ACB_ADAPTER_TYPE_A: {
714 arcmsr_abort_hba_allcmd(acb);
715 }
716 break;
717 case ACB_ADAPTER_TYPE_B: {
718 arcmsr_abort_hbb_allcmd(acb);
719 }
720 break;
721 case ACB_ADAPTER_TYPE_C: {
722 arcmsr_abort_hbc_allcmd(acb);
723 }
724 break;
725 case ACB_ADAPTER_TYPE_D: {
726 arcmsr_abort_hbd_allcmd(acb);
727 }
728 break;
729 case ACB_ADAPTER_TYPE_E:
730 case ACB_ADAPTER_TYPE_F: {
731 arcmsr_abort_hbe_allcmd(acb);
732 }
733 break;
734 }
735 }
736 /*
737 **********************************************************************
738 **********************************************************************
739 */
arcmsr_srb_complete(struct CommandControlBlock * srb,int stand_flag)740 static void arcmsr_srb_complete(struct CommandControlBlock *srb, int stand_flag)
741 {
742 struct AdapterControlBlock *acb = srb->acb;
743 union ccb *pccb = srb->pccb;
744
745 if(srb->srb_flags & SRB_FLAG_TIMER_START)
746 callout_stop(&srb->ccb_callout);
747 if((pccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
748 bus_dmasync_op_t op;
749
750 if((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) {
751 op = BUS_DMASYNC_POSTREAD;
752 } else {
753 op = BUS_DMASYNC_POSTWRITE;
754 }
755 bus_dmamap_sync(acb->dm_segs_dmat, srb->dm_segs_dmamap, op);
756 bus_dmamap_unload(acb->dm_segs_dmat, srb->dm_segs_dmamap);
757 }
758 if(stand_flag == 1) {
759 atomic_subtract_int(&acb->srboutstandingcount, 1);
760 if((acb->acb_flags & ACB_F_CAM_DEV_QFRZN) && (
761 acb->srboutstandingcount < (acb->maxOutstanding -10))) {
762 acb->acb_flags &= ~ACB_F_CAM_DEV_QFRZN;
763 pccb->ccb_h.status |= CAM_RELEASE_SIMQ;
764 }
765 }
766 if(srb->srb_state != ARCMSR_SRB_TIMEOUT)
767 arcmsr_free_srb(srb);
768 acb->pktReturnCount++;
769 xpt_done(pccb);
770 }
771 /*
772 **************************************************************************
773 **************************************************************************
774 */
arcmsr_report_srb_state(struct AdapterControlBlock * acb,struct CommandControlBlock * srb,u_int16_t error)775 static void arcmsr_report_srb_state(struct AdapterControlBlock *acb, struct CommandControlBlock *srb, u_int16_t error)
776 {
777 int target, lun;
778
779 target = srb->pccb->ccb_h.target_id;
780 lun = srb->pccb->ccb_h.target_lun;
781 if(error == FALSE) {
782 if(acb->devstate[target][lun] == ARECA_RAID_GONE) {
783 acb->devstate[target][lun] = ARECA_RAID_GOOD;
784 }
785 srb->pccb->ccb_h.status |= CAM_REQ_CMP;
786 arcmsr_srb_complete(srb, 1);
787 } else {
788 switch(srb->arcmsr_cdb.DeviceStatus) {
789 case ARCMSR_DEV_SELECT_TIMEOUT: {
790 if(acb->devstate[target][lun] == ARECA_RAID_GOOD) {
791 printf( "arcmsr%d: Target=%x, Lun=%x, selection timeout, raid volume was lost\n", acb->pci_unit, target, lun);
792 }
793 acb->devstate[target][lun] = ARECA_RAID_GONE;
794 srb->pccb->ccb_h.status |= CAM_DEV_NOT_THERE;
795 arcmsr_srb_complete(srb, 1);
796 }
797 break;
798 case ARCMSR_DEV_ABORTED:
799 case ARCMSR_DEV_INIT_FAIL: {
800 acb->devstate[target][lun] = ARECA_RAID_GONE;
801 srb->pccb->ccb_h.status |= CAM_DEV_NOT_THERE;
802 arcmsr_srb_complete(srb, 1);
803 }
804 break;
805 case SCSISTAT_CHECK_CONDITION: {
806 acb->devstate[target][lun] = ARECA_RAID_GOOD;
807 arcmsr_report_sense_info(srb);
808 arcmsr_srb_complete(srb, 1);
809 }
810 break;
811 default:
812 printf("arcmsr%d: scsi id=%d lun=%d isr got command error done,but got unknown DeviceStatus=0x%x \n"
813 , acb->pci_unit, target, lun ,srb->arcmsr_cdb.DeviceStatus);
814 acb->devstate[target][lun] = ARECA_RAID_GONE;
815 srb->pccb->ccb_h.status |= CAM_UNCOR_PARITY;
816 /*unknown error or crc error just for retry*/
817 arcmsr_srb_complete(srb, 1);
818 break;
819 }
820 }
821 }
822 /*
823 **************************************************************************
824 **************************************************************************
825 */
arcmsr_drain_donequeue(struct AdapterControlBlock * acb,u_int32_t flag_srb,u_int16_t error)826 static void arcmsr_drain_donequeue(struct AdapterControlBlock *acb, u_int32_t flag_srb, u_int16_t error)
827 {
828 struct CommandControlBlock *srb;
829
830 /* check if command done with no error*/
831 switch (acb->adapter_type) {
832 case ACB_ADAPTER_TYPE_A:
833 case ACB_ADAPTER_TYPE_B:
834 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/
835 break;
836 case ACB_ADAPTER_TYPE_C:
837 case ACB_ADAPTER_TYPE_D:
838 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0)); /*frame must be 32 bytes aligned*/
839 break;
840 case ACB_ADAPTER_TYPE_E:
841 case ACB_ADAPTER_TYPE_F:
842 srb = acb->psrb_pool[flag_srb];
843 break;
844 default:
845 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/
846 break;
847 }
848 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
849 if(srb->srb_state == ARCMSR_SRB_TIMEOUT) {
850 arcmsr_free_srb(srb);
851 printf("arcmsr%d: srb='%p' return srb has been timeouted\n", acb->pci_unit, srb);
852 return;
853 }
854 printf("arcmsr%d: return srb has been completed\n"
855 "srb='%p' srb_state=0x%x outstanding srb count=%d \n",
856 acb->pci_unit, srb, srb->srb_state, acb->srboutstandingcount);
857 return;
858 }
859 arcmsr_report_srb_state(acb, srb, error);
860 }
861 /*
862 **************************************************************************
863 **************************************************************************
864 */
arcmsr_srb_timeout(void * arg)865 static void arcmsr_srb_timeout(void *arg)
866 {
867 struct CommandControlBlock *srb = (struct CommandControlBlock *)arg;
868 struct AdapterControlBlock *acb;
869 int target, lun;
870 u_int8_t cmd;
871
872 target = srb->pccb->ccb_h.target_id;
873 lun = srb->pccb->ccb_h.target_lun;
874 acb = srb->acb;
875 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
876 if(srb->srb_state == ARCMSR_SRB_START)
877 {
878 cmd = scsiio_cdb_ptr(&srb->pccb->csio)[0];
879 srb->srb_state = ARCMSR_SRB_TIMEOUT;
880 srb->pccb->ccb_h.status |= CAM_CMD_TIMEOUT;
881 arcmsr_srb_complete(srb, 1);
882 printf("arcmsr%d: scsi id %d lun %d cmd=0x%x srb='%p' ccb command time out!\n",
883 acb->pci_unit, target, lun, cmd, srb);
884 }
885 ARCMSR_LOCK_RELEASE(&acb->isr_lock);
886 #ifdef ARCMSR_DEBUG1
887 arcmsr_dump_data(acb);
888 #endif
889 }
890
891 /*
892 **********************************************************************
893 **********************************************************************
894 */
arcmsr_done4abort_postqueue(struct AdapterControlBlock * acb)895 static void arcmsr_done4abort_postqueue(struct AdapterControlBlock *acb)
896 {
897 int i=0;
898 u_int32_t flag_srb;
899 u_int16_t error;
900
901 switch (acb->adapter_type) {
902 case ACB_ADAPTER_TYPE_A: {
903 u_int32_t outbound_intstatus;
904
905 /*clear and abort all outbound posted Q*/
906 outbound_intstatus = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable;
907 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus);/*clear interrupt*/
908 while(((flag_srb=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_queueport)) != 0xFFFFFFFF) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) {
909 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
910 arcmsr_drain_donequeue(acb, flag_srb, error);
911 }
912 }
913 break;
914 case ACB_ADAPTER_TYPE_B: {
915 struct HBB_MessageUnit *phbbmu=(struct HBB_MessageUnit *)acb->pmu;
916
917 /*clear all outbound posted Q*/
918 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN); /* clear doorbell interrupt */
919 for(i=0; i < ARCMSR_MAX_HBB_POSTQUEUE; i++) {
920 if((flag_srb = phbbmu->done_qbuffer[i]) != 0) {
921 phbbmu->done_qbuffer[i] = 0;
922 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
923 arcmsr_drain_donequeue(acb, flag_srb, error);
924 }
925 phbbmu->post_qbuffer[i] = 0;
926 }/*drain reply FIFO*/
927 phbbmu->doneq_index = 0;
928 phbbmu->postq_index = 0;
929 }
930 break;
931 case ACB_ADAPTER_TYPE_C: {
932 while((CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) {
933 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low);
934 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE;
935 arcmsr_drain_donequeue(acb, flag_srb, error);
936 }
937 }
938 break;
939 case ACB_ADAPTER_TYPE_D:
940 arcmsr_hbd_postqueue_isr(acb);
941 break;
942 case ACB_ADAPTER_TYPE_E:
943 arcmsr_hbe_postqueue_isr(acb);
944 break;
945 case ACB_ADAPTER_TYPE_F:
946 arcmsr_hbf_postqueue_isr(acb);
947 break;
948 }
949 }
950 /*
951 ****************************************************************************
952 ****************************************************************************
953 */
arcmsr_iop_reset(struct AdapterControlBlock * acb)954 static void arcmsr_iop_reset(struct AdapterControlBlock *acb)
955 {
956 struct CommandControlBlock *srb;
957 u_int32_t intmask_org;
958 u_int32_t i=0;
959
960 if(acb->srboutstandingcount>0) {
961 /* disable all outbound interrupt */
962 intmask_org = arcmsr_disable_allintr(acb);
963 /*clear and abort all outbound posted Q*/
964 arcmsr_done4abort_postqueue(acb);
965 /* talk to iop 331 outstanding command aborted*/
966 arcmsr_abort_allcmd(acb);
967 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) {
968 srb = acb->psrb_pool[i];
969 if(srb->srb_state == ARCMSR_SRB_START) {
970 srb->srb_state = ARCMSR_SRB_ABORTED;
971 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
972 arcmsr_srb_complete(srb, 1);
973 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p' aborted\n"
974 , acb->pci_unit, srb->pccb->ccb_h.target_id
975 , (uintmax_t)srb->pccb->ccb_h.target_lun, srb);
976 }
977 }
978 /* enable all outbound interrupt */
979 arcmsr_enable_allintr(acb, intmask_org);
980 }
981 acb->srboutstandingcount = 0;
982 acb->workingsrb_doneindex = 0;
983 acb->workingsrb_startindex = 0;
984 acb->pktRequestCount = 0;
985 acb->pktReturnCount = 0;
986 }
987 /*
988 **********************************************************************
989 **********************************************************************
990 */
arcmsr_build_srb(struct CommandControlBlock * srb,bus_dma_segment_t * dm_segs,u_int32_t nseg)991 static void arcmsr_build_srb(struct CommandControlBlock *srb,
992 bus_dma_segment_t *dm_segs, u_int32_t nseg)
993 {
994 struct ARCMSR_CDB *arcmsr_cdb = &srb->arcmsr_cdb;
995 u_int8_t *psge = (u_int8_t *)&arcmsr_cdb->u;
996 u_int32_t address_lo, address_hi;
997 union ccb *pccb = srb->pccb;
998 struct ccb_scsiio *pcsio = &pccb->csio;
999 u_int32_t arccdbsize = 0x30;
1000
1001 memset(arcmsr_cdb, 0, sizeof(struct ARCMSR_CDB));
1002 arcmsr_cdb->Bus = 0;
1003 arcmsr_cdb->TargetID = pccb->ccb_h.target_id;
1004 arcmsr_cdb->LUN = pccb->ccb_h.target_lun;
1005 arcmsr_cdb->Function = 1;
1006 arcmsr_cdb->CdbLength = (u_int8_t)pcsio->cdb_len;
1007 bcopy(scsiio_cdb_ptr(pcsio), arcmsr_cdb->Cdb, pcsio->cdb_len);
1008 if(nseg != 0) {
1009 struct AdapterControlBlock *acb = srb->acb;
1010 bus_dmasync_op_t op;
1011 u_int32_t length, i, cdb_sgcount = 0;
1012
1013 if((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) {
1014 op = BUS_DMASYNC_PREREAD;
1015 } else {
1016 op = BUS_DMASYNC_PREWRITE;
1017 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_WRITE;
1018 srb->srb_flags |= SRB_FLAG_WRITE;
1019 }
1020 bus_dmamap_sync(acb->dm_segs_dmat, srb->dm_segs_dmamap, op);
1021 for(i=0; i < nseg; i++) {
1022 /* Get the physical address of the current data pointer */
1023 length = arcmsr_htole32(dm_segs[i].ds_len);
1024 address_lo = arcmsr_htole32(dma_addr_lo32(dm_segs[i].ds_addr));
1025 address_hi = arcmsr_htole32(dma_addr_hi32(dm_segs[i].ds_addr));
1026 if(address_hi == 0) {
1027 struct SG32ENTRY *pdma_sg = (struct SG32ENTRY *)psge;
1028 pdma_sg->address = address_lo;
1029 pdma_sg->length = length;
1030 psge += sizeof(struct SG32ENTRY);
1031 arccdbsize += sizeof(struct SG32ENTRY);
1032 } else {
1033 u_int32_t sg64s_size = 0, tmplength = length;
1034
1035 while(1) {
1036 u_int64_t span4G, length0;
1037 struct SG64ENTRY *pdma_sg = (struct SG64ENTRY *)psge;
1038
1039 span4G = (u_int64_t)address_lo + tmplength;
1040 pdma_sg->addresshigh = address_hi;
1041 pdma_sg->address = address_lo;
1042 if(span4G > 0x100000000) {
1043 /*see if cross 4G boundary*/
1044 length0 = 0x100000000-address_lo;
1045 pdma_sg->length = (u_int32_t)length0 | IS_SG64_ADDR;
1046 address_hi = address_hi+1;
1047 address_lo = 0;
1048 tmplength = tmplength - (u_int32_t)length0;
1049 sg64s_size += sizeof(struct SG64ENTRY);
1050 psge += sizeof(struct SG64ENTRY);
1051 cdb_sgcount++;
1052 } else {
1053 pdma_sg->length = tmplength | IS_SG64_ADDR;
1054 sg64s_size += sizeof(struct SG64ENTRY);
1055 psge += sizeof(struct SG64ENTRY);
1056 break;
1057 }
1058 }
1059 arccdbsize += sg64s_size;
1060 }
1061 cdb_sgcount++;
1062 }
1063 arcmsr_cdb->sgcount = (u_int8_t)cdb_sgcount;
1064 arcmsr_cdb->DataLength = pcsio->dxfer_len;
1065 if( arccdbsize > 256) {
1066 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_SGL_BSIZE;
1067 }
1068 } else {
1069 arcmsr_cdb->DataLength = 0;
1070 }
1071 srb->arc_cdb_size = arccdbsize;
1072 arcmsr_cdb->msgPages = (arccdbsize/256) + ((arccdbsize % 256) ? 1 : 0);
1073 }
1074 /*
1075 **************************************************************************
1076 **************************************************************************
1077 */
arcmsr_post_srb(struct AdapterControlBlock * acb,struct CommandControlBlock * srb)1078 static void arcmsr_post_srb(struct AdapterControlBlock *acb, struct CommandControlBlock *srb)
1079 {
1080 u_int32_t cdb_phyaddr_low = (u_int32_t) srb->cdb_phyaddr_low;
1081 struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&srb->arcmsr_cdb;
1082
1083 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, (srb->srb_flags & SRB_FLAG_WRITE) ? BUS_DMASYNC_POSTWRITE:BUS_DMASYNC_POSTREAD);
1084 atomic_add_int(&acb->srboutstandingcount, 1);
1085 srb->srb_state = ARCMSR_SRB_START;
1086
1087 switch (acb->adapter_type) {
1088 case ACB_ADAPTER_TYPE_A: {
1089 if(arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) {
1090 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_phyaddr_low|ARCMSR_SRBPOST_FLAG_SGL_BSIZE);
1091 } else {
1092 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_phyaddr_low);
1093 }
1094 }
1095 break;
1096 case ACB_ADAPTER_TYPE_B: {
1097 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1098 int ending_index, index;
1099
1100 index = phbbmu->postq_index;
1101 ending_index = ((index+1) % ARCMSR_MAX_HBB_POSTQUEUE);
1102 phbbmu->post_qbuffer[ending_index] = 0;
1103 if(arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) {
1104 phbbmu->post_qbuffer[index] = cdb_phyaddr_low | ARCMSR_SRBPOST_FLAG_SGL_BSIZE;
1105 } else {
1106 phbbmu->post_qbuffer[index] = cdb_phyaddr_low;
1107 }
1108 index++;
1109 index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */
1110 phbbmu->postq_index = index;
1111 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_CDB_POSTED);
1112 }
1113 break;
1114 case ACB_ADAPTER_TYPE_C: {
1115 u_int32_t ccb_post_stamp, arc_cdb_size, cdb_phyaddr_hi32;
1116
1117 arc_cdb_size = (srb->arc_cdb_size > 0x300) ? 0x300 : srb->arc_cdb_size;
1118 ccb_post_stamp = (cdb_phyaddr_low | ((arc_cdb_size-1) >> 6) | 1);
1119 cdb_phyaddr_hi32 = acb->srb_phyaddr.B.phyadd_high;
1120 if(cdb_phyaddr_hi32)
1121 {
1122 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_high, cdb_phyaddr_hi32);
1123 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_low, ccb_post_stamp);
1124 }
1125 else
1126 {
1127 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_low, ccb_post_stamp);
1128 }
1129 }
1130 break;
1131 case ACB_ADAPTER_TYPE_D: {
1132 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
1133 u_int16_t index_stripped;
1134 u_int16_t postq_index;
1135 struct InBound_SRB *pinbound_srb;
1136
1137 ARCMSR_LOCK_ACQUIRE(&acb->postDone_lock);
1138 postq_index = phbdmu->postq_index;
1139 pinbound_srb = (struct InBound_SRB *)&phbdmu->post_qbuffer[postq_index & 0xFF];
1140 pinbound_srb->addressHigh = srb->cdb_phyaddr_high;
1141 pinbound_srb->addressLow = srb->cdb_phyaddr_low;
1142 pinbound_srb->length = srb->arc_cdb_size >> 2;
1143 arcmsr_cdb->Context = srb->cdb_phyaddr_low;
1144 if (postq_index & 0x4000) {
1145 index_stripped = postq_index & 0xFF;
1146 index_stripped += 1;
1147 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE;
1148 phbdmu->postq_index = index_stripped ? (index_stripped | 0x4000) : index_stripped;
1149 } else {
1150 index_stripped = postq_index;
1151 index_stripped += 1;
1152 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE;
1153 phbdmu->postq_index = index_stripped ? index_stripped : (index_stripped | 0x4000);
1154 }
1155 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inboundlist_write_pointer, postq_index);
1156 ARCMSR_LOCK_RELEASE(&acb->postDone_lock);
1157 }
1158 break;
1159 case ACB_ADAPTER_TYPE_E: {
1160 u_int32_t ccb_post_stamp, arc_cdb_size;
1161
1162 arc_cdb_size = (srb->arc_cdb_size > 0x300) ? 0x300 : srb->arc_cdb_size;
1163 ccb_post_stamp = (srb->smid | ((arc_cdb_size-1) >> 6));
1164 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_queueport_high, 0);
1165 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_queueport_low, ccb_post_stamp);
1166 }
1167 break;
1168 case ACB_ADAPTER_TYPE_F: {
1169 u_int32_t ccb_post_stamp, arc_cdb_size;
1170
1171 if (srb->arc_cdb_size <= 0x300)
1172 arc_cdb_size = (srb->arc_cdb_size - 1) >> 6 | 1;
1173 else {
1174 arc_cdb_size = ((srb->arc_cdb_size + 0xff) >> 8) + 2;
1175 if (arc_cdb_size > 0xF)
1176 arc_cdb_size = 0xF;
1177 arc_cdb_size = (arc_cdb_size << 1) | 1;
1178 }
1179 ccb_post_stamp = (srb->smid | arc_cdb_size);
1180 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_queueport_high, 0);
1181 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_queueport_low, ccb_post_stamp);
1182 }
1183 break;
1184 }
1185 }
1186 /*
1187 ************************************************************************
1188 ************************************************************************
1189 */
arcmsr_get_iop_rqbuffer(struct AdapterControlBlock * acb)1190 static struct QBUFFER *arcmsr_get_iop_rqbuffer( struct AdapterControlBlock *acb)
1191 {
1192 struct QBUFFER *qbuffer=NULL;
1193
1194 switch (acb->adapter_type) {
1195 case ACB_ADAPTER_TYPE_A: {
1196 struct HBA_MessageUnit *phbamu = (struct HBA_MessageUnit *)acb->pmu;
1197
1198 qbuffer = (struct QBUFFER *)&phbamu->message_rbuffer;
1199 }
1200 break;
1201 case ACB_ADAPTER_TYPE_B: {
1202 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1203
1204 qbuffer = (struct QBUFFER *)&phbbmu->hbb_rwbuffer->message_rbuffer;
1205 }
1206 break;
1207 case ACB_ADAPTER_TYPE_C: {
1208 struct HBC_MessageUnit *phbcmu = (struct HBC_MessageUnit *)acb->pmu;
1209
1210 qbuffer = (struct QBUFFER *)&phbcmu->message_rbuffer;
1211 }
1212 break;
1213 case ACB_ADAPTER_TYPE_D: {
1214 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
1215
1216 qbuffer = (struct QBUFFER *)&phbdmu->phbdmu->message_rbuffer;
1217 }
1218 break;
1219 case ACB_ADAPTER_TYPE_E: {
1220 struct HBE_MessageUnit *phbcmu = (struct HBE_MessageUnit *)acb->pmu;
1221
1222 qbuffer = (struct QBUFFER *)&phbcmu->message_rbuffer;
1223 }
1224 break;
1225 case ACB_ADAPTER_TYPE_F:
1226 qbuffer = (struct QBUFFER *)acb->message_rbuffer;
1227 break;
1228 }
1229 return(qbuffer);
1230 }
1231 /*
1232 ************************************************************************
1233 ************************************************************************
1234 */
arcmsr_get_iop_wqbuffer(struct AdapterControlBlock * acb)1235 static struct QBUFFER *arcmsr_get_iop_wqbuffer( struct AdapterControlBlock *acb)
1236 {
1237 struct QBUFFER *qbuffer = NULL;
1238
1239 switch (acb->adapter_type) {
1240 case ACB_ADAPTER_TYPE_A: {
1241 struct HBA_MessageUnit *phbamu = (struct HBA_MessageUnit *)acb->pmu;
1242
1243 qbuffer = (struct QBUFFER *)&phbamu->message_wbuffer;
1244 }
1245 break;
1246 case ACB_ADAPTER_TYPE_B: {
1247 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1248
1249 qbuffer = (struct QBUFFER *)&phbbmu->hbb_rwbuffer->message_wbuffer;
1250 }
1251 break;
1252 case ACB_ADAPTER_TYPE_C: {
1253 struct HBC_MessageUnit *phbcmu = (struct HBC_MessageUnit *)acb->pmu;
1254
1255 qbuffer = (struct QBUFFER *)&phbcmu->message_wbuffer;
1256 }
1257 break;
1258 case ACB_ADAPTER_TYPE_D: {
1259 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
1260
1261 qbuffer = (struct QBUFFER *)&phbdmu->phbdmu->message_wbuffer;
1262 }
1263 break;
1264 case ACB_ADAPTER_TYPE_E: {
1265 struct HBE_MessageUnit *phbcmu = (struct HBE_MessageUnit *)acb->pmu;
1266
1267 qbuffer = (struct QBUFFER *)&phbcmu->message_wbuffer;
1268 }
1269 break;
1270 case ACB_ADAPTER_TYPE_F:
1271 qbuffer = (struct QBUFFER *)acb->message_wbuffer;
1272 break;
1273 }
1274 return(qbuffer);
1275 }
1276 /*
1277 **************************************************************************
1278 **************************************************************************
1279 */
arcmsr_iop_message_read(struct AdapterControlBlock * acb)1280 static void arcmsr_iop_message_read(struct AdapterControlBlock *acb)
1281 {
1282 switch (acb->adapter_type) {
1283 case ACB_ADAPTER_TYPE_A: {
1284 /* let IOP know data has been read */
1285 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_READ_OK);
1286 }
1287 break;
1288 case ACB_ADAPTER_TYPE_B: {
1289 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1290 /* let IOP know data has been read */
1291 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_READ_OK);
1292 }
1293 break;
1294 case ACB_ADAPTER_TYPE_C: {
1295 /* let IOP know data has been read */
1296 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK);
1297 }
1298 break;
1299 case ACB_ADAPTER_TYPE_D: {
1300 /* let IOP know data has been read */
1301 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ);
1302 }
1303 break;
1304 case ACB_ADAPTER_TYPE_E:
1305 case ACB_ADAPTER_TYPE_F: {
1306 /* let IOP know data has been read */
1307 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK;
1308 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
1309 }
1310 break;
1311 }
1312 }
1313 /*
1314 **************************************************************************
1315 **************************************************************************
1316 */
arcmsr_iop_message_wrote(struct AdapterControlBlock * acb)1317 static void arcmsr_iop_message_wrote(struct AdapterControlBlock *acb)
1318 {
1319 switch (acb->adapter_type) {
1320 case ACB_ADAPTER_TYPE_A: {
1321 /*
1322 ** push inbound doorbell tell iop, driver data write ok
1323 ** and wait reply on next hwinterrupt for next Qbuffer post
1324 */
1325 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK);
1326 }
1327 break;
1328 case ACB_ADAPTER_TYPE_B: {
1329 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1330 /*
1331 ** push inbound doorbell tell iop, driver data write ok
1332 ** and wait reply on next hwinterrupt for next Qbuffer post
1333 */
1334 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_WRITE_OK);
1335 }
1336 break;
1337 case ACB_ADAPTER_TYPE_C: {
1338 /*
1339 ** push inbound doorbell tell iop, driver data write ok
1340 ** and wait reply on next hwinterrupt for next Qbuffer post
1341 */
1342 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK);
1343 }
1344 break;
1345 case ACB_ADAPTER_TYPE_D: {
1346 /*
1347 ** push inbound doorbell tell iop, driver data write ok
1348 ** and wait reply on next hwinterrupt for next Qbuffer post
1349 */
1350 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_IN_READY);
1351 }
1352 break;
1353 case ACB_ADAPTER_TYPE_E:
1354 case ACB_ADAPTER_TYPE_F: {
1355 /*
1356 ** push inbound doorbell tell iop, driver data write ok
1357 ** and wait reply on next hwinterrupt for next Qbuffer post
1358 */
1359 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_WRITE_OK;
1360 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
1361 }
1362 break;
1363 }
1364 }
1365 /*
1366 ************************************************************************
1367 ************************************************************************
1368 */
arcmsr_stop_hba_bgrb(struct AdapterControlBlock * acb)1369 static void arcmsr_stop_hba_bgrb(struct AdapterControlBlock *acb)
1370 {
1371 acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1372 CHIP_REG_WRITE32(HBA_MessageUnit,
1373 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB);
1374 if(!arcmsr_hba_wait_msgint_ready(acb)) {
1375 printf("arcmsr%d: wait 'stop adapter background rebuild' timeout \n"
1376 , acb->pci_unit);
1377 }
1378 }
1379 /*
1380 ************************************************************************
1381 ************************************************************************
1382 */
arcmsr_stop_hbb_bgrb(struct AdapterControlBlock * acb)1383 static void arcmsr_stop_hbb_bgrb(struct AdapterControlBlock *acb)
1384 {
1385 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1386 acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1387 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_STOP_BGRB);
1388 if(!arcmsr_hbb_wait_msgint_ready(acb)) {
1389 printf( "arcmsr%d: wait 'stop adapter background rebuild' timeout \n"
1390 , acb->pci_unit);
1391 }
1392 }
1393 /*
1394 ************************************************************************
1395 ************************************************************************
1396 */
arcmsr_stop_hbc_bgrb(struct AdapterControlBlock * acb)1397 static void arcmsr_stop_hbc_bgrb(struct AdapterControlBlock *acb)
1398 {
1399 acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1400 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB);
1401 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
1402 if(!arcmsr_hbc_wait_msgint_ready(acb)) {
1403 printf("arcmsr%d: wait 'stop adapter background rebuild' timeout \n", acb->pci_unit);
1404 }
1405 }
1406 /*
1407 ************************************************************************
1408 ************************************************************************
1409 */
arcmsr_stop_hbd_bgrb(struct AdapterControlBlock * acb)1410 static void arcmsr_stop_hbd_bgrb(struct AdapterControlBlock *acb)
1411 {
1412 acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1413 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB);
1414 if(!arcmsr_hbd_wait_msgint_ready(acb)) {
1415 printf("arcmsr%d: wait 'stop adapter background rebuild' timeout \n", acb->pci_unit);
1416 }
1417 }
1418 /*
1419 ************************************************************************
1420 ************************************************************************
1421 */
arcmsr_stop_hbe_bgrb(struct AdapterControlBlock * acb)1422 static void arcmsr_stop_hbe_bgrb(struct AdapterControlBlock *acb)
1423 {
1424 acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1425 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB);
1426 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
1427 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
1428 if(!arcmsr_hbe_wait_msgint_ready(acb)) {
1429 printf("arcmsr%d: wait 'stop adapter background rebuild' timeout \n", acb->pci_unit);
1430 }
1431 }
1432 /*
1433 ************************************************************************
1434 ************************************************************************
1435 */
arcmsr_stop_adapter_bgrb(struct AdapterControlBlock * acb)1436 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb)
1437 {
1438 switch (acb->adapter_type) {
1439 case ACB_ADAPTER_TYPE_A: {
1440 arcmsr_stop_hba_bgrb(acb);
1441 }
1442 break;
1443 case ACB_ADAPTER_TYPE_B: {
1444 arcmsr_stop_hbb_bgrb(acb);
1445 }
1446 break;
1447 case ACB_ADAPTER_TYPE_C: {
1448 arcmsr_stop_hbc_bgrb(acb);
1449 }
1450 break;
1451 case ACB_ADAPTER_TYPE_D: {
1452 arcmsr_stop_hbd_bgrb(acb);
1453 }
1454 break;
1455 case ACB_ADAPTER_TYPE_E:
1456 case ACB_ADAPTER_TYPE_F: {
1457 arcmsr_stop_hbe_bgrb(acb);
1458 }
1459 break;
1460 }
1461 }
1462 /*
1463 ************************************************************************
1464 ************************************************************************
1465 */
arcmsr_poll(struct cam_sim * psim)1466 static void arcmsr_poll(struct cam_sim *psim)
1467 {
1468 struct AdapterControlBlock *acb;
1469 int mutex;
1470
1471 acb = (struct AdapterControlBlock *)cam_sim_softc(psim);
1472 mutex = mtx_owned(&acb->isr_lock);
1473 if( mutex == 0 )
1474 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
1475 arcmsr_interrupt(acb);
1476 if( mutex == 0 )
1477 ARCMSR_LOCK_RELEASE(&acb->isr_lock);
1478 }
1479 /*
1480 **************************************************************************
1481 **************************************************************************
1482 */
arcmsr_Read_iop_rqbuffer_data_D(struct AdapterControlBlock * acb,struct QBUFFER * prbuffer)1483 static u_int32_t arcmsr_Read_iop_rqbuffer_data_D(struct AdapterControlBlock *acb,
1484 struct QBUFFER *prbuffer) {
1485 u_int8_t *pQbuffer;
1486 u_int8_t *buf1 = NULL;
1487 u_int32_t *iop_data, *buf2 = NULL;
1488 u_int32_t iop_len, data_len;
1489
1490 iop_data = (u_int32_t *)prbuffer->data;
1491 iop_len = (u_int32_t)prbuffer->data_len;
1492 if ( iop_len > 0 )
1493 {
1494 buf1 = malloc(128, M_DEVBUF, M_NOWAIT | M_ZERO);
1495 buf2 = (u_int32_t *)buf1;
1496 if( buf1 == NULL)
1497 return (0);
1498 data_len = iop_len;
1499 while(data_len >= 4)
1500 {
1501 *buf2++ = *iop_data++;
1502 data_len -= 4;
1503 }
1504 if(data_len)
1505 *buf2 = *iop_data;
1506 buf2 = (u_int32_t *)buf1;
1507 }
1508 while (iop_len > 0) {
1509 pQbuffer = &acb->rqbuffer[acb->rqbuf_lastindex];
1510 *pQbuffer = *buf1;
1511 acb->rqbuf_lastindex++;
1512 /* if last, index number set it to 0 */
1513 acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
1514 buf1++;
1515 iop_len--;
1516 }
1517 if(buf2)
1518 free( (u_int8_t *)buf2, M_DEVBUF);
1519 /* let IOP know data has been read */
1520 arcmsr_iop_message_read(acb);
1521 return (1);
1522 }
1523 /*
1524 **************************************************************************
1525 **************************************************************************
1526 */
arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock * acb,struct QBUFFER * prbuffer)1527 static u_int32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb,
1528 struct QBUFFER *prbuffer) {
1529 u_int8_t *pQbuffer;
1530 u_int8_t *iop_data;
1531 u_int32_t iop_len;
1532
1533 if(acb->adapter_type >= ACB_ADAPTER_TYPE_B) {
1534 return(arcmsr_Read_iop_rqbuffer_data_D(acb, prbuffer));
1535 }
1536 iop_data = (u_int8_t *)prbuffer->data;
1537 iop_len = (u_int32_t)prbuffer->data_len;
1538 while (iop_len > 0) {
1539 pQbuffer = &acb->rqbuffer[acb->rqbuf_lastindex];
1540 *pQbuffer = *iop_data;
1541 acb->rqbuf_lastindex++;
1542 /* if last, index number set it to 0 */
1543 acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
1544 iop_data++;
1545 iop_len--;
1546 }
1547 /* let IOP know data has been read */
1548 arcmsr_iop_message_read(acb);
1549 return (1);
1550 }
1551 /*
1552 **************************************************************************
1553 **************************************************************************
1554 */
arcmsr_iop2drv_data_wrote_handle(struct AdapterControlBlock * acb)1555 static void arcmsr_iop2drv_data_wrote_handle(struct AdapterControlBlock *acb)
1556 {
1557 struct QBUFFER *prbuffer;
1558 int my_empty_len;
1559
1560 /*check this iop data if overflow my rqbuffer*/
1561 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
1562 prbuffer = arcmsr_get_iop_rqbuffer(acb);
1563 if (acb->rqbuf_lastindex >= acb->rqbuf_firstindex)
1564 my_empty_len = (ARCMSR_MAX_QBUFFER - 1) - (acb->rqbuf_lastindex - acb->rqbuf_firstindex);
1565 else
1566 my_empty_len = acb->rqbuf_firstindex - acb->rqbuf_lastindex - 1;
1567 if(my_empty_len >= prbuffer->data_len) {
1568 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0)
1569 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
1570 } else {
1571 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
1572 }
1573 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
1574 }
1575 /*
1576 **********************************************************************
1577 **********************************************************************
1578 */
arcmsr_Write_data_2iop_wqbuffer_D(struct AdapterControlBlock * acb)1579 static void arcmsr_Write_data_2iop_wqbuffer_D(struct AdapterControlBlock *acb)
1580 {
1581 u_int8_t *pQbuffer;
1582 struct QBUFFER *pwbuffer;
1583 u_int8_t *buf1 = NULL;
1584 u_int32_t *iop_data, *buf2 = NULL;
1585 u_int32_t allxfer_len = 0, data_len;
1586
1587 if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READ) {
1588 buf1 = malloc(128, M_DEVBUF, M_NOWAIT | M_ZERO);
1589 buf2 = (u_int32_t *)buf1;
1590 if( buf1 == NULL)
1591 return;
1592
1593 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READ);
1594 pwbuffer = arcmsr_get_iop_wqbuffer(acb);
1595 iop_data = (u_int32_t *)pwbuffer->data;
1596 while((acb->wqbuf_firstindex != acb->wqbuf_lastindex)
1597 && (allxfer_len < 124)) {
1598 pQbuffer = &acb->wqbuffer[acb->wqbuf_firstindex];
1599 *buf1 = *pQbuffer;
1600 acb->wqbuf_firstindex++;
1601 acb->wqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
1602 buf1++;
1603 allxfer_len++;
1604 }
1605 pwbuffer->data_len = allxfer_len;
1606 data_len = allxfer_len;
1607 buf1 = (u_int8_t *)buf2;
1608 while(data_len >= 4)
1609 {
1610 *iop_data++ = *buf2++;
1611 data_len -= 4;
1612 }
1613 if(data_len)
1614 *iop_data = *buf2;
1615 free( buf1, M_DEVBUF);
1616 arcmsr_iop_message_wrote(acb);
1617 }
1618 }
1619 /*
1620 **********************************************************************
1621 **********************************************************************
1622 */
arcmsr_Write_data_2iop_wqbuffer(struct AdapterControlBlock * acb)1623 static void arcmsr_Write_data_2iop_wqbuffer(struct AdapterControlBlock *acb)
1624 {
1625 u_int8_t *pQbuffer;
1626 struct QBUFFER *pwbuffer;
1627 u_int8_t *iop_data;
1628 int32_t allxfer_len=0;
1629
1630 if(acb->adapter_type >= ACB_ADAPTER_TYPE_B) {
1631 arcmsr_Write_data_2iop_wqbuffer_D(acb);
1632 return;
1633 }
1634 if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READ) {
1635 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READ);
1636 pwbuffer = arcmsr_get_iop_wqbuffer(acb);
1637 iop_data = (u_int8_t *)pwbuffer->data;
1638 while((acb->wqbuf_firstindex != acb->wqbuf_lastindex)
1639 && (allxfer_len < 124)) {
1640 pQbuffer = &acb->wqbuffer[acb->wqbuf_firstindex];
1641 *iop_data = *pQbuffer;
1642 acb->wqbuf_firstindex++;
1643 acb->wqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
1644 iop_data++;
1645 allxfer_len++;
1646 }
1647 pwbuffer->data_len = allxfer_len;
1648 arcmsr_iop_message_wrote(acb);
1649 }
1650 }
1651 /*
1652 **************************************************************************
1653 **************************************************************************
1654 */
arcmsr_iop2drv_data_read_handle(struct AdapterControlBlock * acb)1655 static void arcmsr_iop2drv_data_read_handle(struct AdapterControlBlock *acb)
1656 {
1657 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
1658 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_READ;
1659 /*
1660 *****************************************************************
1661 ** check if there are any mail packages from user space program
1662 ** in my post bag, now is the time to send them into Areca's firmware
1663 *****************************************************************
1664 */
1665 if(acb->wqbuf_firstindex != acb->wqbuf_lastindex) {
1666 arcmsr_Write_data_2iop_wqbuffer(acb);
1667 }
1668 if(acb->wqbuf_firstindex == acb->wqbuf_lastindex) {
1669 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_CLEARED;
1670 }
1671 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
1672 }
1673 /*
1674 **************************************************************************
1675 **************************************************************************
1676 */
arcmsr_rescanLun_cb(struct cam_periph * periph,union ccb * ccb)1677 static void arcmsr_rescanLun_cb(struct cam_periph *periph, union ccb *ccb)
1678 {
1679 /*
1680 if (ccb->ccb_h.status != CAM_REQ_CMP)
1681 printf("arcmsr_rescanLun_cb: Rescan Target=%x, lun=%x,"
1682 "failure status=%x\n", ccb->ccb_h.target_id,
1683 ccb->ccb_h.target_lun, ccb->ccb_h.status);
1684 else
1685 printf("arcmsr_rescanLun_cb: Rescan lun successfully!\n");
1686 */
1687 xpt_free_path(ccb->ccb_h.path);
1688 xpt_free_ccb(ccb);
1689 }
1690
arcmsr_rescan_lun(struct AdapterControlBlock * acb,int target,int lun)1691 static void arcmsr_rescan_lun(struct AdapterControlBlock *acb, int target, int lun)
1692 {
1693 struct cam_path *path;
1694 union ccb *ccb;
1695
1696 if ((ccb = (union ccb *)xpt_alloc_ccb_nowait()) == NULL)
1697 return;
1698 if (xpt_create_path(&path, NULL, cam_sim_path(acb->psim), target, lun) != CAM_REQ_CMP)
1699 {
1700 xpt_free_ccb(ccb);
1701 return;
1702 }
1703 /* printf("arcmsr_rescan_lun: Rescan Target=%x, Lun=%x\n", target, lun); */
1704 xpt_setup_ccb(&ccb->ccb_h, path, 5);
1705 ccb->ccb_h.func_code = XPT_SCAN_LUN;
1706 ccb->ccb_h.cbfcnp = arcmsr_rescanLun_cb;
1707 ccb->crcn.flags = CAM_FLAG_NONE;
1708 xpt_action(ccb);
1709 }
1710
arcmsr_abort_dr_ccbs(struct AdapterControlBlock * acb,int target,int lun)1711 static void arcmsr_abort_dr_ccbs(struct AdapterControlBlock *acb, int target, int lun)
1712 {
1713 struct CommandControlBlock *srb;
1714 u_int32_t intmask_org;
1715 int i;
1716
1717 /* disable all outbound interrupts */
1718 intmask_org = arcmsr_disable_allintr(acb);
1719 for (i = 0; i < ARCMSR_MAX_FREESRB_NUM; i++)
1720 {
1721 srb = acb->psrb_pool[i];
1722 if (srb->srb_state == ARCMSR_SRB_START)
1723 {
1724 if((target == srb->pccb->ccb_h.target_id) && (lun == srb->pccb->ccb_h.target_lun))
1725 {
1726 srb->srb_state = ARCMSR_SRB_ABORTED;
1727 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
1728 arcmsr_srb_complete(srb, 1);
1729 printf("arcmsr%d: abort scsi id %d lun %d srb=%p \n", acb->pci_unit, target, lun, srb);
1730 }
1731 }
1732 }
1733 /* enable outbound Post Queue, outbound doorbell Interrupt */
1734 arcmsr_enable_allintr(acb, intmask_org);
1735 }
1736 /*
1737 **************************************************************************
1738 **************************************************************************
1739 */
arcmsr_dr_handle(struct AdapterControlBlock * acb)1740 static void arcmsr_dr_handle(struct AdapterControlBlock *acb) {
1741 u_int32_t devicemap;
1742 u_int32_t target, lun;
1743 u_int32_t deviceMapCurrent[4]={0};
1744 u_int8_t *pDevMap;
1745
1746 switch (acb->adapter_type) {
1747 case ACB_ADAPTER_TYPE_A:
1748 devicemap = offsetof(struct HBA_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
1749 for (target = 0; target < 4; target++)
1750 {
1751 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap);
1752 devicemap += 4;
1753 }
1754 break;
1755
1756 case ACB_ADAPTER_TYPE_B:
1757 devicemap = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
1758 for (target = 0; target < 4; target++)
1759 {
1760 deviceMapCurrent[target]=bus_space_read_4(acb->btag[1], acb->bhandle[1], devicemap);
1761 devicemap += 4;
1762 }
1763 break;
1764
1765 case ACB_ADAPTER_TYPE_C:
1766 devicemap = offsetof(struct HBC_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
1767 for (target = 0; target < 4; target++)
1768 {
1769 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap);
1770 devicemap += 4;
1771 }
1772 break;
1773 case ACB_ADAPTER_TYPE_D:
1774 devicemap = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
1775 for (target = 0; target < 4; target++)
1776 {
1777 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap);
1778 devicemap += 4;
1779 }
1780 break;
1781 case ACB_ADAPTER_TYPE_E:
1782 devicemap = offsetof(struct HBE_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
1783 for (target = 0; target < 4; target++)
1784 {
1785 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap);
1786 devicemap += 4;
1787 }
1788 break;
1789 case ACB_ADAPTER_TYPE_F:
1790 devicemap = ARCMSR_FW_DEVMAP_OFFSET;
1791 for (target = 0; target < 4; target++)
1792 {
1793 deviceMapCurrent[target] = acb->msgcode_rwbuffer[devicemap];
1794 devicemap += 1;
1795 }
1796 break;
1797 }
1798
1799 if(acb->acb_flags & ACB_F_BUS_HANG_ON)
1800 {
1801 acb->acb_flags &= ~ACB_F_BUS_HANG_ON;
1802 }
1803 /*
1804 ** adapter posted CONFIG message
1805 ** copy the new map, note if there are differences with the current map
1806 */
1807 pDevMap = (u_int8_t *)&deviceMapCurrent[0];
1808 for (target = 0; target < ARCMSR_MAX_TARGETID - 1; target++)
1809 {
1810 if (*pDevMap != acb->device_map[target])
1811 {
1812 u_int8_t difference, bit_check;
1813
1814 difference = *pDevMap ^ acb->device_map[target];
1815 for(lun=0; lun < ARCMSR_MAX_TARGETLUN; lun++)
1816 {
1817 bit_check = (1 << lun); /*check bit from 0....31*/
1818 if(difference & bit_check)
1819 {
1820 if(acb->device_map[target] & bit_check)
1821 {/* unit departed */
1822 printf("arcmsr_dr_handle: Target=%x, lun=%x, GONE!!!\n",target,lun);
1823 arcmsr_abort_dr_ccbs(acb, target, lun);
1824 arcmsr_rescan_lun(acb, target, lun);
1825 acb->devstate[target][lun] = ARECA_RAID_GONE;
1826 }
1827 else
1828 {/* unit arrived */
1829 printf("arcmsr_dr_handle: Target=%x, lun=%x, Plug-IN!!!\n",target,lun);
1830 arcmsr_rescan_lun(acb, target, lun);
1831 acb->devstate[target][lun] = ARECA_RAID_GOOD;
1832 }
1833 }
1834 }
1835 /* printf("arcmsr_dr_handle: acb->device_map[%x]=0x%x, deviceMapCurrent[%x]=%x\n",target,acb->device_map[target],target,*pDevMap); */
1836 acb->device_map[target] = *pDevMap;
1837 }
1838 pDevMap++;
1839 }
1840 }
1841 /*
1842 **************************************************************************
1843 **************************************************************************
1844 */
arcmsr_hba_message_isr(struct AdapterControlBlock * acb)1845 static void arcmsr_hba_message_isr(struct AdapterControlBlock *acb) {
1846 u_int32_t outbound_message;
1847
1848 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, ARCMSR_MU_OUTBOUND_MESSAGE0_INT);
1849 outbound_message = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[0]);
1850 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG)
1851 arcmsr_dr_handle( acb );
1852 }
1853 /*
1854 **************************************************************************
1855 **************************************************************************
1856 */
arcmsr_hbb_message_isr(struct AdapterControlBlock * acb)1857 static void arcmsr_hbb_message_isr(struct AdapterControlBlock *acb) {
1858 u_int32_t outbound_message;
1859 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1860
1861 /* clear interrupts */
1862 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN);
1863 outbound_message = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[0]);
1864 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG)
1865 arcmsr_dr_handle( acb );
1866 }
1867 /*
1868 **************************************************************************
1869 **************************************************************************
1870 */
arcmsr_hbc_message_isr(struct AdapterControlBlock * acb)1871 static void arcmsr_hbc_message_isr(struct AdapterControlBlock *acb) {
1872 u_int32_t outbound_message;
1873
1874 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR);
1875 outbound_message = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[0]);
1876 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG)
1877 arcmsr_dr_handle( acb );
1878 }
1879 /*
1880 **************************************************************************
1881 **************************************************************************
1882 */
arcmsr_hbd_message_isr(struct AdapterControlBlock * acb)1883 static void arcmsr_hbd_message_isr(struct AdapterControlBlock *acb) {
1884 u_int32_t outbound_message;
1885
1886 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR);
1887 outbound_message = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[0]);
1888 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG)
1889 arcmsr_dr_handle( acb );
1890 }
1891 /*
1892 **************************************************************************
1893 **************************************************************************
1894 */
arcmsr_hbe_message_isr(struct AdapterControlBlock * acb)1895 static void arcmsr_hbe_message_isr(struct AdapterControlBlock *acb) {
1896 u_int32_t outbound_message;
1897
1898 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0);
1899 if (acb->adapter_type == ACB_ADAPTER_TYPE_E)
1900 outbound_message = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[0]);
1901 else
1902 outbound_message = acb->msgcode_rwbuffer[0];
1903 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG)
1904 arcmsr_dr_handle( acb );
1905 }
1906 /*
1907 **************************************************************************
1908 **************************************************************************
1909 */
arcmsr_hba_doorbell_isr(struct AdapterControlBlock * acb)1910 static void arcmsr_hba_doorbell_isr(struct AdapterControlBlock *acb)
1911 {
1912 u_int32_t doorbell_status;
1913
1914 /*
1915 *******************************************************************
1916 ** Maybe here we need to check wrqbuffer_lock is lock or not
1917 ** DOORBELL: din! don!
1918 ** check if there are any mail need to pack from firmware
1919 *******************************************************************
1920 */
1921 doorbell_status = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_doorbell);
1922 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */
1923 if(doorbell_status & ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK) {
1924 arcmsr_iop2drv_data_wrote_handle(acb);
1925 }
1926 if(doorbell_status & ARCMSR_OUTBOUND_IOP331_DATA_READ_OK) {
1927 arcmsr_iop2drv_data_read_handle(acb);
1928 }
1929 }
1930 /*
1931 **************************************************************************
1932 **************************************************************************
1933 */
arcmsr_hbc_doorbell_isr(struct AdapterControlBlock * acb)1934 static void arcmsr_hbc_doorbell_isr(struct AdapterControlBlock *acb)
1935 {
1936 u_int32_t doorbell_status;
1937
1938 /*
1939 *******************************************************************
1940 ** Maybe here we need to check wrqbuffer_lock is lock or not
1941 ** DOORBELL: din! don!
1942 ** check if there are any mail need to pack from firmware
1943 *******************************************************************
1944 */
1945 doorbell_status = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell);
1946 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, doorbell_status); /* clear doorbell interrupt */
1947 if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK) {
1948 arcmsr_iop2drv_data_wrote_handle(acb);
1949 }
1950 if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK) {
1951 arcmsr_iop2drv_data_read_handle(acb);
1952 }
1953 if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
1954 arcmsr_hbc_message_isr(acb); /* messenger of "driver to iop commands" */
1955 }
1956 }
1957 /*
1958 **************************************************************************
1959 **************************************************************************
1960 */
arcmsr_hbd_doorbell_isr(struct AdapterControlBlock * acb)1961 static void arcmsr_hbd_doorbell_isr(struct AdapterControlBlock *acb)
1962 {
1963 u_int32_t doorbell_status;
1964
1965 /*
1966 *******************************************************************
1967 ** Maybe here we need to check wrqbuffer_lock is lock or not
1968 ** DOORBELL: din! don!
1969 ** check if there are any mail need to pack from firmware
1970 *******************************************************************
1971 */
1972 doorbell_status = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_F0_DOORBELL_CAUSE;
1973 if(doorbell_status)
1974 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */
1975 while( doorbell_status & ARCMSR_HBDMU_F0_DOORBELL_CAUSE ) {
1976 if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_DATA_WRITE_OK) {
1977 arcmsr_iop2drv_data_wrote_handle(acb);
1978 }
1979 if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_DATA_READ_OK) {
1980 arcmsr_iop2drv_data_read_handle(acb);
1981 }
1982 if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) {
1983 arcmsr_hbd_message_isr(acb); /* messenger of "driver to iop commands" */
1984 }
1985 doorbell_status = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_F0_DOORBELL_CAUSE;
1986 if(doorbell_status)
1987 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */
1988 }
1989 }
1990 /*
1991 **************************************************************************
1992 **************************************************************************
1993 */
arcmsr_hbe_doorbell_isr(struct AdapterControlBlock * acb)1994 static void arcmsr_hbe_doorbell_isr(struct AdapterControlBlock *acb)
1995 {
1996 u_int32_t doorbell_status, in_doorbell;
1997
1998 /*
1999 *******************************************************************
2000 ** Maybe here we need to check wrqbuffer_lock is lock or not
2001 ** DOORBELL: din! don!
2002 ** check if there are any mail need to pack from firmware
2003 *******************************************************************
2004 */
2005 in_doorbell = CHIP_REG_READ32(HBE_MessageUnit, 0, iobound_doorbell);
2006 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); /* clear doorbell interrupt */
2007 doorbell_status = in_doorbell ^ acb->in_doorbell;
2008 if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK) {
2009 arcmsr_iop2drv_data_wrote_handle(acb);
2010 }
2011 if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK) {
2012 arcmsr_iop2drv_data_read_handle(acb);
2013 }
2014 if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE) {
2015 arcmsr_hbe_message_isr(acb); /* messenger of "driver to iop commands" */
2016 }
2017 acb->in_doorbell = in_doorbell;
2018 }
2019 /*
2020 **************************************************************************
2021 **************************************************************************
2022 */
arcmsr_hbf_doorbell_isr(struct AdapterControlBlock * acb)2023 static void arcmsr_hbf_doorbell_isr(struct AdapterControlBlock *acb)
2024 {
2025 u_int32_t doorbell_status, in_doorbell;
2026
2027 /*
2028 *******************************************************************
2029 ** Maybe here we need to check wrqbuffer_lock is lock or not
2030 ** DOORBELL: din! don!
2031 ** check if there are any mail need to pack from firmware
2032 *******************************************************************
2033 */
2034 while(1) {
2035 in_doorbell = CHIP_REG_READ32(HBE_MessageUnit, 0, iobound_doorbell);
2036 if ((in_doorbell != 0) && (in_doorbell != 0xFFFFFFFF))
2037 break;
2038 }
2039 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); /* clear doorbell interrupt */
2040 doorbell_status = in_doorbell ^ acb->in_doorbell;
2041 if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK) {
2042 arcmsr_iop2drv_data_wrote_handle(acb);
2043 }
2044 if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK) {
2045 arcmsr_iop2drv_data_read_handle(acb);
2046 }
2047 if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE) {
2048 arcmsr_hbe_message_isr(acb); /* messenger of "driver to iop commands" */
2049 }
2050 acb->in_doorbell = in_doorbell;
2051 }
2052 /*
2053 **************************************************************************
2054 **************************************************************************
2055 */
arcmsr_hba_postqueue_isr(struct AdapterControlBlock * acb)2056 static void arcmsr_hba_postqueue_isr(struct AdapterControlBlock *acb)
2057 {
2058 u_int32_t flag_srb;
2059 u_int16_t error;
2060
2061 /*
2062 *****************************************************************************
2063 ** areca cdb command done
2064 *****************************************************************************
2065 */
2066 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap,
2067 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
2068 while((flag_srb = CHIP_REG_READ32(HBA_MessageUnit,
2069 0, outbound_queueport)) != 0xFFFFFFFF) {
2070 /* check if command done with no error*/
2071 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0) ? TRUE : FALSE;
2072 arcmsr_drain_donequeue(acb, flag_srb, error);
2073 } /*drain reply FIFO*/
2074 }
2075 /*
2076 **************************************************************************
2077 **************************************************************************
2078 */
arcmsr_hbb_postqueue_isr(struct AdapterControlBlock * acb)2079 static void arcmsr_hbb_postqueue_isr(struct AdapterControlBlock *acb)
2080 {
2081 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
2082 u_int32_t flag_srb;
2083 int index;
2084 u_int16_t error;
2085
2086 /*
2087 *****************************************************************************
2088 ** areca cdb command done
2089 *****************************************************************************
2090 */
2091 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap,
2092 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
2093 index = phbbmu->doneq_index;
2094 while((flag_srb = phbbmu->done_qbuffer[index]) != 0) {
2095 phbbmu->done_qbuffer[index] = 0;
2096 index++;
2097 index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */
2098 phbbmu->doneq_index = index;
2099 /* check if command done with no error*/
2100 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
2101 arcmsr_drain_donequeue(acb, flag_srb, error);
2102 } /*drain reply FIFO*/
2103 }
2104 /*
2105 **************************************************************************
2106 **************************************************************************
2107 */
arcmsr_hbc_postqueue_isr(struct AdapterControlBlock * acb)2108 static void arcmsr_hbc_postqueue_isr(struct AdapterControlBlock *acb)
2109 {
2110 u_int32_t flag_srb,throttling = 0;
2111 u_int16_t error;
2112
2113 /*
2114 *****************************************************************************
2115 ** areca cdb command done
2116 *****************************************************************************
2117 */
2118 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2119 do {
2120 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low);
2121 if (flag_srb == 0xFFFFFFFF)
2122 break;
2123 /* check if command done with no error*/
2124 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE;
2125 arcmsr_drain_donequeue(acb, flag_srb, error);
2126 throttling++;
2127 if(throttling == ARCMSR_HBC_ISR_THROTTLING_LEVEL) {
2128 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING);
2129 throttling = 0;
2130 }
2131 } while(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR);
2132 }
2133 /*
2134 **********************************************************************
2135 **
2136 **********************************************************************
2137 */
arcmsr_get_doneq_index(struct HBD_MessageUnit0 * phbdmu)2138 static uint16_t arcmsr_get_doneq_index(struct HBD_MessageUnit0 *phbdmu)
2139 {
2140 uint16_t doneq_index, index_stripped;
2141
2142 doneq_index = phbdmu->doneq_index;
2143 if (doneq_index & 0x4000) {
2144 index_stripped = doneq_index & 0xFF;
2145 index_stripped += 1;
2146 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE;
2147 phbdmu->doneq_index = index_stripped ?
2148 (index_stripped | 0x4000) : index_stripped;
2149 } else {
2150 index_stripped = doneq_index;
2151 index_stripped += 1;
2152 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE;
2153 phbdmu->doneq_index = index_stripped ?
2154 index_stripped : (index_stripped | 0x4000);
2155 }
2156 return (phbdmu->doneq_index);
2157 }
2158 /*
2159 **************************************************************************
2160 **************************************************************************
2161 */
arcmsr_hbd_postqueue_isr(struct AdapterControlBlock * acb)2162 static void arcmsr_hbd_postqueue_isr(struct AdapterControlBlock *acb)
2163 {
2164 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
2165 u_int32_t outbound_write_pointer;
2166 u_int32_t addressLow;
2167 uint16_t doneq_index;
2168 u_int16_t error;
2169 /*
2170 *****************************************************************************
2171 ** areca cdb command done
2172 *****************************************************************************
2173 */
2174 if((CHIP_REG_READ32(HBD_MessageUnit, 0, outboundlist_interrupt_cause) &
2175 ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT) == 0)
2176 return;
2177 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap,
2178 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2179 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow;
2180 doneq_index = phbdmu->doneq_index;
2181 while ((doneq_index & 0xFF) != (outbound_write_pointer & 0xFF)) {
2182 doneq_index = arcmsr_get_doneq_index(phbdmu);
2183 addressLow = phbdmu->done_qbuffer[(doneq_index & 0xFF)+1].addressLow;
2184 error = (addressLow & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE;
2185 arcmsr_drain_donequeue(acb, addressLow, error); /*Check if command done with no error */
2186 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_read_pointer, doneq_index);
2187 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow;
2188 }
2189 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_interrupt_cause, ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT_CLEAR);
2190 CHIP_REG_READ32(HBD_MessageUnit, 0, outboundlist_interrupt_cause); /*Dummy ioread32 to force pci flush */
2191 }
2192 /*
2193 **************************************************************************
2194 **************************************************************************
2195 */
arcmsr_hbe_postqueue_isr(struct AdapterControlBlock * acb)2196 static void arcmsr_hbe_postqueue_isr(struct AdapterControlBlock *acb)
2197 {
2198 u_int16_t error;
2199 uint32_t doneq_index;
2200 uint16_t cmdSMID;
2201
2202 /*
2203 *****************************************************************************
2204 ** areca cdb command done
2205 *****************************************************************************
2206 */
2207 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2208 doneq_index = acb->doneq_index;
2209 while ((CHIP_REG_READ32(HBE_MessageUnit, 0, reply_post_producer_index) & 0xFFFF) != doneq_index) {
2210 cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID;
2211 error = (acb->pCompletionQ[doneq_index].cmdFlag & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE;
2212 arcmsr_drain_donequeue(acb, (u_int32_t)cmdSMID, error);
2213 doneq_index++;
2214 if (doneq_index >= acb->completionQ_entry)
2215 doneq_index = 0;
2216 }
2217 acb->doneq_index = doneq_index;
2218 CHIP_REG_WRITE32(HBE_MessageUnit, 0, reply_post_consumer_index, doneq_index);
2219 }
2220
arcmsr_hbf_postqueue_isr(struct AdapterControlBlock * acb)2221 static void arcmsr_hbf_postqueue_isr(struct AdapterControlBlock *acb)
2222 {
2223 uint16_t error;
2224 uint32_t doneq_index;
2225 uint16_t cmdSMID;
2226
2227 /*
2228 *****************************************************************************
2229 ** areca cdb command done
2230 *****************************************************************************
2231 */
2232 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2233 doneq_index = acb->doneq_index;
2234 while (1) {
2235 cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID;
2236 if (cmdSMID == 0xffff)
2237 break;
2238 error = (acb->pCompletionQ[doneq_index].cmdFlag & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE;
2239 arcmsr_drain_donequeue(acb, (u_int32_t)cmdSMID, error);
2240 acb->pCompletionQ[doneq_index].cmdSMID = 0xffff;
2241 doneq_index++;
2242 if (doneq_index >= acb->completionQ_entry)
2243 doneq_index = 0;
2244 }
2245 acb->doneq_index = doneq_index;
2246 CHIP_REG_WRITE32(HBF_MessageUnit, 0, reply_post_consumer_index, doneq_index);
2247 }
2248
2249 /*
2250 **********************************************************************
2251 **********************************************************************
2252 */
arcmsr_handle_hba_isr(struct AdapterControlBlock * acb)2253 static void arcmsr_handle_hba_isr( struct AdapterControlBlock *acb)
2254 {
2255 u_int32_t outbound_intStatus;
2256 /*
2257 *********************************************
2258 ** check outbound intstatus
2259 *********************************************
2260 */
2261 outbound_intStatus = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable;
2262 if(!outbound_intStatus) {
2263 /*it must be share irq*/
2264 return;
2265 }
2266 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intStatus); /*clear interrupt*/
2267 /* MU doorbell interrupts*/
2268 if(outbound_intStatus & ARCMSR_MU_OUTBOUND_DOORBELL_INT) {
2269 arcmsr_hba_doorbell_isr(acb);
2270 }
2271 /* MU post queue interrupts*/
2272 if(outbound_intStatus & ARCMSR_MU_OUTBOUND_POSTQUEUE_INT) {
2273 arcmsr_hba_postqueue_isr(acb);
2274 }
2275 if(outbound_intStatus & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) {
2276 arcmsr_hba_message_isr(acb);
2277 }
2278 }
2279 /*
2280 **********************************************************************
2281 **********************************************************************
2282 */
arcmsr_handle_hbb_isr(struct AdapterControlBlock * acb)2283 static void arcmsr_handle_hbb_isr( struct AdapterControlBlock *acb)
2284 {
2285 u_int32_t outbound_doorbell;
2286 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
2287 /*
2288 *********************************************
2289 ** check outbound intstatus
2290 *********************************************
2291 */
2292 outbound_doorbell = READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell) & acb->outbound_int_enable;
2293 if(!outbound_doorbell) {
2294 /*it must be share irq*/
2295 return;
2296 }
2297 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ~outbound_doorbell); /* clear doorbell interrupt */
2298 READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell);
2299 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT);
2300 /* MU ioctl transfer doorbell interrupts*/
2301 if(outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK) {
2302 arcmsr_iop2drv_data_wrote_handle(acb);
2303 }
2304 if(outbound_doorbell & ARCMSR_IOP2DRV_DATA_READ_OK) {
2305 arcmsr_iop2drv_data_read_handle(acb);
2306 }
2307 /* MU post queue interrupts*/
2308 if(outbound_doorbell & ARCMSR_IOP2DRV_CDB_DONE) {
2309 arcmsr_hbb_postqueue_isr(acb);
2310 }
2311 if(outbound_doorbell & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) {
2312 arcmsr_hbb_message_isr(acb);
2313 }
2314 }
2315 /*
2316 **********************************************************************
2317 **********************************************************************
2318 */
arcmsr_handle_hbc_isr(struct AdapterControlBlock * acb)2319 static void arcmsr_handle_hbc_isr( struct AdapterControlBlock *acb)
2320 {
2321 u_int32_t host_interrupt_status;
2322 /*
2323 *********************************************
2324 ** check outbound intstatus
2325 *********************************************
2326 */
2327 host_interrupt_status = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) &
2328 (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR |
2329 ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR);
2330 if(!host_interrupt_status) {
2331 /*it must be share irq*/
2332 return;
2333 }
2334 do {
2335 /* MU doorbell interrupts*/
2336 if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR) {
2337 arcmsr_hbc_doorbell_isr(acb);
2338 }
2339 /* MU post queue interrupts*/
2340 if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) {
2341 arcmsr_hbc_postqueue_isr(acb);
2342 }
2343 host_interrupt_status = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status);
2344 } while (host_interrupt_status & (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR));
2345 }
2346 /*
2347 **********************************************************************
2348 **********************************************************************
2349 */
arcmsr_handle_hbd_isr(struct AdapterControlBlock * acb)2350 static void arcmsr_handle_hbd_isr( struct AdapterControlBlock *acb)
2351 {
2352 u_int32_t host_interrupt_status;
2353 u_int32_t intmask_org;
2354 /*
2355 *********************************************
2356 ** check outbound intstatus
2357 *********************************************
2358 */
2359 host_interrupt_status = CHIP_REG_READ32(HBD_MessageUnit, 0, host_int_status) & acb->outbound_int_enable;
2360 if(!(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_INT)) {
2361 /*it must be share irq*/
2362 return;
2363 }
2364 /* disable outbound interrupt */
2365 intmask_org = CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable) ; /* disable outbound message0 int */
2366 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, ARCMSR_HBDMU_ALL_INT_DISABLE);
2367 /* MU doorbell interrupts*/
2368 if(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_DOORBELL_INT) {
2369 arcmsr_hbd_doorbell_isr(acb);
2370 }
2371 /* MU post queue interrupts*/
2372 if(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_POSTQUEUE_INT) {
2373 arcmsr_hbd_postqueue_isr(acb);
2374 }
2375 /* enable all outbound interrupt */
2376 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, intmask_org | ARCMSR_HBDMU_ALL_INT_ENABLE);
2377 // CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable);
2378 }
2379 /*
2380 **********************************************************************
2381 **********************************************************************
2382 */
arcmsr_handle_hbe_isr(struct AdapterControlBlock * acb)2383 static void arcmsr_handle_hbe_isr( struct AdapterControlBlock *acb)
2384 {
2385 u_int32_t host_interrupt_status;
2386 /*
2387 *********************************************
2388 ** check outbound intstatus
2389 *********************************************
2390 */
2391 host_interrupt_status = CHIP_REG_READ32(HBE_MessageUnit, 0, host_int_status) &
2392 (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR |
2393 ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR);
2394 if(!host_interrupt_status) {
2395 /*it must be share irq*/
2396 return;
2397 }
2398 do {
2399 /* MU doorbell interrupts*/
2400 if(host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR) {
2401 arcmsr_hbe_doorbell_isr(acb);
2402 }
2403 /* MU post queue interrupts*/
2404 if(host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR) {
2405 arcmsr_hbe_postqueue_isr(acb);
2406 }
2407 host_interrupt_status = CHIP_REG_READ32(HBE_MessageUnit, 0, host_int_status);
2408 } while (host_interrupt_status & (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR | ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR));
2409 }
2410
arcmsr_handle_hbf_isr(struct AdapterControlBlock * acb)2411 static void arcmsr_handle_hbf_isr( struct AdapterControlBlock *acb)
2412 {
2413 u_int32_t host_interrupt_status;
2414 /*
2415 *********************************************
2416 ** check outbound intstatus
2417 *********************************************
2418 */
2419 host_interrupt_status = CHIP_REG_READ32(HBF_MessageUnit, 0, host_int_status) &
2420 (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR |
2421 ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR);
2422 if(!host_interrupt_status) {
2423 /*it must be share irq*/
2424 return;
2425 }
2426 do {
2427 /* MU doorbell interrupts*/
2428 if(host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR) {
2429 arcmsr_hbf_doorbell_isr(acb);
2430 }
2431 /* MU post queue interrupts*/
2432 if(host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR) {
2433 arcmsr_hbf_postqueue_isr(acb);
2434 }
2435 host_interrupt_status = CHIP_REG_READ32(HBF_MessageUnit, 0, host_int_status);
2436 } while (host_interrupt_status & (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR | ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR));
2437 }
2438 /*
2439 ******************************************************************************
2440 ******************************************************************************
2441 */
arcmsr_interrupt(struct AdapterControlBlock * acb)2442 static void arcmsr_interrupt(struct AdapterControlBlock *acb)
2443 {
2444 switch (acb->adapter_type) {
2445 case ACB_ADAPTER_TYPE_A:
2446 arcmsr_handle_hba_isr(acb);
2447 break;
2448 case ACB_ADAPTER_TYPE_B:
2449 arcmsr_handle_hbb_isr(acb);
2450 break;
2451 case ACB_ADAPTER_TYPE_C:
2452 arcmsr_handle_hbc_isr(acb);
2453 break;
2454 case ACB_ADAPTER_TYPE_D:
2455 arcmsr_handle_hbd_isr(acb);
2456 break;
2457 case ACB_ADAPTER_TYPE_E:
2458 arcmsr_handle_hbe_isr(acb);
2459 break;
2460 case ACB_ADAPTER_TYPE_F:
2461 arcmsr_handle_hbf_isr(acb);
2462 break;
2463 default:
2464 printf("arcmsr%d: interrupt service,"
2465 " unknown adapter type =%d\n", acb->pci_unit, acb->adapter_type);
2466 break;
2467 }
2468 }
2469 /*
2470 **********************************************************************
2471 **********************************************************************
2472 */
arcmsr_intr_handler(void * arg)2473 static void arcmsr_intr_handler(void *arg)
2474 {
2475 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)arg;
2476
2477 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
2478 arcmsr_interrupt(acb);
2479 ARCMSR_LOCK_RELEASE(&acb->isr_lock);
2480 }
2481 /*
2482 ******************************************************************************
2483 ******************************************************************************
2484 */
arcmsr_polling_devmap(void * arg)2485 static void arcmsr_polling_devmap(void *arg)
2486 {
2487 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)arg;
2488 switch (acb->adapter_type) {
2489 case ACB_ADAPTER_TYPE_A:
2490 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
2491 break;
2492
2493 case ACB_ADAPTER_TYPE_B: {
2494 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
2495 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG);
2496 }
2497 break;
2498
2499 case ACB_ADAPTER_TYPE_C:
2500 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
2501 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
2502 break;
2503
2504 case ACB_ADAPTER_TYPE_D:
2505 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
2506 break;
2507
2508 case ACB_ADAPTER_TYPE_E:
2509 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
2510 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
2511 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
2512 break;
2513
2514 case ACB_ADAPTER_TYPE_F: {
2515 u_int32_t outMsg1 = CHIP_REG_READ32(HBF_MessageUnit, 0, outbound_msgaddr1);
2516 if (!(outMsg1 & ARCMSR_HBFMU_MESSAGE_FIRMWARE_OK) ||
2517 (outMsg1 & ARCMSR_HBFMU_MESSAGE_NO_VOLUME_CHANGE))
2518 goto nxt6s;
2519 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
2520 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
2521 CHIP_REG_WRITE32(HBF_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
2522 break;
2523 }
2524 }
2525 nxt6s:
2526 if((acb->acb_flags & ACB_F_SCSISTOPADAPTER) == 0)
2527 {
2528 callout_reset(&acb->devmap_callout, 5 * hz, arcmsr_polling_devmap, acb); /* polling per 5 seconds */
2529 }
2530 }
2531
2532 /*
2533 *******************************************************************************
2534 **
2535 *******************************************************************************
2536 */
arcmsr_iop_parking(struct AdapterControlBlock * acb)2537 static void arcmsr_iop_parking(struct AdapterControlBlock *acb)
2538 {
2539 u_int32_t intmask_org;
2540
2541 if(acb != NULL) {
2542 /* stop adapter background rebuild */
2543 if(acb->acb_flags & ACB_F_MSG_START_BGRB) {
2544 intmask_org = arcmsr_disable_allintr(acb);
2545 arcmsr_stop_adapter_bgrb(acb);
2546 arcmsr_flush_adapter_cache(acb);
2547 arcmsr_enable_allintr(acb, intmask_org);
2548 }
2549 }
2550 }
2551 /*
2552 ***********************************************************************
2553 **
2554 ************************************************************************
2555 */
arcmsr_iop_ioctlcmd(struct AdapterControlBlock * acb,u_int32_t ioctl_cmd,caddr_t arg)2556 static u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_cmd, caddr_t arg)
2557 {
2558 struct CMD_MESSAGE_FIELD *pcmdmessagefld;
2559 u_int32_t retvalue = EINVAL;
2560
2561 pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) arg;
2562 if(memcmp(pcmdmessagefld->cmdmessage.Signature, "ARCMSR", 6)!=0) {
2563 return retvalue;
2564 }
2565 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2566 switch(ioctl_cmd) {
2567 case ARCMSR_MESSAGE_READ_RQBUFFER: {
2568 u_int8_t *pQbuffer;
2569 u_int8_t *ptmpQbuffer = pcmdmessagefld->messagedatabuffer;
2570 u_int32_t allxfer_len=0;
2571
2572 while((acb->rqbuf_firstindex != acb->rqbuf_lastindex)
2573 && (allxfer_len < 1031)) {
2574 /*copy READ QBUFFER to srb*/
2575 pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex];
2576 *ptmpQbuffer = *pQbuffer;
2577 acb->rqbuf_firstindex++;
2578 acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
2579 /*if last index number set it to 0 */
2580 ptmpQbuffer++;
2581 allxfer_len++;
2582 }
2583 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2584 struct QBUFFER *prbuffer;
2585
2586 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2587 prbuffer = arcmsr_get_iop_rqbuffer(acb);
2588 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0)
2589 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
2590 }
2591 pcmdmessagefld->cmdmessage.Length = allxfer_len;
2592 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2593 retvalue = ARCMSR_MESSAGE_SUCCESS;
2594 }
2595 break;
2596 case ARCMSR_MESSAGE_WRITE_WQBUFFER: {
2597 u_int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex;
2598 u_int8_t *pQbuffer;
2599 u_int8_t *ptmpuserbuffer = pcmdmessagefld->messagedatabuffer;
2600
2601 user_len = pcmdmessagefld->cmdmessage.Length;
2602 /*check if data xfer length of this request will overflow my array qbuffer */
2603 wqbuf_lastindex = acb->wqbuf_lastindex;
2604 wqbuf_firstindex = acb->wqbuf_firstindex;
2605 if(wqbuf_lastindex != wqbuf_firstindex) {
2606 arcmsr_Write_data_2iop_wqbuffer(acb);
2607 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR;
2608 } else {
2609 my_empty_len = (wqbuf_firstindex - wqbuf_lastindex - 1) &
2610 (ARCMSR_MAX_QBUFFER - 1);
2611 if(my_empty_len >= user_len) {
2612 while(user_len > 0) {
2613 /*copy srb data to wqbuffer*/
2614 pQbuffer = &acb->wqbuffer[acb->wqbuf_lastindex];
2615 *pQbuffer = *ptmpuserbuffer;
2616 acb->wqbuf_lastindex++;
2617 acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
2618 /*if last index number set it to 0 */
2619 ptmpuserbuffer++;
2620 user_len--;
2621 }
2622 /*post fist Qbuffer*/
2623 if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) {
2624 acb->acb_flags &= ~ACB_F_MESSAGE_WQBUFFER_CLEARED;
2625 arcmsr_Write_data_2iop_wqbuffer(acb);
2626 }
2627 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2628 } else {
2629 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR;
2630 }
2631 }
2632 retvalue = ARCMSR_MESSAGE_SUCCESS;
2633 }
2634 break;
2635 case ARCMSR_MESSAGE_CLEAR_RQBUFFER: {
2636 u_int8_t *pQbuffer = acb->rqbuffer;
2637
2638 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2639 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2640 arcmsr_iop_message_read(acb);
2641 /*signature, let IOP know data has been readed */
2642 }
2643 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED;
2644 acb->rqbuf_firstindex = 0;
2645 acb->rqbuf_lastindex = 0;
2646 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
2647 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2648 retvalue = ARCMSR_MESSAGE_SUCCESS;
2649 }
2650 break;
2651 case ARCMSR_MESSAGE_CLEAR_WQBUFFER:
2652 {
2653 u_int8_t *pQbuffer = acb->wqbuffer;
2654
2655 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2656 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2657 arcmsr_iop_message_read(acb);
2658 /*signature, let IOP know data has been readed */
2659 }
2660 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED|ACB_F_MESSAGE_WQBUFFER_READ);
2661 acb->wqbuf_firstindex = 0;
2662 acb->wqbuf_lastindex = 0;
2663 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
2664 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2665 retvalue = ARCMSR_MESSAGE_SUCCESS;
2666 }
2667 break;
2668 case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: {
2669 u_int8_t *pQbuffer;
2670
2671 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2672 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2673 arcmsr_iop_message_read(acb);
2674 /*signature, let IOP know data has been readed */
2675 }
2676 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED
2677 |ACB_F_MESSAGE_RQBUFFER_CLEARED
2678 |ACB_F_MESSAGE_WQBUFFER_READ);
2679 acb->rqbuf_firstindex = 0;
2680 acb->rqbuf_lastindex = 0;
2681 acb->wqbuf_firstindex = 0;
2682 acb->wqbuf_lastindex = 0;
2683 pQbuffer = acb->rqbuffer;
2684 memset(pQbuffer, 0, sizeof(struct QBUFFER));
2685 pQbuffer = acb->wqbuffer;
2686 memset(pQbuffer, 0, sizeof(struct QBUFFER));
2687 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2688 retvalue = ARCMSR_MESSAGE_SUCCESS;
2689 }
2690 break;
2691 case ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F: {
2692 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_3F;
2693 retvalue = ARCMSR_MESSAGE_SUCCESS;
2694 }
2695 break;
2696 case ARCMSR_MESSAGE_SAY_HELLO: {
2697 u_int8_t *hello_string = "Hello! I am ARCMSR";
2698 u_int8_t *puserbuffer = (u_int8_t *)pcmdmessagefld->messagedatabuffer;
2699
2700 if(memcpy(puserbuffer, hello_string, (int16_t)strlen(hello_string))) {
2701 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR;
2702 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2703 return ENOIOCTL;
2704 }
2705 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2706 retvalue = ARCMSR_MESSAGE_SUCCESS;
2707 }
2708 break;
2709 case ARCMSR_MESSAGE_SAY_GOODBYE: {
2710 arcmsr_iop_parking(acb);
2711 retvalue = ARCMSR_MESSAGE_SUCCESS;
2712 }
2713 break;
2714 case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE: {
2715 arcmsr_flush_adapter_cache(acb);
2716 retvalue = ARCMSR_MESSAGE_SUCCESS;
2717 }
2718 break;
2719 }
2720 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2721 return (retvalue);
2722 }
2723 /*
2724 **************************************************************************
2725 **************************************************************************
2726 */
arcmsr_free_srb(struct CommandControlBlock * srb)2727 static void arcmsr_free_srb(struct CommandControlBlock *srb)
2728 {
2729 struct AdapterControlBlock *acb;
2730
2731 acb = srb->acb;
2732 ARCMSR_LOCK_ACQUIRE(&acb->srb_lock);
2733 srb->srb_state = ARCMSR_SRB_DONE;
2734 srb->srb_flags = 0;
2735 acb->srbworkingQ[acb->workingsrb_doneindex] = srb;
2736 acb->workingsrb_doneindex++;
2737 acb->workingsrb_doneindex %= ARCMSR_MAX_FREESRB_NUM;
2738 ARCMSR_LOCK_RELEASE(&acb->srb_lock);
2739 }
2740 /*
2741 **************************************************************************
2742 **************************************************************************
2743 */
arcmsr_get_freesrb(struct AdapterControlBlock * acb)2744 static struct CommandControlBlock *arcmsr_get_freesrb(struct AdapterControlBlock *acb)
2745 {
2746 struct CommandControlBlock *srb = NULL;
2747 u_int32_t workingsrb_startindex, workingsrb_doneindex;
2748
2749 ARCMSR_LOCK_ACQUIRE(&acb->srb_lock);
2750 workingsrb_doneindex = acb->workingsrb_doneindex;
2751 workingsrb_startindex = acb->workingsrb_startindex;
2752 srb = acb->srbworkingQ[workingsrb_startindex];
2753 workingsrb_startindex++;
2754 workingsrb_startindex %= ARCMSR_MAX_FREESRB_NUM;
2755 if(workingsrb_doneindex != workingsrb_startindex) {
2756 acb->workingsrb_startindex = workingsrb_startindex;
2757 } else {
2758 srb = NULL;
2759 }
2760 ARCMSR_LOCK_RELEASE(&acb->srb_lock);
2761 return(srb);
2762 }
2763 /*
2764 **************************************************************************
2765 **************************************************************************
2766 */
arcmsr_iop_message_xfer(struct AdapterControlBlock * acb,union ccb * pccb)2767 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb *pccb)
2768 {
2769 struct CMD_MESSAGE_FIELD *pcmdmessagefld;
2770 int retvalue = 0, transfer_len = 0;
2771 char *buffer;
2772 uint8_t *ptr = scsiio_cdb_ptr(&pccb->csio);
2773 u_int32_t controlcode = (u_int32_t ) ptr[5] << 24 |
2774 (u_int32_t ) ptr[6] << 16 |
2775 (u_int32_t ) ptr[7] << 8 |
2776 (u_int32_t ) ptr[8];
2777 /* 4 bytes: Areca io control code */
2778 if ((pccb->ccb_h.flags & CAM_DATA_MASK) == CAM_DATA_VADDR) {
2779 buffer = pccb->csio.data_ptr;
2780 transfer_len = pccb->csio.dxfer_len;
2781 } else {
2782 retvalue = ARCMSR_MESSAGE_FAIL;
2783 goto message_out;
2784 }
2785 if (transfer_len > sizeof(struct CMD_MESSAGE_FIELD)) {
2786 retvalue = ARCMSR_MESSAGE_FAIL;
2787 goto message_out;
2788 }
2789 pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) buffer;
2790 switch(controlcode) {
2791 case ARCMSR_MESSAGE_READ_RQBUFFER: {
2792 u_int8_t *pQbuffer;
2793 u_int8_t *ptmpQbuffer = pcmdmessagefld->messagedatabuffer;
2794 int32_t allxfer_len = 0;
2795
2796 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2797 while ((acb->rqbuf_firstindex != acb->rqbuf_lastindex)
2798 && (allxfer_len < 1031)) {
2799 pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex];
2800 *ptmpQbuffer = *pQbuffer;
2801 acb->rqbuf_firstindex++;
2802 acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
2803 ptmpQbuffer++;
2804 allxfer_len++;
2805 }
2806 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2807 struct QBUFFER *prbuffer;
2808
2809 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2810 prbuffer = arcmsr_get_iop_rqbuffer(acb);
2811 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0)
2812 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
2813 }
2814 pcmdmessagefld->cmdmessage.Length = allxfer_len;
2815 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2816 retvalue = ARCMSR_MESSAGE_SUCCESS;
2817 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2818 }
2819 break;
2820 case ARCMSR_MESSAGE_WRITE_WQBUFFER: {
2821 int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex;
2822 u_int8_t *pQbuffer;
2823 u_int8_t *ptmpuserbuffer = pcmdmessagefld->messagedatabuffer;
2824
2825 user_len = pcmdmessagefld->cmdmessage.Length;
2826 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2827 wqbuf_lastindex = acb->wqbuf_lastindex;
2828 wqbuf_firstindex = acb->wqbuf_firstindex;
2829 if (wqbuf_lastindex != wqbuf_firstindex) {
2830 arcmsr_Write_data_2iop_wqbuffer(acb);
2831 /* has error report sensedata */
2832 if(pccb->csio.sense_len) {
2833 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70);
2834 /* Valid,ErrorCode */
2835 ((u_int8_t *)&pccb->csio.sense_data)[2] = 0x05;
2836 /* FileMark,EndOfMedia,IncorrectLength,Reserved,SenseKey */
2837 ((u_int8_t *)&pccb->csio.sense_data)[7] = 0x0A;
2838 /* AdditionalSenseLength */
2839 ((u_int8_t *)&pccb->csio.sense_data)[12] = 0x20;
2840 /* AdditionalSenseCode */
2841 }
2842 retvalue = ARCMSR_MESSAGE_FAIL;
2843 } else {
2844 my_empty_len = (wqbuf_firstindex-wqbuf_lastindex - 1)
2845 &(ARCMSR_MAX_QBUFFER - 1);
2846 if (my_empty_len >= user_len) {
2847 while (user_len > 0) {
2848 pQbuffer = &acb->wqbuffer[acb->wqbuf_lastindex];
2849 *pQbuffer = *ptmpuserbuffer;
2850 acb->wqbuf_lastindex++;
2851 acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
2852 ptmpuserbuffer++;
2853 user_len--;
2854 }
2855 if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) {
2856 acb->acb_flags &=
2857 ~ACB_F_MESSAGE_WQBUFFER_CLEARED;
2858 arcmsr_Write_data_2iop_wqbuffer(acb);
2859 }
2860 } else {
2861 /* has error report sensedata */
2862 if(pccb->csio.sense_len) {
2863 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70);
2864 /* Valid,ErrorCode */
2865 ((u_int8_t *)&pccb->csio.sense_data)[2] = 0x05;
2866 /* FileMark,EndOfMedia,IncorrectLength,Reserved,SenseKey */
2867 ((u_int8_t *)&pccb->csio.sense_data)[7] = 0x0A;
2868 /* AdditionalSenseLength */
2869 ((u_int8_t *)&pccb->csio.sense_data)[12] = 0x20;
2870 /* AdditionalSenseCode */
2871 }
2872 retvalue = ARCMSR_MESSAGE_FAIL;
2873 }
2874 }
2875 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2876 }
2877 break;
2878 case ARCMSR_MESSAGE_CLEAR_RQBUFFER: {
2879 u_int8_t *pQbuffer = acb->rqbuffer;
2880
2881 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2882 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2883 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2884 arcmsr_iop_message_read(acb);
2885 }
2886 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED;
2887 acb->rqbuf_firstindex = 0;
2888 acb->rqbuf_lastindex = 0;
2889 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
2890 pcmdmessagefld->cmdmessage.ReturnCode =
2891 ARCMSR_MESSAGE_RETURNCODE_OK;
2892 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2893 }
2894 break;
2895 case ARCMSR_MESSAGE_CLEAR_WQBUFFER: {
2896 u_int8_t *pQbuffer = acb->wqbuffer;
2897
2898 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2899 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2900 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2901 arcmsr_iop_message_read(acb);
2902 }
2903 acb->acb_flags |=
2904 (ACB_F_MESSAGE_WQBUFFER_CLEARED |
2905 ACB_F_MESSAGE_WQBUFFER_READ);
2906 acb->wqbuf_firstindex = 0;
2907 acb->wqbuf_lastindex = 0;
2908 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
2909 pcmdmessagefld->cmdmessage.ReturnCode =
2910 ARCMSR_MESSAGE_RETURNCODE_OK;
2911 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2912 }
2913 break;
2914 case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: {
2915 u_int8_t *pQbuffer;
2916
2917 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2918 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2919 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2920 arcmsr_iop_message_read(acb);
2921 }
2922 acb->acb_flags |=
2923 (ACB_F_MESSAGE_WQBUFFER_CLEARED
2924 | ACB_F_MESSAGE_RQBUFFER_CLEARED
2925 | ACB_F_MESSAGE_WQBUFFER_READ);
2926 acb->rqbuf_firstindex = 0;
2927 acb->rqbuf_lastindex = 0;
2928 acb->wqbuf_firstindex = 0;
2929 acb->wqbuf_lastindex = 0;
2930 pQbuffer = acb->rqbuffer;
2931 memset(pQbuffer, 0, sizeof (struct QBUFFER));
2932 pQbuffer = acb->wqbuffer;
2933 memset(pQbuffer, 0, sizeof (struct QBUFFER));
2934 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2935 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2936 }
2937 break;
2938 case ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F: {
2939 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_3F;
2940 }
2941 break;
2942 case ARCMSR_MESSAGE_SAY_HELLO: {
2943 int8_t *hello_string = "Hello! I am ARCMSR";
2944
2945 memcpy(pcmdmessagefld->messagedatabuffer, hello_string
2946 , (int16_t)strlen(hello_string));
2947 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2948 }
2949 break;
2950 case ARCMSR_MESSAGE_SAY_GOODBYE:
2951 arcmsr_iop_parking(acb);
2952 break;
2953 case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE:
2954 arcmsr_flush_adapter_cache(acb);
2955 break;
2956 default:
2957 retvalue = ARCMSR_MESSAGE_FAIL;
2958 }
2959 message_out:
2960 return (retvalue);
2961 }
2962 /*
2963 *********************************************************************
2964 *********************************************************************
2965 */
arcmsr_execute_srb(void * arg,bus_dma_segment_t * dm_segs,int nseg,int error)2966 static void arcmsr_execute_srb(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error)
2967 {
2968 struct CommandControlBlock *srb = (struct CommandControlBlock *)arg;
2969 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)srb->acb;
2970 union ccb *pccb;
2971 int target, lun;
2972
2973 pccb = srb->pccb;
2974 target = pccb->ccb_h.target_id;
2975 lun = pccb->ccb_h.target_lun;
2976 acb->pktRequestCount++;
2977 if(error != 0) {
2978 if(error != EFBIG) {
2979 printf("arcmsr%d: unexpected error %x"
2980 " returned from 'bus_dmamap_load' \n"
2981 , acb->pci_unit, error);
2982 }
2983 if((pccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_INPROG) {
2984 pccb->ccb_h.status |= CAM_REQ_TOO_BIG;
2985 }
2986 arcmsr_srb_complete(srb, 0);
2987 return;
2988 }
2989 if(nseg > ARCMSR_MAX_SG_ENTRIES) {
2990 pccb->ccb_h.status |= CAM_REQ_TOO_BIG;
2991 arcmsr_srb_complete(srb, 0);
2992 return;
2993 }
2994 if(acb->acb_flags & ACB_F_BUS_RESET) {
2995 printf("arcmsr%d: bus reset and return busy \n", acb->pci_unit);
2996 pccb->ccb_h.status |= CAM_SCSI_BUS_RESET;
2997 arcmsr_srb_complete(srb, 0);
2998 return;
2999 }
3000 if(acb->devstate[target][lun] == ARECA_RAID_GONE) {
3001 u_int8_t block_cmd, cmd;
3002
3003 cmd = scsiio_cdb_ptr(&pccb->csio)[0];
3004 block_cmd = cmd & 0x0f;
3005 if(block_cmd == 0x08 || block_cmd == 0x0a) {
3006 printf("arcmsr%d:block 'read/write' command "
3007 "with gone raid volume Cmd=0x%2x, TargetId=%d, Lun=%d \n"
3008 , acb->pci_unit, cmd, target, lun);
3009 pccb->ccb_h.status |= CAM_DEV_NOT_THERE;
3010 arcmsr_srb_complete(srb, 0);
3011 return;
3012 }
3013 }
3014 if((pccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_INPROG) {
3015 if(nseg != 0) {
3016 bus_dmamap_unload(acb->dm_segs_dmat, srb->dm_segs_dmamap);
3017 }
3018 arcmsr_srb_complete(srb, 0);
3019 return;
3020 }
3021 if(acb->srboutstandingcount >= acb->maxOutstanding) {
3022 if((acb->acb_flags & ACB_F_CAM_DEV_QFRZN) == 0)
3023 {
3024 xpt_freeze_simq(acb->psim, 1);
3025 acb->acb_flags |= ACB_F_CAM_DEV_QFRZN;
3026 }
3027 pccb->ccb_h.status &= ~CAM_SIM_QUEUED;
3028 pccb->ccb_h.status |= CAM_REQUEUE_REQ;
3029 arcmsr_srb_complete(srb, 0);
3030 return;
3031 }
3032 pccb->ccb_h.status |= CAM_SIM_QUEUED;
3033 arcmsr_build_srb(srb, dm_segs, nseg);
3034 arcmsr_post_srb(acb, srb);
3035 if (pccb->ccb_h.timeout != CAM_TIME_INFINITY)
3036 {
3037 arcmsr_callout_init(&srb->ccb_callout);
3038 callout_reset_sbt(&srb->ccb_callout, SBT_1MS *
3039 (pccb->ccb_h.timeout + (ARCMSR_TIMEOUT_DELAY * 1000)), 0,
3040 arcmsr_srb_timeout, srb, 0);
3041 srb->srb_flags |= SRB_FLAG_TIMER_START;
3042 }
3043 }
3044 /*
3045 *****************************************************************************************
3046 *****************************************************************************************
3047 */
arcmsr_seek_cmd2abort(union ccb * abortccb)3048 static u_int8_t arcmsr_seek_cmd2abort(union ccb *abortccb)
3049 {
3050 struct CommandControlBlock *srb;
3051 struct AdapterControlBlock *acb = (struct AdapterControlBlock *) abortccb->ccb_h.arcmsr_ccbacb_ptr;
3052 u_int32_t intmask_org;
3053 int i = 0;
3054
3055 acb->num_aborts++;
3056 /*
3057 ***************************************************************************
3058 ** It is the upper layer do abort command this lock just prior to calling us.
3059 ** First determine if we currently own this command.
3060 ** Start by searching the device queue. If not found
3061 ** at all, and the system wanted us to just abort the
3062 ** command return success.
3063 ***************************************************************************
3064 */
3065 if(acb->srboutstandingcount != 0) {
3066 /* disable all outbound interrupt */
3067 intmask_org = arcmsr_disable_allintr(acb);
3068 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) {
3069 srb = acb->psrb_pool[i];
3070 if(srb->srb_state == ARCMSR_SRB_START) {
3071 if(srb->pccb == abortccb) {
3072 srb->srb_state = ARCMSR_SRB_ABORTED;
3073 printf("arcmsr%d:scsi id=%d lun=%jx abort srb '%p'"
3074 "outstanding command \n"
3075 , acb->pci_unit, abortccb->ccb_h.target_id
3076 , (uintmax_t)abortccb->ccb_h.target_lun, srb);
3077 arcmsr_polling_srbdone(acb, srb);
3078 /* enable outbound Post Queue, outbound doorbell Interrupt */
3079 arcmsr_enable_allintr(acb, intmask_org);
3080 return (TRUE);
3081 }
3082 }
3083 }
3084 /* enable outbound Post Queue, outbound doorbell Interrupt */
3085 arcmsr_enable_allintr(acb, intmask_org);
3086 }
3087 return(FALSE);
3088 }
3089 /*
3090 ****************************************************************************
3091 ****************************************************************************
3092 */
arcmsr_bus_reset(struct AdapterControlBlock * acb)3093 static void arcmsr_bus_reset(struct AdapterControlBlock *acb)
3094 {
3095 int retry = 0;
3096
3097 acb->num_resets++;
3098 acb->acb_flags |= ACB_F_BUS_RESET;
3099 while(acb->srboutstandingcount != 0 && retry < 400) {
3100 arcmsr_interrupt(acb);
3101 UDELAY(25000);
3102 retry++;
3103 }
3104 arcmsr_iop_reset(acb);
3105 acb->acb_flags &= ~ACB_F_BUS_RESET;
3106 }
3107 /*
3108 **************************************************************************
3109 **************************************************************************
3110 */
arcmsr_handle_virtual_command(struct AdapterControlBlock * acb,union ccb * pccb)3111 static void arcmsr_handle_virtual_command(struct AdapterControlBlock *acb,
3112 union ccb *pccb)
3113 {
3114 if (pccb->ccb_h.target_lun) {
3115 pccb->ccb_h.status |= CAM_DEV_NOT_THERE;
3116 xpt_done(pccb);
3117 return;
3118 }
3119 pccb->ccb_h.status |= CAM_REQ_CMP;
3120 switch (scsiio_cdb_ptr(&pccb->csio)[0]) {
3121 case INQUIRY: {
3122 unsigned char inqdata[36];
3123 char *buffer = pccb->csio.data_ptr;
3124
3125 inqdata[0] = T_PROCESSOR; /* Periph Qualifier & Periph Dev Type */
3126 inqdata[1] = 0; /* rem media bit & Dev Type Modifier */
3127 inqdata[2] = 0; /* ISO, ECMA, & ANSI versions */
3128 inqdata[3] = 0;
3129 inqdata[4] = 31; /* length of additional data */
3130 inqdata[5] = 0;
3131 inqdata[6] = 0;
3132 inqdata[7] = 0;
3133 strncpy(&inqdata[8], "Areca ", 8); /* Vendor Identification */
3134 strncpy(&inqdata[16], "RAID controller ", 16); /* Product Identification */
3135 strncpy(&inqdata[32], "R001", 4); /* Product Revision */
3136 memcpy(buffer, inqdata, sizeof(inqdata));
3137 xpt_done(pccb);
3138 }
3139 break;
3140 case WRITE_BUFFER:
3141 case READ_BUFFER: {
3142 if (arcmsr_iop_message_xfer(acb, pccb)) {
3143 pccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR;
3144 pccb->csio.scsi_status = SCSI_STATUS_CHECK_COND;
3145 }
3146 xpt_done(pccb);
3147 }
3148 break;
3149 default:
3150 xpt_done(pccb);
3151 }
3152 }
3153 /*
3154 *********************************************************************
3155 *********************************************************************
3156 */
arcmsr_action(struct cam_sim * psim,union ccb * pccb)3157 static void arcmsr_action(struct cam_sim *psim, union ccb *pccb)
3158 {
3159 struct AdapterControlBlock *acb;
3160
3161 acb = (struct AdapterControlBlock *) cam_sim_softc(psim);
3162 if(acb == NULL) {
3163 pccb->ccb_h.status |= CAM_REQ_INVALID;
3164 xpt_done(pccb);
3165 return;
3166 }
3167 switch (pccb->ccb_h.func_code) {
3168 case XPT_SCSI_IO: {
3169 struct CommandControlBlock *srb;
3170 int target = pccb->ccb_h.target_id;
3171 int error;
3172
3173 if (pccb->ccb_h.flags & CAM_CDB_PHYS) {
3174 pccb->ccb_h.status = CAM_REQ_INVALID;
3175 xpt_done(pccb);
3176 return;
3177 }
3178
3179 if(target == 16) {
3180 /* virtual device for iop message transfer */
3181 arcmsr_handle_virtual_command(acb, pccb);
3182 return;
3183 }
3184 if((srb = arcmsr_get_freesrb(acb)) == NULL) {
3185 pccb->ccb_h.status |= CAM_RESRC_UNAVAIL;
3186 xpt_done(pccb);
3187 return;
3188 }
3189 pccb->ccb_h.arcmsr_ccbsrb_ptr = srb;
3190 pccb->ccb_h.arcmsr_ccbacb_ptr = acb;
3191 srb->pccb = pccb;
3192 error = bus_dmamap_load_ccb(acb->dm_segs_dmat
3193 , srb->dm_segs_dmamap
3194 , pccb
3195 , arcmsr_execute_srb, srb, /*flags*/0);
3196 if(error == EINPROGRESS) {
3197 xpt_freeze_simq(acb->psim, 1);
3198 pccb->ccb_h.status |= CAM_RELEASE_SIMQ;
3199 }
3200 break;
3201 }
3202 case XPT_PATH_INQ: {
3203 struct ccb_pathinq *cpi = &pccb->cpi;
3204
3205 cpi->version_num = 1;
3206 cpi->hba_inquiry = PI_SDTR_ABLE | PI_TAG_ABLE;
3207 cpi->target_sprt = 0;
3208 cpi->hba_misc = 0;
3209 cpi->hba_eng_cnt = 0;
3210 cpi->max_target = ARCMSR_MAX_TARGETID; /* 0-16 */
3211 cpi->max_lun = ARCMSR_MAX_TARGETLUN; /* 0-7 */
3212 cpi->initiator_id = ARCMSR_SCSI_INITIATOR_ID; /* 255 */
3213 cpi->bus_id = cam_sim_bus(psim);
3214 strlcpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
3215 strlcpy(cpi->hba_vid, "ARCMSR", HBA_IDLEN);
3216 strlcpy(cpi->dev_name, cam_sim_name(psim), DEV_IDLEN);
3217 cpi->unit_number = cam_sim_unit(psim);
3218 if(acb->adapter_bus_speed == ACB_BUS_SPEED_12G)
3219 cpi->base_transfer_speed = 1200000;
3220 else if(acb->adapter_bus_speed == ACB_BUS_SPEED_6G)
3221 cpi->base_transfer_speed = 600000;
3222 else
3223 cpi->base_transfer_speed = 300000;
3224 if((acb->vendor_device_id == PCIDevVenIDARC1880) ||
3225 (acb->vendor_device_id == PCIDevVenIDARC1884) ||
3226 (acb->vendor_device_id == PCIDevVenIDARC1680) ||
3227 (acb->vendor_device_id == PCIDevVenIDARC1214))
3228 {
3229 cpi->transport = XPORT_SAS;
3230 cpi->transport_version = 0;
3231 cpi->protocol_version = SCSI_REV_SPC2;
3232 }
3233 else
3234 {
3235 cpi->transport = XPORT_SPI;
3236 cpi->transport_version = 2;
3237 cpi->protocol_version = SCSI_REV_2;
3238 }
3239 cpi->protocol = PROTO_SCSI;
3240 cpi->ccb_h.status |= CAM_REQ_CMP;
3241 xpt_done(pccb);
3242 break;
3243 }
3244 case XPT_ABORT: {
3245 union ccb *pabort_ccb;
3246
3247 pabort_ccb = pccb->cab.abort_ccb;
3248 switch (pabort_ccb->ccb_h.func_code) {
3249 case XPT_ACCEPT_TARGET_IO:
3250 case XPT_CONT_TARGET_IO:
3251 if(arcmsr_seek_cmd2abort(pabort_ccb)==TRUE) {
3252 pabort_ccb->ccb_h.status |= CAM_REQ_ABORTED;
3253 xpt_done(pabort_ccb);
3254 pccb->ccb_h.status |= CAM_REQ_CMP;
3255 } else {
3256 xpt_print_path(pabort_ccb->ccb_h.path);
3257 printf("Not found\n");
3258 pccb->ccb_h.status |= CAM_PATH_INVALID;
3259 }
3260 break;
3261 case XPT_SCSI_IO:
3262 pccb->ccb_h.status |= CAM_UA_ABORT;
3263 break;
3264 default:
3265 pccb->ccb_h.status |= CAM_REQ_INVALID;
3266 break;
3267 }
3268 xpt_done(pccb);
3269 break;
3270 }
3271 case XPT_RESET_BUS:
3272 case XPT_RESET_DEV: {
3273 u_int32_t i;
3274
3275 arcmsr_bus_reset(acb);
3276 for (i=0; i < 500; i++) {
3277 DELAY(1000);
3278 }
3279 pccb->ccb_h.status |= CAM_REQ_CMP;
3280 xpt_done(pccb);
3281 break;
3282 }
3283 case XPT_TERM_IO: {
3284 pccb->ccb_h.status |= CAM_REQ_INVALID;
3285 xpt_done(pccb);
3286 break;
3287 }
3288 case XPT_GET_TRAN_SETTINGS: {
3289 struct ccb_trans_settings *cts;
3290
3291 if(pccb->ccb_h.target_id == 16) {
3292 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL;
3293 xpt_done(pccb);
3294 break;
3295 }
3296 cts = &pccb->cts;
3297 {
3298 struct ccb_trans_settings_scsi *scsi;
3299 struct ccb_trans_settings_spi *spi;
3300 struct ccb_trans_settings_sas *sas;
3301
3302 scsi = &cts->proto_specific.scsi;
3303 scsi->flags = CTS_SCSI_FLAGS_TAG_ENB;
3304 scsi->valid = CTS_SCSI_VALID_TQ;
3305 cts->protocol = PROTO_SCSI;
3306
3307 if((acb->vendor_device_id == PCIDevVenIDARC1880) ||
3308 (acb->vendor_device_id == PCIDevVenIDARC1884) ||
3309 (acb->vendor_device_id == PCIDevVenIDARC1680) ||
3310 (acb->vendor_device_id == PCIDevVenIDARC1214))
3311 {
3312 cts->protocol_version = SCSI_REV_SPC2;
3313 cts->transport_version = 0;
3314 cts->transport = XPORT_SAS;
3315 sas = &cts->xport_specific.sas;
3316 sas->valid = CTS_SAS_VALID_SPEED;
3317 if (acb->adapter_bus_speed == ACB_BUS_SPEED_12G)
3318 sas->bitrate = 1200000;
3319 else if(acb->adapter_bus_speed == ACB_BUS_SPEED_6G)
3320 sas->bitrate = 600000;
3321 else if(acb->adapter_bus_speed == ACB_BUS_SPEED_3G)
3322 sas->bitrate = 300000;
3323 }
3324 else
3325 {
3326 cts->protocol_version = SCSI_REV_2;
3327 cts->transport_version = 2;
3328 cts->transport = XPORT_SPI;
3329 spi = &cts->xport_specific.spi;
3330 spi->flags = CTS_SPI_FLAGS_DISC_ENB;
3331 if (acb->adapter_bus_speed == ACB_BUS_SPEED_6G)
3332 spi->sync_period = 1;
3333 else
3334 spi->sync_period = 2;
3335 spi->sync_offset = 32;
3336 spi->bus_width = MSG_EXT_WDTR_BUS_16_BIT;
3337 spi->valid = CTS_SPI_VALID_DISC
3338 | CTS_SPI_VALID_SYNC_RATE
3339 | CTS_SPI_VALID_SYNC_OFFSET
3340 | CTS_SPI_VALID_BUS_WIDTH;
3341 }
3342 }
3343 pccb->ccb_h.status |= CAM_REQ_CMP;
3344 xpt_done(pccb);
3345 break;
3346 }
3347 case XPT_SET_TRAN_SETTINGS: {
3348 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL;
3349 xpt_done(pccb);
3350 break;
3351 }
3352 case XPT_CALC_GEOMETRY:
3353 if(pccb->ccb_h.target_id == 16) {
3354 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL;
3355 xpt_done(pccb);
3356 break;
3357 }
3358 cam_calc_geometry(&pccb->ccg, 1);
3359 xpt_done(pccb);
3360 break;
3361 default:
3362 pccb->ccb_h.status |= CAM_REQ_INVALID;
3363 xpt_done(pccb);
3364 break;
3365 }
3366 }
3367 /*
3368 **********************************************************************
3369 **********************************************************************
3370 */
arcmsr_start_hba_bgrb(struct AdapterControlBlock * acb)3371 static void arcmsr_start_hba_bgrb(struct AdapterControlBlock *acb)
3372 {
3373 acb->acb_flags |= ACB_F_MSG_START_BGRB;
3374 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB);
3375 if(!arcmsr_hba_wait_msgint_ready(acb)) {
3376 printf("arcmsr%d: wait 'start adapter background rebuild' timeout \n", acb->pci_unit);
3377 }
3378 }
3379 /*
3380 **********************************************************************
3381 **********************************************************************
3382 */
arcmsr_start_hbb_bgrb(struct AdapterControlBlock * acb)3383 static void arcmsr_start_hbb_bgrb(struct AdapterControlBlock *acb)
3384 {
3385 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
3386 acb->acb_flags |= ACB_F_MSG_START_BGRB;
3387 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_START_BGRB);
3388 if(!arcmsr_hbb_wait_msgint_ready(acb)) {
3389 printf( "arcmsr%d: wait 'start adapter background rebuild' timeout \n", acb->pci_unit);
3390 }
3391 }
3392 /*
3393 **********************************************************************
3394 **********************************************************************
3395 */
arcmsr_start_hbc_bgrb(struct AdapterControlBlock * acb)3396 static void arcmsr_start_hbc_bgrb(struct AdapterControlBlock *acb)
3397 {
3398 acb->acb_flags |= ACB_F_MSG_START_BGRB;
3399 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB);
3400 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
3401 if(!arcmsr_hbc_wait_msgint_ready(acb)) {
3402 printf("arcmsr%d: wait 'start adapter background rebuild' timeout \n", acb->pci_unit);
3403 }
3404 }
3405 /*
3406 **********************************************************************
3407 **********************************************************************
3408 */
arcmsr_start_hbd_bgrb(struct AdapterControlBlock * acb)3409 static void arcmsr_start_hbd_bgrb(struct AdapterControlBlock *acb)
3410 {
3411 acb->acb_flags |= ACB_F_MSG_START_BGRB;
3412 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB);
3413 if(!arcmsr_hbd_wait_msgint_ready(acb)) {
3414 printf("arcmsr%d: wait 'start adapter background rebuild' timeout \n", acb->pci_unit);
3415 }
3416 }
3417 /*
3418 **********************************************************************
3419 **********************************************************************
3420 */
arcmsr_start_hbe_bgrb(struct AdapterControlBlock * acb)3421 static void arcmsr_start_hbe_bgrb(struct AdapterControlBlock *acb)
3422 {
3423 acb->acb_flags |= ACB_F_MSG_START_BGRB;
3424 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB);
3425 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
3426 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
3427 if(!arcmsr_hbe_wait_msgint_ready(acb)) {
3428 printf("arcmsr%d: wait 'start adapter background rebuild' timeout \n", acb->pci_unit);
3429 }
3430 }
3431 /*
3432 **********************************************************************
3433 **********************************************************************
3434 */
arcmsr_start_adapter_bgrb(struct AdapterControlBlock * acb)3435 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb)
3436 {
3437 switch (acb->adapter_type) {
3438 case ACB_ADAPTER_TYPE_A:
3439 arcmsr_start_hba_bgrb(acb);
3440 break;
3441 case ACB_ADAPTER_TYPE_B:
3442 arcmsr_start_hbb_bgrb(acb);
3443 break;
3444 case ACB_ADAPTER_TYPE_C:
3445 arcmsr_start_hbc_bgrb(acb);
3446 break;
3447 case ACB_ADAPTER_TYPE_D:
3448 arcmsr_start_hbd_bgrb(acb);
3449 break;
3450 case ACB_ADAPTER_TYPE_E:
3451 case ACB_ADAPTER_TYPE_F:
3452 arcmsr_start_hbe_bgrb(acb);
3453 break;
3454 }
3455 }
3456 /*
3457 **********************************************************************
3458 **
3459 **********************************************************************
3460 */
arcmsr_polling_hba_srbdone(struct AdapterControlBlock * acb,struct CommandControlBlock * poll_srb)3461 static void arcmsr_polling_hba_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3462 {
3463 struct CommandControlBlock *srb;
3464 u_int32_t flag_srb, outbound_intstatus, poll_srb_done=0, poll_count=0;
3465 u_int16_t error;
3466
3467 polling_ccb_retry:
3468 poll_count++;
3469 outbound_intstatus=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable;
3470 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus); /*clear interrupt*/
3471 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
3472 while(1) {
3473 if((flag_srb = CHIP_REG_READ32(HBA_MessageUnit,
3474 0, outbound_queueport)) == 0xFFFFFFFF) {
3475 if(poll_srb_done) {
3476 break;/*chip FIFO no ccb for completion already*/
3477 } else {
3478 UDELAY(25000);
3479 if ((poll_count > 100) && (poll_srb != NULL)) {
3480 break;
3481 }
3482 goto polling_ccb_retry;
3483 }
3484 }
3485 /* check if command done with no error*/
3486 srb = (struct CommandControlBlock *)
3487 (acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/
3488 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
3489 poll_srb_done = (srb == poll_srb) ? 1:0;
3490 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
3491 if(srb->srb_state == ARCMSR_SRB_ABORTED) {
3492 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'"
3493 "poll command abort successfully \n"
3494 , acb->pci_unit
3495 , srb->pccb->ccb_h.target_id
3496 , (uintmax_t)srb->pccb->ccb_h.target_lun, srb);
3497 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
3498 arcmsr_srb_complete(srb, 1);
3499 continue;
3500 }
3501 printf("arcmsr%d: polling get an illegal srb command done srb='%p'"
3502 "srboutstandingcount=%d \n"
3503 , acb->pci_unit
3504 , srb, acb->srboutstandingcount);
3505 continue;
3506 }
3507 arcmsr_report_srb_state(acb, srb, error);
3508 } /*drain reply FIFO*/
3509 }
3510 /*
3511 **********************************************************************
3512 **
3513 **********************************************************************
3514 */
arcmsr_polling_hbb_srbdone(struct AdapterControlBlock * acb,struct CommandControlBlock * poll_srb)3515 static void arcmsr_polling_hbb_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3516 {
3517 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
3518 struct CommandControlBlock *srb;
3519 u_int32_t flag_srb, poll_srb_done=0, poll_count=0;
3520 int index;
3521 u_int16_t error;
3522
3523 polling_ccb_retry:
3524 poll_count++;
3525 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN); /* clear doorbell interrupt */
3526 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
3527 while(1) {
3528 index = phbbmu->doneq_index;
3529 if((flag_srb = phbbmu->done_qbuffer[index]) == 0) {
3530 if(poll_srb_done) {
3531 break;/*chip FIFO no ccb for completion already*/
3532 } else {
3533 UDELAY(25000);
3534 if ((poll_count > 100) && (poll_srb != NULL)) {
3535 break;
3536 }
3537 goto polling_ccb_retry;
3538 }
3539 }
3540 phbbmu->done_qbuffer[index] = 0;
3541 index++;
3542 index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */
3543 phbbmu->doneq_index = index;
3544 /* check if command done with no error*/
3545 srb = (struct CommandControlBlock *)
3546 (acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/
3547 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
3548 poll_srb_done = (srb == poll_srb) ? 1:0;
3549 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
3550 if(srb->srb_state == ARCMSR_SRB_ABORTED) {
3551 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'"
3552 "poll command abort successfully \n"
3553 , acb->pci_unit
3554 , srb->pccb->ccb_h.target_id
3555 , (uintmax_t)srb->pccb->ccb_h.target_lun, srb);
3556 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
3557 arcmsr_srb_complete(srb, 1);
3558 continue;
3559 }
3560 printf("arcmsr%d: polling get an illegal srb command done srb='%p'"
3561 "srboutstandingcount=%d \n"
3562 , acb->pci_unit
3563 , srb, acb->srboutstandingcount);
3564 continue;
3565 }
3566 arcmsr_report_srb_state(acb, srb, error);
3567 } /*drain reply FIFO*/
3568 }
3569 /*
3570 **********************************************************************
3571 **
3572 **********************************************************************
3573 */
arcmsr_polling_hbc_srbdone(struct AdapterControlBlock * acb,struct CommandControlBlock * poll_srb)3574 static void arcmsr_polling_hbc_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3575 {
3576 struct CommandControlBlock *srb;
3577 u_int32_t flag_srb, poll_srb_done=0, poll_count=0;
3578 u_int16_t error;
3579
3580 polling_ccb_retry:
3581 poll_count++;
3582 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
3583 while(1) {
3584 if(!(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR)) {
3585 if(poll_srb_done) {
3586 break;/*chip FIFO no ccb for completion already*/
3587 } else {
3588 UDELAY(25000);
3589 if ((poll_count > 100) && (poll_srb != NULL)) {
3590 break;
3591 }
3592 if (acb->srboutstandingcount == 0) {
3593 break;
3594 }
3595 goto polling_ccb_retry;
3596 }
3597 }
3598 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low);
3599 /* check if command done with no error*/
3600 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0));/*frame must be 32 bytes aligned*/
3601 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE;
3602 if (poll_srb != NULL)
3603 poll_srb_done = (srb == poll_srb) ? 1:0;
3604 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
3605 if(srb->srb_state == ARCMSR_SRB_ABORTED) {
3606 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'poll command abort successfully \n"
3607 , acb->pci_unit, srb->pccb->ccb_h.target_id, (uintmax_t)srb->pccb->ccb_h.target_lun, srb);
3608 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
3609 arcmsr_srb_complete(srb, 1);
3610 continue;
3611 }
3612 printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n"
3613 , acb->pci_unit, srb, acb->srboutstandingcount);
3614 continue;
3615 }
3616 arcmsr_report_srb_state(acb, srb, error);
3617 } /*drain reply FIFO*/
3618 }
3619 /*
3620 **********************************************************************
3621 **
3622 **********************************************************************
3623 */
arcmsr_polling_hbd_srbdone(struct AdapterControlBlock * acb,struct CommandControlBlock * poll_srb)3624 static void arcmsr_polling_hbd_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3625 {
3626 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
3627 struct CommandControlBlock *srb;
3628 u_int32_t flag_srb, poll_srb_done=0, poll_count=0;
3629 u_int32_t outbound_write_pointer;
3630 u_int16_t error, doneq_index;
3631
3632 polling_ccb_retry:
3633 poll_count++;
3634 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
3635 while(1) {
3636 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow;
3637 doneq_index = phbdmu->doneq_index;
3638 if ((outbound_write_pointer & 0xFF) == (doneq_index & 0xFF)) {
3639 if(poll_srb_done) {
3640 break;/*chip FIFO no ccb for completion already*/
3641 } else {
3642 UDELAY(25000);
3643 if ((poll_count > 100) && (poll_srb != NULL)) {
3644 break;
3645 }
3646 if (acb->srboutstandingcount == 0) {
3647 break;
3648 }
3649 goto polling_ccb_retry;
3650 }
3651 }
3652 doneq_index = arcmsr_get_doneq_index(phbdmu);
3653 flag_srb = phbdmu->done_qbuffer[(doneq_index & 0xFF)+1].addressLow;
3654 /* check if command done with no error*/
3655 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0));/*frame must be 32 bytes aligned*/
3656 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE;
3657 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_read_pointer, doneq_index);
3658 if (poll_srb != NULL)
3659 poll_srb_done = (srb == poll_srb) ? 1:0;
3660 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
3661 if(srb->srb_state == ARCMSR_SRB_ABORTED) {
3662 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'poll command abort successfully \n"
3663 , acb->pci_unit, srb->pccb->ccb_h.target_id, (uintmax_t)srb->pccb->ccb_h.target_lun, srb);
3664 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
3665 arcmsr_srb_complete(srb, 1);
3666 continue;
3667 }
3668 printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n"
3669 , acb->pci_unit, srb, acb->srboutstandingcount);
3670 continue;
3671 }
3672 arcmsr_report_srb_state(acb, srb, error);
3673 } /*drain reply FIFO*/
3674 }
3675 /*
3676 **********************************************************************
3677 **
3678 **********************************************************************
3679 */
arcmsr_polling_hbe_srbdone(struct AdapterControlBlock * acb,struct CommandControlBlock * poll_srb)3680 static void arcmsr_polling_hbe_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3681 {
3682 struct CommandControlBlock *srb;
3683 u_int32_t poll_srb_done=0, poll_count=0, doneq_index;
3684 u_int16_t error, cmdSMID;
3685
3686 polling_ccb_retry:
3687 poll_count++;
3688 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
3689 while(1) {
3690 doneq_index = acb->doneq_index;
3691 if((CHIP_REG_READ32(HBE_MessageUnit, 0, reply_post_producer_index) & 0xFFFF) == doneq_index) {
3692 if(poll_srb_done) {
3693 break;/*chip FIFO no ccb for completion already*/
3694 } else {
3695 UDELAY(25000);
3696 if ((poll_count > 100) && (poll_srb != NULL)) {
3697 break;
3698 }
3699 if (acb->srboutstandingcount == 0) {
3700 break;
3701 }
3702 goto polling_ccb_retry;
3703 }
3704 }
3705 cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID;
3706 doneq_index++;
3707 if (doneq_index >= acb->completionQ_entry)
3708 doneq_index = 0;
3709 acb->doneq_index = doneq_index;
3710 srb = acb->psrb_pool[cmdSMID];
3711 error = (acb->pCompletionQ[doneq_index].cmdFlag & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE;
3712 if (poll_srb != NULL)
3713 poll_srb_done = (srb == poll_srb) ? 1:0;
3714 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
3715 if(srb->srb_state == ARCMSR_SRB_ABORTED) {
3716 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'poll command abort successfully \n"
3717 , acb->pci_unit, srb->pccb->ccb_h.target_id, (uintmax_t)srb->pccb->ccb_h.target_lun, srb);
3718 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
3719 arcmsr_srb_complete(srb, 1);
3720 continue;
3721 }
3722 printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n"
3723 , acb->pci_unit, srb, acb->srboutstandingcount);
3724 continue;
3725 }
3726 arcmsr_report_srb_state(acb, srb, error);
3727 } /*drain reply FIFO*/
3728 CHIP_REG_WRITE32(HBE_MessageUnit, 0, reply_post_producer_index, doneq_index);
3729 }
3730 /*
3731 **********************************************************************
3732 **********************************************************************
3733 */
arcmsr_polling_srbdone(struct AdapterControlBlock * acb,struct CommandControlBlock * poll_srb)3734 static void arcmsr_polling_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3735 {
3736 switch (acb->adapter_type) {
3737 case ACB_ADAPTER_TYPE_A:
3738 arcmsr_polling_hba_srbdone(acb, poll_srb);
3739 break;
3740 case ACB_ADAPTER_TYPE_B:
3741 arcmsr_polling_hbb_srbdone(acb, poll_srb);
3742 break;
3743 case ACB_ADAPTER_TYPE_C:
3744 arcmsr_polling_hbc_srbdone(acb, poll_srb);
3745 break;
3746 case ACB_ADAPTER_TYPE_D:
3747 arcmsr_polling_hbd_srbdone(acb, poll_srb);
3748 break;
3749 case ACB_ADAPTER_TYPE_E:
3750 case ACB_ADAPTER_TYPE_F:
3751 arcmsr_polling_hbe_srbdone(acb, poll_srb);
3752 break;
3753 }
3754 }
3755 /*
3756 **********************************************************************
3757 **********************************************************************
3758 */
arcmsr_get_hba_config(struct AdapterControlBlock * acb)3759 static void arcmsr_get_hba_config(struct AdapterControlBlock *acb)
3760 {
3761 char *acb_firm_model = acb->firm_model;
3762 char *acb_firm_version = acb->firm_version;
3763 char *acb_device_map = acb->device_map;
3764 size_t iop_firm_model = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/
3765 size_t iop_firm_version = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/
3766 size_t iop_device_map = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
3767 int i;
3768
3769 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
3770 if(!arcmsr_hba_wait_msgint_ready(acb)) {
3771 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
3772 }
3773 i = 0;
3774 while(i < 8) {
3775 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i);
3776 /* 8 bytes firm_model, 15, 60-67*/
3777 acb_firm_model++;
3778 i++;
3779 }
3780 i=0;
3781 while(i < 16) {
3782 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i);
3783 /* 16 bytes firm_version, 17, 68-83*/
3784 acb_firm_version++;
3785 i++;
3786 }
3787 i=0;
3788 while(i < 16) {
3789 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i);
3790 acb_device_map++;
3791 i++;
3792 }
3793 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version);
3794 acb->firm_request_len = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/
3795 acb->firm_numbers_queue = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/
3796 acb->firm_sdram_size = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/
3797 acb->firm_ide_channels = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/
3798 acb->firm_cfg_version = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */
3799 if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD)
3800 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1;
3801 else
3802 acb->maxOutstanding = acb->firm_numbers_queue - 1;
3803 }
3804 /*
3805 **********************************************************************
3806 **********************************************************************
3807 */
arcmsr_get_hbb_config(struct AdapterControlBlock * acb)3808 static void arcmsr_get_hbb_config(struct AdapterControlBlock *acb)
3809 {
3810 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
3811 char *acb_firm_model = acb->firm_model;
3812 char *acb_firm_version = acb->firm_version;
3813 char *acb_device_map = acb->device_map;
3814 size_t iop_firm_model = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/
3815 size_t iop_firm_version = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/
3816 size_t iop_device_map = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
3817 int i;
3818
3819 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG);
3820 if(!arcmsr_hbb_wait_msgint_ready(acb)) {
3821 printf( "arcmsr%d: wait" "'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
3822 }
3823 i = 0;
3824 while(i < 8) {
3825 *acb_firm_model = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_firm_model+i);
3826 /* 8 bytes firm_model, 15, 60-67*/
3827 acb_firm_model++;
3828 i++;
3829 }
3830 i = 0;
3831 while(i < 16) {
3832 *acb_firm_version = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_firm_version+i);
3833 /* 16 bytes firm_version, 17, 68-83*/
3834 acb_firm_version++;
3835 i++;
3836 }
3837 i = 0;
3838 while(i < 16) {
3839 *acb_device_map = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_device_map+i);
3840 acb_device_map++;
3841 i++;
3842 }
3843 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version);
3844 acb->firm_request_len = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/
3845 acb->firm_numbers_queue = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/
3846 acb->firm_sdram_size = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/
3847 acb->firm_ide_channels = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/
3848 acb->firm_cfg_version = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */
3849 if(acb->firm_numbers_queue > ARCMSR_MAX_HBB_POSTQUEUE)
3850 acb->maxOutstanding = ARCMSR_MAX_HBB_POSTQUEUE - 1;
3851 else
3852 acb->maxOutstanding = acb->firm_numbers_queue - 1;
3853 }
3854 /*
3855 **********************************************************************
3856 **********************************************************************
3857 */
arcmsr_get_hbc_config(struct AdapterControlBlock * acb)3858 static void arcmsr_get_hbc_config(struct AdapterControlBlock *acb)
3859 {
3860 char *acb_firm_model = acb->firm_model;
3861 char *acb_firm_version = acb->firm_version;
3862 char *acb_device_map = acb->device_map;
3863 size_t iop_firm_model = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/
3864 size_t iop_firm_version = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/
3865 size_t iop_device_map = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
3866 int i;
3867
3868 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
3869 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
3870 if(!arcmsr_hbc_wait_msgint_ready(acb)) {
3871 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
3872 }
3873 i = 0;
3874 while(i < 8) {
3875 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i);
3876 /* 8 bytes firm_model, 15, 60-67*/
3877 acb_firm_model++;
3878 i++;
3879 }
3880 i = 0;
3881 while(i < 16) {
3882 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i);
3883 /* 16 bytes firm_version, 17, 68-83*/
3884 acb_firm_version++;
3885 i++;
3886 }
3887 i = 0;
3888 while(i < 16) {
3889 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i);
3890 acb_device_map++;
3891 i++;
3892 }
3893 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version);
3894 acb->firm_request_len = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/
3895 acb->firm_numbers_queue = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/
3896 acb->firm_sdram_size = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/
3897 acb->firm_ide_channels = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/
3898 acb->firm_cfg_version = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */
3899 if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD)
3900 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1;
3901 else
3902 acb->maxOutstanding = acb->firm_numbers_queue - 1;
3903 }
3904 /*
3905 **********************************************************************
3906 **********************************************************************
3907 */
arcmsr_get_hbd_config(struct AdapterControlBlock * acb)3908 static void arcmsr_get_hbd_config(struct AdapterControlBlock *acb)
3909 {
3910 char *acb_firm_model = acb->firm_model;
3911 char *acb_firm_version = acb->firm_version;
3912 char *acb_device_map = acb->device_map;
3913 size_t iop_firm_model = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/
3914 size_t iop_firm_version = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/
3915 size_t iop_device_map = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
3916 int i;
3917
3918 if(CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE)
3919 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR);
3920 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
3921 if(!arcmsr_hbd_wait_msgint_ready(acb)) {
3922 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
3923 }
3924 i = 0;
3925 while(i < 8) {
3926 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i);
3927 /* 8 bytes firm_model, 15, 60-67*/
3928 acb_firm_model++;
3929 i++;
3930 }
3931 i = 0;
3932 while(i < 16) {
3933 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i);
3934 /* 16 bytes firm_version, 17, 68-83*/
3935 acb_firm_version++;
3936 i++;
3937 }
3938 i = 0;
3939 while(i < 16) {
3940 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i);
3941 acb_device_map++;
3942 i++;
3943 }
3944 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version);
3945 acb->firm_request_len = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/
3946 acb->firm_numbers_queue = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/
3947 acb->firm_sdram_size = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/
3948 acb->firm_ide_channels = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/
3949 acb->firm_cfg_version = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */
3950 if(acb->firm_numbers_queue > ARCMSR_MAX_HBD_POSTQUEUE)
3951 acb->maxOutstanding = ARCMSR_MAX_HBD_POSTQUEUE - 1;
3952 else
3953 acb->maxOutstanding = acb->firm_numbers_queue - 1;
3954 }
3955 /*
3956 **********************************************************************
3957 **********************************************************************
3958 */
arcmsr_get_hbe_config(struct AdapterControlBlock * acb)3959 static void arcmsr_get_hbe_config(struct AdapterControlBlock *acb)
3960 {
3961 char *acb_firm_model = acb->firm_model;
3962 char *acb_firm_version = acb->firm_version;
3963 char *acb_device_map = acb->device_map;
3964 size_t iop_firm_model = offsetof(struct HBE_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/
3965 size_t iop_firm_version = offsetof(struct HBE_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/
3966 size_t iop_device_map = offsetof(struct HBE_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
3967 int i;
3968
3969 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
3970 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
3971 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
3972 if(!arcmsr_hbe_wait_msgint_ready(acb)) {
3973 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
3974 }
3975
3976 i = 0;
3977 while(i < 8) {
3978 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i);
3979 /* 8 bytes firm_model, 15, 60-67*/
3980 acb_firm_model++;
3981 i++;
3982 }
3983 i = 0;
3984 while(i < 16) {
3985 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i);
3986 /* 16 bytes firm_version, 17, 68-83*/
3987 acb_firm_version++;
3988 i++;
3989 }
3990 i = 0;
3991 while(i < 16) {
3992 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i);
3993 acb_device_map++;
3994 i++;
3995 }
3996 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version);
3997 acb->firm_request_len = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/
3998 acb->firm_numbers_queue = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/
3999 acb->firm_sdram_size = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/
4000 acb->firm_ide_channels = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/
4001 acb->firm_cfg_version = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */
4002 if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD)
4003 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1;
4004 else
4005 acb->maxOutstanding = acb->firm_numbers_queue - 1;
4006 }
4007 /*
4008 **********************************************************************
4009 **********************************************************************
4010 */
arcmsr_get_hbf_config(struct AdapterControlBlock * acb)4011 static void arcmsr_get_hbf_config(struct AdapterControlBlock *acb)
4012 {
4013 u_int32_t *acb_firm_model = (u_int32_t *)acb->firm_model;
4014 u_int32_t *acb_firm_version = (u_int32_t *)acb->firm_version;
4015 u_int32_t *acb_device_map = (u_int32_t *)acb->device_map;
4016 size_t iop_firm_model = ARCMSR_FW_MODEL_OFFSET; /*firm_model,15,60-67*/
4017 size_t iop_firm_version = ARCMSR_FW_VERS_OFFSET; /*firm_version,17,68-83*/
4018 size_t iop_device_map = ARCMSR_FW_DEVMAP_OFFSET;
4019 int i;
4020
4021 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
4022 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
4023 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
4024 if(!arcmsr_hbe_wait_msgint_ready(acb))
4025 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
4026
4027 i = 0;
4028 while(i < 2) {
4029 *acb_firm_model = acb->msgcode_rwbuffer[iop_firm_model];
4030 /* 8 bytes firm_model, 15, 60-67*/
4031 acb_firm_model++;
4032 iop_firm_model++;
4033 i++;
4034 }
4035 i = 0;
4036 while(i < 4) {
4037 *acb_firm_version = acb->msgcode_rwbuffer[iop_firm_version];
4038 /* 16 bytes firm_version, 17, 68-83*/
4039 acb_firm_version++;
4040 iop_firm_version++;
4041 i++;
4042 }
4043 i = 0;
4044 while(i < 4) {
4045 *acb_device_map = acb->msgcode_rwbuffer[iop_device_map];
4046 acb_device_map++;
4047 iop_device_map++;
4048 i++;
4049 }
4050 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version);
4051 acb->firm_request_len = acb->msgcode_rwbuffer[1]; /*firm_request_len, 1, 04-07*/
4052 acb->firm_numbers_queue = acb->msgcode_rwbuffer[2]; /*firm_numbers_queue, 2, 08-11*/
4053 acb->firm_sdram_size = acb->msgcode_rwbuffer[3]; /*firm_sdram_size, 3, 12-15*/
4054 acb->firm_ide_channels = acb->msgcode_rwbuffer[4]; /*firm_ide_channels, 4, 16-19*/
4055 acb->firm_cfg_version = acb->msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]; /*firm_cfg_version, 25*/
4056 if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD)
4057 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1;
4058 else
4059 acb->maxOutstanding = acb->firm_numbers_queue - 1;
4060 }
4061 /*
4062 **********************************************************************
4063 **********************************************************************
4064 */
arcmsr_get_firmware_spec(struct AdapterControlBlock * acb)4065 static void arcmsr_get_firmware_spec(struct AdapterControlBlock *acb)
4066 {
4067 switch (acb->adapter_type) {
4068 case ACB_ADAPTER_TYPE_A:
4069 arcmsr_get_hba_config(acb);
4070 break;
4071 case ACB_ADAPTER_TYPE_B:
4072 arcmsr_get_hbb_config(acb);
4073 break;
4074 case ACB_ADAPTER_TYPE_C:
4075 arcmsr_get_hbc_config(acb);
4076 break;
4077 case ACB_ADAPTER_TYPE_D:
4078 arcmsr_get_hbd_config(acb);
4079 break;
4080 case ACB_ADAPTER_TYPE_E:
4081 arcmsr_get_hbe_config(acb);
4082 break;
4083 case ACB_ADAPTER_TYPE_F:
4084 arcmsr_get_hbf_config(acb);
4085 break;
4086 }
4087 }
4088 /*
4089 **********************************************************************
4090 **********************************************************************
4091 */
arcmsr_wait_firmware_ready(struct AdapterControlBlock * acb)4092 static void arcmsr_wait_firmware_ready( struct AdapterControlBlock *acb)
4093 {
4094 int timeout=0;
4095
4096 switch (acb->adapter_type) {
4097 case ACB_ADAPTER_TYPE_A: {
4098 while ((CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0)
4099 {
4100 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */
4101 {
4102 printf( "arcmsr%d:timed out waiting for firmware \n", acb->pci_unit);
4103 return;
4104 }
4105 UDELAY(15000); /* wait 15 milli-seconds */
4106 }
4107 }
4108 break;
4109 case ACB_ADAPTER_TYPE_B: {
4110 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
4111 while ((READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell) & ARCMSR_MESSAGE_FIRMWARE_OK) == 0)
4112 {
4113 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */
4114 {
4115 printf( "arcmsr%d: timed out waiting for firmware \n", acb->pci_unit);
4116 return;
4117 }
4118 UDELAY(15000); /* wait 15 milli-seconds */
4119 }
4120 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT);
4121 }
4122 break;
4123 case ACB_ADAPTER_TYPE_C: {
4124 while ((CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK) == 0)
4125 {
4126 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */
4127 {
4128 printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit);
4129 return;
4130 }
4131 UDELAY(15000); /* wait 15 milli-seconds */
4132 }
4133 }
4134 break;
4135 case ACB_ADAPTER_TYPE_D: {
4136 while ((CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBDMU_MESSAGE_FIRMWARE_OK) == 0)
4137 {
4138 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */
4139 {
4140 printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit);
4141 return;
4142 }
4143 UDELAY(15000); /* wait 15 milli-seconds */
4144 }
4145 }
4146 break;
4147 case ACB_ADAPTER_TYPE_E:
4148 case ACB_ADAPTER_TYPE_F: {
4149 while ((CHIP_REG_READ32(HBE_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBEMU_MESSAGE_FIRMWARE_OK) == 0)
4150 {
4151 if (timeout++ > 4000) /* (4000*15)/1000 = 60 sec */
4152 {
4153 printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit);
4154 return;
4155 }
4156 UDELAY(15000); /* wait 15 milli-seconds */
4157 }
4158 }
4159 break;
4160 }
4161 }
4162 /*
4163 **********************************************************************
4164 **********************************************************************
4165 */
arcmsr_clear_doorbell_queue_buffer(struct AdapterControlBlock * acb)4166 static void arcmsr_clear_doorbell_queue_buffer( struct AdapterControlBlock *acb)
4167 {
4168 u_int32_t outbound_doorbell;
4169
4170 switch (acb->adapter_type) {
4171 case ACB_ADAPTER_TYPE_A: {
4172 /* empty doorbell Qbuffer if door bell ringed */
4173 outbound_doorbell = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_doorbell);
4174 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_doorbell, outbound_doorbell); /*clear doorbell interrupt */
4175 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_READ_OK);
4176 }
4177 break;
4178 case ACB_ADAPTER_TYPE_B: {
4179 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
4180 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN);/*clear interrupt and message state*/
4181 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_READ_OK);
4182 /* let IOP know data has been read */
4183 }
4184 break;
4185 case ACB_ADAPTER_TYPE_C: {
4186 /* empty doorbell Qbuffer if door bell ringed */
4187 outbound_doorbell = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell);
4188 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, outbound_doorbell); /*clear doorbell interrupt */
4189 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK);
4190 CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell_clear); /* Dummy read to force pci flush */
4191 CHIP_REG_READ32(HBC_MessageUnit, 0, inbound_doorbell); /* Dummy read to force pci flush */
4192 }
4193 break;
4194 case ACB_ADAPTER_TYPE_D: {
4195 /* empty doorbell Qbuffer if door bell ringed */
4196 outbound_doorbell = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell);
4197 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, outbound_doorbell); /*clear doorbell interrupt */
4198 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ);
4199 }
4200 break;
4201 case ACB_ADAPTER_TYPE_E:
4202 case ACB_ADAPTER_TYPE_F: {
4203 /* empty doorbell Qbuffer if door bell ringed */
4204 acb->in_doorbell = CHIP_REG_READ32(HBE_MessageUnit, 0, iobound_doorbell);
4205 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); /*clear doorbell interrupt */
4206 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK;
4207 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
4208 }
4209 break;
4210 }
4211 }
4212 /*
4213 ************************************************************************
4214 ************************************************************************
4215 */
arcmsr_iop_confirm(struct AdapterControlBlock * acb)4216 static u_int32_t arcmsr_iop_confirm(struct AdapterControlBlock *acb)
4217 {
4218 unsigned long srb_phyaddr;
4219 u_int32_t srb_phyaddr_hi32;
4220 u_int32_t srb_phyaddr_lo32;
4221
4222 /*
4223 ********************************************************************
4224 ** here we need to tell iop 331 our freesrb.HighPart
4225 ** if freesrb.HighPart is not zero
4226 ********************************************************************
4227 */
4228 srb_phyaddr = (unsigned long) acb->srb_phyaddr.phyaddr;
4229 srb_phyaddr_hi32 = acb->srb_phyaddr.B.phyadd_high;
4230 srb_phyaddr_lo32 = acb->srb_phyaddr.B.phyadd_low;
4231 switch (acb->adapter_type) {
4232 case ACB_ADAPTER_TYPE_A: {
4233 if(srb_phyaddr_hi32 != 0) {
4234 CHIP_REG_WRITE32(HBA_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG);
4235 CHIP_REG_WRITE32(HBA_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32);
4236 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG);
4237 if(!arcmsr_hba_wait_msgint_ready(acb)) {
4238 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit);
4239 return FALSE;
4240 }
4241 }
4242 }
4243 break;
4244 /*
4245 ***********************************************************************
4246 ** if adapter type B, set window of "post command Q"
4247 ***********************************************************************
4248 */
4249 case ACB_ADAPTER_TYPE_B: {
4250 u_int32_t post_queue_phyaddr;
4251 struct HBB_MessageUnit *phbbmu;
4252
4253 phbbmu = (struct HBB_MessageUnit *)acb->pmu;
4254 phbbmu->postq_index = 0;
4255 phbbmu->doneq_index = 0;
4256 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_SET_POST_WINDOW);
4257 if(!arcmsr_hbb_wait_msgint_ready(acb)) {
4258 printf( "arcmsr%d: 'set window of post command Q' timeout\n", acb->pci_unit);
4259 return FALSE;
4260 }
4261 post_queue_phyaddr = srb_phyaddr + ARCMSR_SRBS_POOL_SIZE
4262 + offsetof(struct HBB_MessageUnit, post_qbuffer);
4263 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); /* driver "set config" signature */
4264 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[1], srb_phyaddr_hi32); /* normal should be zero */
4265 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[2], post_queue_phyaddr); /* postQ size (256+8)*4 */
4266 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[3], post_queue_phyaddr+1056); /* doneQ size (256+8)*4 */
4267 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[4], 1056); /* srb maxQ size must be --> [(256+8)*4] */
4268 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_SET_CONFIG);
4269 if(!arcmsr_hbb_wait_msgint_ready(acb)) {
4270 printf( "arcmsr%d: 'set command Q window' timeout \n", acb->pci_unit);
4271 return FALSE;
4272 }
4273 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_START_DRIVER_MODE);
4274 if(!arcmsr_hbb_wait_msgint_ready(acb)) {
4275 printf( "arcmsr%d: 'start diver mode' timeout \n", acb->pci_unit);
4276 return FALSE;
4277 }
4278 }
4279 break;
4280 case ACB_ADAPTER_TYPE_C: {
4281 if(srb_phyaddr_hi32 != 0) {
4282 CHIP_REG_WRITE32(HBC_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG);
4283 CHIP_REG_WRITE32(HBC_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32);
4284 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG);
4285 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
4286 if(!arcmsr_hbc_wait_msgint_ready(acb)) {
4287 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit);
4288 return FALSE;
4289 }
4290 }
4291 }
4292 break;
4293 case ACB_ADAPTER_TYPE_D: {
4294 u_int32_t post_queue_phyaddr, done_queue_phyaddr;
4295 struct HBD_MessageUnit0 *phbdmu;
4296
4297 phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
4298 phbdmu->postq_index = 0;
4299 phbdmu->doneq_index = 0x40FF;
4300 post_queue_phyaddr = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE
4301 + offsetof(struct HBD_MessageUnit0, post_qbuffer);
4302 done_queue_phyaddr = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE
4303 + offsetof(struct HBD_MessageUnit0, done_qbuffer);
4304 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); /* driver "set config" signature */
4305 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32);
4306 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[2], post_queue_phyaddr); /* postQ base */
4307 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[3], done_queue_phyaddr); /* doneQ base */
4308 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[4], 0x100);
4309 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG);
4310 if(!arcmsr_hbd_wait_msgint_ready(acb)) {
4311 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit);
4312 return FALSE;
4313 }
4314 }
4315 break;
4316 case ACB_ADAPTER_TYPE_E: {
4317 u_int32_t cdb_phyaddr_lo32;
4318 cdb_phyaddr_lo32 = srb_phyaddr_lo32 + offsetof(struct CommandControlBlock, arcmsr_cdb);
4319 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG);
4320 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[1], ARCMSR_SIGNATURE_1884);
4321 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[2], cdb_phyaddr_lo32);
4322 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[3], srb_phyaddr_hi32);
4323 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[4], SRB_SIZE);
4324 cdb_phyaddr_lo32 = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE;
4325 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[5], cdb_phyaddr_lo32);
4326 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[6], srb_phyaddr_hi32);
4327 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[7], COMPLETION_Q_POOL_SIZE);
4328 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG);
4329 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
4330 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
4331 if(!arcmsr_hbe_wait_msgint_ready(acb)) {
4332 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit);
4333 return FALSE;
4334 }
4335 }
4336 break;
4337 case ACB_ADAPTER_TYPE_F: {
4338 u_int32_t cdb_phyaddr_lo32;
4339 cdb_phyaddr_lo32 = srb_phyaddr_lo32 + offsetof(struct CommandControlBlock, arcmsr_cdb);
4340 acb->msgcode_rwbuffer[0] = ARCMSR_SIGNATURE_SET_CONFIG;
4341 acb->msgcode_rwbuffer[1] = ARCMSR_SIGNATURE_1886;
4342 acb->msgcode_rwbuffer[2] = cdb_phyaddr_lo32;
4343 acb->msgcode_rwbuffer[3] = srb_phyaddr_hi32;
4344 acb->msgcode_rwbuffer[4] = SRB_SIZE;
4345 cdb_phyaddr_lo32 = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE;
4346 acb->msgcode_rwbuffer[5] = cdb_phyaddr_lo32;
4347 acb->msgcode_rwbuffer[6] = srb_phyaddr_hi32;
4348 acb->msgcode_rwbuffer[7] = COMPLETION_Q_POOL_SIZE;
4349 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG);
4350 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
4351 CHIP_REG_WRITE32(HBF_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
4352 if(!arcmsr_hbe_wait_msgint_ready(acb)) {
4353 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit);
4354 return FALSE;
4355 }
4356 }
4357 break;
4358 }
4359 return (TRUE);
4360 }
4361 /*
4362 ************************************************************************
4363 ************************************************************************
4364 */
arcmsr_enable_eoi_mode(struct AdapterControlBlock * acb)4365 static void arcmsr_enable_eoi_mode(struct AdapterControlBlock *acb)
4366 {
4367 if (acb->adapter_type == ACB_ADAPTER_TYPE_B)
4368 {
4369 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
4370 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_ACTIVE_EOI_MODE);
4371 if(!arcmsr_hbb_wait_msgint_ready(acb)) {
4372 printf( "arcmsr%d: 'iop enable eoi mode' timeout \n", acb->pci_unit);
4373 return;
4374 }
4375 }
4376 }
4377 /*
4378 **********************************************************************
4379 **********************************************************************
4380 */
arcmsr_iop_init(struct AdapterControlBlock * acb)4381 static void arcmsr_iop_init(struct AdapterControlBlock *acb)
4382 {
4383 u_int32_t intmask_org;
4384
4385 /* disable all outbound interrupt */
4386 intmask_org = arcmsr_disable_allintr(acb);
4387 arcmsr_wait_firmware_ready(acb);
4388 arcmsr_iop_confirm(acb);
4389 arcmsr_get_firmware_spec(acb);
4390 /*start background rebuild*/
4391 arcmsr_start_adapter_bgrb(acb);
4392 /* empty doorbell Qbuffer if door bell ringed */
4393 arcmsr_clear_doorbell_queue_buffer(acb);
4394 arcmsr_enable_eoi_mode(acb);
4395 /* enable outbound Post Queue, outbound doorbell Interrupt */
4396 arcmsr_enable_allintr(acb, intmask_org);
4397 acb->acb_flags |= ACB_F_IOP_INITED;
4398 }
4399 /*
4400 **********************************************************************
4401 **********************************************************************
4402 */
arcmsr_map_free_srb(void * arg,bus_dma_segment_t * segs,int nseg,int error)4403 static void arcmsr_map_free_srb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
4404 {
4405 struct AdapterControlBlock *acb = arg;
4406 struct CommandControlBlock *srb_tmp;
4407 u_int32_t i;
4408 unsigned long srb_phyaddr = (unsigned long)segs->ds_addr;
4409
4410 acb->srb_phyaddr.phyaddr = srb_phyaddr;
4411 srb_tmp = (struct CommandControlBlock *)acb->uncacheptr;
4412 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) {
4413 if(bus_dmamap_create(acb->dm_segs_dmat,
4414 /*flags*/0, &srb_tmp->dm_segs_dmamap) != 0) {
4415 acb->acb_flags |= ACB_F_MAPFREESRB_FAILD;
4416 printf("arcmsr%d:"
4417 " srb dmamap bus_dmamap_create error\n", acb->pci_unit);
4418 return;
4419 }
4420 if((acb->adapter_type == ACB_ADAPTER_TYPE_C) || (acb->adapter_type == ACB_ADAPTER_TYPE_D)
4421 || (acb->adapter_type == ACB_ADAPTER_TYPE_E) || (acb->adapter_type == ACB_ADAPTER_TYPE_F))
4422 {
4423 srb_tmp->cdb_phyaddr_low = srb_phyaddr;
4424 srb_tmp->cdb_phyaddr_high = (u_int32_t)((srb_phyaddr >> 16) >> 16);
4425 }
4426 else
4427 srb_tmp->cdb_phyaddr_low = srb_phyaddr >> 5;
4428 srb_tmp->acb = acb;
4429 srb_tmp->smid = i << 16;
4430 acb->srbworkingQ[i] = acb->psrb_pool[i] = srb_tmp;
4431 srb_phyaddr = srb_phyaddr + SRB_SIZE;
4432 srb_tmp = (struct CommandControlBlock *)((unsigned long)srb_tmp + SRB_SIZE);
4433 }
4434 if (acb->adapter_type == ACB_ADAPTER_TYPE_E)
4435 acb->pCompletionQ = (pCompletion_Q)srb_tmp;
4436 else if (acb->adapter_type == ACB_ADAPTER_TYPE_F) {
4437 acb->pCompletionQ = (pCompletion_Q)srb_tmp;
4438 acb->completeQ_phys = srb_phyaddr;
4439 memset(acb->pCompletionQ, 0xff, COMPLETION_Q_POOL_SIZE);
4440 acb->message_wbuffer = (u_int32_t *)((unsigned long)acb->pCompletionQ + COMPLETION_Q_POOL_SIZE);
4441 acb->message_rbuffer = (u_int32_t *)((unsigned long)acb->message_wbuffer + 0x100);
4442 acb->msgcode_rwbuffer = (u_int32_t *)((unsigned long)acb->message_wbuffer + 0x200);
4443 memset((void *)acb->message_wbuffer, 0, MESG_RW_BUFFER_SIZE);
4444 }
4445 acb->vir2phy_offset = (unsigned long)srb_tmp - (unsigned long)srb_phyaddr;
4446 }
4447 /*
4448 ************************************************************************
4449 ************************************************************************
4450 */
arcmsr_free_resource(struct AdapterControlBlock * acb)4451 static void arcmsr_free_resource(struct AdapterControlBlock *acb)
4452 {
4453 /* remove the control device */
4454 if(acb->ioctl_dev != NULL) {
4455 destroy_dev(acb->ioctl_dev);
4456 }
4457 bus_dmamap_unload(acb->srb_dmat, acb->srb_dmamap);
4458 bus_dmamap_destroy(acb->srb_dmat, acb->srb_dmamap);
4459 bus_dma_tag_destroy(acb->srb_dmat);
4460 bus_dma_tag_destroy(acb->dm_segs_dmat);
4461 bus_dma_tag_destroy(acb->parent_dmat);
4462 }
4463 /*
4464 ************************************************************************
4465 ************************************************************************
4466 */
arcmsr_mutex_init(struct AdapterControlBlock * acb)4467 static void arcmsr_mutex_init(struct AdapterControlBlock *acb)
4468 {
4469 ARCMSR_LOCK_INIT(&acb->isr_lock, "arcmsr isr lock");
4470 ARCMSR_LOCK_INIT(&acb->srb_lock, "arcmsr srb lock");
4471 ARCMSR_LOCK_INIT(&acb->postDone_lock, "arcmsr postQ lock");
4472 ARCMSR_LOCK_INIT(&acb->qbuffer_lock, "arcmsr RW buffer lock");
4473 }
4474 /*
4475 ************************************************************************
4476 ************************************************************************
4477 */
arcmsr_mutex_destroy(struct AdapterControlBlock * acb)4478 static void arcmsr_mutex_destroy(struct AdapterControlBlock *acb)
4479 {
4480 ARCMSR_LOCK_DESTROY(&acb->qbuffer_lock);
4481 ARCMSR_LOCK_DESTROY(&acb->postDone_lock);
4482 ARCMSR_LOCK_DESTROY(&acb->srb_lock);
4483 ARCMSR_LOCK_DESTROY(&acb->isr_lock);
4484 }
4485 /*
4486 ************************************************************************
4487 ************************************************************************
4488 */
arcmsr_initialize(device_t dev)4489 static u_int32_t arcmsr_initialize(device_t dev)
4490 {
4491 struct AdapterControlBlock *acb = device_get_softc(dev);
4492 u_int16_t pci_command;
4493 int i, j,max_coherent_size;
4494 u_int32_t vendor_dev_id;
4495
4496 vendor_dev_id = pci_get_devid(dev);
4497 acb->vendor_device_id = vendor_dev_id;
4498 acb->sub_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2);
4499 switch (vendor_dev_id) {
4500 case PCIDevVenIDARC1880:
4501 case PCIDevVenIDARC1882:
4502 case PCIDevVenIDARC1213:
4503 case PCIDevVenIDARC1223: {
4504 acb->adapter_type = ACB_ADAPTER_TYPE_C;
4505 if ((acb->sub_device_id == ARECA_SUB_DEV_ID_1883) ||
4506 (acb->sub_device_id == ARECA_SUB_DEV_ID_1216) ||
4507 (acb->sub_device_id == ARECA_SUB_DEV_ID_1226))
4508 acb->adapter_bus_speed = ACB_BUS_SPEED_12G;
4509 else
4510 acb->adapter_bus_speed = ACB_BUS_SPEED_6G;
4511 max_coherent_size = ARCMSR_SRBS_POOL_SIZE;
4512 }
4513 break;
4514 case PCIDevVenIDARC1884:
4515 acb->adapter_type = ACB_ADAPTER_TYPE_E;
4516 acb->adapter_bus_speed = ACB_BUS_SPEED_12G;
4517 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + COMPLETION_Q_POOL_SIZE;
4518 acb->completionQ_entry = COMPLETION_Q_POOL_SIZE / sizeof(struct deliver_completeQ);
4519 break;
4520 case PCIDevVenIDARC1886_:
4521 case PCIDevVenIDARC1886:
4522 acb->adapter_type = ACB_ADAPTER_TYPE_F;
4523 acb->adapter_bus_speed = ACB_BUS_SPEED_12G;
4524 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + COMPLETION_Q_POOL_SIZE + MESG_RW_BUFFER_SIZE;
4525 acb->completionQ_entry = COMPLETION_Q_POOL_SIZE / sizeof(struct deliver_completeQ);
4526 break;
4527 case PCIDevVenIDARC1214: {
4528 acb->adapter_type = ACB_ADAPTER_TYPE_D;
4529 acb->adapter_bus_speed = ACB_BUS_SPEED_6G;
4530 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBD_MessageUnit0));
4531 }
4532 break;
4533 case PCIDevVenIDARC1200:
4534 case PCIDevVenIDARC1201: {
4535 acb->adapter_type = ACB_ADAPTER_TYPE_B;
4536 acb->adapter_bus_speed = ACB_BUS_SPEED_3G;
4537 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBB_MessageUnit));
4538 }
4539 break;
4540 case PCIDevVenIDARC1203: {
4541 acb->adapter_type = ACB_ADAPTER_TYPE_B;
4542 acb->adapter_bus_speed = ACB_BUS_SPEED_6G;
4543 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBB_MessageUnit));
4544 }
4545 break;
4546 case PCIDevVenIDARC1110:
4547 case PCIDevVenIDARC1120:
4548 case PCIDevVenIDARC1130:
4549 case PCIDevVenIDARC1160:
4550 case PCIDevVenIDARC1170:
4551 case PCIDevVenIDARC1210:
4552 case PCIDevVenIDARC1220:
4553 case PCIDevVenIDARC1230:
4554 case PCIDevVenIDARC1231:
4555 case PCIDevVenIDARC1260:
4556 case PCIDevVenIDARC1261:
4557 case PCIDevVenIDARC1270:
4558 case PCIDevVenIDARC1280:
4559 case PCIDevVenIDARC1212:
4560 case PCIDevVenIDARC1222:
4561 case PCIDevVenIDARC1380:
4562 case PCIDevVenIDARC1381:
4563 case PCIDevVenIDARC1680:
4564 case PCIDevVenIDARC1681: {
4565 acb->adapter_type = ACB_ADAPTER_TYPE_A;
4566 acb->adapter_bus_speed = ACB_BUS_SPEED_3G;
4567 max_coherent_size = ARCMSR_SRBS_POOL_SIZE;
4568 }
4569 break;
4570 default: {
4571 printf("arcmsr%d:"
4572 " unknown RAID adapter type \n", device_get_unit(dev));
4573 return ENOMEM;
4574 }
4575 }
4576 if(bus_dma_tag_create( /*PCI parent*/ bus_get_dma_tag(dev),
4577 /*alignemnt*/ 1,
4578 /*boundary*/ 0,
4579 /*lowaddr*/ BUS_SPACE_MAXADDR,
4580 /*highaddr*/ BUS_SPACE_MAXADDR,
4581 /*filter*/ NULL,
4582 /*filterarg*/ NULL,
4583 /*maxsize*/ BUS_SPACE_MAXSIZE_32BIT,
4584 /*nsegments*/ BUS_SPACE_UNRESTRICTED,
4585 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT,
4586 /*flags*/ 0,
4587 /*lockfunc*/ NULL,
4588 /*lockarg*/ NULL,
4589 &acb->parent_dmat) != 0)
4590 {
4591 printf("arcmsr%d: parent_dmat bus_dma_tag_create failure!\n", device_get_unit(dev));
4592 return ENOMEM;
4593 }
4594
4595 /* Create a single tag describing a region large enough to hold all of the s/g lists we will need. */
4596 if(bus_dma_tag_create( /*parent_dmat*/ acb->parent_dmat,
4597 /*alignment*/ 1,
4598 /*boundary*/ 0,
4599 #ifdef PAE
4600 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT,
4601 #else
4602 /*lowaddr*/ BUS_SPACE_MAXADDR,
4603 #endif
4604 /*highaddr*/ BUS_SPACE_MAXADDR,
4605 /*filter*/ NULL,
4606 /*filterarg*/ NULL,
4607 /*maxsize*/ ARCMSR_MAX_SG_ENTRIES * PAGE_SIZE * ARCMSR_MAX_FREESRB_NUM,
4608 /*nsegments*/ ARCMSR_MAX_SG_ENTRIES,
4609 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT,
4610 /*flags*/ 0,
4611 /*lockfunc*/ busdma_lock_mutex,
4612 /*lockarg*/ &acb->isr_lock,
4613 &acb->dm_segs_dmat) != 0)
4614 {
4615 bus_dma_tag_destroy(acb->parent_dmat);
4616 printf("arcmsr%d: dm_segs_dmat bus_dma_tag_create failure!\n", device_get_unit(dev));
4617 return ENOMEM;
4618 }
4619
4620 /* DMA tag for our srb structures.... Allocate the freesrb memory */
4621 if(bus_dma_tag_create( /*parent_dmat*/ acb->parent_dmat,
4622 /*alignment*/ 0x20,
4623 /*boundary*/ 0,
4624 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT,
4625 /*highaddr*/ BUS_SPACE_MAXADDR,
4626 /*filter*/ NULL,
4627 /*filterarg*/ NULL,
4628 /*maxsize*/ max_coherent_size,
4629 /*nsegments*/ 1,
4630 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT,
4631 /*flags*/ 0,
4632 /*lockfunc*/ NULL,
4633 /*lockarg*/ NULL,
4634 &acb->srb_dmat) != 0)
4635 {
4636 bus_dma_tag_destroy(acb->dm_segs_dmat);
4637 bus_dma_tag_destroy(acb->parent_dmat);
4638 printf("arcmsr%d: srb_dmat bus_dma_tag_create failure!\n", device_get_unit(dev));
4639 return ENXIO;
4640 }
4641 /* Allocation for our srbs */
4642 if(bus_dmamem_alloc(acb->srb_dmat, (void **)&acb->uncacheptr, BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, &acb->srb_dmamap) != 0) {
4643 bus_dma_tag_destroy(acb->srb_dmat);
4644 bus_dma_tag_destroy(acb->dm_segs_dmat);
4645 bus_dma_tag_destroy(acb->parent_dmat);
4646 printf("arcmsr%d: srb_dmat bus_dmamem_alloc failure!\n", device_get_unit(dev));
4647 return ENXIO;
4648 }
4649 /* And permanently map them */
4650 if(bus_dmamap_load(acb->srb_dmat, acb->srb_dmamap, acb->uncacheptr, max_coherent_size, arcmsr_map_free_srb, acb, /*flags*/0)) {
4651 bus_dma_tag_destroy(acb->srb_dmat);
4652 bus_dma_tag_destroy(acb->dm_segs_dmat);
4653 bus_dma_tag_destroy(acb->parent_dmat);
4654 printf("arcmsr%d: srb_dmat bus_dmamap_load failure!\n", device_get_unit(dev));
4655 return ENXIO;
4656 }
4657 pci_command = pci_read_config(dev, PCIR_COMMAND, 2);
4658 pci_command |= PCIM_CMD_BUSMASTEREN;
4659 pci_command |= PCIM_CMD_PERRESPEN;
4660 pci_command |= PCIM_CMD_MWRICEN;
4661 /* Enable Busmaster */
4662 pci_write_config(dev, PCIR_COMMAND, pci_command, 2);
4663 switch(acb->adapter_type) {
4664 case ACB_ADAPTER_TYPE_A: {
4665 u_int32_t rid0 = PCIR_BAR(0);
4666 vm_offset_t mem_base0;
4667
4668 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev,SYS_RES_MEMORY, &rid0, RF_ACTIVE);
4669 if(acb->sys_res_arcmsr[0] == NULL) {
4670 arcmsr_free_resource(acb);
4671 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev));
4672 return ENOMEM;
4673 }
4674 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) {
4675 arcmsr_free_resource(acb);
4676 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev));
4677 return ENXIO;
4678 }
4679 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]);
4680 if(mem_base0 == 0) {
4681 arcmsr_free_resource(acb);
4682 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev));
4683 return ENXIO;
4684 }
4685 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]);
4686 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]);
4687 acb->pmu = (struct MessageUnit_UNION *)mem_base0;
4688 acb->rid[0] = rid0;
4689 }
4690 break;
4691 case ACB_ADAPTER_TYPE_B: {
4692 struct HBB_MessageUnit *phbbmu;
4693 struct CommandControlBlock *freesrb;
4694 u_int32_t rid[]={ PCIR_BAR(0), PCIR_BAR(2) };
4695 vm_offset_t mem_base[]={0,0};
4696 for(i=0; i < 2; i++) {
4697 acb->sys_res_arcmsr[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid[i], RF_ACTIVE);
4698 if(acb->sys_res_arcmsr[i] == NULL) {
4699 arcmsr_free_resource(acb);
4700 printf("arcmsr%d: bus_alloc_resource %d failure!\n", device_get_unit(dev), i);
4701 return ENOMEM;
4702 }
4703 if(rman_get_start(acb->sys_res_arcmsr[i]) <= 0) {
4704 arcmsr_free_resource(acb);
4705 printf("arcmsr%d: rman_get_start %d failure!\n", device_get_unit(dev), i);
4706 return ENXIO;
4707 }
4708 mem_base[i] = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[i]);
4709 if(mem_base[i] == 0) {
4710 arcmsr_free_resource(acb);
4711 printf("arcmsr%d: rman_get_virtual %d failure!\n", device_get_unit(dev), i);
4712 return ENXIO;
4713 }
4714 acb->btag[i] = rman_get_bustag(acb->sys_res_arcmsr[i]);
4715 acb->bhandle[i] = rman_get_bushandle(acb->sys_res_arcmsr[i]);
4716 }
4717 freesrb = (struct CommandControlBlock *)acb->uncacheptr;
4718 acb->pmu = (struct MessageUnit_UNION *)((unsigned long)freesrb+ARCMSR_SRBS_POOL_SIZE);
4719 phbbmu = (struct HBB_MessageUnit *)acb->pmu;
4720 phbbmu->hbb_doorbell = (struct HBB_DOORBELL *)mem_base[0];
4721 phbbmu->hbb_rwbuffer = (struct HBB_RWBUFFER *)mem_base[1];
4722 if (vendor_dev_id == PCIDevVenIDARC1203) {
4723 phbbmu->drv2iop_doorbell = offsetof(struct HBB_DOORBELL_1203, drv2iop_doorbell);
4724 phbbmu->drv2iop_doorbell_mask = offsetof(struct HBB_DOORBELL_1203, drv2iop_doorbell_mask);
4725 phbbmu->iop2drv_doorbell = offsetof(struct HBB_DOORBELL_1203, iop2drv_doorbell);
4726 phbbmu->iop2drv_doorbell_mask = offsetof(struct HBB_DOORBELL_1203, iop2drv_doorbell_mask);
4727 } else {
4728 phbbmu->drv2iop_doorbell = offsetof(struct HBB_DOORBELL, drv2iop_doorbell);
4729 phbbmu->drv2iop_doorbell_mask = offsetof(struct HBB_DOORBELL, drv2iop_doorbell_mask);
4730 phbbmu->iop2drv_doorbell = offsetof(struct HBB_DOORBELL, iop2drv_doorbell);
4731 phbbmu->iop2drv_doorbell_mask = offsetof(struct HBB_DOORBELL, iop2drv_doorbell_mask);
4732 }
4733 acb->rid[0] = rid[0];
4734 acb->rid[1] = rid[1];
4735 }
4736 break;
4737 case ACB_ADAPTER_TYPE_C: {
4738 u_int32_t rid0 = PCIR_BAR(1);
4739 vm_offset_t mem_base0;
4740
4741 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid0, RF_ACTIVE);
4742 if(acb->sys_res_arcmsr[0] == NULL) {
4743 arcmsr_free_resource(acb);
4744 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev));
4745 return ENOMEM;
4746 }
4747 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) {
4748 arcmsr_free_resource(acb);
4749 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev));
4750 return ENXIO;
4751 }
4752 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]);
4753 if(mem_base0 == 0) {
4754 arcmsr_free_resource(acb);
4755 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev));
4756 return ENXIO;
4757 }
4758 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]);
4759 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]);
4760 acb->pmu = (struct MessageUnit_UNION *)mem_base0;
4761 acb->rid[0] = rid0;
4762 }
4763 break;
4764 case ACB_ADAPTER_TYPE_D: {
4765 struct HBD_MessageUnit0 *phbdmu;
4766 u_int32_t rid0 = PCIR_BAR(0);
4767 vm_offset_t mem_base0;
4768
4769 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid0, RF_ACTIVE);
4770 if(acb->sys_res_arcmsr[0] == NULL) {
4771 arcmsr_free_resource(acb);
4772 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev));
4773 return ENOMEM;
4774 }
4775 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) {
4776 arcmsr_free_resource(acb);
4777 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev));
4778 return ENXIO;
4779 }
4780 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]);
4781 if(mem_base0 == 0) {
4782 arcmsr_free_resource(acb);
4783 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev));
4784 return ENXIO;
4785 }
4786 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]);
4787 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]);
4788 acb->pmu = (struct MessageUnit_UNION *)((unsigned long)acb->uncacheptr+ARCMSR_SRBS_POOL_SIZE);
4789 phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
4790 phbdmu->phbdmu = (struct HBD_MessageUnit *)mem_base0;
4791 acb->rid[0] = rid0;
4792 }
4793 break;
4794 case ACB_ADAPTER_TYPE_E: {
4795 u_int32_t rid0 = PCIR_BAR(1);
4796 vm_offset_t mem_base0;
4797
4798 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid0, RF_ACTIVE);
4799 if(acb->sys_res_arcmsr[0] == NULL) {
4800 arcmsr_free_resource(acb);
4801 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev));
4802 return ENOMEM;
4803 }
4804 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) {
4805 arcmsr_free_resource(acb);
4806 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev));
4807 return ENXIO;
4808 }
4809 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]);
4810 if(mem_base0 == 0) {
4811 arcmsr_free_resource(acb);
4812 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev));
4813 return ENXIO;
4814 }
4815 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]);
4816 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]);
4817 acb->pmu = (struct MessageUnit_UNION *)mem_base0;
4818 acb->doneq_index = 0;
4819 acb->in_doorbell = 0;
4820 acb->out_doorbell = 0;
4821 acb->rid[0] = rid0;
4822 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); /*clear interrupt*/
4823 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, ARCMSR_HBEMU_DOORBELL_SYNC); /* synchronize doorbell to 0 */
4824 }
4825 break;
4826 case ACB_ADAPTER_TYPE_F: {
4827 u_int32_t rid0 = PCIR_BAR(0);
4828 vm_offset_t mem_base0;
4829 unsigned long host_buffer_dma;
4830
4831 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid0, RF_ACTIVE);
4832 if(acb->sys_res_arcmsr[0] == NULL) {
4833 arcmsr_free_resource(acb);
4834 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev));
4835 return ENOMEM;
4836 }
4837 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) {
4838 arcmsr_free_resource(acb);
4839 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev));
4840 return ENXIO;
4841 }
4842 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]);
4843 if(mem_base0 == 0) {
4844 arcmsr_free_resource(acb);
4845 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev));
4846 return ENXIO;
4847 }
4848 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]);
4849 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]);
4850 acb->pmu = (struct MessageUnit_UNION *)mem_base0;
4851 acb->doneq_index = 0;
4852 acb->in_doorbell = 0;
4853 acb->out_doorbell = 0;
4854 acb->rid[0] = rid0;
4855 CHIP_REG_WRITE32(HBF_MessageUnit, 0, host_int_status, 0); /*clear interrupt*/
4856 CHIP_REG_WRITE32(HBF_MessageUnit, 0, iobound_doorbell, ARCMSR_HBEMU_DOORBELL_SYNC); /* synchronize doorbell to 0 */
4857 arcmsr_wait_firmware_ready(acb);
4858 host_buffer_dma = acb->completeQ_phys + COMPLETION_Q_POOL_SIZE;
4859 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr0, (u_int32_t)(host_buffer_dma | 1)); /* host buffer low addr, bit0:1 all buffer active */
4860 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr1, (u_int32_t)((host_buffer_dma >> 16) >> 16));/* host buffer high addr */
4861 CHIP_REG_WRITE32(HBF_MessageUnit, 0, iobound_doorbell, ARCMSR_HBFMU_DOORBELL_SYNC1); /* set host buffer physical address */
4862 }
4863 break;
4864 }
4865 if(acb->acb_flags & ACB_F_MAPFREESRB_FAILD) {
4866 arcmsr_free_resource(acb);
4867 printf("arcmsr%d: map free srb failure!\n", device_get_unit(dev));
4868 return ENXIO;
4869 }
4870 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED|ACB_F_MESSAGE_RQBUFFER_CLEARED|ACB_F_MESSAGE_WQBUFFER_READ);
4871 acb->acb_flags &= ~ACB_F_SCSISTOPADAPTER;
4872 /*
4873 ********************************************************************
4874 ** init raid volume state
4875 ********************************************************************
4876 */
4877 for(i=0; i < ARCMSR_MAX_TARGETID; i++) {
4878 for(j=0; j < ARCMSR_MAX_TARGETLUN; j++) {
4879 acb->devstate[i][j] = ARECA_RAID_GONE;
4880 }
4881 }
4882 arcmsr_iop_init(acb);
4883 return(0);
4884 }
4885
arcmsr_setup_msix(struct AdapterControlBlock * acb)4886 static int arcmsr_setup_msix(struct AdapterControlBlock *acb)
4887 {
4888 int i;
4889
4890 for (i = 0; i < acb->msix_vectors; i++) {
4891 acb->irq_id[i] = 1 + i;
4892 acb->irqres[i] = bus_alloc_resource_any(acb->pci_dev,
4893 SYS_RES_IRQ, &acb->irq_id[i], RF_ACTIVE);
4894 if (acb->irqres[i] == NULL) {
4895 printf("arcmsr: Can't allocate MSI-X resource\n");
4896 goto irq_alloc_failed;
4897 }
4898 if (bus_setup_intr(acb->pci_dev, acb->irqres[i],
4899 INTR_MPSAFE | INTR_TYPE_CAM, NULL, arcmsr_intr_handler,
4900 acb, &acb->ih[i])) {
4901 printf("arcmsr: Cannot set up MSI-X interrupt handler\n");
4902 goto irq_alloc_failed;
4903 }
4904 }
4905 printf("arcmsr: MSI-X INT enabled\n");
4906 acb->acb_flags |= ACB_F_MSIX_ENABLED;
4907 return TRUE;
4908
4909 irq_alloc_failed:
4910 arcmsr_teardown_intr(acb->pci_dev, acb);
4911 return FALSE;
4912 }
4913
4914 /*
4915 ************************************************************************
4916 ************************************************************************
4917 */
arcmsr_attach(device_t dev)4918 static int arcmsr_attach(device_t dev)
4919 {
4920 struct make_dev_args args;
4921 struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev);
4922 u_int32_t unit=device_get_unit(dev);
4923 struct ccb_setasync csa;
4924 struct cam_devq *devq; /* Device Queue to use for this SIM */
4925 struct resource *irqres;
4926
4927 if(acb == NULL) {
4928 printf("arcmsr%d: cannot allocate softc\n", unit);
4929 return (ENOMEM);
4930 }
4931 arcmsr_mutex_init(acb);
4932 acb->pci_dev = dev;
4933 acb->pci_unit = unit;
4934 if(arcmsr_initialize(dev)) {
4935 printf("arcmsr%d: initialize failure!\n", unit);
4936 goto initialize_failed;
4937 }
4938 /* After setting up the adapter, map our interrupt */
4939 acb->msix_vectors = ARCMSR_NUM_MSIX_VECTORS;
4940 if (pci_alloc_msix(dev, &acb->msix_vectors) == 0) {
4941 if (arcmsr_setup_msix(acb) == TRUE)
4942 goto irqx;
4943 }
4944 acb->irq_id[0] = 0;
4945 irqres = bus_alloc_resource_any(dev, SYS_RES_IRQ, &acb->irq_id[0], RF_SHAREABLE | RF_ACTIVE);
4946 if(irqres == NULL ||
4947 bus_setup_intr(dev, irqres, INTR_TYPE_CAM|INTR_ENTROPY|INTR_MPSAFE, NULL, arcmsr_intr_handler, acb, &acb->ih[0])) {
4948 printf("arcmsr%d: unable to register interrupt handler!\n", unit);
4949 goto setup_intr_failed;
4950 }
4951 acb->irqres[0] = irqres;
4952 irqx:
4953 /*
4954 * Now let the CAM generic SCSI layer find the SCSI devices on
4955 * the bus * start queue to reset to the idle loop. *
4956 * Create device queue of SIM(s) * (MAX_START_JOB - 1) :
4957 * max_sim_transactions
4958 */
4959 devq = cam_simq_alloc(acb->maxOutstanding);
4960 if(devq == NULL) {
4961 printf("arcmsr%d: cam_simq_alloc failure!\n", unit);
4962 goto simq_alloc_failed;
4963 }
4964 acb->psim = cam_sim_alloc(arcmsr_action, arcmsr_poll, "arcmsr", acb, unit, &acb->isr_lock, 1, ARCMSR_MAX_OUTSTANDING_CMD, devq);
4965 if(acb->psim == NULL) {
4966 printf("arcmsr%d: cam_sim_alloc failure!\n", unit);
4967 goto sim_alloc_failed;
4968 }
4969 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
4970 if(xpt_bus_register(acb->psim, dev, 0) != CAM_SUCCESS) {
4971 printf("arcmsr%d: xpt_bus_register failure!\n", unit);
4972 goto xpt_bus_failed;
4973 }
4974 if(xpt_create_path(&acb->ppath, /* periph */ NULL, cam_sim_path(acb->psim), CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
4975 printf("arcmsr%d: xpt_create_path failure!\n", unit);
4976 goto xpt_path_failed;
4977 }
4978 /*
4979 ****************************************************
4980 */
4981 xpt_setup_ccb(&csa.ccb_h, acb->ppath, /*priority*/5);
4982 csa.ccb_h.func_code = XPT_SASYNC_CB;
4983 csa.event_enable = AC_FOUND_DEVICE|AC_LOST_DEVICE;
4984 csa.callback = arcmsr_async;
4985 csa.callback_arg = acb->psim;
4986 xpt_action((union ccb *)&csa);
4987 ARCMSR_LOCK_RELEASE(&acb->isr_lock);
4988 /* Create the control device. */
4989 make_dev_args_init(&args);
4990 args.mda_devsw = &arcmsr_cdevsw;
4991 args.mda_uid = UID_ROOT;
4992 args.mda_gid = GID_WHEEL /* GID_OPERATOR */;
4993 args.mda_mode = S_IRUSR | S_IWUSR;
4994 args.mda_si_drv1 = acb;
4995 (void)make_dev_s(&args, &acb->ioctl_dev, "arcmsr%d", unit);
4996
4997 (void)make_dev_alias(acb->ioctl_dev, "arc%d", unit);
4998 arcmsr_callout_init(&acb->devmap_callout);
4999 callout_reset(&acb->devmap_callout, 60 * hz, arcmsr_polling_devmap, acb);
5000 return (0);
5001 xpt_path_failed:
5002 xpt_bus_deregister(cam_sim_path(acb->psim));
5003 xpt_bus_failed:
5004 cam_sim_free(acb->psim, /* free_simq */ TRUE);
5005 sim_alloc_failed:
5006 cam_simq_free(devq);
5007 simq_alloc_failed:
5008 arcmsr_teardown_intr(dev, acb);
5009 setup_intr_failed:
5010 arcmsr_free_resource(acb);
5011 initialize_failed:
5012 arcmsr_mutex_destroy(acb);
5013 return ENXIO;
5014 }
5015
5016 /*
5017 ************************************************************************
5018 ************************************************************************
5019 */
arcmsr_probe(device_t dev)5020 static int arcmsr_probe(device_t dev)
5021 {
5022 u_int32_t id;
5023 u_int16_t sub_device_id;
5024 static char buf[256];
5025 char x_type[]={"unknown"};
5026 char *type;
5027 int raid6 = 1;
5028
5029 if (pci_get_vendor(dev) != PCI_VENDOR_ID_ARECA) {
5030 return (ENXIO);
5031 }
5032 sub_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2);
5033 switch(id = pci_get_devid(dev)) {
5034 case PCIDevVenIDARC1110:
5035 case PCIDevVenIDARC1200:
5036 case PCIDevVenIDARC1201:
5037 case PCIDevVenIDARC1210:
5038 raid6 = 0;
5039 /*FALLTHRU*/
5040 case PCIDevVenIDARC1120:
5041 case PCIDevVenIDARC1130:
5042 case PCIDevVenIDARC1160:
5043 case PCIDevVenIDARC1170:
5044 case PCIDevVenIDARC1220:
5045 case PCIDevVenIDARC1230:
5046 case PCIDevVenIDARC1231:
5047 case PCIDevVenIDARC1260:
5048 case PCIDevVenIDARC1261:
5049 case PCIDevVenIDARC1270:
5050 case PCIDevVenIDARC1280:
5051 type = "SATA 3G";
5052 break;
5053 case PCIDevVenIDARC1212:
5054 case PCIDevVenIDARC1222:
5055 case PCIDevVenIDARC1380:
5056 case PCIDevVenIDARC1381:
5057 case PCIDevVenIDARC1680:
5058 case PCIDevVenIDARC1681:
5059 type = "SAS 3G";
5060 break;
5061 case PCIDevVenIDARC1880:
5062 case PCIDevVenIDARC1882:
5063 case PCIDevVenIDARC1213:
5064 case PCIDevVenIDARC1223:
5065 if ((sub_device_id == ARECA_SUB_DEV_ID_1883) ||
5066 (sub_device_id == ARECA_SUB_DEV_ID_1216) ||
5067 (sub_device_id == ARECA_SUB_DEV_ID_1226))
5068 type = "SAS 12G";
5069 else
5070 type = "SAS 6G";
5071 break;
5072 case PCIDevVenIDARC1884:
5073 type = "SAS 12G";
5074 break;
5075 case PCIDevVenIDARC1886_:
5076 case PCIDevVenIDARC1886:
5077 type = "NVME,SAS-12G,SATA-6G";
5078 break;
5079 case PCIDevVenIDARC1214:
5080 case PCIDevVenIDARC1203:
5081 type = "SATA 6G";
5082 break;
5083 default:
5084 type = x_type;
5085 raid6 = 0;
5086 break;
5087 }
5088 if(type == x_type)
5089 return(ENXIO);
5090 sprintf(buf, "Areca %s Host Adapter RAID Controller %s\n%s\n",
5091 type, raid6 ? "(RAID6 capable)" : "", ARCMSR_DRIVER_VERSION);
5092 device_set_desc_copy(dev, buf);
5093 return (BUS_PROBE_DEFAULT);
5094 }
5095 /*
5096 ************************************************************************
5097 ************************************************************************
5098 */
arcmsr_shutdown(device_t dev)5099 static int arcmsr_shutdown(device_t dev)
5100 {
5101 u_int32_t i;
5102 u_int32_t intmask_org;
5103 struct CommandControlBlock *srb;
5104 struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev);
5105
5106 /* stop adapter background rebuild */
5107 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
5108 /* disable all outbound interrupt */
5109 intmask_org = arcmsr_disable_allintr(acb);
5110 arcmsr_stop_adapter_bgrb(acb);
5111 arcmsr_flush_adapter_cache(acb);
5112 /* abort all outstanding command */
5113 acb->acb_flags |= ACB_F_SCSISTOPADAPTER;
5114 acb->acb_flags &= ~ACB_F_IOP_INITED;
5115 if(acb->srboutstandingcount != 0) {
5116 /*clear and abort all outbound posted Q*/
5117 arcmsr_done4abort_postqueue(acb);
5118 /* talk to iop 331 outstanding command aborted*/
5119 arcmsr_abort_allcmd(acb);
5120 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) {
5121 srb = acb->psrb_pool[i];
5122 if(srb->srb_state == ARCMSR_SRB_START) {
5123 srb->srb_state = ARCMSR_SRB_ABORTED;
5124 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
5125 arcmsr_srb_complete(srb, 1);
5126 }
5127 }
5128 }
5129 acb->srboutstandingcount = 0;
5130 acb->workingsrb_doneindex = 0;
5131 acb->workingsrb_startindex = 0;
5132 acb->pktRequestCount = 0;
5133 acb->pktReturnCount = 0;
5134 ARCMSR_LOCK_RELEASE(&acb->isr_lock);
5135 return (0);
5136 }
5137 /*
5138 ************************************************************************
5139 ************************************************************************
5140 */
arcmsr_teardown_intr(device_t dev,struct AdapterControlBlock * acb)5141 static void arcmsr_teardown_intr(device_t dev, struct AdapterControlBlock *acb)
5142 {
5143 int i;
5144
5145 if (acb->acb_flags & ACB_F_MSIX_ENABLED) {
5146 for (i = 0; i < acb->msix_vectors; i++) {
5147 if (acb->ih[i])
5148 bus_teardown_intr(dev, acb->irqres[i], acb->ih[i]);
5149 if (acb->irqres[i] != NULL)
5150 bus_release_resource(dev, SYS_RES_IRQ,
5151 acb->irq_id[i], acb->irqres[i]);
5152
5153 acb->ih[i] = NULL;
5154 }
5155 pci_release_msi(dev);
5156 } else {
5157 if (acb->ih[0])
5158 bus_teardown_intr(dev, acb->irqres[0], acb->ih[0]);
5159 if (acb->irqres[0] != NULL)
5160 bus_release_resource(dev, SYS_RES_IRQ,
5161 acb->irq_id[0], acb->irqres[0]);
5162 acb->ih[0] = NULL;
5163 }
5164
5165 }
5166 /*
5167 ************************************************************************
5168 ************************************************************************
5169 */
arcmsr_detach(device_t dev)5170 static int arcmsr_detach(device_t dev)
5171 {
5172 struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev);
5173 int i;
5174
5175 callout_stop(&acb->devmap_callout);
5176 arcmsr_teardown_intr(dev, acb);
5177 arcmsr_shutdown(dev);
5178 arcmsr_free_resource(acb);
5179 for(i=0; (acb->sys_res_arcmsr[i]!=NULL) && (i<2); i++) {
5180 bus_release_resource(dev, SYS_RES_MEMORY, acb->rid[i], acb->sys_res_arcmsr[i]);
5181 }
5182 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
5183 xpt_async(AC_LOST_DEVICE, acb->ppath, NULL);
5184 xpt_free_path(acb->ppath);
5185 xpt_bus_deregister(cam_sim_path(acb->psim));
5186 cam_sim_free(acb->psim, TRUE);
5187 ARCMSR_LOCK_RELEASE(&acb->isr_lock);
5188 arcmsr_mutex_destroy(acb);
5189 return (0);
5190 }
5191
5192 #ifdef ARCMSR_DEBUG1
arcmsr_dump_data(struct AdapterControlBlock * acb)5193 static void arcmsr_dump_data(struct AdapterControlBlock *acb)
5194 {
5195 if((acb->pktRequestCount - acb->pktReturnCount) == 0)
5196 return;
5197 printf("Command Request Count =0x%x\n",acb->pktRequestCount);
5198 printf("Command Return Count =0x%x\n",acb->pktReturnCount);
5199 printf("Command (Req-Rtn) Count =0x%x\n",(acb->pktRequestCount - acb->pktReturnCount));
5200 printf("Queued Command Count =0x%x\n",acb->srboutstandingcount);
5201 }
5202 #endif
5203