1 /*-
2 * Copyright (c) 2013-2017, Mellanox Technologies, Ltd. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 */
25
26 #include "opt_rss.h"
27 #include "opt_ratelimit.h"
28
29 #include <dev/mlx5/driver.h>
30 #include <linux/module.h>
31 #include <dev/mlx5/mlx5_core/mlx5_core.h>
32
mlx5_cmd_query_adapter(struct mlx5_core_dev * dev,u32 * out,int outlen)33 static int mlx5_cmd_query_adapter(struct mlx5_core_dev *dev, u32 *out,
34 int outlen)
35 {
36 u32 in[MLX5_ST_SZ_DW(query_adapter_in)];
37 int err;
38
39 memset(in, 0, sizeof(in));
40
41 MLX5_SET(query_adapter_in, in, opcode, MLX5_CMD_OP_QUERY_ADAPTER);
42
43 err = mlx5_cmd_exec(dev, in, sizeof(in), out, outlen);
44 return err;
45 }
46
mlx5_query_board_id(struct mlx5_core_dev * dev)47 int mlx5_query_board_id(struct mlx5_core_dev *dev)
48 {
49 u32 *out;
50 int outlen = MLX5_ST_SZ_BYTES(query_adapter_out);
51 int err;
52
53 out = kzalloc(outlen, GFP_KERNEL);
54
55 err = mlx5_cmd_query_adapter(dev, out, outlen);
56 if (err)
57 goto out_out;
58
59 memcpy(dev->board_id,
60 MLX5_ADDR_OF(query_adapter_out, out,
61 query_adapter_struct.vsd_contd_psid),
62 MLX5_FLD_SZ_BYTES(query_adapter_out,
63 query_adapter_struct.vsd_contd_psid));
64
65 out_out:
66 kfree(out);
67
68 return err;
69 }
70
mlx5_core_query_vendor_id(struct mlx5_core_dev * mdev,u32 * vendor_id)71 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id)
72 {
73 u32 *out;
74 int outlen = MLX5_ST_SZ_BYTES(query_adapter_out);
75 int err;
76
77 out = kzalloc(outlen, GFP_KERNEL);
78
79 err = mlx5_cmd_query_adapter(mdev, out, outlen);
80 if (err)
81 goto out_out;
82
83 *vendor_id = MLX5_GET(query_adapter_out, out,
84 query_adapter_struct.ieee_vendor_id);
85
86 out_out:
87 kfree(out);
88
89 return err;
90 }
91 EXPORT_SYMBOL(mlx5_core_query_vendor_id);
92
mlx5_core_query_special_contexts(struct mlx5_core_dev * dev)93 static int mlx5_core_query_special_contexts(struct mlx5_core_dev *dev)
94 {
95 u32 in[MLX5_ST_SZ_DW(query_special_contexts_in)];
96 u32 out[MLX5_ST_SZ_DW(query_special_contexts_out)];
97 int err;
98
99 memset(in, 0, sizeof(in));
100 memset(out, 0, sizeof(out));
101
102 MLX5_SET(query_special_contexts_in, in, opcode,
103 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS);
104 err = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
105 if (err)
106 return err;
107
108 dev->special_contexts.resd_lkey = MLX5_GET(query_special_contexts_out,
109 out, resd_lkey);
110
111 return err;
112 }
113
mlx5_get_qcam_reg(struct mlx5_core_dev * dev)114 static int mlx5_get_qcam_reg(struct mlx5_core_dev *dev)
115 {
116 return mlx5_query_qcam_reg(dev, dev->caps.qcam,
117 MLX5_QCAM_FEATURE_ENHANCED_FEATURES,
118 MLX5_QCAM_REGS_FIRST_128);
119 }
120
mlx5_get_pcam_reg(struct mlx5_core_dev * dev)121 static int mlx5_get_pcam_reg(struct mlx5_core_dev *dev)
122 {
123 return mlx5_query_pcam_reg(dev, dev->caps.pcam,
124 MLX5_PCAM_FEATURE_ENHANCED_FEATURES,
125 MLX5_PCAM_REGS_5000_TO_507F);
126 }
127
mlx5_get_mcam_reg(struct mlx5_core_dev * dev)128 static int mlx5_get_mcam_reg(struct mlx5_core_dev *dev)
129 {
130 return mlx5_query_mcam_reg(dev, dev->caps.mcam,
131 MLX5_MCAM_FEATURE_ENHANCED_FEATURES,
132 MLX5_MCAM_REGS_FIRST_128);
133 }
134
mlx5_query_hca_caps(struct mlx5_core_dev * dev)135 int mlx5_query_hca_caps(struct mlx5_core_dev *dev)
136 {
137 int err;
138
139 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
140 if (err)
141 return err;
142
143 if (MLX5_CAP_GEN(dev, eth_net_offloads)) {
144 err = mlx5_core_get_caps(dev, MLX5_CAP_ETHERNET_OFFLOADS);
145 if (err)
146 return err;
147 }
148
149 if (MLX5_CAP_GEN(dev, pg)) {
150 err = mlx5_core_get_caps(dev, MLX5_CAP_ODP);
151 if (err)
152 return err;
153 }
154
155 if (MLX5_CAP_GEN(dev, atomic)) {
156 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
157 if (err)
158 return err;
159 }
160
161 if (MLX5_CAP_GEN(dev, roce)) {
162 err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE);
163 if (err)
164 return err;
165 }
166
167 if ((MLX5_CAP_GEN(dev, port_type) ==
168 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET &&
169 MLX5_CAP_GEN(dev, nic_flow_table)) ||
170 (MLX5_CAP_GEN(dev, port_type) == MLX5_CMD_HCA_CAP_PORT_TYPE_IB &&
171 MLX5_CAP_GEN(dev, ipoib_enhanced_offloads))) {
172 err = mlx5_core_get_caps(dev, MLX5_CAP_FLOW_TABLE);
173 if (err)
174 return err;
175 }
176
177 if (MLX5_CAP_GEN(dev, eswitch_flow_table)) {
178 err = mlx5_core_get_caps(dev, MLX5_CAP_ESWITCH_FLOW_TABLE);
179 if (err)
180 return err;
181 }
182
183 if (MLX5_CAP_GEN(dev, vport_group_manager)) {
184 err = mlx5_core_get_caps(dev, MLX5_CAP_ESWITCH);
185 if (err)
186 return err;
187 }
188
189 if (MLX5_CAP_GEN(dev, snapshot)) {
190 err = mlx5_core_get_caps(dev, MLX5_CAP_SNAPSHOT);
191 if (err)
192 return err;
193 }
194
195 if (MLX5_CAP_GEN(dev, ipoib_enhanced_offloads)) {
196 err = mlx5_core_get_caps(dev, MLX5_CAP_EOIB_OFFLOADS);
197 if (err)
198 return err;
199 }
200
201 if (MLX5_CAP_GEN(dev, debug)) {
202 err = mlx5_core_get_caps(dev, MLX5_CAP_DEBUG);
203 if (err)
204 return err;
205 }
206
207 if (MLX5_CAP_GEN(dev, qos)) {
208 err = mlx5_core_get_caps(dev, MLX5_CAP_QOS);
209 if (err)
210 return err;
211 }
212
213 if (MLX5_CAP_GEN(dev, qcam_reg)) {
214 err = mlx5_get_qcam_reg(dev);
215 if (err)
216 return err;
217 }
218
219 if (MLX5_CAP_GEN(dev, mcam_reg)) {
220 err = mlx5_get_mcam_reg(dev);
221 if (err)
222 return err;
223 }
224
225 if (MLX5_CAP_GEN(dev, pcam_reg)) {
226 err = mlx5_get_pcam_reg(dev);
227 if (err)
228 return err;
229 }
230
231 if (MLX5_CAP_GEN(dev, tls_tx)) {
232 err = mlx5_core_get_caps(dev, MLX5_CAP_TLS);
233 if (err)
234 return err;
235 }
236
237 err = mlx5_core_query_special_contexts(dev);
238 if (err)
239 return err;
240
241 return 0;
242 }
243
mlx5_cmd_init_hca(struct mlx5_core_dev * dev)244 int mlx5_cmd_init_hca(struct mlx5_core_dev *dev)
245 {
246 u32 in[MLX5_ST_SZ_DW(init_hca_in)];
247 u32 out[MLX5_ST_SZ_DW(init_hca_out)];
248
249 memset(in, 0, sizeof(in));
250
251 MLX5_SET(init_hca_in, in, opcode, MLX5_CMD_OP_INIT_HCA);
252
253 memset(out, 0, sizeof(out));
254 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
255 }
256
mlx5_cmd_teardown_hca(struct mlx5_core_dev * dev)257 int mlx5_cmd_teardown_hca(struct mlx5_core_dev *dev)
258 {
259 u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {0};
260 u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {0};
261
262 MLX5_SET(teardown_hca_in, in, opcode, MLX5_CMD_OP_TEARDOWN_HCA);
263 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
264 }
265
mlx5_cmd_force_teardown_hca(struct mlx5_core_dev * dev)266 int mlx5_cmd_force_teardown_hca(struct mlx5_core_dev *dev)
267 {
268 u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {0};
269 u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {0};
270 int force_state;
271 int ret;
272
273 if (!MLX5_CAP_GEN(dev, force_teardown)) {
274 mlx5_core_dbg(dev, "force teardown is not supported in the firmware\n");
275 return -EOPNOTSUPP;
276 }
277
278 MLX5_SET(teardown_hca_in, in, opcode, MLX5_CMD_OP_TEARDOWN_HCA);
279 MLX5_SET(teardown_hca_in, in, profile, MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE);
280
281 ret = mlx5_cmd_exec_polling(dev, in, sizeof(in), out, sizeof(out));
282 if (ret)
283 return ret;
284
285 force_state = MLX5_GET(teardown_hca_out, out, state);
286 if (force_state == MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL) {
287 mlx5_core_err(dev, "teardown with force mode failed\n");
288 return -EIO;
289 }
290
291 return 0;
292 }
293
294 #define MLX5_FAST_TEARDOWN_WAIT_MS 3000
mlx5_cmd_fast_teardown_hca(struct mlx5_core_dev * dev)295 int mlx5_cmd_fast_teardown_hca(struct mlx5_core_dev *dev)
296 {
297 int end, delay_ms = MLX5_FAST_TEARDOWN_WAIT_MS;
298 u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {};
299 u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {};
300 int state;
301 int ret;
302
303 if (!MLX5_CAP_GEN(dev, fast_teardown)) {
304 mlx5_core_dbg(dev, "fast teardown is not supported in the firmware\n");
305 return -EOPNOTSUPP;
306 }
307
308 MLX5_SET(teardown_hca_in, in, opcode, MLX5_CMD_OP_TEARDOWN_HCA);
309 MLX5_SET(teardown_hca_in, in, profile,
310 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN);
311
312 ret = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
313 if (ret)
314 return ret;
315
316 state = MLX5_GET(teardown_hca_out, out, state);
317 if (state == MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL) {
318 mlx5_core_warn(dev, "teardown with fast mode failed\n");
319 return -EIO;
320 }
321
322 mlx5_set_nic_state(dev, MLX5_NIC_IFC_DISABLED);
323
324 /* Loop until device state turns to disable */
325 end = jiffies + msecs_to_jiffies(delay_ms);
326 do {
327 if (mlx5_get_nic_state(dev) == MLX5_NIC_IFC_DISABLED)
328 break;
329
330 pause("W", 1);
331 } while (!time_after(jiffies, end));
332
333 if (mlx5_get_nic_state(dev) != MLX5_NIC_IFC_DISABLED) {
334 mlx5_core_err(dev, "NIC IFC still %d after %ums.\n",
335 mlx5_get_nic_state(dev), delay_ms);
336 return -EIO;
337 }
338 return 0;
339 }
340
mlx5_core_set_dc_cnak_trace(struct mlx5_core_dev * dev,int enable,u64 addr)341 int mlx5_core_set_dc_cnak_trace(struct mlx5_core_dev *dev, int enable,
342 u64 addr)
343 {
344 u32 in[MLX5_ST_SZ_DW(set_dc_cnak_trace_in)] = {0};
345 u32 out[MLX5_ST_SZ_DW(set_dc_cnak_trace_out)] = {0};
346 __be64 be_addr;
347 void *pas;
348
349 MLX5_SET(set_dc_cnak_trace_in, in, opcode, MLX5_CMD_OP_SET_DC_CNAK_TRACE);
350 MLX5_SET(set_dc_cnak_trace_in, in, enable, enable);
351 pas = MLX5_ADDR_OF(set_dc_cnak_trace_in, in, pas);
352 be_addr = cpu_to_be64(addr);
353 memcpy(MLX5_ADDR_OF(cmd_pas, pas, pa_h), &be_addr, sizeof(be_addr));
354
355 return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
356 }
357
358 enum mlxsw_reg_mcc_instruction {
359 MLX5_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01,
360 MLX5_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02,
361 MLX5_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03,
362 MLX5_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04,
363 MLX5_REG_MCC_INSTRUCTION_ACTIVATE = 0x06,
364 MLX5_REG_MCC_INSTRUCTION_CANCEL = 0x08,
365 };
366
mlx5_reg_mcc_set(struct mlx5_core_dev * dev,enum mlxsw_reg_mcc_instruction instr,u16 component_index,u32 update_handle,u32 component_size)367 static int mlx5_reg_mcc_set(struct mlx5_core_dev *dev,
368 enum mlxsw_reg_mcc_instruction instr,
369 u16 component_index, u32 update_handle,
370 u32 component_size)
371 {
372 u32 out[MLX5_ST_SZ_DW(mcc_reg)];
373 u32 in[MLX5_ST_SZ_DW(mcc_reg)];
374
375 memset(in, 0, sizeof(in));
376
377 MLX5_SET(mcc_reg, in, instruction, instr);
378 MLX5_SET(mcc_reg, in, component_index, component_index);
379 MLX5_SET(mcc_reg, in, update_handle, update_handle);
380 MLX5_SET(mcc_reg, in, component_size, component_size);
381
382 return mlx5_core_access_reg(dev, in, sizeof(in), out,
383 sizeof(out), MLX5_REG_MCC, 0, 1);
384 }
385
mlx5_reg_mcc_query(struct mlx5_core_dev * dev,u32 * update_handle,u8 * error_code,u8 * control_state)386 static int mlx5_reg_mcc_query(struct mlx5_core_dev *dev,
387 u32 *update_handle, u8 *error_code,
388 u8 *control_state)
389 {
390 u32 out[MLX5_ST_SZ_DW(mcc_reg)];
391 u32 in[MLX5_ST_SZ_DW(mcc_reg)];
392 int err;
393
394 memset(in, 0, sizeof(in));
395 memset(out, 0, sizeof(out));
396 MLX5_SET(mcc_reg, in, update_handle, *update_handle);
397
398 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
399 sizeof(out), MLX5_REG_MCC, 0, 0);
400 if (err)
401 goto out;
402
403 *update_handle = MLX5_GET(mcc_reg, out, update_handle);
404 *error_code = MLX5_GET(mcc_reg, out, error_code);
405 *control_state = MLX5_GET(mcc_reg, out, control_state);
406
407 out:
408 return err;
409 }
410
mlx5_reg_mcda_set(struct mlx5_core_dev * dev,u32 update_handle,u32 offset,u16 size,u8 * data)411 static int mlx5_reg_mcda_set(struct mlx5_core_dev *dev,
412 u32 update_handle,
413 u32 offset, u16 size,
414 u8 *data)
415 {
416 int err, in_size = MLX5_ST_SZ_BYTES(mcda_reg) + size;
417 u32 out[MLX5_ST_SZ_DW(mcda_reg)];
418 int i, j, dw_size = size >> 2;
419 __be32 data_element;
420 u32 *in;
421
422 in = kzalloc(in_size, GFP_KERNEL);
423 if (!in)
424 return -ENOMEM;
425
426 MLX5_SET(mcda_reg, in, update_handle, update_handle);
427 MLX5_SET(mcda_reg, in, offset, offset);
428 MLX5_SET(mcda_reg, in, size, size);
429
430 for (i = 0; i < dw_size; i++) {
431 j = i * 4;
432 data_element = htonl(*(u32 *)&data[j]);
433 memcpy(MLX5_ADDR_OF(mcda_reg, in, data) + j, &data_element, 4);
434 }
435
436 err = mlx5_core_access_reg(dev, in, in_size, out,
437 sizeof(out), MLX5_REG_MCDA, 0, 1);
438 kfree(in);
439 return err;
440 }
441
mlx5_reg_mcqi_query(struct mlx5_core_dev * dev,u16 component_index,u32 * max_component_size,u8 * log_mcda_word_size,u16 * mcda_max_write_size)442 static int mlx5_reg_mcqi_query(struct mlx5_core_dev *dev,
443 u16 component_index,
444 u32 *max_component_size,
445 u8 *log_mcda_word_size,
446 u16 *mcda_max_write_size)
447 {
448 u32 out[MLX5_ST_SZ_DW(mcqi_reg) + MLX5_ST_SZ_DW(mcqi_cap)];
449 int offset = MLX5_ST_SZ_DW(mcqi_reg);
450 u32 in[MLX5_ST_SZ_DW(mcqi_reg)];
451 int err;
452
453 memset(in, 0, sizeof(in));
454 memset(out, 0, sizeof(out));
455
456 MLX5_SET(mcqi_reg, in, component_index, component_index);
457 MLX5_SET(mcqi_reg, in, data_size, MLX5_ST_SZ_BYTES(mcqi_cap));
458
459 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
460 sizeof(out), MLX5_REG_MCQI, 0, 0);
461 if (err)
462 goto out;
463
464 *max_component_size = MLX5_GET(mcqi_cap, out + offset, max_component_size);
465 *log_mcda_word_size = MLX5_GET(mcqi_cap, out + offset, log_mcda_word_size);
466 *mcda_max_write_size = MLX5_GET(mcqi_cap, out + offset, mcda_max_write_size);
467
468 out:
469 return err;
470 }
471
472 struct mlx5_mlxfw_dev {
473 struct mlxfw_dev mlxfw_dev;
474 struct mlx5_core_dev *mlx5_core_dev;
475 };
476
mlx5_component_query(struct mlxfw_dev * mlxfw_dev,u16 component_index,u32 * p_max_size,u8 * p_align_bits,u16 * p_max_write_size)477 static int mlx5_component_query(struct mlxfw_dev *mlxfw_dev,
478 u16 component_index, u32 *p_max_size,
479 u8 *p_align_bits, u16 *p_max_write_size)
480 {
481 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
482 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
483 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
484
485 return mlx5_reg_mcqi_query(dev, component_index, p_max_size,
486 p_align_bits, p_max_write_size);
487 }
488
mlx5_fsm_lock(struct mlxfw_dev * mlxfw_dev,u32 * fwhandle)489 static int mlx5_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle)
490 {
491 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
492 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
493 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
494 u8 control_state, error_code;
495 int err;
496
497 *fwhandle = 0;
498 err = mlx5_reg_mcc_query(dev, fwhandle, &error_code, &control_state);
499 if (err)
500 return err;
501
502 if (control_state != MLXFW_FSM_STATE_IDLE)
503 return -EBUSY;
504
505 return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE,
506 0, *fwhandle, 0);
507 }
508
mlx5_fsm_component_update(struct mlxfw_dev * mlxfw_dev,u32 fwhandle,u16 component_index,u32 component_size)509 static int mlx5_fsm_component_update(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
510 u16 component_index, u32 component_size)
511 {
512 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
513 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
514 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
515
516 return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_UPDATE_COMPONENT,
517 component_index, fwhandle, component_size);
518 }
519
mlx5_fsm_block_download(struct mlxfw_dev * mlxfw_dev,u32 fwhandle,u8 * data,u16 size,u32 offset)520 static int mlx5_fsm_block_download(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
521 u8 *data, u16 size, u32 offset)
522 {
523 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
524 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
525 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
526
527 return mlx5_reg_mcda_set(dev, fwhandle, offset, size, data);
528 }
529
mlx5_fsm_component_verify(struct mlxfw_dev * mlxfw_dev,u32 fwhandle,u16 component_index)530 static int mlx5_fsm_component_verify(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
531 u16 component_index)
532 {
533 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
534 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
535 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
536
537 return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_VERIFY_COMPONENT,
538 component_index, fwhandle, 0);
539 }
540
mlx5_fsm_activate(struct mlxfw_dev * mlxfw_dev,u32 fwhandle)541 static int mlx5_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
542 {
543 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
544 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
545 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
546
547 return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_ACTIVATE, 0,
548 fwhandle, 0);
549 }
550
mlx5_fsm_query_state(struct mlxfw_dev * mlxfw_dev,u32 fwhandle,enum mlxfw_fsm_state * fsm_state,enum mlxfw_fsm_state_err * fsm_state_err)551 static int mlx5_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
552 enum mlxfw_fsm_state *fsm_state,
553 enum mlxfw_fsm_state_err *fsm_state_err)
554 {
555 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
556 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
557 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
558 u8 control_state, error_code;
559 int err;
560
561 err = mlx5_reg_mcc_query(dev, &fwhandle, &error_code, &control_state);
562 if (err)
563 return err;
564
565 *fsm_state = control_state;
566 *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code,
567 MLXFW_FSM_STATE_ERR_MAX);
568 return 0;
569 }
570
mlx5_fsm_cancel(struct mlxfw_dev * mlxfw_dev,u32 fwhandle)571 static void mlx5_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
572 {
573 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
574 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
575 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
576
577 mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_CANCEL, 0, fwhandle, 0);
578 }
579
mlx5_fsm_release(struct mlxfw_dev * mlxfw_dev,u32 fwhandle)580 static void mlx5_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
581 {
582 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
583 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
584 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
585
586 mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0,
587 fwhandle, 0);
588 }
589
590 static const struct mlxfw_dev_ops mlx5_mlxfw_dev_ops = {
591 .component_query = mlx5_component_query,
592 .fsm_lock = mlx5_fsm_lock,
593 .fsm_component_update = mlx5_fsm_component_update,
594 .fsm_block_download = mlx5_fsm_block_download,
595 .fsm_component_verify = mlx5_fsm_component_verify,
596 .fsm_activate = mlx5_fsm_activate,
597 .fsm_query_state = mlx5_fsm_query_state,
598 .fsm_cancel = mlx5_fsm_cancel,
599 .fsm_release = mlx5_fsm_release
600 };
601
mlx5_firmware_flash(struct mlx5_core_dev * dev,const struct firmware * firmware)602 int mlx5_firmware_flash(struct mlx5_core_dev *dev,
603 const struct firmware *firmware)
604 {
605 struct mlx5_mlxfw_dev mlx5_mlxfw_dev = {
606 .mlxfw_dev = {
607 .ops = &mlx5_mlxfw_dev_ops,
608 .psid = dev->board_id,
609 .psid_size = strlen(dev->board_id),
610 },
611 .mlx5_core_dev = dev
612 };
613
614 if (!MLX5_CAP_GEN(dev, mcam_reg) ||
615 !MLX5_CAP_MCAM_REG(dev, mcqi) ||
616 !MLX5_CAP_MCAM_REG(dev, mcc) ||
617 !MLX5_CAP_MCAM_REG(dev, mcda)) {
618 pr_info("%s flashing isn't supported by the running FW\n", __func__);
619 return -EOPNOTSUPP;
620 }
621
622 return mlxfw_firmware_flash(&mlx5_mlxfw_dev.mlxfw_dev, firmware);
623 }
624