1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (C) 2012-2013 Intel Corporation
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #ifndef __NVME_H__
30 #define __NVME_H__
31
32 #ifdef _KERNEL
33 #include <sys/types.h>
34 #endif
35
36 #include <sys/param.h>
37 #include <sys/endian.h>
38
39 #define NVME_PASSTHROUGH_CMD _IOWR('n', 0, struct nvme_pt_command)
40 #define NVME_RESET_CONTROLLER _IO('n', 1)
41 #define NVME_GET_NSID _IOR('n', 2, struct nvme_get_nsid)
42 #define NVME_GET_MAX_XFER_SIZE _IOR('n', 3, uint64_t)
43
44 #define NVME_IO_TEST _IOWR('n', 100, struct nvme_io_test)
45 #define NVME_BIO_TEST _IOWR('n', 101, struct nvme_io_test)
46
47 /*
48 * Macros to deal with NVME revisions, as defined VS register
49 */
50 #define NVME_REV(x, y) (((x) << 16) | ((y) << 8))
51 #define NVME_MAJOR(r) (((r) >> 16) & 0xffff)
52 #define NVME_MINOR(r) (((r) >> 8) & 0xff)
53
54 /*
55 * Use to mark a command to apply to all namespaces, or to retrieve global
56 * log pages.
57 */
58 #define NVME_GLOBAL_NAMESPACE_TAG ((uint32_t)0xFFFFFFFF)
59
60 /* Cap transfers by the maximum addressable by page-sized PRP (4KB -> 2MB). */
61 #define NVME_MAX_XFER_SIZE MIN(maxphys, (PAGE_SIZE/8*PAGE_SIZE))
62
63 /* Register field definitions */
64 #define NVME_CAP_LO_REG_MQES_SHIFT (0)
65 #define NVME_CAP_LO_REG_MQES_MASK (0xFFFF)
66 #define NVME_CAP_LO_REG_CQR_SHIFT (16)
67 #define NVME_CAP_LO_REG_CQR_MASK (0x1)
68 #define NVME_CAP_LO_REG_AMS_SHIFT (17)
69 #define NVME_CAP_LO_REG_AMS_MASK (0x3)
70 #define NVME_CAP_LO_REG_TO_SHIFT (24)
71 #define NVME_CAP_LO_REG_TO_MASK (0xFF)
72 #define NVME_CAP_LO_MQES(x) \
73 (((x) >> NVME_CAP_LO_REG_MQES_SHIFT) & NVME_CAP_LO_REG_MQES_MASK)
74 #define NVME_CAP_LO_CQR(x) \
75 (((x) >> NVME_CAP_LO_REG_CQR_SHIFT) & NVME_CAP_LO_REG_CQR_MASK)
76 #define NVME_CAP_LO_AMS(x) \
77 (((x) >> NVME_CAP_LO_REG_AMS_SHIFT) & NVME_CAP_LO_REG_AMS_MASK)
78 #define NVME_CAP_LO_TO(x) \
79 (((x) >> NVME_CAP_LO_REG_TO_SHIFT) & NVME_CAP_LO_REG_TO_MASK)
80
81 #define NVME_CAP_HI_REG_DSTRD_SHIFT (0)
82 #define NVME_CAP_HI_REG_DSTRD_MASK (0xF)
83 #define NVME_CAP_HI_REG_NSSRS_SHIFT (4)
84 #define NVME_CAP_HI_REG_NSSRS_MASK (0x1)
85 #define NVME_CAP_HI_REG_CSS_SHIFT (5)
86 #define NVME_CAP_HI_REG_CSS_MASK (0xff)
87 #define NVME_CAP_HI_REG_CSS_NVM_SHIFT (5)
88 #define NVME_CAP_HI_REG_CSS_NVM_MASK (0x1)
89 #define NVME_CAP_HI_REG_BPS_SHIFT (13)
90 #define NVME_CAP_HI_REG_BPS_MASK (0x1)
91 #define NVME_CAP_HI_REG_MPSMIN_SHIFT (16)
92 #define NVME_CAP_HI_REG_MPSMIN_MASK (0xF)
93 #define NVME_CAP_HI_REG_MPSMAX_SHIFT (20)
94 #define NVME_CAP_HI_REG_MPSMAX_MASK (0xF)
95 #define NVME_CAP_HI_REG_PMRS_SHIFT (24)
96 #define NVME_CAP_HI_REG_PMRS_MASK (0x1)
97 #define NVME_CAP_HI_REG_CMBS_SHIFT (25)
98 #define NVME_CAP_HI_REG_CMBS_MASK (0x1)
99 #define NVME_CAP_HI_DSTRD(x) \
100 (((x) >> NVME_CAP_HI_REG_DSTRD_SHIFT) & NVME_CAP_HI_REG_DSTRD_MASK)
101 #define NVME_CAP_HI_NSSRS(x) \
102 (((x) >> NVME_CAP_HI_REG_NSSRS_SHIFT) & NVME_CAP_HI_REG_NSSRS_MASK)
103 #define NVME_CAP_HI_CSS(x) \
104 (((x) >> NVME_CAP_HI_REG_CSS_SHIFT) & NVME_CAP_HI_REG_CSS_MASK)
105 #define NVME_CAP_HI_CSS_NVM(x) \
106 (((x) >> NVME_CAP_HI_REG_CSS_NVM_SHIFT) & NVME_CAP_HI_REG_CSS_NVM_MASK)
107 #define NVME_CAP_HI_BPS(x) \
108 (((x) >> NVME_CAP_HI_REG_BPS_SHIFT) & NVME_CAP_HI_REG_BPS_MASK)
109 #define NVME_CAP_HI_MPSMIN(x) \
110 (((x) >> NVME_CAP_HI_REG_MPSMIN_SHIFT) & NVME_CAP_HI_REG_MPSMIN_MASK)
111 #define NVME_CAP_HI_MPSMAX(x) \
112 (((x) >> NVME_CAP_HI_REG_MPSMAX_SHIFT) & NVME_CAP_HI_REG_MPSMAX_MASK)
113 #define NVME_CAP_HI_PMRS(x) \
114 (((x) >> NVME_CAP_HI_REG_PMRS_SHIFT) & NVME_CAP_HI_REG_PMRS_MASK)
115 #define NVME_CAP_HI_CMBS(x) \
116 (((x) >> NVME_CAP_HI_REG_CMBS_SHIFT) & NVME_CAP_HI_REG_CMBS_MASK)
117
118 #define NVME_CC_REG_EN_SHIFT (0)
119 #define NVME_CC_REG_EN_MASK (0x1)
120 #define NVME_CC_REG_CSS_SHIFT (4)
121 #define NVME_CC_REG_CSS_MASK (0x7)
122 #define NVME_CC_REG_MPS_SHIFT (7)
123 #define NVME_CC_REG_MPS_MASK (0xF)
124 #define NVME_CC_REG_AMS_SHIFT (11)
125 #define NVME_CC_REG_AMS_MASK (0x7)
126 #define NVME_CC_REG_SHN_SHIFT (14)
127 #define NVME_CC_REG_SHN_MASK (0x3)
128 #define NVME_CC_REG_IOSQES_SHIFT (16)
129 #define NVME_CC_REG_IOSQES_MASK (0xF)
130 #define NVME_CC_REG_IOCQES_SHIFT (20)
131 #define NVME_CC_REG_IOCQES_MASK (0xF)
132
133 #define NVME_CSTS_REG_RDY_SHIFT (0)
134 #define NVME_CSTS_REG_RDY_MASK (0x1)
135 #define NVME_CSTS_REG_CFS_SHIFT (1)
136 #define NVME_CSTS_REG_CFS_MASK (0x1)
137 #define NVME_CSTS_REG_SHST_SHIFT (2)
138 #define NVME_CSTS_REG_SHST_MASK (0x3)
139 #define NVME_CSTS_REG_NVSRO_SHIFT (4)
140 #define NVME_CSTS_REG_NVSRO_MASK (0x1)
141 #define NVME_CSTS_REG_PP_SHIFT (5)
142 #define NVME_CSTS_REG_PP_MASK (0x1)
143
144 #define NVME_CSTS_GET_SHST(csts) (((csts) >> NVME_CSTS_REG_SHST_SHIFT) & NVME_CSTS_REG_SHST_MASK)
145
146 #define NVME_AQA_REG_ASQS_SHIFT (0)
147 #define NVME_AQA_REG_ASQS_MASK (0xFFF)
148 #define NVME_AQA_REG_ACQS_SHIFT (16)
149 #define NVME_AQA_REG_ACQS_MASK (0xFFF)
150
151 #define NVME_PMRCAP_REG_RDS_SHIFT (3)
152 #define NVME_PMRCAP_REG_RDS_MASK (0x1)
153 #define NVME_PMRCAP_REG_WDS_SHIFT (4)
154 #define NVME_PMRCAP_REG_WDS_MASK (0x1)
155 #define NVME_PMRCAP_REG_BIR_SHIFT (5)
156 #define NVME_PMRCAP_REG_BIR_MASK (0x7)
157 #define NVME_PMRCAP_REG_PMRTU_SHIFT (8)
158 #define NVME_PMRCAP_REG_PMRTU_MASK (0x3)
159 #define NVME_PMRCAP_REG_PMRWBM_SHIFT (10)
160 #define NVME_PMRCAP_REG_PMRWBM_MASK (0xf)
161 #define NVME_PMRCAP_REG_PMRTO_SHIFT (16)
162 #define NVME_PMRCAP_REG_PMRTO_MASK (0xff)
163 #define NVME_PMRCAP_REG_CMSS_SHIFT (24)
164 #define NVME_PMRCAP_REG_CMSS_MASK (0x1)
165
166 #define NVME_PMRCAP_RDS(x) \
167 (((x) >> NVME_PMRCAP_REG_RDS_SHIFT) & NVME_PMRCAP_REG_RDS_MASK)
168 #define NVME_PMRCAP_WDS(x) \
169 (((x) >> NVME_PMRCAP_REG_WDS_SHIFT) & NVME_PMRCAP_REG_WDS_MASK)
170 #define NVME_PMRCAP_BIR(x) \
171 (((x) >> NVME_PMRCAP_REG_BIR_SHIFT) & NVME_PMRCAP_REG_BIR_MASK)
172 #define NVME_PMRCAP_PMRTU(x) \
173 (((x) >> NVME_PMRCAP_REG_PMRTU_SHIFT) & NVME_PMRCAP_REG_PMRTU_MASK)
174 #define NVME_PMRCAP_PMRWBM(x) \
175 (((x) >> NVME_PMRCAP_REG_PMRWBM_SHIFT) & NVME_PMRCAP_REG_PMRWBM_MASK)
176 #define NVME_PMRCAP_PMRTO(x) \
177 (((x) >> NVME_PMRCAP_REG_PMRTO_SHIFT) & NVME_PMRCAP_REG_PMRTO_MASK)
178 #define NVME_PMRCAP_CMSS(x) \
179 (((x) >> NVME_PMRCAP_REG_CMSS_SHIFT) & NVME_PMRCAP_REG_CMSS_MASK)
180
181 /* Command field definitions */
182
183 #define NVME_CMD_FUSE_SHIFT (8)
184 #define NVME_CMD_FUSE_MASK (0x3)
185
186 #define NVME_STATUS_P_SHIFT (0)
187 #define NVME_STATUS_P_MASK (0x1)
188 #define NVME_STATUS_SC_SHIFT (1)
189 #define NVME_STATUS_SC_MASK (0xFF)
190 #define NVME_STATUS_SCT_SHIFT (9)
191 #define NVME_STATUS_SCT_MASK (0x7)
192 #define NVME_STATUS_CRD_SHIFT (12)
193 #define NVME_STATUS_CRD_MASK (0x3)
194 #define NVME_STATUS_M_SHIFT (14)
195 #define NVME_STATUS_M_MASK (0x1)
196 #define NVME_STATUS_DNR_SHIFT (15)
197 #define NVME_STATUS_DNR_MASK (0x1)
198
199 #define NVME_STATUS_GET_P(st) (((st) >> NVME_STATUS_P_SHIFT) & NVME_STATUS_P_MASK)
200 #define NVME_STATUS_GET_SC(st) (((st) >> NVME_STATUS_SC_SHIFT) & NVME_STATUS_SC_MASK)
201 #define NVME_STATUS_GET_SCT(st) (((st) >> NVME_STATUS_SCT_SHIFT) & NVME_STATUS_SCT_MASK)
202 #define NVME_STATUS_GET_CRD(st) (((st) >> NVME_STATUS_CRD_SHIFT) & NVME_STATUS_CRD_MASK)
203 #define NVME_STATUS_GET_M(st) (((st) >> NVME_STATUS_M_SHIFT) & NVME_STATUS_M_MASK)
204 #define NVME_STATUS_GET_DNR(st) (((st) >> NVME_STATUS_DNR_SHIFT) & NVME_STATUS_DNR_MASK)
205
206 #define NVME_PWR_ST_MPS_SHIFT (0)
207 #define NVME_PWR_ST_MPS_MASK (0x1)
208 #define NVME_PWR_ST_NOPS_SHIFT (1)
209 #define NVME_PWR_ST_NOPS_MASK (0x1)
210 #define NVME_PWR_ST_RRT_SHIFT (0)
211 #define NVME_PWR_ST_RRT_MASK (0x1F)
212 #define NVME_PWR_ST_RRL_SHIFT (0)
213 #define NVME_PWR_ST_RRL_MASK (0x1F)
214 #define NVME_PWR_ST_RWT_SHIFT (0)
215 #define NVME_PWR_ST_RWT_MASK (0x1F)
216 #define NVME_PWR_ST_RWL_SHIFT (0)
217 #define NVME_PWR_ST_RWL_MASK (0x1F)
218 #define NVME_PWR_ST_IPS_SHIFT (6)
219 #define NVME_PWR_ST_IPS_MASK (0x3)
220 #define NVME_PWR_ST_APW_SHIFT (0)
221 #define NVME_PWR_ST_APW_MASK (0x7)
222 #define NVME_PWR_ST_APS_SHIFT (6)
223 #define NVME_PWR_ST_APS_MASK (0x3)
224
225 /** Controller Multi-path I/O and Namespace Sharing Capabilities */
226 /* More then one port */
227 #define NVME_CTRLR_DATA_MIC_MPORTS_SHIFT (0)
228 #define NVME_CTRLR_DATA_MIC_MPORTS_MASK (0x1)
229 /* More then one controller */
230 #define NVME_CTRLR_DATA_MIC_MCTRLRS_SHIFT (1)
231 #define NVME_CTRLR_DATA_MIC_MCTRLRS_MASK (0x1)
232 /* SR-IOV Virtual Function */
233 #define NVME_CTRLR_DATA_MIC_SRIOVVF_SHIFT (2)
234 #define NVME_CTRLR_DATA_MIC_SRIOVVF_MASK (0x1)
235 /* Asymmetric Namespace Access Reporting */
236 #define NVME_CTRLR_DATA_MIC_ANAR_SHIFT (3)
237 #define NVME_CTRLR_DATA_MIC_ANAR_MASK (0x1)
238
239 /** OAES - Optional Asynchronous Events Supported */
240 /* supports Namespace Attribute Notices event */
241 #define NVME_CTRLR_DATA_OAES_NS_ATTR_SHIFT (8)
242 #define NVME_CTRLR_DATA_OAES_NS_ATTR_MASK (0x1)
243 /* supports Firmware Activation Notices event */
244 #define NVME_CTRLR_DATA_OAES_FW_ACTIVATE_SHIFT (9)
245 #define NVME_CTRLR_DATA_OAES_FW_ACTIVATE_MASK (0x1)
246 /* supports Asymmetric Namespace Access Change Notices event */
247 #define NVME_CTRLR_DATA_OAES_ASYM_NS_CHANGE_SHIFT (11)
248 #define NVME_CTRLR_DATA_OAES_ASYM_NS_CHANGE_MASK (0x1)
249 /* supports Predictable Latency Event Aggregate Log Change Notices event */
250 #define NVME_CTRLR_DATA_OAES_PREDICT_LATENCY_SHIFT (12)
251 #define NVME_CTRLR_DATA_OAES_PREDICT_LATENCY_MASK (0x1)
252 /* supports LBA Status Information Notices event */
253 #define NVME_CTRLR_DATA_OAES_LBA_STATUS_SHIFT (13)
254 #define NVME_CTRLR_DATA_OAES_LBA_STATUS_MASK (0x1)
255 /* supports Endurance Group Event Aggregate Log Page Changes Notices event */
256 #define NVME_CTRLR_DATA_OAES_ENDURANCE_GROUP_SHIFT (14)
257 #define NVME_CTRLR_DATA_OAES_ENDURANCE_GROUP_MASK (0x1)
258 /* supports Normal NVM Subsystem Shutdown event */
259 #define NVME_CTRLR_DATA_OAES_NORMAL_SHUTDOWN_SHIFT (15)
260 #define NVME_CTRLR_DATA_OAES_NORMAL_SHUTDOWN_MASK (0x1)
261 /* supports Zone Descriptor Changed Notices event */
262 #define NVME_CTRLR_DATA_OAES_ZONE_DESC_CHANGE_SHIFT (27)
263 #define NVME_CTRLR_DATA_OAES_ZONE_DESC_CHANGE_MASK (0x1)
264 /* supports Discovery Log Page Change Notification event */
265 #define NVME_CTRLR_DATA_OAES_LOG_PAGE_CHANGE_SHIFT (31)
266 #define NVME_CTRLR_DATA_OAES_LOG_PAGE_CHANGE_MASK (0x1)
267
268 /** OACS - optional admin command support */
269 /* supports security send/receive commands */
270 #define NVME_CTRLR_DATA_OACS_SECURITY_SHIFT (0)
271 #define NVME_CTRLR_DATA_OACS_SECURITY_MASK (0x1)
272 /* supports format nvm command */
273 #define NVME_CTRLR_DATA_OACS_FORMAT_SHIFT (1)
274 #define NVME_CTRLR_DATA_OACS_FORMAT_MASK (0x1)
275 /* supports firmware activate/download commands */
276 #define NVME_CTRLR_DATA_OACS_FIRMWARE_SHIFT (2)
277 #define NVME_CTRLR_DATA_OACS_FIRMWARE_MASK (0x1)
278 /* supports namespace management commands */
279 #define NVME_CTRLR_DATA_OACS_NSMGMT_SHIFT (3)
280 #define NVME_CTRLR_DATA_OACS_NSMGMT_MASK (0x1)
281 /* supports Device Self-test command */
282 #define NVME_CTRLR_DATA_OACS_SELFTEST_SHIFT (4)
283 #define NVME_CTRLR_DATA_OACS_SELFTEST_MASK (0x1)
284 /* supports Directives */
285 #define NVME_CTRLR_DATA_OACS_DIRECTIVES_SHIFT (5)
286 #define NVME_CTRLR_DATA_OACS_DIRECTIVES_MASK (0x1)
287 /* supports NVMe-MI Send/Receive */
288 #define NVME_CTRLR_DATA_OACS_NVMEMI_SHIFT (6)
289 #define NVME_CTRLR_DATA_OACS_NVMEMI_MASK (0x1)
290 /* supports Virtualization Management */
291 #define NVME_CTRLR_DATA_OACS_VM_SHIFT (7)
292 #define NVME_CTRLR_DATA_OACS_VM_MASK (0x1)
293 /* supports Doorbell Buffer Config */
294 #define NVME_CTRLR_DATA_OACS_DBBUFFER_SHIFT (8)
295 #define NVME_CTRLR_DATA_OACS_DBBUFFER_MASK (0x1)
296 /* supports Get LBA Status */
297 #define NVME_CTRLR_DATA_OACS_GETLBA_SHIFT (9)
298 #define NVME_CTRLR_DATA_OACS_GETLBA_MASK (0x1)
299
300 /** firmware updates */
301 /* first slot is read-only */
302 #define NVME_CTRLR_DATA_FRMW_SLOT1_RO_SHIFT (0)
303 #define NVME_CTRLR_DATA_FRMW_SLOT1_RO_MASK (0x1)
304 /* number of firmware slots */
305 #define NVME_CTRLR_DATA_FRMW_NUM_SLOTS_SHIFT (1)
306 #define NVME_CTRLR_DATA_FRMW_NUM_SLOTS_MASK (0x7)
307 /* firmware activation without reset */
308 #define NVME_CTRLR_DATA_FRMW_ACT_WO_RESET_SHIFT (4)
309 #define NVME_CTRLR_DATA_FRMW_ACT_WO_RESET_MASK (0x1)
310
311 /** log page attributes */
312 /* per namespace smart/health log page */
313 #define NVME_CTRLR_DATA_LPA_NS_SMART_SHIFT (0)
314 #define NVME_CTRLR_DATA_LPA_NS_SMART_MASK (0x1)
315
316 /** AVSCC - admin vendor specific command configuration */
317 /* admin vendor specific commands use spec format */
318 #define NVME_CTRLR_DATA_AVSCC_SPEC_FORMAT_SHIFT (0)
319 #define NVME_CTRLR_DATA_AVSCC_SPEC_FORMAT_MASK (0x1)
320
321 /** Autonomous Power State Transition Attributes */
322 /* Autonomous Power State Transitions supported */
323 #define NVME_CTRLR_DATA_APSTA_APST_SUPP_SHIFT (0)
324 #define NVME_CTRLR_DATA_APSTA_APST_SUPP_MASK (0x1)
325
326 /** Sanitize Capabilities */
327 /* Crypto Erase Support */
328 #define NVME_CTRLR_DATA_SANICAP_CES_SHIFT (0)
329 #define NVME_CTRLR_DATA_SANICAP_CES_MASK (0x1)
330 /* Block Erase Support */
331 #define NVME_CTRLR_DATA_SANICAP_BES_SHIFT (1)
332 #define NVME_CTRLR_DATA_SANICAP_BES_MASK (0x1)
333 /* Overwrite Support */
334 #define NVME_CTRLR_DATA_SANICAP_OWS_SHIFT (2)
335 #define NVME_CTRLR_DATA_SANICAP_OWS_MASK (0x1)
336 /* No-Deallocate Inhibited */
337 #define NVME_CTRLR_DATA_SANICAP_NDI_SHIFT (29)
338 #define NVME_CTRLR_DATA_SANICAP_NDI_MASK (0x1)
339 /* No-Deallocate Modifies Media After Sanitize */
340 #define NVME_CTRLR_DATA_SANICAP_NODMMAS_SHIFT (30)
341 #define NVME_CTRLR_DATA_SANICAP_NODMMAS_MASK (0x3)
342 #define NVME_CTRLR_DATA_SANICAP_NODMMAS_UNDEF (0)
343 #define NVME_CTRLR_DATA_SANICAP_NODMMAS_NO (1)
344 #define NVME_CTRLR_DATA_SANICAP_NODMMAS_YES (2)
345
346 /** submission queue entry size */
347 #define NVME_CTRLR_DATA_SQES_MIN_SHIFT (0)
348 #define NVME_CTRLR_DATA_SQES_MIN_MASK (0xF)
349 #define NVME_CTRLR_DATA_SQES_MAX_SHIFT (4)
350 #define NVME_CTRLR_DATA_SQES_MAX_MASK (0xF)
351
352 /** completion queue entry size */
353 #define NVME_CTRLR_DATA_CQES_MIN_SHIFT (0)
354 #define NVME_CTRLR_DATA_CQES_MIN_MASK (0xF)
355 #define NVME_CTRLR_DATA_CQES_MAX_SHIFT (4)
356 #define NVME_CTRLR_DATA_CQES_MAX_MASK (0xF)
357
358 /** optional nvm command support */
359 #define NVME_CTRLR_DATA_ONCS_COMPARE_SHIFT (0)
360 #define NVME_CTRLR_DATA_ONCS_COMPARE_MASK (0x1)
361 #define NVME_CTRLR_DATA_ONCS_WRITE_UNC_SHIFT (1)
362 #define NVME_CTRLR_DATA_ONCS_WRITE_UNC_MASK (0x1)
363 #define NVME_CTRLR_DATA_ONCS_DSM_SHIFT (2)
364 #define NVME_CTRLR_DATA_ONCS_DSM_MASK (0x1)
365 #define NVME_CTRLR_DATA_ONCS_WRZERO_SHIFT (3)
366 #define NVME_CTRLR_DATA_ONCS_WRZERO_MASK (0x1)
367 #define NVME_CTRLR_DATA_ONCS_SAVEFEAT_SHIFT (4)
368 #define NVME_CTRLR_DATA_ONCS_SAVEFEAT_MASK (0x1)
369 #define NVME_CTRLR_DATA_ONCS_RESERV_SHIFT (5)
370 #define NVME_CTRLR_DATA_ONCS_RESERV_MASK (0x1)
371 #define NVME_CTRLR_DATA_ONCS_TIMESTAMP_SHIFT (6)
372 #define NVME_CTRLR_DATA_ONCS_TIMESTAMP_MASK (0x1)
373 #define NVME_CTRLR_DATA_ONCS_VERIFY_SHIFT (7)
374 #define NVME_CTRLR_DATA_ONCS_VERIFY_MASK (0x1)
375
376 /** Fused Operation Support */
377 #define NVME_CTRLR_DATA_FUSES_CNW_SHIFT (0)
378 #define NVME_CTRLR_DATA_FUSES_CNW_MASK (0x1)
379
380 /** Format NVM Attributes */
381 #define NVME_CTRLR_DATA_FNA_FORMAT_ALL_SHIFT (0)
382 #define NVME_CTRLR_DATA_FNA_FORMAT_ALL_MASK (0x1)
383 #define NVME_CTRLR_DATA_FNA_ERASE_ALL_SHIFT (1)
384 #define NVME_CTRLR_DATA_FNA_ERASE_ALL_MASK (0x1)
385 #define NVME_CTRLR_DATA_FNA_CRYPTO_ERASE_SHIFT (2)
386 #define NVME_CTRLR_DATA_FNA_CRYPTO_ERASE_MASK (0x1)
387
388 /** volatile write cache */
389 /* volatile write cache present */
390 #define NVME_CTRLR_DATA_VWC_PRESENT_SHIFT (0)
391 #define NVME_CTRLR_DATA_VWC_PRESENT_MASK (0x1)
392 /* flush all namespaces supported */
393 #define NVME_CTRLR_DATA_VWC_ALL_SHIFT (1)
394 #define NVME_CTRLR_DATA_VWC_ALL_MASK (0x3)
395 #define NVME_CTRLR_DATA_VWC_ALL_UNKNOWN (0)
396 #define NVME_CTRLR_DATA_VWC_ALL_NO (2)
397 #define NVME_CTRLR_DATA_VWC_ALL_YES (3)
398
399 /** namespace features */
400 /* thin provisioning */
401 #define NVME_NS_DATA_NSFEAT_THIN_PROV_SHIFT (0)
402 #define NVME_NS_DATA_NSFEAT_THIN_PROV_MASK (0x1)
403 /* NAWUN, NAWUPF, and NACWU fields are valid */
404 #define NVME_NS_DATA_NSFEAT_NA_FIELDS_SHIFT (1)
405 #define NVME_NS_DATA_NSFEAT_NA_FIELDS_MASK (0x1)
406 /* Deallocated or Unwritten Logical Block errors supported */
407 #define NVME_NS_DATA_NSFEAT_DEALLOC_SHIFT (2)
408 #define NVME_NS_DATA_NSFEAT_DEALLOC_MASK (0x1)
409 /* NGUID and EUI64 fields are not reusable */
410 #define NVME_NS_DATA_NSFEAT_NO_ID_REUSE_SHIFT (3)
411 #define NVME_NS_DATA_NSFEAT_NO_ID_REUSE_MASK (0x1)
412 /* NPWG, NPWA, NPDG, NPDA, and NOWS are valid */
413 #define NVME_NS_DATA_NSFEAT_NPVALID_SHIFT (4)
414 #define NVME_NS_DATA_NSFEAT_NPVALID_MASK (0x1)
415
416 /** formatted lba size */
417 #define NVME_NS_DATA_FLBAS_FORMAT_SHIFT (0)
418 #define NVME_NS_DATA_FLBAS_FORMAT_MASK (0xF)
419 #define NVME_NS_DATA_FLBAS_EXTENDED_SHIFT (4)
420 #define NVME_NS_DATA_FLBAS_EXTENDED_MASK (0x1)
421
422 /** metadata capabilities */
423 /* metadata can be transferred as part of data prp list */
424 #define NVME_NS_DATA_MC_EXTENDED_SHIFT (0)
425 #define NVME_NS_DATA_MC_EXTENDED_MASK (0x1)
426 /* metadata can be transferred with separate metadata pointer */
427 #define NVME_NS_DATA_MC_POINTER_SHIFT (1)
428 #define NVME_NS_DATA_MC_POINTER_MASK (0x1)
429
430 /** end-to-end data protection capabilities */
431 /* protection information type 1 */
432 #define NVME_NS_DATA_DPC_PIT1_SHIFT (0)
433 #define NVME_NS_DATA_DPC_PIT1_MASK (0x1)
434 /* protection information type 2 */
435 #define NVME_NS_DATA_DPC_PIT2_SHIFT (1)
436 #define NVME_NS_DATA_DPC_PIT2_MASK (0x1)
437 /* protection information type 3 */
438 #define NVME_NS_DATA_DPC_PIT3_SHIFT (2)
439 #define NVME_NS_DATA_DPC_PIT3_MASK (0x1)
440 /* first eight bytes of metadata */
441 #define NVME_NS_DATA_DPC_MD_START_SHIFT (3)
442 #define NVME_NS_DATA_DPC_MD_START_MASK (0x1)
443 /* last eight bytes of metadata */
444 #define NVME_NS_DATA_DPC_MD_END_SHIFT (4)
445 #define NVME_NS_DATA_DPC_MD_END_MASK (0x1)
446
447 /** end-to-end data protection type settings */
448 /* protection information type */
449 #define NVME_NS_DATA_DPS_PIT_SHIFT (0)
450 #define NVME_NS_DATA_DPS_PIT_MASK (0x7)
451 /* 1 == protection info transferred at start of metadata */
452 /* 0 == protection info transferred at end of metadata */
453 #define NVME_NS_DATA_DPS_MD_START_SHIFT (3)
454 #define NVME_NS_DATA_DPS_MD_START_MASK (0x1)
455
456 /** Namespace Multi-path I/O and Namespace Sharing Capabilities */
457 /* the namespace may be attached to two or more controllers */
458 #define NVME_NS_DATA_NMIC_MAY_BE_SHARED_SHIFT (0)
459 #define NVME_NS_DATA_NMIC_MAY_BE_SHARED_MASK (0x1)
460
461 /** Reservation Capabilities */
462 /* Persist Through Power Loss */
463 #define NVME_NS_DATA_RESCAP_PTPL_SHIFT (0)
464 #define NVME_NS_DATA_RESCAP_PTPL_MASK (0x1)
465 /* supports the Write Exclusive */
466 #define NVME_NS_DATA_RESCAP_WR_EX_SHIFT (1)
467 #define NVME_NS_DATA_RESCAP_WR_EX_MASK (0x1)
468 /* supports the Exclusive Access */
469 #define NVME_NS_DATA_RESCAP_EX_AC_SHIFT (2)
470 #define NVME_NS_DATA_RESCAP_EX_AC_MASK (0x1)
471 /* supports the Write Exclusive – Registrants Only */
472 #define NVME_NS_DATA_RESCAP_WR_EX_RO_SHIFT (3)
473 #define NVME_NS_DATA_RESCAP_WR_EX_RO_MASK (0x1)
474 /* supports the Exclusive Access - Registrants Only */
475 #define NVME_NS_DATA_RESCAP_EX_AC_RO_SHIFT (4)
476 #define NVME_NS_DATA_RESCAP_EX_AC_RO_MASK (0x1)
477 /* supports the Write Exclusive – All Registrants */
478 #define NVME_NS_DATA_RESCAP_WR_EX_AR_SHIFT (5)
479 #define NVME_NS_DATA_RESCAP_WR_EX_AR_MASK (0x1)
480 /* supports the Exclusive Access - All Registrants */
481 #define NVME_NS_DATA_RESCAP_EX_AC_AR_SHIFT (6)
482 #define NVME_NS_DATA_RESCAP_EX_AC_AR_MASK (0x1)
483 /* Ignore Existing Key is used as defined in revision 1.3 or later */
484 #define NVME_NS_DATA_RESCAP_IEKEY13_SHIFT (7)
485 #define NVME_NS_DATA_RESCAP_IEKEY13_MASK (0x1)
486
487 /** Format Progress Indicator */
488 /* percentage of the Format NVM command that remains to be completed */
489 #define NVME_NS_DATA_FPI_PERC_SHIFT (0)
490 #define NVME_NS_DATA_FPI_PERC_MASK (0x7f)
491 /* namespace supports the Format Progress Indicator */
492 #define NVME_NS_DATA_FPI_SUPP_SHIFT (7)
493 #define NVME_NS_DATA_FPI_SUPP_MASK (0x1)
494
495 /** Deallocate Logical Block Features */
496 /* deallocated logical block read behavior */
497 #define NVME_NS_DATA_DLFEAT_READ_SHIFT (0)
498 #define NVME_NS_DATA_DLFEAT_READ_MASK (0x07)
499 #define NVME_NS_DATA_DLFEAT_READ_NR (0x00)
500 #define NVME_NS_DATA_DLFEAT_READ_00 (0x01)
501 #define NVME_NS_DATA_DLFEAT_READ_FF (0x02)
502 /* supports the Deallocate bit in the Write Zeroes */
503 #define NVME_NS_DATA_DLFEAT_DWZ_SHIFT (3)
504 #define NVME_NS_DATA_DLFEAT_DWZ_MASK (0x01)
505 /* Guard field for deallocated logical blocks is set to the CRC */
506 #define NVME_NS_DATA_DLFEAT_GCRC_SHIFT (4)
507 #define NVME_NS_DATA_DLFEAT_GCRC_MASK (0x01)
508
509 /** lba format support */
510 /* metadata size */
511 #define NVME_NS_DATA_LBAF_MS_SHIFT (0)
512 #define NVME_NS_DATA_LBAF_MS_MASK (0xFFFF)
513 /* lba data size */
514 #define NVME_NS_DATA_LBAF_LBADS_SHIFT (16)
515 #define NVME_NS_DATA_LBAF_LBADS_MASK (0xFF)
516 /* relative performance */
517 #define NVME_NS_DATA_LBAF_RP_SHIFT (24)
518 #define NVME_NS_DATA_LBAF_RP_MASK (0x3)
519
520 enum nvme_critical_warning_state {
521 NVME_CRIT_WARN_ST_AVAILABLE_SPARE = 0x1,
522 NVME_CRIT_WARN_ST_TEMPERATURE = 0x2,
523 NVME_CRIT_WARN_ST_DEVICE_RELIABILITY = 0x4,
524 NVME_CRIT_WARN_ST_READ_ONLY = 0x8,
525 NVME_CRIT_WARN_ST_VOLATILE_MEMORY_BACKUP = 0x10,
526 };
527 #define NVME_CRIT_WARN_ST_RESERVED_MASK (0xE0)
528 #define NVME_ASYNC_EVENT_NS_ATTRIBUTE (0x100)
529 #define NVME_ASYNC_EVENT_FW_ACTIVATE (0x200)
530
531 /* slot for current FW */
532 #define NVME_FIRMWARE_PAGE_AFI_SLOT_SHIFT (0)
533 #define NVME_FIRMWARE_PAGE_AFI_SLOT_MASK (0x7)
534
535 /* Commands Supported and Effects */
536 #define NVME_CE_PAGE_CSUP_SHIFT (0)
537 #define NVME_CE_PAGE_CSUP_MASK (0x1)
538 #define NVME_CE_PAGE_LBCC_SHIFT (1)
539 #define NVME_CE_PAGE_LBCC_MASK (0x1)
540 #define NVME_CE_PAGE_NCC_SHIFT (2)
541 #define NVME_CE_PAGE_NCC_MASK (0x1)
542 #define NVME_CE_PAGE_NIC_SHIFT (3)
543 #define NVME_CE_PAGE_NIC_MASK (0x1)
544 #define NVME_CE_PAGE_CCC_SHIFT (4)
545 #define NVME_CE_PAGE_CCC_MASK (0x1)
546 #define NVME_CE_PAGE_CSE_SHIFT (16)
547 #define NVME_CE_PAGE_CSE_MASK (0x7)
548 #define NVME_CE_PAGE_UUID_SHIFT (19)
549 #define NVME_CE_PAGE_UUID_MASK (0x1)
550
551 /* Sanitize Status */
552 #define NVME_SS_PAGE_SSTAT_STATUS_SHIFT (0)
553 #define NVME_SS_PAGE_SSTAT_STATUS_MASK (0x7)
554 #define NVME_SS_PAGE_SSTAT_STATUS_NEVER (0)
555 #define NVME_SS_PAGE_SSTAT_STATUS_COMPLETED (1)
556 #define NVME_SS_PAGE_SSTAT_STATUS_INPROG (2)
557 #define NVME_SS_PAGE_SSTAT_STATUS_FAILED (3)
558 #define NVME_SS_PAGE_SSTAT_STATUS_COMPLETEDWD (4)
559 #define NVME_SS_PAGE_SSTAT_PASSES_SHIFT (3)
560 #define NVME_SS_PAGE_SSTAT_PASSES_MASK (0x1f)
561 #define NVME_SS_PAGE_SSTAT_GDE_SHIFT (8)
562 #define NVME_SS_PAGE_SSTAT_GDE_MASK (0x1)
563
564 /* Features */
565 /* Get Features */
566 #define NVME_FEAT_GET_SEL_SHIFT (8)
567 #define NVME_FEAT_GET_SEL_MASK (0x7)
568 #define NVME_FEAT_GET_FID_SHIFT (0)
569 #define NVME_FEAT_GET_FID_MASK (0xff)
570
571 /* Set Features */
572 #define NVME_FEAT_SET_SV_SHIFT (31)
573 #define NVME_FEAT_SET_SV_MASK (0x1)
574 #define NVME_FEAT_SET_FID_SHIFT (0)
575 #define NVME_FEAT_SET_FID_MASK (0xff)
576
577 /* Helper macro to combine *_MASK and *_SHIFT defines */
578 #define NVMEB(name) (name##_MASK << name##_SHIFT)
579
580 /* Helper macro to extract value from x */
581 #define NVMEV(name, x) (((x) >> name##_SHIFT) & name##_MASK)
582
583 /* CC register SHN field values */
584 enum shn_value {
585 NVME_SHN_NORMAL = 0x1,
586 NVME_SHN_ABRUPT = 0x2,
587 };
588
589 /* CSTS register SHST field values */
590 enum shst_value {
591 NVME_SHST_NORMAL = 0x0,
592 NVME_SHST_OCCURRING = 0x1,
593 NVME_SHST_COMPLETE = 0x2,
594 };
595
596 struct nvme_registers {
597 uint32_t cap_lo; /* controller capabilities */
598 uint32_t cap_hi;
599 uint32_t vs; /* version */
600 uint32_t intms; /* interrupt mask set */
601 uint32_t intmc; /* interrupt mask clear */
602 uint32_t cc; /* controller configuration */
603 uint32_t reserved1;
604 uint32_t csts; /* controller status */
605 uint32_t nssr; /* NVM Subsystem Reset */
606 uint32_t aqa; /* admin queue attributes */
607 uint64_t asq; /* admin submission queue base addr */
608 uint64_t acq; /* admin completion queue base addr */
609 uint32_t cmbloc; /* Controller Memory Buffer Location */
610 uint32_t cmbsz; /* Controller Memory Buffer Size */
611 uint32_t bpinfo; /* Boot Partition Information */
612 uint32_t bprsel; /* Boot Partition Read Select */
613 uint64_t bpmbl; /* Boot Partition Memory Buffer Location */
614 uint64_t cmbmsc; /* Controller Memory Buffer Memory Space Control */
615 uint32_t cmbsts; /* Controller Memory Buffer Status */
616 uint8_t reserved3[3492]; /* 5Ch - DFFh */
617 uint32_t pmrcap; /* Persistent Memory Capabilities */
618 uint32_t pmrctl; /* Persistent Memory Region Control */
619 uint32_t pmrsts; /* Persistent Memory Region Status */
620 uint32_t pmrebs; /* Persistent Memory Region Elasticity Buffer Size */
621 uint32_t pmrswtp; /* Persistent Memory Region Sustained Write Throughput */
622 uint32_t pmrmsc_lo; /* Persistent Memory Region Controller Memory Space Control */
623 uint32_t pmrmsc_hi;
624 uint8_t reserved4[484]; /* E1Ch - FFFh */
625 struct {
626 uint32_t sq_tdbl; /* submission queue tail doorbell */
627 uint32_t cq_hdbl; /* completion queue head doorbell */
628 } doorbell[1];
629 };
630
631 _Static_assert(sizeof(struct nvme_registers) == 0x1008, "bad size for nvme_registers");
632
633 struct nvme_command {
634 /* dword 0 */
635 uint8_t opc; /* opcode */
636 uint8_t fuse; /* fused operation */
637 uint16_t cid; /* command identifier */
638
639 /* dword 1 */
640 uint32_t nsid; /* namespace identifier */
641
642 /* dword 2-3 */
643 uint32_t rsvd2;
644 uint32_t rsvd3;
645
646 /* dword 4-5 */
647 uint64_t mptr; /* metadata pointer */
648
649 /* dword 6-7 */
650 uint64_t prp1; /* prp entry 1 */
651
652 /* dword 8-9 */
653 uint64_t prp2; /* prp entry 2 */
654
655 /* dword 10-15 */
656 uint32_t cdw10; /* command-specific */
657 uint32_t cdw11; /* command-specific */
658 uint32_t cdw12; /* command-specific */
659 uint32_t cdw13; /* command-specific */
660 uint32_t cdw14; /* command-specific */
661 uint32_t cdw15; /* command-specific */
662 };
663
664 _Static_assert(sizeof(struct nvme_command) == 16 * 4, "bad size for nvme_command");
665
666 struct nvme_completion {
667 /* dword 0 */
668 uint32_t cdw0; /* command-specific */
669
670 /* dword 1 */
671 uint32_t rsvd1;
672
673 /* dword 2 */
674 uint16_t sqhd; /* submission queue head pointer */
675 uint16_t sqid; /* submission queue identifier */
676
677 /* dword 3 */
678 uint16_t cid; /* command identifier */
679 uint16_t status;
680 } __aligned(8); /* riscv: nvme_qpair_process_completions has better code gen */
681
682 _Static_assert(sizeof(struct nvme_completion) == 4 * 4, "bad size for nvme_completion");
683
684 struct nvme_dsm_range {
685 uint32_t attributes;
686 uint32_t length;
687 uint64_t starting_lba;
688 };
689
690 /* Largest DSM Trim that can be done */
691 #define NVME_MAX_DSM_TRIM 4096
692
693 _Static_assert(sizeof(struct nvme_dsm_range) == 16, "bad size for nvme_dsm_ranage");
694
695 /* status code types */
696 enum nvme_status_code_type {
697 NVME_SCT_GENERIC = 0x0,
698 NVME_SCT_COMMAND_SPECIFIC = 0x1,
699 NVME_SCT_MEDIA_ERROR = 0x2,
700 NVME_SCT_PATH_RELATED = 0x3,
701 /* 0x3-0x6 - reserved */
702 NVME_SCT_VENDOR_SPECIFIC = 0x7,
703 };
704
705 /* generic command status codes */
706 enum nvme_generic_command_status_code {
707 NVME_SC_SUCCESS = 0x00,
708 NVME_SC_INVALID_OPCODE = 0x01,
709 NVME_SC_INVALID_FIELD = 0x02,
710 NVME_SC_COMMAND_ID_CONFLICT = 0x03,
711 NVME_SC_DATA_TRANSFER_ERROR = 0x04,
712 NVME_SC_ABORTED_POWER_LOSS = 0x05,
713 NVME_SC_INTERNAL_DEVICE_ERROR = 0x06,
714 NVME_SC_ABORTED_BY_REQUEST = 0x07,
715 NVME_SC_ABORTED_SQ_DELETION = 0x08,
716 NVME_SC_ABORTED_FAILED_FUSED = 0x09,
717 NVME_SC_ABORTED_MISSING_FUSED = 0x0a,
718 NVME_SC_INVALID_NAMESPACE_OR_FORMAT = 0x0b,
719 NVME_SC_COMMAND_SEQUENCE_ERROR = 0x0c,
720 NVME_SC_INVALID_SGL_SEGMENT_DESCR = 0x0d,
721 NVME_SC_INVALID_NUMBER_OF_SGL_DESCR = 0x0e,
722 NVME_SC_DATA_SGL_LENGTH_INVALID = 0x0f,
723 NVME_SC_METADATA_SGL_LENGTH_INVALID = 0x10,
724 NVME_SC_SGL_DESCRIPTOR_TYPE_INVALID = 0x11,
725 NVME_SC_INVALID_USE_OF_CMB = 0x12,
726 NVME_SC_PRP_OFFET_INVALID = 0x13,
727 NVME_SC_ATOMIC_WRITE_UNIT_EXCEEDED = 0x14,
728 NVME_SC_OPERATION_DENIED = 0x15,
729 NVME_SC_SGL_OFFSET_INVALID = 0x16,
730 /* 0x17 - reserved */
731 NVME_SC_HOST_ID_INCONSISTENT_FORMAT = 0x18,
732 NVME_SC_KEEP_ALIVE_TIMEOUT_EXPIRED = 0x19,
733 NVME_SC_KEEP_ALIVE_TIMEOUT_INVALID = 0x1a,
734 NVME_SC_ABORTED_DUE_TO_PREEMPT = 0x1b,
735 NVME_SC_SANITIZE_FAILED = 0x1c,
736 NVME_SC_SANITIZE_IN_PROGRESS = 0x1d,
737 NVME_SC_SGL_DATA_BLOCK_GRAN_INVALID = 0x1e,
738 NVME_SC_NOT_SUPPORTED_IN_CMB = 0x1f,
739 NVME_SC_NAMESPACE_IS_WRITE_PROTECTED = 0x20,
740 NVME_SC_COMMAND_INTERRUPTED = 0x21,
741 NVME_SC_TRANSIENT_TRANSPORT_ERROR = 0x22,
742
743 NVME_SC_LBA_OUT_OF_RANGE = 0x80,
744 NVME_SC_CAPACITY_EXCEEDED = 0x81,
745 NVME_SC_NAMESPACE_NOT_READY = 0x82,
746 NVME_SC_RESERVATION_CONFLICT = 0x83,
747 NVME_SC_FORMAT_IN_PROGRESS = 0x84,
748 };
749
750 /* command specific status codes */
751 enum nvme_command_specific_status_code {
752 NVME_SC_COMPLETION_QUEUE_INVALID = 0x00,
753 NVME_SC_INVALID_QUEUE_IDENTIFIER = 0x01,
754 NVME_SC_MAXIMUM_QUEUE_SIZE_EXCEEDED = 0x02,
755 NVME_SC_ABORT_COMMAND_LIMIT_EXCEEDED = 0x03,
756 /* 0x04 - reserved */
757 NVME_SC_ASYNC_EVENT_REQUEST_LIMIT_EXCEEDED = 0x05,
758 NVME_SC_INVALID_FIRMWARE_SLOT = 0x06,
759 NVME_SC_INVALID_FIRMWARE_IMAGE = 0x07,
760 NVME_SC_INVALID_INTERRUPT_VECTOR = 0x08,
761 NVME_SC_INVALID_LOG_PAGE = 0x09,
762 NVME_SC_INVALID_FORMAT = 0x0a,
763 NVME_SC_FIRMWARE_REQUIRES_RESET = 0x0b,
764 NVME_SC_INVALID_QUEUE_DELETION = 0x0c,
765 NVME_SC_FEATURE_NOT_SAVEABLE = 0x0d,
766 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x0e,
767 NVME_SC_FEATURE_NOT_NS_SPECIFIC = 0x0f,
768 NVME_SC_FW_ACT_REQUIRES_NVMS_RESET = 0x10,
769 NVME_SC_FW_ACT_REQUIRES_RESET = 0x11,
770 NVME_SC_FW_ACT_REQUIRES_TIME = 0x12,
771 NVME_SC_FW_ACT_PROHIBITED = 0x13,
772 NVME_SC_OVERLAPPING_RANGE = 0x14,
773 NVME_SC_NS_INSUFFICIENT_CAPACITY = 0x15,
774 NVME_SC_NS_ID_UNAVAILABLE = 0x16,
775 /* 0x17 - reserved */
776 NVME_SC_NS_ALREADY_ATTACHED = 0x18,
777 NVME_SC_NS_IS_PRIVATE = 0x19,
778 NVME_SC_NS_NOT_ATTACHED = 0x1a,
779 NVME_SC_THIN_PROV_NOT_SUPPORTED = 0x1b,
780 NVME_SC_CTRLR_LIST_INVALID = 0x1c,
781 NVME_SC_SELF_TEST_IN_PROGRESS = 0x1d,
782 NVME_SC_BOOT_PART_WRITE_PROHIB = 0x1e,
783 NVME_SC_INVALID_CTRLR_ID = 0x1f,
784 NVME_SC_INVALID_SEC_CTRLR_STATE = 0x20,
785 NVME_SC_INVALID_NUM_OF_CTRLR_RESRC = 0x21,
786 NVME_SC_INVALID_RESOURCE_ID = 0x22,
787 NVME_SC_SANITIZE_PROHIBITED_WPMRE = 0x23,
788 NVME_SC_ANA_GROUP_ID_INVALID = 0x24,
789 NVME_SC_ANA_ATTACH_FAILED = 0x25,
790
791 NVME_SC_CONFLICTING_ATTRIBUTES = 0x80,
792 NVME_SC_INVALID_PROTECTION_INFO = 0x81,
793 NVME_SC_ATTEMPTED_WRITE_TO_RO_PAGE = 0x82,
794 };
795
796 /* media error status codes */
797 enum nvme_media_error_status_code {
798 NVME_SC_WRITE_FAULTS = 0x80,
799 NVME_SC_UNRECOVERED_READ_ERROR = 0x81,
800 NVME_SC_GUARD_CHECK_ERROR = 0x82,
801 NVME_SC_APPLICATION_TAG_CHECK_ERROR = 0x83,
802 NVME_SC_REFERENCE_TAG_CHECK_ERROR = 0x84,
803 NVME_SC_COMPARE_FAILURE = 0x85,
804 NVME_SC_ACCESS_DENIED = 0x86,
805 NVME_SC_DEALLOCATED_OR_UNWRITTEN = 0x87,
806 };
807
808 /* path related status codes */
809 enum nvme_path_related_status_code {
810 NVME_SC_INTERNAL_PATH_ERROR = 0x00,
811 NVME_SC_ASYMMETRIC_ACCESS_PERSISTENT_LOSS = 0x01,
812 NVME_SC_ASYMMETRIC_ACCESS_INACCESSIBLE = 0x02,
813 NVME_SC_ASYMMETRIC_ACCESS_TRANSITION = 0x03,
814 NVME_SC_CONTROLLER_PATHING_ERROR = 0x60,
815 NVME_SC_HOST_PATHING_ERROR = 0x70,
816 NVME_SC_COMMAND_ABOTHED_BY_HOST = 0x71,
817 };
818
819 /* admin opcodes */
820 enum nvme_admin_opcode {
821 NVME_OPC_DELETE_IO_SQ = 0x00,
822 NVME_OPC_CREATE_IO_SQ = 0x01,
823 NVME_OPC_GET_LOG_PAGE = 0x02,
824 /* 0x03 - reserved */
825 NVME_OPC_DELETE_IO_CQ = 0x04,
826 NVME_OPC_CREATE_IO_CQ = 0x05,
827 NVME_OPC_IDENTIFY = 0x06,
828 /* 0x07 - reserved */
829 NVME_OPC_ABORT = 0x08,
830 NVME_OPC_SET_FEATURES = 0x09,
831 NVME_OPC_GET_FEATURES = 0x0a,
832 /* 0x0b - reserved */
833 NVME_OPC_ASYNC_EVENT_REQUEST = 0x0c,
834 NVME_OPC_NAMESPACE_MANAGEMENT = 0x0d,
835 /* 0x0e-0x0f - reserved */
836 NVME_OPC_FIRMWARE_ACTIVATE = 0x10,
837 NVME_OPC_FIRMWARE_IMAGE_DOWNLOAD = 0x11,
838 /* 0x12-0x13 - reserved */
839 NVME_OPC_DEVICE_SELF_TEST = 0x14,
840 NVME_OPC_NAMESPACE_ATTACHMENT = 0x15,
841 /* 0x16-0x17 - reserved */
842 NVME_OPC_KEEP_ALIVE = 0x18,
843 NVME_OPC_DIRECTIVE_SEND = 0x19,
844 NVME_OPC_DIRECTIVE_RECEIVE = 0x1a,
845 /* 0x1b - reserved */
846 NVME_OPC_VIRTUALIZATION_MANAGEMENT = 0x1c,
847 NVME_OPC_NVME_MI_SEND = 0x1d,
848 NVME_OPC_NVME_MI_RECEIVE = 0x1e,
849 /* 0x1f-0x7b - reserved */
850 NVME_OPC_DOORBELL_BUFFER_CONFIG = 0x7c,
851
852 NVME_OPC_FORMAT_NVM = 0x80,
853 NVME_OPC_SECURITY_SEND = 0x81,
854 NVME_OPC_SECURITY_RECEIVE = 0x82,
855 /* 0x83 - reserved */
856 NVME_OPC_SANITIZE = 0x84,
857 /* 0x85 - reserved */
858 NVME_OPC_GET_LBA_STATUS = 0x86,
859 };
860
861 /* nvme nvm opcodes */
862 enum nvme_nvm_opcode {
863 NVME_OPC_FLUSH = 0x00,
864 NVME_OPC_WRITE = 0x01,
865 NVME_OPC_READ = 0x02,
866 /* 0x03 - reserved */
867 NVME_OPC_WRITE_UNCORRECTABLE = 0x04,
868 NVME_OPC_COMPARE = 0x05,
869 /* 0x06-0x07 - reserved */
870 NVME_OPC_WRITE_ZEROES = 0x08,
871 NVME_OPC_DATASET_MANAGEMENT = 0x09,
872 /* 0x0a-0x0b - reserved */
873 NVME_OPC_VERIFY = 0x0c,
874 NVME_OPC_RESERVATION_REGISTER = 0x0d,
875 NVME_OPC_RESERVATION_REPORT = 0x0e,
876 /* 0x0f-0x10 - reserved */
877 NVME_OPC_RESERVATION_ACQUIRE = 0x11,
878 /* 0x12-0x14 - reserved */
879 NVME_OPC_RESERVATION_RELEASE = 0x15,
880 };
881
882 enum nvme_feature {
883 /* 0x00 - reserved */
884 NVME_FEAT_ARBITRATION = 0x01,
885 NVME_FEAT_POWER_MANAGEMENT = 0x02,
886 NVME_FEAT_LBA_RANGE_TYPE = 0x03,
887 NVME_FEAT_TEMPERATURE_THRESHOLD = 0x04,
888 NVME_FEAT_ERROR_RECOVERY = 0x05,
889 NVME_FEAT_VOLATILE_WRITE_CACHE = 0x06,
890 NVME_FEAT_NUMBER_OF_QUEUES = 0x07,
891 NVME_FEAT_INTERRUPT_COALESCING = 0x08,
892 NVME_FEAT_INTERRUPT_VECTOR_CONFIGURATION = 0x09,
893 NVME_FEAT_WRITE_ATOMICITY = 0x0A,
894 NVME_FEAT_ASYNC_EVENT_CONFIGURATION = 0x0B,
895 NVME_FEAT_AUTONOMOUS_POWER_STATE_TRANSITION = 0x0C,
896 NVME_FEAT_HOST_MEMORY_BUFFER = 0x0D,
897 NVME_FEAT_TIMESTAMP = 0x0E,
898 NVME_FEAT_KEEP_ALIVE_TIMER = 0x0F,
899 NVME_FEAT_HOST_CONTROLLED_THERMAL_MGMT = 0x10,
900 NVME_FEAT_NON_OP_POWER_STATE_CONFIG = 0x11,
901 NVME_FEAT_READ_RECOVERY_LEVEL_CONFIG = 0x12,
902 NVME_FEAT_PREDICTABLE_LATENCY_MODE_CONFIG = 0x13,
903 NVME_FEAT_PREDICTABLE_LATENCY_MODE_WINDOW = 0x14,
904 NVME_FEAT_LBA_STATUS_INFORMATION_ATTRIBUTES = 0x15,
905 NVME_FEAT_HOST_BEHAVIOR_SUPPORT = 0x16,
906 NVME_FEAT_SANITIZE_CONFIG = 0x17,
907 NVME_FEAT_ENDURANCE_GROUP_EVENT_CONFIGURATION = 0x18,
908 /* 0x19-0x77 - reserved */
909 /* 0x78-0x7f - NVMe Management Interface */
910 NVME_FEAT_SOFTWARE_PROGRESS_MARKER = 0x80,
911 NVME_FEAT_HOST_IDENTIFIER = 0x81,
912 NVME_FEAT_RESERVATION_NOTIFICATION_MASK = 0x82,
913 NVME_FEAT_RESERVATION_PERSISTENCE = 0x83,
914 NVME_FEAT_NAMESPACE_WRITE_PROTECTION_CONFIG = 0x84,
915 /* 0x85-0xBF - command set specific (reserved) */
916 /* 0xC0-0xFF - vendor specific */
917 };
918
919 enum nvme_dsm_attribute {
920 NVME_DSM_ATTR_INTEGRAL_READ = 0x1,
921 NVME_DSM_ATTR_INTEGRAL_WRITE = 0x2,
922 NVME_DSM_ATTR_DEALLOCATE = 0x4,
923 };
924
925 enum nvme_activate_action {
926 NVME_AA_REPLACE_NO_ACTIVATE = 0x0,
927 NVME_AA_REPLACE_ACTIVATE = 0x1,
928 NVME_AA_ACTIVATE = 0x2,
929 };
930
931 struct nvme_power_state {
932 /** Maximum Power */
933 uint16_t mp; /* Maximum Power */
934 uint8_t ps_rsvd1;
935 uint8_t mps_nops; /* Max Power Scale, Non-Operational State */
936
937 uint32_t enlat; /* Entry Latency */
938 uint32_t exlat; /* Exit Latency */
939
940 uint8_t rrt; /* Relative Read Throughput */
941 uint8_t rrl; /* Relative Read Latency */
942 uint8_t rwt; /* Relative Write Throughput */
943 uint8_t rwl; /* Relative Write Latency */
944
945 uint16_t idlp; /* Idle Power */
946 uint8_t ips; /* Idle Power Scale */
947 uint8_t ps_rsvd8;
948
949 uint16_t actp; /* Active Power */
950 uint8_t apw_aps; /* Active Power Workload, Active Power Scale */
951 uint8_t ps_rsvd10[9];
952 } __packed;
953
954 _Static_assert(sizeof(struct nvme_power_state) == 32, "bad size for nvme_power_state");
955
956 #define NVME_SERIAL_NUMBER_LENGTH 20
957 #define NVME_MODEL_NUMBER_LENGTH 40
958 #define NVME_FIRMWARE_REVISION_LENGTH 8
959
960 struct nvme_controller_data {
961 /* bytes 0-255: controller capabilities and features */
962
963 /** pci vendor id */
964 uint16_t vid;
965
966 /** pci subsystem vendor id */
967 uint16_t ssvid;
968
969 /** serial number */
970 uint8_t sn[NVME_SERIAL_NUMBER_LENGTH];
971
972 /** model number */
973 uint8_t mn[NVME_MODEL_NUMBER_LENGTH];
974
975 /** firmware revision */
976 uint8_t fr[NVME_FIRMWARE_REVISION_LENGTH];
977
978 /** recommended arbitration burst */
979 uint8_t rab;
980
981 /** ieee oui identifier */
982 uint8_t ieee[3];
983
984 /** multi-interface capabilities */
985 uint8_t mic;
986
987 /** maximum data transfer size */
988 uint8_t mdts;
989
990 /** Controller ID */
991 uint16_t ctrlr_id;
992
993 /** Version */
994 uint32_t ver;
995
996 /** RTD3 Resume Latency */
997 uint32_t rtd3r;
998
999 /** RTD3 Enter Latency */
1000 uint32_t rtd3e;
1001
1002 /** Optional Asynchronous Events Supported */
1003 uint32_t oaes; /* bitfield really */
1004
1005 /** Controller Attributes */
1006 uint32_t ctratt; /* bitfield really */
1007
1008 /** Read Recovery Levels Supported */
1009 uint16_t rrls;
1010
1011 uint8_t reserved1[9];
1012
1013 /** Controller Type */
1014 uint8_t cntrltype;
1015
1016 /** FRU Globally Unique Identifier */
1017 uint8_t fguid[16];
1018
1019 /** Command Retry Delay Time 1 */
1020 uint16_t crdt1;
1021
1022 /** Command Retry Delay Time 2 */
1023 uint16_t crdt2;
1024
1025 /** Command Retry Delay Time 3 */
1026 uint16_t crdt3;
1027
1028 uint8_t reserved2[122];
1029
1030 /* bytes 256-511: admin command set attributes */
1031
1032 /** optional admin command support */
1033 uint16_t oacs;
1034
1035 /** abort command limit */
1036 uint8_t acl;
1037
1038 /** asynchronous event request limit */
1039 uint8_t aerl;
1040
1041 /** firmware updates */
1042 uint8_t frmw;
1043
1044 /** log page attributes */
1045 uint8_t lpa;
1046
1047 /** error log page entries */
1048 uint8_t elpe;
1049
1050 /** number of power states supported */
1051 uint8_t npss;
1052
1053 /** admin vendor specific command configuration */
1054 uint8_t avscc;
1055
1056 /** Autonomous Power State Transition Attributes */
1057 uint8_t apsta;
1058
1059 /** Warning Composite Temperature Threshold */
1060 uint16_t wctemp;
1061
1062 /** Critical Composite Temperature Threshold */
1063 uint16_t cctemp;
1064
1065 /** Maximum Time for Firmware Activation */
1066 uint16_t mtfa;
1067
1068 /** Host Memory Buffer Preferred Size */
1069 uint32_t hmpre;
1070
1071 /** Host Memory Buffer Minimum Size */
1072 uint32_t hmmin;
1073
1074 /** Name space capabilities */
1075 struct {
1076 /* if nsmgmt, report tnvmcap and unvmcap */
1077 uint8_t tnvmcap[16];
1078 uint8_t unvmcap[16];
1079 } __packed untncap;
1080
1081 /** Replay Protected Memory Block Support */
1082 uint32_t rpmbs; /* Really a bitfield */
1083
1084 /** Extended Device Self-test Time */
1085 uint16_t edstt;
1086
1087 /** Device Self-test Options */
1088 uint8_t dsto; /* Really a bitfield */
1089
1090 /** Firmware Update Granularity */
1091 uint8_t fwug;
1092
1093 /** Keep Alive Support */
1094 uint16_t kas;
1095
1096 /** Host Controlled Thermal Management Attributes */
1097 uint16_t hctma; /* Really a bitfield */
1098
1099 /** Minimum Thermal Management Temperature */
1100 uint16_t mntmt;
1101
1102 /** Maximum Thermal Management Temperature */
1103 uint16_t mxtmt;
1104
1105 /** Sanitize Capabilities */
1106 uint32_t sanicap; /* Really a bitfield */
1107
1108 /** Host Memory Buffer Minimum Descriptor Entry Size */
1109 uint32_t hmminds;
1110
1111 /** Host Memory Maximum Descriptors Entries */
1112 uint16_t hmmaxd;
1113
1114 /** NVM Set Identifier Maximum */
1115 uint16_t nsetidmax;
1116
1117 /** Endurance Group Identifier Maximum */
1118 uint16_t endgidmax;
1119
1120 /** ANA Transition Time */
1121 uint8_t anatt;
1122
1123 /** Asymmetric Namespace Access Capabilities */
1124 uint8_t anacap;
1125
1126 /** ANA Group Identifier Maximum */
1127 uint32_t anagrpmax;
1128
1129 /** Number of ANA Group Identifiers */
1130 uint32_t nanagrpid;
1131
1132 /** Persistent Event Log Size */
1133 uint32_t pels;
1134
1135 uint8_t reserved3[156];
1136 /* bytes 512-703: nvm command set attributes */
1137
1138 /** submission queue entry size */
1139 uint8_t sqes;
1140
1141 /** completion queue entry size */
1142 uint8_t cqes;
1143
1144 /** Maximum Outstanding Commands */
1145 uint16_t maxcmd;
1146
1147 /** number of namespaces */
1148 uint32_t nn;
1149
1150 /** optional nvm command support */
1151 uint16_t oncs;
1152
1153 /** fused operation support */
1154 uint16_t fuses;
1155
1156 /** format nvm attributes */
1157 uint8_t fna;
1158
1159 /** volatile write cache */
1160 uint8_t vwc;
1161
1162 /** Atomic Write Unit Normal */
1163 uint16_t awun;
1164
1165 /** Atomic Write Unit Power Fail */
1166 uint16_t awupf;
1167
1168 /** NVM Vendor Specific Command Configuration */
1169 uint8_t nvscc;
1170
1171 /** Namespace Write Protection Capabilities */
1172 uint8_t nwpc;
1173
1174 /** Atomic Compare & Write Unit */
1175 uint16_t acwu;
1176 uint16_t reserved6;
1177
1178 /** SGL Support */
1179 uint32_t sgls;
1180
1181 /** Maximum Number of Allowed Namespaces */
1182 uint32_t mnan;
1183
1184 /* bytes 540-767: Reserved */
1185 uint8_t reserved7[224];
1186
1187 /** NVM Subsystem NVMe Qualified Name */
1188 uint8_t subnqn[256];
1189
1190 /* bytes 1024-1791: Reserved */
1191 uint8_t reserved8[768];
1192
1193 /* bytes 1792-2047: NVMe over Fabrics specification */
1194 uint8_t reserved9[256];
1195
1196 /* bytes 2048-3071: power state descriptors */
1197 struct nvme_power_state power_state[32];
1198
1199 /* bytes 3072-4095: vendor specific */
1200 uint8_t vs[1024];
1201 } __packed __aligned(4);
1202
1203 _Static_assert(sizeof(struct nvme_controller_data) == 4096, "bad size for nvme_controller_data");
1204
1205 struct nvme_namespace_data {
1206 /** namespace size */
1207 uint64_t nsze;
1208
1209 /** namespace capacity */
1210 uint64_t ncap;
1211
1212 /** namespace utilization */
1213 uint64_t nuse;
1214
1215 /** namespace features */
1216 uint8_t nsfeat;
1217
1218 /** number of lba formats */
1219 uint8_t nlbaf;
1220
1221 /** formatted lba size */
1222 uint8_t flbas;
1223
1224 /** metadata capabilities */
1225 uint8_t mc;
1226
1227 /** end-to-end data protection capabilities */
1228 uint8_t dpc;
1229
1230 /** end-to-end data protection type settings */
1231 uint8_t dps;
1232
1233 /** Namespace Multi-path I/O and Namespace Sharing Capabilities */
1234 uint8_t nmic;
1235
1236 /** Reservation Capabilities */
1237 uint8_t rescap;
1238
1239 /** Format Progress Indicator */
1240 uint8_t fpi;
1241
1242 /** Deallocate Logical Block Features */
1243 uint8_t dlfeat;
1244
1245 /** Namespace Atomic Write Unit Normal */
1246 uint16_t nawun;
1247
1248 /** Namespace Atomic Write Unit Power Fail */
1249 uint16_t nawupf;
1250
1251 /** Namespace Atomic Compare & Write Unit */
1252 uint16_t nacwu;
1253
1254 /** Namespace Atomic Boundary Size Normal */
1255 uint16_t nabsn;
1256
1257 /** Namespace Atomic Boundary Offset */
1258 uint16_t nabo;
1259
1260 /** Namespace Atomic Boundary Size Power Fail */
1261 uint16_t nabspf;
1262
1263 /** Namespace Optimal IO Boundary */
1264 uint16_t noiob;
1265
1266 /** NVM Capacity */
1267 uint8_t nvmcap[16];
1268
1269 /** Namespace Preferred Write Granularity */
1270 uint16_t npwg;
1271
1272 /** Namespace Preferred Write Alignment */
1273 uint16_t npwa;
1274
1275 /** Namespace Preferred Deallocate Granularity */
1276 uint16_t npdg;
1277
1278 /** Namespace Preferred Deallocate Alignment */
1279 uint16_t npda;
1280
1281 /** Namespace Optimal Write Size */
1282 uint16_t nows;
1283
1284 /* bytes 74-91: Reserved */
1285 uint8_t reserved5[18];
1286
1287 /** ANA Group Identifier */
1288 uint32_t anagrpid;
1289
1290 /* bytes 96-98: Reserved */
1291 uint8_t reserved6[3];
1292
1293 /** Namespace Attributes */
1294 uint8_t nsattr;
1295
1296 /** NVM Set Identifier */
1297 uint16_t nvmsetid;
1298
1299 /** Endurance Group Identifier */
1300 uint16_t endgid;
1301
1302 /** Namespace Globally Unique Identifier */
1303 uint8_t nguid[16];
1304
1305 /** IEEE Extended Unique Identifier */
1306 uint8_t eui64[8];
1307
1308 /** lba format support */
1309 uint32_t lbaf[16];
1310
1311 uint8_t reserved7[192];
1312
1313 uint8_t vendor_specific[3712];
1314 } __packed __aligned(4);
1315
1316 _Static_assert(sizeof(struct nvme_namespace_data) == 4096, "bad size for nvme_namepsace_data");
1317
1318 enum nvme_log_page {
1319 /* 0x00 - reserved */
1320 NVME_LOG_ERROR = 0x01,
1321 NVME_LOG_HEALTH_INFORMATION = 0x02,
1322 NVME_LOG_FIRMWARE_SLOT = 0x03,
1323 NVME_LOG_CHANGED_NAMESPACE = 0x04,
1324 NVME_LOG_COMMAND_EFFECT = 0x05,
1325 NVME_LOG_DEVICE_SELF_TEST = 0x06,
1326 NVME_LOG_TELEMETRY_HOST_INITIATED = 0x07,
1327 NVME_LOG_TELEMETRY_CONTROLLER_INITIATED = 0x08,
1328 NVME_LOG_ENDURANCE_GROUP_INFORMATION = 0x09,
1329 NVME_LOG_PREDICTABLE_LATENCY_PER_NVM_SET = 0x0a,
1330 NVME_LOG_PREDICTABLE_LATENCY_EVENT_AGGREGATE = 0x0b,
1331 NVME_LOG_ASYMMETRIC_NAMESPACE_ACCESS = 0x0c,
1332 NVME_LOG_PERSISTENT_EVENT_LOG = 0x0d,
1333 NVME_LOG_LBA_STATUS_INFORMATION = 0x0e,
1334 NVME_LOG_ENDURANCE_GROUP_EVENT_AGGREGATE = 0x0f,
1335 /* 0x06-0x7F - reserved */
1336 /* 0x80-0xBF - I/O command set specific */
1337 NVME_LOG_RES_NOTIFICATION = 0x80,
1338 NVME_LOG_SANITIZE_STATUS = 0x81,
1339 /* 0x82-0xBF - reserved */
1340 /* 0xC0-0xFF - vendor specific */
1341
1342 /*
1343 * The following are Intel Specific log pages, but they seem
1344 * to be widely implemented.
1345 */
1346 INTEL_LOG_READ_LAT_LOG = 0xc1,
1347 INTEL_LOG_WRITE_LAT_LOG = 0xc2,
1348 INTEL_LOG_TEMP_STATS = 0xc5,
1349 INTEL_LOG_ADD_SMART = 0xca,
1350 INTEL_LOG_DRIVE_MKT_NAME = 0xdd,
1351
1352 /*
1353 * HGST log page, with lots ofs sub pages.
1354 */
1355 HGST_INFO_LOG = 0xc1,
1356 };
1357
1358 struct nvme_error_information_entry {
1359 uint64_t error_count;
1360 uint16_t sqid;
1361 uint16_t cid;
1362 uint16_t status;
1363 uint16_t error_location;
1364 uint64_t lba;
1365 uint32_t nsid;
1366 uint8_t vendor_specific;
1367 uint8_t trtype;
1368 uint16_t reserved30;
1369 uint64_t csi;
1370 uint16_t ttsi;
1371 uint8_t reserved[22];
1372 } __packed __aligned(4);
1373
1374 _Static_assert(sizeof(struct nvme_error_information_entry) == 64, "bad size for nvme_error_information_entry");
1375
1376 struct nvme_health_information_page {
1377 uint8_t critical_warning;
1378 uint16_t temperature;
1379 uint8_t available_spare;
1380 uint8_t available_spare_threshold;
1381 uint8_t percentage_used;
1382
1383 uint8_t reserved[26];
1384
1385 /*
1386 * Note that the following are 128-bit values, but are
1387 * defined as an array of 2 64-bit values.
1388 */
1389 /* Data Units Read is always in 512-byte units. */
1390 uint64_t data_units_read[2];
1391 /* Data Units Written is always in 512-byte units. */
1392 uint64_t data_units_written[2];
1393 /* For NVM command set, this includes Compare commands. */
1394 uint64_t host_read_commands[2];
1395 uint64_t host_write_commands[2];
1396 /* Controller Busy Time is reported in minutes. */
1397 uint64_t controller_busy_time[2];
1398 uint64_t power_cycles[2];
1399 uint64_t power_on_hours[2];
1400 uint64_t unsafe_shutdowns[2];
1401 uint64_t media_errors[2];
1402 uint64_t num_error_info_log_entries[2];
1403 uint32_t warning_temp_time;
1404 uint32_t error_temp_time;
1405 uint16_t temp_sensor[8];
1406 /* Thermal Management Temperature 1 Transition Count */
1407 uint32_t tmt1tc;
1408 /* Thermal Management Temperature 2 Transition Count */
1409 uint32_t tmt2tc;
1410 /* Total Time For Thermal Management Temperature 1 */
1411 uint32_t ttftmt1;
1412 /* Total Time For Thermal Management Temperature 2 */
1413 uint32_t ttftmt2;
1414
1415 uint8_t reserved2[280];
1416 } __packed __aligned(4);
1417
1418 _Static_assert(sizeof(struct nvme_health_information_page) == 512, "bad size for nvme_health_information_page");
1419
1420 struct nvme_firmware_page {
1421 uint8_t afi;
1422 uint8_t reserved[7];
1423 /* revisions for 7 slots */
1424 uint8_t revision[7][NVME_FIRMWARE_REVISION_LENGTH];
1425 uint8_t reserved2[448];
1426 } __packed __aligned(4);
1427
1428 _Static_assert(sizeof(struct nvme_firmware_page) == 512, "bad size for nvme_firmware_page");
1429
1430 struct nvme_ns_list {
1431 uint32_t ns[1024];
1432 } __packed __aligned(4);
1433
1434 _Static_assert(sizeof(struct nvme_ns_list) == 4096, "bad size for nvme_ns_list");
1435
1436 struct nvme_command_effects_page {
1437 uint32_t acs[256];
1438 uint32_t iocs[256];
1439 uint8_t reserved[2048];
1440 } __packed __aligned(4);
1441
1442 _Static_assert(sizeof(struct nvme_command_effects_page) == 4096,
1443 "bad size for nvme_command_effects_page");
1444
1445 struct nvme_device_self_test_page {
1446 uint8_t curr_operation;
1447 uint8_t curr_compl;
1448 uint8_t rsvd2[2];
1449 struct {
1450 uint8_t status;
1451 uint8_t segment_num;
1452 uint8_t valid_diag_info;
1453 uint8_t rsvd3;
1454 uint64_t poh;
1455 uint32_t nsid;
1456 /* Define as an array to simplify alignment issues */
1457 uint8_t failing_lba[8];
1458 uint8_t status_code_type;
1459 uint8_t status_code;
1460 uint8_t vendor_specific[2];
1461 } __packed result[20];
1462 } __packed __aligned(4);
1463
1464 _Static_assert(sizeof(struct nvme_device_self_test_page) == 564,
1465 "bad size for nvme_device_self_test_page");
1466
1467 struct nvme_res_notification_page {
1468 uint64_t log_page_count;
1469 uint8_t log_page_type;
1470 uint8_t available_log_pages;
1471 uint8_t reserved2;
1472 uint32_t nsid;
1473 uint8_t reserved[48];
1474 } __packed __aligned(4);
1475
1476 _Static_assert(sizeof(struct nvme_res_notification_page) == 64,
1477 "bad size for nvme_res_notification_page");
1478
1479 struct nvme_sanitize_status_page {
1480 uint16_t sprog;
1481 uint16_t sstat;
1482 uint32_t scdw10;
1483 uint32_t etfo;
1484 uint32_t etfbe;
1485 uint32_t etfce;
1486 uint32_t etfownd;
1487 uint32_t etfbewnd;
1488 uint32_t etfcewnd;
1489 uint8_t reserved[480];
1490 } __packed __aligned(4);
1491
1492 _Static_assert(sizeof(struct nvme_sanitize_status_page) == 512,
1493 "bad size for nvme_sanitize_status_page");
1494
1495 struct intel_log_temp_stats {
1496 uint64_t current;
1497 uint64_t overtemp_flag_last;
1498 uint64_t overtemp_flag_life;
1499 uint64_t max_temp;
1500 uint64_t min_temp;
1501 uint64_t _rsvd[5];
1502 uint64_t max_oper_temp;
1503 uint64_t min_oper_temp;
1504 uint64_t est_offset;
1505 } __packed __aligned(4);
1506
1507 _Static_assert(sizeof(struct intel_log_temp_stats) == 13 * 8, "bad size for intel_log_temp_stats");
1508
1509 struct nvme_resv_reg_ctrlr {
1510 uint16_t ctrlr_id; /* Controller ID */
1511 uint8_t rcsts; /* Reservation Status */
1512 uint8_t reserved3[5];
1513 uint64_t hostid; /* Host Identifier */
1514 uint64_t rkey; /* Reservation Key */
1515 } __packed __aligned(4);
1516
1517 _Static_assert(sizeof(struct nvme_resv_reg_ctrlr) == 24, "bad size for nvme_resv_reg_ctrlr");
1518
1519 struct nvme_resv_reg_ctrlr_ext {
1520 uint16_t ctrlr_id; /* Controller ID */
1521 uint8_t rcsts; /* Reservation Status */
1522 uint8_t reserved3[5];
1523 uint64_t rkey; /* Reservation Key */
1524 uint64_t hostid[2]; /* Host Identifier */
1525 uint8_t reserved32[32];
1526 } __packed __aligned(4);
1527
1528 _Static_assert(sizeof(struct nvme_resv_reg_ctrlr_ext) == 64, "bad size for nvme_resv_reg_ctrlr_ext");
1529
1530 struct nvme_resv_status {
1531 uint32_t gen; /* Generation */
1532 uint8_t rtype; /* Reservation Type */
1533 uint8_t regctl[2]; /* Number of Registered Controllers */
1534 uint8_t reserved7[2];
1535 uint8_t ptpls; /* Persist Through Power Loss State */
1536 uint8_t reserved10[14];
1537 struct nvme_resv_reg_ctrlr ctrlr[0];
1538 } __packed __aligned(4);
1539
1540 _Static_assert(sizeof(struct nvme_resv_status) == 24, "bad size for nvme_resv_status");
1541
1542 struct nvme_resv_status_ext {
1543 uint32_t gen; /* Generation */
1544 uint8_t rtype; /* Reservation Type */
1545 uint8_t regctl[2]; /* Number of Registered Controllers */
1546 uint8_t reserved7[2];
1547 uint8_t ptpls; /* Persist Through Power Loss State */
1548 uint8_t reserved10[14];
1549 uint8_t reserved24[40];
1550 struct nvme_resv_reg_ctrlr_ext ctrlr[0];
1551 } __packed __aligned(4);
1552
1553 _Static_assert(sizeof(struct nvme_resv_status_ext) == 64, "bad size for nvme_resv_status_ext");
1554
1555 #define NVME_TEST_MAX_THREADS 128
1556
1557 struct nvme_io_test {
1558 enum nvme_nvm_opcode opc;
1559 uint32_t size;
1560 uint32_t time; /* in seconds */
1561 uint32_t num_threads;
1562 uint32_t flags;
1563 uint64_t io_completed[NVME_TEST_MAX_THREADS];
1564 };
1565
1566 enum nvme_io_test_flags {
1567 /*
1568 * Specifies whether dev_refthread/dev_relthread should be
1569 * called during NVME_BIO_TEST. Ignored for other test
1570 * types.
1571 */
1572 NVME_TEST_FLAG_REFTHREAD = 0x1,
1573 };
1574
1575 struct nvme_pt_command {
1576 /*
1577 * cmd is used to specify a passthrough command to a controller or
1578 * namespace.
1579 *
1580 * The following fields from cmd may be specified by the caller:
1581 * * opc (opcode)
1582 * * nsid (namespace id) - for admin commands only
1583 * * cdw10-cdw15
1584 *
1585 * Remaining fields must be set to 0 by the caller.
1586 */
1587 struct nvme_command cmd;
1588
1589 /*
1590 * cpl returns completion status for the passthrough command
1591 * specified by cmd.
1592 *
1593 * The following fields will be filled out by the driver, for
1594 * consumption by the caller:
1595 * * cdw0
1596 * * status (except for phase)
1597 *
1598 * Remaining fields will be set to 0 by the driver.
1599 */
1600 struct nvme_completion cpl;
1601
1602 /* buf is the data buffer associated with this passthrough command. */
1603 void * buf;
1604
1605 /*
1606 * len is the length of the data buffer associated with this
1607 * passthrough command.
1608 */
1609 uint32_t len;
1610
1611 /*
1612 * is_read = 1 if the passthrough command will read data into the
1613 * supplied buffer from the controller.
1614 *
1615 * is_read = 0 if the passthrough command will write data from the
1616 * supplied buffer to the controller.
1617 */
1618 uint32_t is_read;
1619
1620 /*
1621 * driver_lock is used by the driver only. It must be set to 0
1622 * by the caller.
1623 */
1624 struct mtx * driver_lock;
1625 };
1626
1627 struct nvme_get_nsid {
1628 char cdev[SPECNAMELEN + 1];
1629 uint32_t nsid;
1630 };
1631
1632 struct nvme_hmb_desc {
1633 uint64_t addr;
1634 uint32_t size;
1635 uint32_t reserved;
1636 };
1637
1638 #define nvme_completion_is_error(cpl) \
1639 (NVME_STATUS_GET_SC((cpl)->status) != 0 || NVME_STATUS_GET_SCT((cpl)->status) != 0)
1640
1641 void nvme_strvis(uint8_t *dst, const uint8_t *src, int dstlen, int srclen);
1642
1643 #ifdef _KERNEL
1644
1645 struct bio;
1646 struct thread;
1647
1648 struct nvme_namespace;
1649 struct nvme_controller;
1650 struct nvme_consumer;
1651
1652 typedef void (*nvme_cb_fn_t)(void *, const struct nvme_completion *);
1653
1654 typedef void *(*nvme_cons_ns_fn_t)(struct nvme_namespace *, void *);
1655 typedef void *(*nvme_cons_ctrlr_fn_t)(struct nvme_controller *);
1656 typedef void (*nvme_cons_async_fn_t)(void *, const struct nvme_completion *,
1657 uint32_t, void *, uint32_t);
1658 typedef void (*nvme_cons_fail_fn_t)(void *);
1659
1660 enum nvme_namespace_flags {
1661 NVME_NS_DEALLOCATE_SUPPORTED = 0x1,
1662 NVME_NS_FLUSH_SUPPORTED = 0x2,
1663 };
1664
1665 int nvme_ctrlr_passthrough_cmd(struct nvme_controller *ctrlr,
1666 struct nvme_pt_command *pt,
1667 uint32_t nsid, int is_user_buffer,
1668 int is_admin_cmd);
1669
1670 /* Admin functions */
1671 void nvme_ctrlr_cmd_set_feature(struct nvme_controller *ctrlr,
1672 uint8_t feature, uint32_t cdw11,
1673 uint32_t cdw12, uint32_t cdw13,
1674 uint32_t cdw14, uint32_t cdw15,
1675 void *payload, uint32_t payload_size,
1676 nvme_cb_fn_t cb_fn, void *cb_arg);
1677 void nvme_ctrlr_cmd_get_feature(struct nvme_controller *ctrlr,
1678 uint8_t feature, uint32_t cdw11,
1679 void *payload, uint32_t payload_size,
1680 nvme_cb_fn_t cb_fn, void *cb_arg);
1681 void nvme_ctrlr_cmd_get_log_page(struct nvme_controller *ctrlr,
1682 uint8_t log_page, uint32_t nsid,
1683 void *payload, uint32_t payload_size,
1684 nvme_cb_fn_t cb_fn, void *cb_arg);
1685
1686 /* NVM I/O functions */
1687 int nvme_ns_cmd_write(struct nvme_namespace *ns, void *payload,
1688 uint64_t lba, uint32_t lba_count, nvme_cb_fn_t cb_fn,
1689 void *cb_arg);
1690 int nvme_ns_cmd_write_bio(struct nvme_namespace *ns, struct bio *bp,
1691 nvme_cb_fn_t cb_fn, void *cb_arg);
1692 int nvme_ns_cmd_read(struct nvme_namespace *ns, void *payload,
1693 uint64_t lba, uint32_t lba_count, nvme_cb_fn_t cb_fn,
1694 void *cb_arg);
1695 int nvme_ns_cmd_read_bio(struct nvme_namespace *ns, struct bio *bp,
1696 nvme_cb_fn_t cb_fn, void *cb_arg);
1697 int nvme_ns_cmd_deallocate(struct nvme_namespace *ns, void *payload,
1698 uint8_t num_ranges, nvme_cb_fn_t cb_fn,
1699 void *cb_arg);
1700 int nvme_ns_cmd_flush(struct nvme_namespace *ns, nvme_cb_fn_t cb_fn,
1701 void *cb_arg);
1702 int nvme_ns_dump(struct nvme_namespace *ns, void *virt, off_t offset,
1703 size_t len);
1704
1705 /* Registration functions */
1706 struct nvme_consumer * nvme_register_consumer(nvme_cons_ns_fn_t ns_fn,
1707 nvme_cons_ctrlr_fn_t ctrlr_fn,
1708 nvme_cons_async_fn_t async_fn,
1709 nvme_cons_fail_fn_t fail_fn);
1710 void nvme_unregister_consumer(struct nvme_consumer *consumer);
1711
1712 /* Controller helper functions */
1713 device_t nvme_ctrlr_get_device(struct nvme_controller *ctrlr);
1714 const struct nvme_controller_data *
1715 nvme_ctrlr_get_data(struct nvme_controller *ctrlr);
1716 static inline bool
nvme_ctrlr_has_dataset_mgmt(const struct nvme_controller_data * cd)1717 nvme_ctrlr_has_dataset_mgmt(const struct nvme_controller_data *cd)
1718 {
1719 /* Assumes cd was byte swapped by nvme_controller_data_swapbytes() */
1720 return ((cd->oncs >> NVME_CTRLR_DATA_ONCS_DSM_SHIFT) &
1721 NVME_CTRLR_DATA_ONCS_DSM_MASK);
1722 }
1723
1724 /* Namespace helper functions */
1725 uint32_t nvme_ns_get_max_io_xfer_size(struct nvme_namespace *ns);
1726 uint32_t nvme_ns_get_sector_size(struct nvme_namespace *ns);
1727 uint64_t nvme_ns_get_num_sectors(struct nvme_namespace *ns);
1728 uint64_t nvme_ns_get_size(struct nvme_namespace *ns);
1729 uint32_t nvme_ns_get_flags(struct nvme_namespace *ns);
1730 const char * nvme_ns_get_serial_number(struct nvme_namespace *ns);
1731 const char * nvme_ns_get_model_number(struct nvme_namespace *ns);
1732 const struct nvme_namespace_data *
1733 nvme_ns_get_data(struct nvme_namespace *ns);
1734 uint32_t nvme_ns_get_stripesize(struct nvme_namespace *ns);
1735
1736 int nvme_ns_bio_process(struct nvme_namespace *ns, struct bio *bp,
1737 nvme_cb_fn_t cb_fn);
1738 int nvme_ns_ioctl_process(struct nvme_namespace *ns, u_long cmd,
1739 caddr_t arg, int flag, struct thread *td);
1740
1741 /*
1742 * Command building helper functions -- shared with CAM
1743 * These functions assume allocator zeros out cmd structure
1744 * CAM's xpt_get_ccb and the request allocator for nvme both
1745 * do zero'd allocations.
1746 */
1747 static inline
nvme_ns_flush_cmd(struct nvme_command * cmd,uint32_t nsid)1748 void nvme_ns_flush_cmd(struct nvme_command *cmd, uint32_t nsid)
1749 {
1750
1751 cmd->opc = NVME_OPC_FLUSH;
1752 cmd->nsid = htole32(nsid);
1753 }
1754
1755 static inline
nvme_ns_rw_cmd(struct nvme_command * cmd,uint32_t rwcmd,uint32_t nsid,uint64_t lba,uint32_t count)1756 void nvme_ns_rw_cmd(struct nvme_command *cmd, uint32_t rwcmd, uint32_t nsid,
1757 uint64_t lba, uint32_t count)
1758 {
1759 cmd->opc = rwcmd;
1760 cmd->nsid = htole32(nsid);
1761 cmd->cdw10 = htole32(lba & 0xffffffffu);
1762 cmd->cdw11 = htole32(lba >> 32);
1763 cmd->cdw12 = htole32(count-1);
1764 }
1765
1766 static inline
nvme_ns_write_cmd(struct nvme_command * cmd,uint32_t nsid,uint64_t lba,uint32_t count)1767 void nvme_ns_write_cmd(struct nvme_command *cmd, uint32_t nsid,
1768 uint64_t lba, uint32_t count)
1769 {
1770 nvme_ns_rw_cmd(cmd, NVME_OPC_WRITE, nsid, lba, count);
1771 }
1772
1773 static inline
nvme_ns_read_cmd(struct nvme_command * cmd,uint32_t nsid,uint64_t lba,uint32_t count)1774 void nvme_ns_read_cmd(struct nvme_command *cmd, uint32_t nsid,
1775 uint64_t lba, uint32_t count)
1776 {
1777 nvme_ns_rw_cmd(cmd, NVME_OPC_READ, nsid, lba, count);
1778 }
1779
1780 static inline
nvme_ns_trim_cmd(struct nvme_command * cmd,uint32_t nsid,uint32_t num_ranges)1781 void nvme_ns_trim_cmd(struct nvme_command *cmd, uint32_t nsid,
1782 uint32_t num_ranges)
1783 {
1784 cmd->opc = NVME_OPC_DATASET_MANAGEMENT;
1785 cmd->nsid = htole32(nsid);
1786 cmd->cdw10 = htole32(num_ranges - 1);
1787 cmd->cdw11 = htole32(NVME_DSM_ATTR_DEALLOCATE);
1788 }
1789
1790 extern int nvme_use_nvd;
1791
1792 #endif /* _KERNEL */
1793
1794 /* Endianess conversion functions for NVMe structs */
1795 static inline
nvme_completion_swapbytes(struct nvme_completion * s __unused)1796 void nvme_completion_swapbytes(struct nvme_completion *s __unused)
1797 {
1798 #if _BYTE_ORDER != _LITTLE_ENDIAN
1799
1800 s->cdw0 = le32toh(s->cdw0);
1801 /* omit rsvd1 */
1802 s->sqhd = le16toh(s->sqhd);
1803 s->sqid = le16toh(s->sqid);
1804 /* omit cid */
1805 s->status = le16toh(s->status);
1806 #endif
1807 }
1808
1809 static inline
nvme_power_state_swapbytes(struct nvme_power_state * s __unused)1810 void nvme_power_state_swapbytes(struct nvme_power_state *s __unused)
1811 {
1812 #if _BYTE_ORDER != _LITTLE_ENDIAN
1813
1814 s->mp = le16toh(s->mp);
1815 s->enlat = le32toh(s->enlat);
1816 s->exlat = le32toh(s->exlat);
1817 s->idlp = le16toh(s->idlp);
1818 s->actp = le16toh(s->actp);
1819 #endif
1820 }
1821
1822 static inline
nvme_controller_data_swapbytes(struct nvme_controller_data * s __unused)1823 void nvme_controller_data_swapbytes(struct nvme_controller_data *s __unused)
1824 {
1825 #if _BYTE_ORDER != _LITTLE_ENDIAN
1826 int i;
1827
1828 s->vid = le16toh(s->vid);
1829 s->ssvid = le16toh(s->ssvid);
1830 s->ctrlr_id = le16toh(s->ctrlr_id);
1831 s->ver = le32toh(s->ver);
1832 s->rtd3r = le32toh(s->rtd3r);
1833 s->rtd3e = le32toh(s->rtd3e);
1834 s->oaes = le32toh(s->oaes);
1835 s->ctratt = le32toh(s->ctratt);
1836 s->rrls = le16toh(s->rrls);
1837 s->crdt1 = le16toh(s->crdt1);
1838 s->crdt2 = le16toh(s->crdt2);
1839 s->crdt3 = le16toh(s->crdt3);
1840 s->oacs = le16toh(s->oacs);
1841 s->wctemp = le16toh(s->wctemp);
1842 s->cctemp = le16toh(s->cctemp);
1843 s->mtfa = le16toh(s->mtfa);
1844 s->hmpre = le32toh(s->hmpre);
1845 s->hmmin = le32toh(s->hmmin);
1846 s->rpmbs = le32toh(s->rpmbs);
1847 s->edstt = le16toh(s->edstt);
1848 s->kas = le16toh(s->kas);
1849 s->hctma = le16toh(s->hctma);
1850 s->mntmt = le16toh(s->mntmt);
1851 s->mxtmt = le16toh(s->mxtmt);
1852 s->sanicap = le32toh(s->sanicap);
1853 s->hmminds = le32toh(s->hmminds);
1854 s->hmmaxd = le16toh(s->hmmaxd);
1855 s->nsetidmax = le16toh(s->nsetidmax);
1856 s->endgidmax = le16toh(s->endgidmax);
1857 s->anagrpmax = le32toh(s->anagrpmax);
1858 s->nanagrpid = le32toh(s->nanagrpid);
1859 s->pels = le32toh(s->pels);
1860 s->maxcmd = le16toh(s->maxcmd);
1861 s->nn = le32toh(s->nn);
1862 s->oncs = le16toh(s->oncs);
1863 s->fuses = le16toh(s->fuses);
1864 s->awun = le16toh(s->awun);
1865 s->awupf = le16toh(s->awupf);
1866 s->acwu = le16toh(s->acwu);
1867 s->sgls = le32toh(s->sgls);
1868 s->mnan = le32toh(s->mnan);
1869 for (i = 0; i < 32; i++)
1870 nvme_power_state_swapbytes(&s->power_state[i]);
1871 #endif
1872 }
1873
1874 static inline
nvme_namespace_data_swapbytes(struct nvme_namespace_data * s __unused)1875 void nvme_namespace_data_swapbytes(struct nvme_namespace_data *s __unused)
1876 {
1877 #if _BYTE_ORDER != _LITTLE_ENDIAN
1878 int i;
1879
1880 s->nsze = le64toh(s->nsze);
1881 s->ncap = le64toh(s->ncap);
1882 s->nuse = le64toh(s->nuse);
1883 s->nawun = le16toh(s->nawun);
1884 s->nawupf = le16toh(s->nawupf);
1885 s->nacwu = le16toh(s->nacwu);
1886 s->nabsn = le16toh(s->nabsn);
1887 s->nabo = le16toh(s->nabo);
1888 s->nabspf = le16toh(s->nabspf);
1889 s->noiob = le16toh(s->noiob);
1890 s->npwg = le16toh(s->npwg);
1891 s->npwa = le16toh(s->npwa);
1892 s->npdg = le16toh(s->npdg);
1893 s->npda = le16toh(s->npda);
1894 s->nows = le16toh(s->nows);
1895 s->anagrpid = le32toh(s->anagrpid);
1896 s->nvmsetid = le16toh(s->nvmsetid);
1897 s->endgid = le16toh(s->endgid);
1898 for (i = 0; i < 16; i++)
1899 s->lbaf[i] = le32toh(s->lbaf[i]);
1900 #endif
1901 }
1902
1903 static inline
nvme_error_information_entry_swapbytes(struct nvme_error_information_entry * s __unused)1904 void nvme_error_information_entry_swapbytes(
1905 struct nvme_error_information_entry *s __unused)
1906 {
1907 #if _BYTE_ORDER != _LITTLE_ENDIAN
1908
1909 s->error_count = le64toh(s->error_count);
1910 s->sqid = le16toh(s->sqid);
1911 s->cid = le16toh(s->cid);
1912 s->status = le16toh(s->status);
1913 s->error_location = le16toh(s->error_location);
1914 s->lba = le64toh(s->lba);
1915 s->nsid = le32toh(s->nsid);
1916 s->csi = le64toh(s->csi);
1917 s->ttsi = le16toh(s->ttsi);
1918 #endif
1919 }
1920
1921 static inline
nvme_le128toh(void * p __unused)1922 void nvme_le128toh(void *p __unused)
1923 {
1924 #if _BYTE_ORDER != _LITTLE_ENDIAN
1925 /* Swap 16 bytes in place */
1926 char *tmp = (char*)p;
1927 char b;
1928 int i;
1929 for (i = 0; i < 8; i++) {
1930 b = tmp[i];
1931 tmp[i] = tmp[15-i];
1932 tmp[15-i] = b;
1933 }
1934 #endif
1935 }
1936
1937 static inline
nvme_health_information_page_swapbytes(struct nvme_health_information_page * s __unused)1938 void nvme_health_information_page_swapbytes(
1939 struct nvme_health_information_page *s __unused)
1940 {
1941 #if _BYTE_ORDER != _LITTLE_ENDIAN
1942 int i;
1943
1944 s->temperature = le16toh(s->temperature);
1945 nvme_le128toh((void *)s->data_units_read);
1946 nvme_le128toh((void *)s->data_units_written);
1947 nvme_le128toh((void *)s->host_read_commands);
1948 nvme_le128toh((void *)s->host_write_commands);
1949 nvme_le128toh((void *)s->controller_busy_time);
1950 nvme_le128toh((void *)s->power_cycles);
1951 nvme_le128toh((void *)s->power_on_hours);
1952 nvme_le128toh((void *)s->unsafe_shutdowns);
1953 nvme_le128toh((void *)s->media_errors);
1954 nvme_le128toh((void *)s->num_error_info_log_entries);
1955 s->warning_temp_time = le32toh(s->warning_temp_time);
1956 s->error_temp_time = le32toh(s->error_temp_time);
1957 for (i = 0; i < 8; i++)
1958 s->temp_sensor[i] = le16toh(s->temp_sensor[i]);
1959 s->tmt1tc = le32toh(s->tmt1tc);
1960 s->tmt2tc = le32toh(s->tmt2tc);
1961 s->ttftmt1 = le32toh(s->ttftmt1);
1962 s->ttftmt2 = le32toh(s->ttftmt2);
1963 #endif
1964 }
1965
1966 static inline
nvme_ns_list_swapbytes(struct nvme_ns_list * s __unused)1967 void nvme_ns_list_swapbytes(struct nvme_ns_list *s __unused)
1968 {
1969 #if _BYTE_ORDER != _LITTLE_ENDIAN
1970 int i;
1971
1972 for (i = 0; i < 1024; i++)
1973 s->ns[i] = le32toh(s->ns[i]);
1974 #endif
1975 }
1976
1977 static inline
nvme_command_effects_page_swapbytes(struct nvme_command_effects_page * s __unused)1978 void nvme_command_effects_page_swapbytes(
1979 struct nvme_command_effects_page *s __unused)
1980 {
1981 #if _BYTE_ORDER != _LITTLE_ENDIAN
1982 int i;
1983
1984 for (i = 0; i < 256; i++)
1985 s->acs[i] = le32toh(s->acs[i]);
1986 for (i = 0; i < 256; i++)
1987 s->iocs[i] = le32toh(s->iocs[i]);
1988 #endif
1989 }
1990
1991 static inline
nvme_res_notification_page_swapbytes(struct nvme_res_notification_page * s __unused)1992 void nvme_res_notification_page_swapbytes(
1993 struct nvme_res_notification_page *s __unused)
1994 {
1995 #if _BYTE_ORDER != _LITTLE_ENDIAN
1996 s->log_page_count = le64toh(s->log_page_count);
1997 s->nsid = le32toh(s->nsid);
1998 #endif
1999 }
2000
2001 static inline
nvme_sanitize_status_page_swapbytes(struct nvme_sanitize_status_page * s __unused)2002 void nvme_sanitize_status_page_swapbytes(
2003 struct nvme_sanitize_status_page *s __unused)
2004 {
2005 #if _BYTE_ORDER != _LITTLE_ENDIAN
2006 s->sprog = le16toh(s->sprog);
2007 s->sstat = le16toh(s->sstat);
2008 s->scdw10 = le32toh(s->scdw10);
2009 s->etfo = le32toh(s->etfo);
2010 s->etfbe = le32toh(s->etfbe);
2011 s->etfce = le32toh(s->etfce);
2012 s->etfownd = le32toh(s->etfownd);
2013 s->etfbewnd = le32toh(s->etfbewnd);
2014 s->etfcewnd = le32toh(s->etfcewnd);
2015 #endif
2016 }
2017
2018 static inline
intel_log_temp_stats_swapbytes(struct intel_log_temp_stats * s __unused)2019 void intel_log_temp_stats_swapbytes(struct intel_log_temp_stats *s __unused)
2020 {
2021 #if _BYTE_ORDER != _LITTLE_ENDIAN
2022
2023 s->current = le64toh(s->current);
2024 s->overtemp_flag_last = le64toh(s->overtemp_flag_last);
2025 s->overtemp_flag_life = le64toh(s->overtemp_flag_life);
2026 s->max_temp = le64toh(s->max_temp);
2027 s->min_temp = le64toh(s->min_temp);
2028 /* omit _rsvd[] */
2029 s->max_oper_temp = le64toh(s->max_oper_temp);
2030 s->min_oper_temp = le64toh(s->min_oper_temp);
2031 s->est_offset = le64toh(s->est_offset);
2032 #endif
2033 }
2034
2035 static inline
nvme_resv_status_swapbytes(struct nvme_resv_status * s __unused,size_t size __unused)2036 void nvme_resv_status_swapbytes(struct nvme_resv_status *s __unused,
2037 size_t size __unused)
2038 {
2039 #if _BYTE_ORDER != _LITTLE_ENDIAN
2040 u_int i, n;
2041
2042 s->gen = le32toh(s->gen);
2043 n = (s->regctl[1] << 8) | s->regctl[0];
2044 n = MIN(n, (size - sizeof(s)) / sizeof(s->ctrlr[0]));
2045 for (i = 0; i < n; i++) {
2046 s->ctrlr[i].ctrlr_id = le16toh(s->ctrlr[i].ctrlr_id);
2047 s->ctrlr[i].hostid = le64toh(s->ctrlr[i].hostid);
2048 s->ctrlr[i].rkey = le64toh(s->ctrlr[i].rkey);
2049 }
2050 #endif
2051 }
2052
2053 static inline
nvme_resv_status_ext_swapbytes(struct nvme_resv_status_ext * s __unused,size_t size __unused)2054 void nvme_resv_status_ext_swapbytes(struct nvme_resv_status_ext *s __unused,
2055 size_t size __unused)
2056 {
2057 #if _BYTE_ORDER != _LITTLE_ENDIAN
2058 u_int i, n;
2059
2060 s->gen = le32toh(s->gen);
2061 n = (s->regctl[1] << 8) | s->regctl[0];
2062 n = MIN(n, (size - sizeof(s)) / sizeof(s->ctrlr[0]));
2063 for (i = 0; i < n; i++) {
2064 s->ctrlr[i].ctrlr_id = le16toh(s->ctrlr[i].ctrlr_id);
2065 s->ctrlr[i].rkey = le64toh(s->ctrlr[i].rkey);
2066 nvme_le128toh((void *)s->ctrlr[i].hostid);
2067 }
2068 #endif
2069 }
2070
2071 static inline void
nvme_device_self_test_swapbytes(struct nvme_device_self_test_page * s __unused)2072 nvme_device_self_test_swapbytes(struct nvme_device_self_test_page *s __unused)
2073 {
2074 #if _BYTE_ORDER != _LITTLE_ENDIAN
2075 uint8_t *tmp;
2076 uint32_t r, i;
2077 uint8_t b;
2078
2079 for (r = 0; r < 20; r++) {
2080 s->result[r].poh = le64toh(s->result[r].poh);
2081 s->result[r].nsid = le32toh(s->result[r].nsid);
2082 /* Unaligned 64-bit loads fail on some architectures */
2083 tmp = s->result[r].failing_lba;
2084 for (i = 0; i < 4; i++) {
2085 b = tmp[i];
2086 tmp[i] = tmp[7-i];
2087 tmp[7-i] = b;
2088 }
2089 }
2090 #endif
2091 }
2092 #endif /* __NVME_H__ */
2093