1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (C) 2012-2014 Intel Corporation
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 #include <sys/param.h>
31 #include <sys/bus.h>
32 #include <sys/conf.h>
33 #include <sys/domainset.h>
34 #include <sys/proc.h>
35
36 #include <dev/pci/pcivar.h>
37
38 #include "nvme_private.h"
39
40 typedef enum error_print { ERROR_PRINT_NONE, ERROR_PRINT_NO_RETRY, ERROR_PRINT_ALL } error_print_t;
41 #define DO_NOT_RETRY 1
42
43 static void _nvme_qpair_submit_request(struct nvme_qpair *qpair,
44 struct nvme_request *req);
45 static void nvme_qpair_destroy(struct nvme_qpair *qpair);
46
47 struct nvme_opcode_string {
48 uint16_t opc;
49 const char * str;
50 };
51
52 static struct nvme_opcode_string admin_opcode[] = {
53 { NVME_OPC_DELETE_IO_SQ, "DELETE IO SQ" },
54 { NVME_OPC_CREATE_IO_SQ, "CREATE IO SQ" },
55 { NVME_OPC_GET_LOG_PAGE, "GET LOG PAGE" },
56 { NVME_OPC_DELETE_IO_CQ, "DELETE IO CQ" },
57 { NVME_OPC_CREATE_IO_CQ, "CREATE IO CQ" },
58 { NVME_OPC_IDENTIFY, "IDENTIFY" },
59 { NVME_OPC_ABORT, "ABORT" },
60 { NVME_OPC_SET_FEATURES, "SET FEATURES" },
61 { NVME_OPC_GET_FEATURES, "GET FEATURES" },
62 { NVME_OPC_ASYNC_EVENT_REQUEST, "ASYNC EVENT REQUEST" },
63 { NVME_OPC_NAMESPACE_MANAGEMENT, "NAMESPACE MANAGEMENT" },
64 { NVME_OPC_FIRMWARE_ACTIVATE, "FIRMWARE ACTIVATE" },
65 { NVME_OPC_FIRMWARE_IMAGE_DOWNLOAD, "FIRMWARE IMAGE DOWNLOAD" },
66 { NVME_OPC_DEVICE_SELF_TEST, "DEVICE SELF-TEST" },
67 { NVME_OPC_NAMESPACE_ATTACHMENT, "NAMESPACE ATTACHMENT" },
68 { NVME_OPC_KEEP_ALIVE, "KEEP ALIVE" },
69 { NVME_OPC_DIRECTIVE_SEND, "DIRECTIVE SEND" },
70 { NVME_OPC_DIRECTIVE_RECEIVE, "DIRECTIVE RECEIVE" },
71 { NVME_OPC_VIRTUALIZATION_MANAGEMENT, "VIRTUALIZATION MANAGEMENT" },
72 { NVME_OPC_NVME_MI_SEND, "NVME-MI SEND" },
73 { NVME_OPC_NVME_MI_RECEIVE, "NVME-MI RECEIVE" },
74 { NVME_OPC_DOORBELL_BUFFER_CONFIG, "DOORBELL BUFFER CONFIG" },
75 { NVME_OPC_FORMAT_NVM, "FORMAT NVM" },
76 { NVME_OPC_SECURITY_SEND, "SECURITY SEND" },
77 { NVME_OPC_SECURITY_RECEIVE, "SECURITY RECEIVE" },
78 { NVME_OPC_SANITIZE, "SANITIZE" },
79 { NVME_OPC_GET_LBA_STATUS, "GET LBA STATUS" },
80 { 0xFFFF, "ADMIN COMMAND" }
81 };
82
83 static struct nvme_opcode_string io_opcode[] = {
84 { NVME_OPC_FLUSH, "FLUSH" },
85 { NVME_OPC_WRITE, "WRITE" },
86 { NVME_OPC_READ, "READ" },
87 { NVME_OPC_WRITE_UNCORRECTABLE, "WRITE UNCORRECTABLE" },
88 { NVME_OPC_COMPARE, "COMPARE" },
89 { NVME_OPC_WRITE_ZEROES, "WRITE ZEROES" },
90 { NVME_OPC_DATASET_MANAGEMENT, "DATASET MANAGEMENT" },
91 { NVME_OPC_VERIFY, "VERIFY" },
92 { NVME_OPC_RESERVATION_REGISTER, "RESERVATION REGISTER" },
93 { NVME_OPC_RESERVATION_REPORT, "RESERVATION REPORT" },
94 { NVME_OPC_RESERVATION_ACQUIRE, "RESERVATION ACQUIRE" },
95 { NVME_OPC_RESERVATION_RELEASE, "RESERVATION RELEASE" },
96 { 0xFFFF, "IO COMMAND" }
97 };
98
99 static const char *
get_admin_opcode_string(uint16_t opc)100 get_admin_opcode_string(uint16_t opc)
101 {
102 struct nvme_opcode_string *entry;
103
104 entry = admin_opcode;
105
106 while (entry->opc != 0xFFFF) {
107 if (entry->opc == opc)
108 return (entry->str);
109 entry++;
110 }
111 return (entry->str);
112 }
113
114 static const char *
get_io_opcode_string(uint16_t opc)115 get_io_opcode_string(uint16_t opc)
116 {
117 struct nvme_opcode_string *entry;
118
119 entry = io_opcode;
120
121 while (entry->opc != 0xFFFF) {
122 if (entry->opc == opc)
123 return (entry->str);
124 entry++;
125 }
126 return (entry->str);
127 }
128
129 static void
nvme_admin_qpair_print_command(struct nvme_qpair * qpair,struct nvme_command * cmd)130 nvme_admin_qpair_print_command(struct nvme_qpair *qpair,
131 struct nvme_command *cmd)
132 {
133
134 nvme_printf(qpair->ctrlr, "%s (%02x) sqid:%d cid:%d nsid:%x "
135 "cdw10:%08x cdw11:%08x\n",
136 get_admin_opcode_string(cmd->opc), cmd->opc, qpair->id, cmd->cid,
137 le32toh(cmd->nsid), le32toh(cmd->cdw10), le32toh(cmd->cdw11));
138 }
139
140 static void
nvme_io_qpair_print_command(struct nvme_qpair * qpair,struct nvme_command * cmd)141 nvme_io_qpair_print_command(struct nvme_qpair *qpair,
142 struct nvme_command *cmd)
143 {
144
145 switch (cmd->opc) {
146 case NVME_OPC_WRITE:
147 case NVME_OPC_READ:
148 case NVME_OPC_WRITE_UNCORRECTABLE:
149 case NVME_OPC_COMPARE:
150 case NVME_OPC_WRITE_ZEROES:
151 case NVME_OPC_VERIFY:
152 nvme_printf(qpair->ctrlr, "%s sqid:%d cid:%d nsid:%d "
153 "lba:%llu len:%d\n",
154 get_io_opcode_string(cmd->opc), qpair->id, cmd->cid, le32toh(cmd->nsid),
155 ((unsigned long long)le32toh(cmd->cdw11) << 32) + le32toh(cmd->cdw10),
156 (le32toh(cmd->cdw12) & 0xFFFF) + 1);
157 break;
158 case NVME_OPC_FLUSH:
159 case NVME_OPC_DATASET_MANAGEMENT:
160 case NVME_OPC_RESERVATION_REGISTER:
161 case NVME_OPC_RESERVATION_REPORT:
162 case NVME_OPC_RESERVATION_ACQUIRE:
163 case NVME_OPC_RESERVATION_RELEASE:
164 nvme_printf(qpair->ctrlr, "%s sqid:%d cid:%d nsid:%d\n",
165 get_io_opcode_string(cmd->opc), qpair->id, cmd->cid, le32toh(cmd->nsid));
166 break;
167 default:
168 nvme_printf(qpair->ctrlr, "%s (%02x) sqid:%d cid:%d nsid:%d\n",
169 get_io_opcode_string(cmd->opc), cmd->opc, qpair->id,
170 cmd->cid, le32toh(cmd->nsid));
171 break;
172 }
173 }
174
175 static void
nvme_qpair_print_command(struct nvme_qpair * qpair,struct nvme_command * cmd)176 nvme_qpair_print_command(struct nvme_qpair *qpair, struct nvme_command *cmd)
177 {
178 if (qpair->id == 0)
179 nvme_admin_qpair_print_command(qpair, cmd);
180 else
181 nvme_io_qpair_print_command(qpair, cmd);
182 if (nvme_verbose_cmd_dump) {
183 nvme_printf(qpair->ctrlr,
184 "nsid:%#x rsvd2:%#x rsvd3:%#x mptr:%#jx prp1:%#jx prp2:%#jx\n",
185 cmd->nsid, cmd->rsvd2, cmd->rsvd3, (uintmax_t)cmd->mptr,
186 (uintmax_t)cmd->prp1, (uintmax_t)cmd->prp2);
187 nvme_printf(qpair->ctrlr,
188 "cdw10: %#x cdw11:%#x cdw12:%#x cdw13:%#x cdw14:%#x cdw15:%#x\n",
189 cmd->cdw10, cmd->cdw11, cmd->cdw12, cmd->cdw13, cmd->cdw14,
190 cmd->cdw15);
191 }
192 }
193
194 struct nvme_status_string {
195 uint16_t sc;
196 const char * str;
197 };
198
199 static struct nvme_status_string generic_status[] = {
200 { NVME_SC_SUCCESS, "SUCCESS" },
201 { NVME_SC_INVALID_OPCODE, "INVALID OPCODE" },
202 { NVME_SC_INVALID_FIELD, "INVALID_FIELD" },
203 { NVME_SC_COMMAND_ID_CONFLICT, "COMMAND ID CONFLICT" },
204 { NVME_SC_DATA_TRANSFER_ERROR, "DATA TRANSFER ERROR" },
205 { NVME_SC_ABORTED_POWER_LOSS, "ABORTED - POWER LOSS" },
206 { NVME_SC_INTERNAL_DEVICE_ERROR, "INTERNAL DEVICE ERROR" },
207 { NVME_SC_ABORTED_BY_REQUEST, "ABORTED - BY REQUEST" },
208 { NVME_SC_ABORTED_SQ_DELETION, "ABORTED - SQ DELETION" },
209 { NVME_SC_ABORTED_FAILED_FUSED, "ABORTED - FAILED FUSED" },
210 { NVME_SC_ABORTED_MISSING_FUSED, "ABORTED - MISSING FUSED" },
211 { NVME_SC_INVALID_NAMESPACE_OR_FORMAT, "INVALID NAMESPACE OR FORMAT" },
212 { NVME_SC_COMMAND_SEQUENCE_ERROR, "COMMAND SEQUENCE ERROR" },
213 { NVME_SC_INVALID_SGL_SEGMENT_DESCR, "INVALID SGL SEGMENT DESCRIPTOR" },
214 { NVME_SC_INVALID_NUMBER_OF_SGL_DESCR, "INVALID NUMBER OF SGL DESCRIPTORS" },
215 { NVME_SC_DATA_SGL_LENGTH_INVALID, "DATA SGL LENGTH INVALID" },
216 { NVME_SC_METADATA_SGL_LENGTH_INVALID, "METADATA SGL LENGTH INVALID" },
217 { NVME_SC_SGL_DESCRIPTOR_TYPE_INVALID, "SGL DESCRIPTOR TYPE INVALID" },
218 { NVME_SC_INVALID_USE_OF_CMB, "INVALID USE OF CONTROLLER MEMORY BUFFER" },
219 { NVME_SC_PRP_OFFET_INVALID, "PRP OFFET INVALID" },
220 { NVME_SC_ATOMIC_WRITE_UNIT_EXCEEDED, "ATOMIC WRITE UNIT EXCEEDED" },
221 { NVME_SC_OPERATION_DENIED, "OPERATION DENIED" },
222 { NVME_SC_SGL_OFFSET_INVALID, "SGL OFFSET INVALID" },
223 { NVME_SC_HOST_ID_INCONSISTENT_FORMAT, "HOST IDENTIFIER INCONSISTENT FORMAT" },
224 { NVME_SC_KEEP_ALIVE_TIMEOUT_EXPIRED, "KEEP ALIVE TIMEOUT EXPIRED" },
225 { NVME_SC_KEEP_ALIVE_TIMEOUT_INVALID, "KEEP ALIVE TIMEOUT INVALID" },
226 { NVME_SC_ABORTED_DUE_TO_PREEMPT, "COMMAND ABORTED DUE TO PREEMPT AND ABORT" },
227 { NVME_SC_SANITIZE_FAILED, "SANITIZE FAILED" },
228 { NVME_SC_SANITIZE_IN_PROGRESS, "SANITIZE IN PROGRESS" },
229 { NVME_SC_SGL_DATA_BLOCK_GRAN_INVALID, "SGL_DATA_BLOCK_GRANULARITY_INVALID" },
230 { NVME_SC_NOT_SUPPORTED_IN_CMB, "COMMAND NOT SUPPORTED FOR QUEUE IN CMB" },
231 { NVME_SC_NAMESPACE_IS_WRITE_PROTECTED, "NAMESPACE IS WRITE PROTECTED" },
232 { NVME_SC_COMMAND_INTERRUPTED, "COMMAND INTERRUPTED" },
233 { NVME_SC_TRANSIENT_TRANSPORT_ERROR, "TRANSIENT TRANSPORT ERROR" },
234
235 { NVME_SC_LBA_OUT_OF_RANGE, "LBA OUT OF RANGE" },
236 { NVME_SC_CAPACITY_EXCEEDED, "CAPACITY EXCEEDED" },
237 { NVME_SC_NAMESPACE_NOT_READY, "NAMESPACE NOT READY" },
238 { NVME_SC_RESERVATION_CONFLICT, "RESERVATION CONFLICT" },
239 { NVME_SC_FORMAT_IN_PROGRESS, "FORMAT IN PROGRESS" },
240 { 0xFFFF, "GENERIC" }
241 };
242
243 static struct nvme_status_string command_specific_status[] = {
244 { NVME_SC_COMPLETION_QUEUE_INVALID, "INVALID COMPLETION QUEUE" },
245 { NVME_SC_INVALID_QUEUE_IDENTIFIER, "INVALID QUEUE IDENTIFIER" },
246 { NVME_SC_MAXIMUM_QUEUE_SIZE_EXCEEDED, "MAX QUEUE SIZE EXCEEDED" },
247 { NVME_SC_ABORT_COMMAND_LIMIT_EXCEEDED, "ABORT CMD LIMIT EXCEEDED" },
248 { NVME_SC_ASYNC_EVENT_REQUEST_LIMIT_EXCEEDED, "ASYNC LIMIT EXCEEDED" },
249 { NVME_SC_INVALID_FIRMWARE_SLOT, "INVALID FIRMWARE SLOT" },
250 { NVME_SC_INVALID_FIRMWARE_IMAGE, "INVALID FIRMWARE IMAGE" },
251 { NVME_SC_INVALID_INTERRUPT_VECTOR, "INVALID INTERRUPT VECTOR" },
252 { NVME_SC_INVALID_LOG_PAGE, "INVALID LOG PAGE" },
253 { NVME_SC_INVALID_FORMAT, "INVALID FORMAT" },
254 { NVME_SC_FIRMWARE_REQUIRES_RESET, "FIRMWARE REQUIRES RESET" },
255 { NVME_SC_INVALID_QUEUE_DELETION, "INVALID QUEUE DELETION" },
256 { NVME_SC_FEATURE_NOT_SAVEABLE, "FEATURE IDENTIFIER NOT SAVEABLE" },
257 { NVME_SC_FEATURE_NOT_CHANGEABLE, "FEATURE NOT CHANGEABLE" },
258 { NVME_SC_FEATURE_NOT_NS_SPECIFIC, "FEATURE NOT NAMESPACE SPECIFIC" },
259 { NVME_SC_FW_ACT_REQUIRES_NVMS_RESET, "FIRMWARE ACTIVATION REQUIRES NVM SUBSYSTEM RESET" },
260 { NVME_SC_FW_ACT_REQUIRES_RESET, "FIRMWARE ACTIVATION REQUIRES RESET" },
261 { NVME_SC_FW_ACT_REQUIRES_TIME, "FIRMWARE ACTIVATION REQUIRES MAXIMUM TIME VIOLATION" },
262 { NVME_SC_FW_ACT_PROHIBITED, "FIRMWARE ACTIVATION PROHIBITED" },
263 { NVME_SC_OVERLAPPING_RANGE, "OVERLAPPING RANGE" },
264 { NVME_SC_NS_INSUFFICIENT_CAPACITY, "NAMESPACE INSUFFICIENT CAPACITY" },
265 { NVME_SC_NS_ID_UNAVAILABLE, "NAMESPACE IDENTIFIER UNAVAILABLE" },
266 { NVME_SC_NS_ALREADY_ATTACHED, "NAMESPACE ALREADY ATTACHED" },
267 { NVME_SC_NS_IS_PRIVATE, "NAMESPACE IS PRIVATE" },
268 { NVME_SC_NS_NOT_ATTACHED, "NS NOT ATTACHED" },
269 { NVME_SC_THIN_PROV_NOT_SUPPORTED, "THIN PROVISIONING NOT SUPPORTED" },
270 { NVME_SC_CTRLR_LIST_INVALID, "CONTROLLER LIST INVALID" },
271 { NVME_SC_SELF_TEST_IN_PROGRESS, "DEVICE SELF-TEST IN PROGRESS" },
272 { NVME_SC_BOOT_PART_WRITE_PROHIB, "BOOT PARTITION WRITE PROHIBITED" },
273 { NVME_SC_INVALID_CTRLR_ID, "INVALID CONTROLLER IDENTIFIER" },
274 { NVME_SC_INVALID_SEC_CTRLR_STATE, "INVALID SECONDARY CONTROLLER STATE" },
275 { NVME_SC_INVALID_NUM_OF_CTRLR_RESRC, "INVALID NUMBER OF CONTROLLER RESOURCES" },
276 { NVME_SC_INVALID_RESOURCE_ID, "INVALID RESOURCE IDENTIFIER" },
277 { NVME_SC_SANITIZE_PROHIBITED_WPMRE, "SANITIZE PROHIBITED WRITE PERSISTENT MEMORY REGION ENABLED" },
278 { NVME_SC_ANA_GROUP_ID_INVALID, "ANA GROUP IDENTIFIED INVALID" },
279 { NVME_SC_ANA_ATTACH_FAILED, "ANA ATTACH FAILED" },
280
281 { NVME_SC_CONFLICTING_ATTRIBUTES, "CONFLICTING ATTRIBUTES" },
282 { NVME_SC_INVALID_PROTECTION_INFO, "INVALID PROTECTION INFO" },
283 { NVME_SC_ATTEMPTED_WRITE_TO_RO_PAGE, "WRITE TO RO PAGE" },
284 { 0xFFFF, "COMMAND SPECIFIC" }
285 };
286
287 static struct nvme_status_string media_error_status[] = {
288 { NVME_SC_WRITE_FAULTS, "WRITE FAULTS" },
289 { NVME_SC_UNRECOVERED_READ_ERROR, "UNRECOVERED READ ERROR" },
290 { NVME_SC_GUARD_CHECK_ERROR, "GUARD CHECK ERROR" },
291 { NVME_SC_APPLICATION_TAG_CHECK_ERROR, "APPLICATION TAG CHECK ERROR" },
292 { NVME_SC_REFERENCE_TAG_CHECK_ERROR, "REFERENCE TAG CHECK ERROR" },
293 { NVME_SC_COMPARE_FAILURE, "COMPARE FAILURE" },
294 { NVME_SC_ACCESS_DENIED, "ACCESS DENIED" },
295 { NVME_SC_DEALLOCATED_OR_UNWRITTEN, "DEALLOCATED OR UNWRITTEN LOGICAL BLOCK" },
296 { 0xFFFF, "MEDIA ERROR" }
297 };
298
299 static struct nvme_status_string path_related_status[] = {
300 { NVME_SC_INTERNAL_PATH_ERROR, "INTERNAL PATH ERROR" },
301 { NVME_SC_ASYMMETRIC_ACCESS_PERSISTENT_LOSS, "ASYMMETRIC ACCESS PERSISTENT LOSS" },
302 { NVME_SC_ASYMMETRIC_ACCESS_INACCESSIBLE, "ASYMMETRIC ACCESS INACCESSIBLE" },
303 { NVME_SC_ASYMMETRIC_ACCESS_TRANSITION, "ASYMMETRIC ACCESS TRANSITION" },
304 { NVME_SC_CONTROLLER_PATHING_ERROR, "CONTROLLER PATHING ERROR" },
305 { NVME_SC_HOST_PATHING_ERROR, "HOST PATHING ERROR" },
306 { NVME_SC_COMMAND_ABOTHED_BY_HOST, "COMMAND ABOTHED BY HOST" },
307 { 0xFFFF, "PATH RELATED" },
308 };
309
310 static const char *
get_status_string(uint16_t sct,uint16_t sc)311 get_status_string(uint16_t sct, uint16_t sc)
312 {
313 struct nvme_status_string *entry;
314
315 switch (sct) {
316 case NVME_SCT_GENERIC:
317 entry = generic_status;
318 break;
319 case NVME_SCT_COMMAND_SPECIFIC:
320 entry = command_specific_status;
321 break;
322 case NVME_SCT_MEDIA_ERROR:
323 entry = media_error_status;
324 break;
325 case NVME_SCT_PATH_RELATED:
326 entry = path_related_status;
327 break;
328 case NVME_SCT_VENDOR_SPECIFIC:
329 return ("VENDOR SPECIFIC");
330 default:
331 return ("RESERVED");
332 }
333
334 while (entry->sc != 0xFFFF) {
335 if (entry->sc == sc)
336 return (entry->str);
337 entry++;
338 }
339 return (entry->str);
340 }
341
342 static void
nvme_qpair_print_completion(struct nvme_qpair * qpair,struct nvme_completion * cpl)343 nvme_qpair_print_completion(struct nvme_qpair *qpair,
344 struct nvme_completion *cpl)
345 {
346 uint8_t sct, sc, crd, m, dnr;
347
348 sct = NVME_STATUS_GET_SCT(cpl->status);
349 sc = NVME_STATUS_GET_SC(cpl->status);
350 crd = NVME_STATUS_GET_CRD(cpl->status);
351 m = NVME_STATUS_GET_M(cpl->status);
352 dnr = NVME_STATUS_GET_DNR(cpl->status);
353
354 nvme_printf(qpair->ctrlr, "%s (%02x/%02x) crd:%x m:%x dnr:%x "
355 "sqid:%d cid:%d cdw0:%x\n",
356 get_status_string(sct, sc), sct, sc, crd, m, dnr,
357 cpl->sqid, cpl->cid, cpl->cdw0);
358 }
359
360 static bool
nvme_completion_is_retry(const struct nvme_completion * cpl)361 nvme_completion_is_retry(const struct nvme_completion *cpl)
362 {
363 uint8_t sct, sc, dnr;
364
365 sct = NVME_STATUS_GET_SCT(cpl->status);
366 sc = NVME_STATUS_GET_SC(cpl->status);
367 dnr = NVME_STATUS_GET_DNR(cpl->status); /* Do Not Retry Bit */
368
369 /*
370 * TODO: spec is not clear how commands that are aborted due
371 * to TLER will be marked. So for now, it seems
372 * NAMESPACE_NOT_READY is the only case where we should
373 * look at the DNR bit. Requests failed with ABORTED_BY_REQUEST
374 * set the DNR bit correctly since the driver controls that.
375 */
376 switch (sct) {
377 case NVME_SCT_GENERIC:
378 switch (sc) {
379 case NVME_SC_ABORTED_BY_REQUEST:
380 case NVME_SC_NAMESPACE_NOT_READY:
381 if (dnr)
382 return (0);
383 else
384 return (1);
385 case NVME_SC_INVALID_OPCODE:
386 case NVME_SC_INVALID_FIELD:
387 case NVME_SC_COMMAND_ID_CONFLICT:
388 case NVME_SC_DATA_TRANSFER_ERROR:
389 case NVME_SC_ABORTED_POWER_LOSS:
390 case NVME_SC_INTERNAL_DEVICE_ERROR:
391 case NVME_SC_ABORTED_SQ_DELETION:
392 case NVME_SC_ABORTED_FAILED_FUSED:
393 case NVME_SC_ABORTED_MISSING_FUSED:
394 case NVME_SC_INVALID_NAMESPACE_OR_FORMAT:
395 case NVME_SC_COMMAND_SEQUENCE_ERROR:
396 case NVME_SC_LBA_OUT_OF_RANGE:
397 case NVME_SC_CAPACITY_EXCEEDED:
398 default:
399 return (0);
400 }
401 case NVME_SCT_COMMAND_SPECIFIC:
402 case NVME_SCT_MEDIA_ERROR:
403 return (0);
404 case NVME_SCT_PATH_RELATED:
405 switch (sc) {
406 case NVME_SC_INTERNAL_PATH_ERROR:
407 if (dnr)
408 return (0);
409 else
410 return (1);
411 default:
412 return (0);
413 }
414 case NVME_SCT_VENDOR_SPECIFIC:
415 default:
416 return (0);
417 }
418 }
419
420 static void
nvme_qpair_complete_tracker(struct nvme_tracker * tr,struct nvme_completion * cpl,error_print_t print_on_error)421 nvme_qpair_complete_tracker(struct nvme_tracker *tr,
422 struct nvme_completion *cpl, error_print_t print_on_error)
423 {
424 struct nvme_qpair * qpair = tr->qpair;
425 struct nvme_request *req;
426 bool retry, error, retriable;
427
428 req = tr->req;
429 error = nvme_completion_is_error(cpl);
430 retriable = nvme_completion_is_retry(cpl);
431 retry = error && retriable && req->retries < nvme_retry_count;
432 if (retry)
433 qpair->num_retries++;
434 if (error && req->retries >= nvme_retry_count && retriable)
435 qpair->num_failures++;
436
437 if (error && (print_on_error == ERROR_PRINT_ALL ||
438 (!retry && print_on_error == ERROR_PRINT_NO_RETRY))) {
439 nvme_qpair_print_command(qpair, &req->cmd);
440 nvme_qpair_print_completion(qpair, cpl);
441 }
442
443 qpair->act_tr[cpl->cid] = NULL;
444
445 KASSERT(cpl->cid == req->cmd.cid, ("cpl cid does not match cmd cid\n"));
446
447 if (!retry) {
448 if (req->type != NVME_REQUEST_NULL) {
449 bus_dmamap_sync(qpair->dma_tag_payload,
450 tr->payload_dma_map,
451 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
452 }
453 if (req->cb_fn)
454 req->cb_fn(req->cb_arg, cpl);
455 }
456
457 mtx_lock(&qpair->lock);
458
459 if (retry) {
460 req->retries++;
461 nvme_qpair_submit_tracker(qpair, tr);
462 } else {
463 if (req->type != NVME_REQUEST_NULL) {
464 bus_dmamap_unload(qpair->dma_tag_payload,
465 tr->payload_dma_map);
466 }
467
468 nvme_free_request(req);
469 tr->req = NULL;
470
471 TAILQ_REMOVE(&qpair->outstanding_tr, tr, tailq);
472 TAILQ_INSERT_HEAD(&qpair->free_tr, tr, tailq);
473
474 /*
475 * If the controller is in the middle of resetting, don't
476 * try to submit queued requests here - let the reset logic
477 * handle that instead.
478 */
479 if (!STAILQ_EMPTY(&qpair->queued_req) &&
480 !qpair->ctrlr->is_resetting) {
481 req = STAILQ_FIRST(&qpair->queued_req);
482 STAILQ_REMOVE_HEAD(&qpair->queued_req, stailq);
483 _nvme_qpair_submit_request(qpair, req);
484 }
485 }
486
487 mtx_unlock(&qpair->lock);
488 }
489
490 static void
nvme_qpair_manual_complete_tracker(struct nvme_tracker * tr,uint32_t sct,uint32_t sc,uint32_t dnr,error_print_t print_on_error)491 nvme_qpair_manual_complete_tracker(
492 struct nvme_tracker *tr, uint32_t sct, uint32_t sc, uint32_t dnr,
493 error_print_t print_on_error)
494 {
495 struct nvme_completion cpl;
496
497 memset(&cpl, 0, sizeof(cpl));
498
499 struct nvme_qpair * qpair = tr->qpair;
500
501 cpl.sqid = qpair->id;
502 cpl.cid = tr->cid;
503 cpl.status |= (sct & NVME_STATUS_SCT_MASK) << NVME_STATUS_SCT_SHIFT;
504 cpl.status |= (sc & NVME_STATUS_SC_MASK) << NVME_STATUS_SC_SHIFT;
505 cpl.status |= (dnr & NVME_STATUS_DNR_MASK) << NVME_STATUS_DNR_SHIFT;
506 nvme_qpair_complete_tracker(tr, &cpl, print_on_error);
507 }
508
509 void
nvme_qpair_manual_complete_request(struct nvme_qpair * qpair,struct nvme_request * req,uint32_t sct,uint32_t sc)510 nvme_qpair_manual_complete_request(struct nvme_qpair *qpair,
511 struct nvme_request *req, uint32_t sct, uint32_t sc)
512 {
513 struct nvme_completion cpl;
514 bool error;
515
516 memset(&cpl, 0, sizeof(cpl));
517 cpl.sqid = qpair->id;
518 cpl.status |= (sct & NVME_STATUS_SCT_MASK) << NVME_STATUS_SCT_SHIFT;
519 cpl.status |= (sc & NVME_STATUS_SC_MASK) << NVME_STATUS_SC_SHIFT;
520
521 error = nvme_completion_is_error(&cpl);
522
523 if (error) {
524 nvme_qpair_print_command(qpair, &req->cmd);
525 nvme_qpair_print_completion(qpair, &cpl);
526 }
527
528 if (req->cb_fn)
529 req->cb_fn(req->cb_arg, &cpl);
530
531 nvme_free_request(req);
532 }
533
534 bool
nvme_qpair_process_completions(struct nvme_qpair * qpair)535 nvme_qpair_process_completions(struct nvme_qpair *qpair)
536 {
537 struct nvme_tracker *tr;
538 struct nvme_completion cpl;
539 int done = 0;
540 bool in_panic = dumping || SCHEDULER_STOPPED();
541
542 /*
543 * qpair is not enabled, likely because a controller reset is in
544 * progress. Ignore the interrupt - any I/O that was associated with
545 * this interrupt will get retried when the reset is complete. Any
546 * pending completions for when we're in startup will be completed
547 * as soon as initialization is complete and we start sending commands
548 * to the device.
549 */
550 if (qpair->recovery_state != RECOVERY_NONE) {
551 qpair->num_ignored++;
552 return (false);
553 }
554
555 /*
556 * Sanity check initialization. After we reset the hardware, the phase
557 * is defined to be 1. So if we get here with zero prior calls and the
558 * phase is 0, it means that we've lost a race between the
559 * initialization and the ISR running. With the phase wrong, we'll
560 * process a bunch of completions that aren't really completions leading
561 * to a KASSERT below.
562 */
563 KASSERT(!(qpair->num_intr_handler_calls == 0 && qpair->phase == 0),
564 ("%s: Phase wrong for first interrupt call.",
565 device_get_nameunit(qpair->ctrlr->dev)));
566
567 qpair->num_intr_handler_calls++;
568
569 bus_dmamap_sync(qpair->dma_tag, qpair->queuemem_map,
570 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
571 /*
572 * A panic can stop the CPU this routine is running on at any point. If
573 * we're called during a panic, complete the sq_head wrap protocol for
574 * the case where we are interrupted just after the increment at 1
575 * below, but before we can reset cq_head to zero at 2. Also cope with
576 * the case where we do the zero at 2, but may or may not have done the
577 * phase adjustment at step 3. The panic machinery flushes all pending
578 * memory writes, so we can make these strong ordering assumptions
579 * that would otherwise be unwise if we were racing in real time.
580 */
581 if (__predict_false(in_panic)) {
582 if (qpair->cq_head == qpair->num_entries) {
583 /*
584 * Here we know that we need to zero cq_head and then negate
585 * the phase, which hasn't been assigned if cq_head isn't
586 * zero due to the atomic_store_rel.
587 */
588 qpair->cq_head = 0;
589 qpair->phase = !qpair->phase;
590 } else if (qpair->cq_head == 0) {
591 /*
592 * In this case, we know that the assignment at 2
593 * happened below, but we don't know if it 3 happened or
594 * not. To do this, we look at the last completion
595 * entry and set the phase to the opposite phase
596 * that it has. This gets us back in sync
597 */
598 cpl = qpair->cpl[qpair->num_entries - 1];
599 nvme_completion_swapbytes(&cpl);
600 qpair->phase = !NVME_STATUS_GET_P(cpl.status);
601 }
602 }
603
604 while (1) {
605 uint16_t status;
606
607 /*
608 * We need to do this dance to avoid a race between the host and
609 * the device where the device overtakes the host while the host
610 * is reading this record, leaving the status field 'new' and
611 * the sqhd and cid fields potentially stale. If the phase
612 * doesn't match, that means status hasn't yet been updated and
613 * we'll get any pending changes next time. It also means that
614 * the phase must be the same the second time. We have to sync
615 * before reading to ensure any bouncing completes.
616 */
617 status = le16toh(qpair->cpl[qpair->cq_head].status);
618 if (NVME_STATUS_GET_P(status) != qpair->phase)
619 break;
620
621 bus_dmamap_sync(qpair->dma_tag, qpair->queuemem_map,
622 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
623 cpl = qpair->cpl[qpair->cq_head];
624 nvme_completion_swapbytes(&cpl);
625
626 KASSERT(
627 NVME_STATUS_GET_P(status) == NVME_STATUS_GET_P(cpl.status),
628 ("Phase unexpectedly inconsistent"));
629
630 if (cpl.cid < qpair->num_trackers)
631 tr = qpair->act_tr[cpl.cid];
632 else
633 tr = NULL;
634
635 done++;
636 if (tr != NULL) {
637 nvme_qpair_complete_tracker(tr, &cpl, ERROR_PRINT_ALL);
638 qpair->sq_head = cpl.sqhd;
639 } else if (!in_panic) {
640 /*
641 * A missing tracker is normally an error. However, a
642 * panic can stop the CPU this routine is running on
643 * after completing an I/O but before updating
644 * qpair->cq_head at 1 below. Later, we re-enter this
645 * routine to poll I/O associated with the kernel
646 * dump. We find that the tr has been set to null before
647 * calling the completion routine. If it hasn't
648 * completed (or it triggers a panic), then '1' below
649 * won't have updated cq_head. Rather than panic again,
650 * ignore this condition because it's not unexpected.
651 */
652 nvme_printf(qpair->ctrlr,
653 "cpl (cid = %u) does not map to outstanding cmd\n",
654 cpl.cid);
655 /* nvme_dump_completion expects device endianess */
656 nvme_dump_completion(&qpair->cpl[qpair->cq_head]);
657 KASSERT(0, ("received completion for unknown cmd"));
658 }
659
660 /*
661 * There's a number of races with the following (see above) when
662 * the system panics. We compensate for each one of them by
663 * using the atomic store to force strong ordering (at least when
664 * viewed in the aftermath of a panic).
665 */
666 if (++qpair->cq_head == qpair->num_entries) { /* 1 */
667 atomic_store_rel_int(&qpair->cq_head, 0); /* 2 */
668 qpair->phase = !qpair->phase; /* 3 */
669 }
670 }
671
672 if (done != 0) {
673 bus_space_write_4(qpair->ctrlr->bus_tag, qpair->ctrlr->bus_handle,
674 qpair->cq_hdbl_off, qpair->cq_head);
675 }
676
677 return (done != 0);
678 }
679
680 static void
nvme_qpair_msi_handler(void * arg)681 nvme_qpair_msi_handler(void *arg)
682 {
683 struct nvme_qpair *qpair = arg;
684
685 nvme_qpair_process_completions(qpair);
686 }
687
688 int
nvme_qpair_construct(struct nvme_qpair * qpair,uint32_t num_entries,uint32_t num_trackers,struct nvme_controller * ctrlr)689 nvme_qpair_construct(struct nvme_qpair *qpair,
690 uint32_t num_entries, uint32_t num_trackers,
691 struct nvme_controller *ctrlr)
692 {
693 struct nvme_tracker *tr;
694 size_t cmdsz, cplsz, prpsz, allocsz, prpmemsz;
695 uint64_t queuemem_phys, prpmem_phys, list_phys;
696 uint8_t *queuemem, *prpmem, *prp_list;
697 int i, err;
698
699 qpair->vector = ctrlr->msi_count > 1 ? qpair->id : 0;
700 qpair->num_entries = num_entries;
701 qpair->num_trackers = num_trackers;
702 qpair->ctrlr = ctrlr;
703
704 mtx_init(&qpair->lock, "nvme qpair lock", NULL, MTX_DEF);
705
706 /* Note: NVMe PRP format is restricted to 4-byte alignment. */
707 err = bus_dma_tag_create(bus_get_dma_tag(ctrlr->dev),
708 4, PAGE_SIZE, BUS_SPACE_MAXADDR,
709 BUS_SPACE_MAXADDR, NULL, NULL, ctrlr->max_xfer_size,
710 btoc(ctrlr->max_xfer_size) + 1, PAGE_SIZE, 0,
711 NULL, NULL, &qpair->dma_tag_payload);
712 if (err != 0) {
713 nvme_printf(ctrlr, "payload tag create failed %d\n", err);
714 goto out;
715 }
716
717 /*
718 * Each component must be page aligned, and individual PRP lists
719 * cannot cross a page boundary.
720 */
721 cmdsz = qpair->num_entries * sizeof(struct nvme_command);
722 cmdsz = roundup2(cmdsz, PAGE_SIZE);
723 cplsz = qpair->num_entries * sizeof(struct nvme_completion);
724 cplsz = roundup2(cplsz, PAGE_SIZE);
725 /*
726 * For commands requiring more than 2 PRP entries, one PRP will be
727 * embedded in the command (prp1), and the rest of the PRP entries
728 * will be in a list pointed to by the command (prp2).
729 */
730 prpsz = sizeof(uint64_t) * btoc(ctrlr->max_xfer_size);
731 prpmemsz = qpair->num_trackers * prpsz;
732 allocsz = cmdsz + cplsz + prpmemsz;
733
734 err = bus_dma_tag_create(bus_get_dma_tag(ctrlr->dev),
735 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
736 allocsz, 1, allocsz, 0, NULL, NULL, &qpair->dma_tag);
737 if (err != 0) {
738 nvme_printf(ctrlr, "tag create failed %d\n", err);
739 goto out;
740 }
741 bus_dma_tag_set_domain(qpair->dma_tag, qpair->domain);
742
743 if (bus_dmamem_alloc(qpair->dma_tag, (void **)&queuemem,
744 BUS_DMA_COHERENT | BUS_DMA_NOWAIT, &qpair->queuemem_map)) {
745 nvme_printf(ctrlr, "failed to alloc qpair memory\n");
746 goto out;
747 }
748
749 if (bus_dmamap_load(qpair->dma_tag, qpair->queuemem_map,
750 queuemem, allocsz, nvme_single_map, &queuemem_phys, 0) != 0) {
751 nvme_printf(ctrlr, "failed to load qpair memory\n");
752 bus_dmamem_free(qpair->dma_tag, qpair->cmd,
753 qpair->queuemem_map);
754 goto out;
755 }
756
757 qpair->num_cmds = 0;
758 qpair->num_intr_handler_calls = 0;
759 qpair->num_retries = 0;
760 qpair->num_failures = 0;
761 qpair->num_ignored = 0;
762 qpair->cmd = (struct nvme_command *)queuemem;
763 qpair->cpl = (struct nvme_completion *)(queuemem + cmdsz);
764 prpmem = (uint8_t *)(queuemem + cmdsz + cplsz);
765 qpair->cmd_bus_addr = queuemem_phys;
766 qpair->cpl_bus_addr = queuemem_phys + cmdsz;
767 prpmem_phys = queuemem_phys + cmdsz + cplsz;
768
769 callout_init(&qpair->timer, 1);
770 qpair->timer_armed = false;
771 qpair->recovery_state = RECOVERY_WAITING;
772
773 /*
774 * Calcuate the stride of the doorbell register. Many emulators set this
775 * value to correspond to a cache line. However, some hardware has set
776 * it to various small values.
777 */
778 qpair->sq_tdbl_off = nvme_mmio_offsetof(doorbell[0]) +
779 (qpair->id << (ctrlr->dstrd + 1));
780 qpair->cq_hdbl_off = nvme_mmio_offsetof(doorbell[0]) +
781 (qpair->id << (ctrlr->dstrd + 1)) + (1 << ctrlr->dstrd);
782
783 TAILQ_INIT(&qpair->free_tr);
784 TAILQ_INIT(&qpair->outstanding_tr);
785 STAILQ_INIT(&qpair->queued_req);
786
787 list_phys = prpmem_phys;
788 prp_list = prpmem;
789 for (i = 0; i < qpair->num_trackers; i++) {
790 if (list_phys + prpsz > prpmem_phys + prpmemsz) {
791 qpair->num_trackers = i;
792 break;
793 }
794
795 /*
796 * Make sure that the PRP list for this tracker doesn't
797 * overflow to another page.
798 */
799 if (trunc_page(list_phys) !=
800 trunc_page(list_phys + prpsz - 1)) {
801 list_phys = roundup2(list_phys, PAGE_SIZE);
802 prp_list =
803 (uint8_t *)roundup2((uintptr_t)prp_list, PAGE_SIZE);
804 }
805
806 tr = malloc_domainset(sizeof(*tr), M_NVME,
807 DOMAINSET_PREF(qpair->domain), M_ZERO | M_WAITOK);
808 bus_dmamap_create(qpair->dma_tag_payload, 0,
809 &tr->payload_dma_map);
810 tr->cid = i;
811 tr->qpair = qpair;
812 tr->prp = (uint64_t *)prp_list;
813 tr->prp_bus_addr = list_phys;
814 TAILQ_INSERT_HEAD(&qpair->free_tr, tr, tailq);
815 list_phys += prpsz;
816 prp_list += prpsz;
817 }
818
819 if (qpair->num_trackers == 0) {
820 nvme_printf(ctrlr, "failed to allocate enough trackers\n");
821 goto out;
822 }
823
824 qpair->act_tr = malloc_domainset(sizeof(struct nvme_tracker *) *
825 qpair->num_entries, M_NVME, DOMAINSET_PREF(qpair->domain),
826 M_ZERO | M_WAITOK);
827
828 if (ctrlr->msi_count > 1) {
829 /*
830 * MSI-X vector resource IDs start at 1, so we add one to
831 * the queue's vector to get the corresponding rid to use.
832 */
833 qpair->rid = qpair->vector + 1;
834
835 qpair->res = bus_alloc_resource_any(ctrlr->dev, SYS_RES_IRQ,
836 &qpair->rid, RF_ACTIVE);
837 if (qpair->res == NULL) {
838 nvme_printf(ctrlr, "unable to allocate MSI\n");
839 goto out;
840 }
841 if (bus_setup_intr(ctrlr->dev, qpair->res,
842 INTR_TYPE_MISC | INTR_MPSAFE, NULL,
843 nvme_qpair_msi_handler, qpair, &qpair->tag) != 0) {
844 nvme_printf(ctrlr, "unable to setup MSI\n");
845 goto out;
846 }
847 if (qpair->id == 0) {
848 bus_describe_intr(ctrlr->dev, qpair->res, qpair->tag,
849 "admin");
850 } else {
851 bus_describe_intr(ctrlr->dev, qpair->res, qpair->tag,
852 "io%d", qpair->id - 1);
853 }
854 }
855
856 return (0);
857
858 out:
859 nvme_qpair_destroy(qpair);
860 return (ENOMEM);
861 }
862
863 static void
nvme_qpair_destroy(struct nvme_qpair * qpair)864 nvme_qpair_destroy(struct nvme_qpair *qpair)
865 {
866 struct nvme_tracker *tr;
867
868 callout_drain(&qpair->timer);
869
870 if (qpair->tag) {
871 bus_teardown_intr(qpair->ctrlr->dev, qpair->res, qpair->tag);
872 qpair->tag = NULL;
873 }
874
875 if (qpair->act_tr) {
876 free(qpair->act_tr, M_NVME);
877 qpair->act_tr = NULL;
878 }
879
880 while (!TAILQ_EMPTY(&qpair->free_tr)) {
881 tr = TAILQ_FIRST(&qpair->free_tr);
882 TAILQ_REMOVE(&qpair->free_tr, tr, tailq);
883 bus_dmamap_destroy(qpair->dma_tag_payload,
884 tr->payload_dma_map);
885 free(tr, M_NVME);
886 }
887
888 if (qpair->cmd != NULL) {
889 bus_dmamap_unload(qpair->dma_tag, qpair->queuemem_map);
890 bus_dmamem_free(qpair->dma_tag, qpair->cmd,
891 qpair->queuemem_map);
892 qpair->cmd = NULL;
893 }
894
895 if (qpair->dma_tag) {
896 bus_dma_tag_destroy(qpair->dma_tag);
897 qpair->dma_tag = NULL;
898 }
899
900 if (qpair->dma_tag_payload) {
901 bus_dma_tag_destroy(qpair->dma_tag_payload);
902 qpair->dma_tag_payload = NULL;
903 }
904
905 if (mtx_initialized(&qpair->lock))
906 mtx_destroy(&qpair->lock);
907
908 if (qpair->res) {
909 bus_release_resource(qpair->ctrlr->dev, SYS_RES_IRQ,
910 rman_get_rid(qpair->res), qpair->res);
911 qpair->res = NULL;
912 }
913 }
914
915 static void
nvme_admin_qpair_abort_aers(struct nvme_qpair * qpair)916 nvme_admin_qpair_abort_aers(struct nvme_qpair *qpair)
917 {
918 struct nvme_tracker *tr;
919
920 tr = TAILQ_FIRST(&qpair->outstanding_tr);
921 while (tr != NULL) {
922 if (tr->req->cmd.opc == NVME_OPC_ASYNC_EVENT_REQUEST) {
923 nvme_qpair_manual_complete_tracker(tr,
924 NVME_SCT_GENERIC, NVME_SC_ABORTED_SQ_DELETION, 0,
925 ERROR_PRINT_NONE);
926 tr = TAILQ_FIRST(&qpair->outstanding_tr);
927 } else {
928 tr = TAILQ_NEXT(tr, tailq);
929 }
930 }
931 }
932
933 void
nvme_admin_qpair_destroy(struct nvme_qpair * qpair)934 nvme_admin_qpair_destroy(struct nvme_qpair *qpair)
935 {
936
937 nvme_admin_qpair_abort_aers(qpair);
938 nvme_qpair_destroy(qpair);
939 }
940
941 void
nvme_io_qpair_destroy(struct nvme_qpair * qpair)942 nvme_io_qpair_destroy(struct nvme_qpair *qpair)
943 {
944
945 nvme_qpair_destroy(qpair);
946 }
947
948 static void
nvme_qpair_timeout(void * arg)949 nvme_qpair_timeout(void *arg)
950 {
951 struct nvme_qpair *qpair = arg;
952 struct nvme_controller *ctrlr = qpair->ctrlr;
953 struct nvme_tracker *tr;
954 sbintime_t now;
955 bool idle;
956 uint32_t csts;
957 uint8_t cfs;
958
959 mtx_lock(&qpair->lock);
960 idle = TAILQ_EMPTY(&qpair->outstanding_tr);
961 again:
962 switch (qpair->recovery_state) {
963 case RECOVERY_NONE:
964 if (idle)
965 break;
966 now = getsbinuptime();
967 idle = true;
968 TAILQ_FOREACH(tr, &qpair->outstanding_tr, tailq) {
969 if (tr->deadline == SBT_MAX)
970 continue;
971 idle = false;
972 if (now > tr->deadline) {
973 /*
974 * We're now passed our earliest deadline. We
975 * need to do expensive things to cope, but next
976 * time. Flag that and close the door to any
977 * further processing.
978 */
979 qpair->recovery_state = RECOVERY_START;
980 nvme_printf(ctrlr, "RECOVERY_START %jd vs %jd\n",
981 (uintmax_t)now, (uintmax_t)tr->deadline);
982 break;
983 }
984 }
985 break;
986 case RECOVERY_START:
987 /*
988 * Read csts to get value of cfs - controller fatal status.
989 * If no fatal status, try to call the completion routine, and
990 * if completes transactions, report a missed interrupt and
991 * return (this may need to be rate limited). Otherwise, if
992 * aborts are enabled and the controller is not reporting
993 * fatal status, abort the command. Otherwise, just reset the
994 * controller and hope for the best.
995 */
996 csts = nvme_mmio_read_4(ctrlr, csts);
997 cfs = (csts >> NVME_CSTS_REG_CFS_SHIFT) & NVME_CSTS_REG_CFS_MASK;
998 if (cfs) {
999 nvme_printf(ctrlr, "Controller in fatal status, resetting\n");
1000 qpair->recovery_state = RECOVERY_RESET;
1001 goto again;
1002 }
1003 mtx_unlock(&qpair->lock);
1004 if (nvme_qpair_process_completions(qpair)) {
1005 nvme_printf(ctrlr, "Completions present in output without an interrupt\n");
1006 qpair->recovery_state = RECOVERY_NONE;
1007 } else {
1008 nvme_printf(ctrlr, "timeout with nothing complete, resetting\n");
1009 qpair->recovery_state = RECOVERY_RESET;
1010 mtx_lock(&qpair->lock);
1011 goto again;
1012 }
1013 mtx_lock(&qpair->lock);
1014 break;
1015 case RECOVERY_RESET:
1016 /*
1017 * If we get here due to a possible surprise hot-unplug event,
1018 * then we let nvme_ctrlr_reset confirm and fail the
1019 * controller.
1020 */
1021 nvme_printf(ctrlr, "Resetting controller due to a timeout%s.\n",
1022 (csts == 0xffffffff) ? " and possible hot unplug" :
1023 (cfs ? " and fatal error status" : ""));
1024 nvme_printf(ctrlr, "RECOVERY_WAITING\n");
1025 qpair->recovery_state = RECOVERY_WAITING;
1026 nvme_ctrlr_reset(ctrlr);
1027 break;
1028 case RECOVERY_WAITING:
1029 nvme_printf(ctrlr, "waiting\n");
1030 break;
1031 }
1032
1033 /*
1034 * Rearm the timeout.
1035 */
1036 if (!idle) {
1037 callout_schedule_sbt(&qpair->timer, SBT_1S / 2, SBT_1S / 2, 0);
1038 } else {
1039 qpair->timer_armed = false;
1040 }
1041 mtx_unlock(&qpair->lock);
1042 }
1043
1044 /*
1045 * Submit the tracker to the hardware. Must already be in the
1046 * outstanding queue when called.
1047 */
1048 void
nvme_qpair_submit_tracker(struct nvme_qpair * qpair,struct nvme_tracker * tr)1049 nvme_qpair_submit_tracker(struct nvme_qpair *qpair, struct nvme_tracker *tr)
1050 {
1051 struct nvme_request *req;
1052 struct nvme_controller *ctrlr;
1053 int timeout;
1054
1055 mtx_assert(&qpair->lock, MA_OWNED);
1056
1057 req = tr->req;
1058 req->cmd.cid = tr->cid;
1059 qpair->act_tr[tr->cid] = tr;
1060 ctrlr = qpair->ctrlr;
1061
1062 if (req->timeout) {
1063 if (req->cb_fn == nvme_completion_poll_cb)
1064 timeout = 1;
1065 else if (qpair->id == 0)
1066 timeout = ctrlr->admin_timeout_period;
1067 else
1068 timeout = ctrlr->timeout_period;
1069 tr->deadline = getsbinuptime() + timeout * SBT_1S;
1070 if (!qpair->timer_armed) {
1071 qpair->timer_armed = true;
1072 callout_reset_sbt_on(&qpair->timer, SBT_1S / 2, SBT_1S / 2,
1073 nvme_qpair_timeout, qpair, qpair->cpu, 0);
1074 }
1075 } else
1076 tr->deadline = SBT_MAX;
1077
1078 /* Copy the command from the tracker to the submission queue. */
1079 memcpy(&qpair->cmd[qpair->sq_tail], &req->cmd, sizeof(req->cmd));
1080
1081 if (++qpair->sq_tail == qpair->num_entries)
1082 qpair->sq_tail = 0;
1083
1084 bus_dmamap_sync(qpair->dma_tag, qpair->queuemem_map,
1085 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1086 bus_space_write_4(qpair->ctrlr->bus_tag, qpair->ctrlr->bus_handle,
1087 qpair->sq_tdbl_off, qpair->sq_tail);
1088 qpair->num_cmds++;
1089 }
1090
1091 static void
nvme_payload_map(void * arg,bus_dma_segment_t * seg,int nseg,int error)1092 nvme_payload_map(void *arg, bus_dma_segment_t *seg, int nseg, int error)
1093 {
1094 struct nvme_tracker *tr = arg;
1095 uint32_t cur_nseg;
1096
1097 /*
1098 * If the mapping operation failed, return immediately. The caller
1099 * is responsible for detecting the error status and failing the
1100 * tracker manually.
1101 */
1102 if (error != 0) {
1103 nvme_printf(tr->qpair->ctrlr,
1104 "nvme_payload_map err %d\n", error);
1105 return;
1106 }
1107
1108 /*
1109 * Note that we specified PAGE_SIZE for alignment and max
1110 * segment size when creating the bus dma tags. So here
1111 * we can safely just transfer each segment to its
1112 * associated PRP entry.
1113 */
1114 tr->req->cmd.prp1 = htole64(seg[0].ds_addr);
1115
1116 if (nseg == 2) {
1117 tr->req->cmd.prp2 = htole64(seg[1].ds_addr);
1118 } else if (nseg > 2) {
1119 cur_nseg = 1;
1120 tr->req->cmd.prp2 = htole64((uint64_t)tr->prp_bus_addr);
1121 while (cur_nseg < nseg) {
1122 tr->prp[cur_nseg-1] =
1123 htole64((uint64_t)seg[cur_nseg].ds_addr);
1124 cur_nseg++;
1125 }
1126 } else {
1127 /*
1128 * prp2 should not be used by the controller
1129 * since there is only one segment, but set
1130 * to 0 just to be safe.
1131 */
1132 tr->req->cmd.prp2 = 0;
1133 }
1134
1135 bus_dmamap_sync(tr->qpair->dma_tag_payload, tr->payload_dma_map,
1136 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1137 nvme_qpair_submit_tracker(tr->qpair, tr);
1138 }
1139
1140 static void
_nvme_qpair_submit_request(struct nvme_qpair * qpair,struct nvme_request * req)1141 _nvme_qpair_submit_request(struct nvme_qpair *qpair, struct nvme_request *req)
1142 {
1143 struct nvme_tracker *tr;
1144 int err = 0;
1145
1146 mtx_assert(&qpair->lock, MA_OWNED);
1147
1148 tr = TAILQ_FIRST(&qpair->free_tr);
1149 req->qpair = qpair;
1150
1151 if (tr == NULL || qpair->recovery_state != RECOVERY_NONE) {
1152 /*
1153 * No tracker is available, or the qpair is disabled due to
1154 * an in-progress controller-level reset or controller
1155 * failure.
1156 */
1157
1158 if (qpair->ctrlr->is_failed) {
1159 /*
1160 * The controller has failed, so fail the request.
1161 */
1162 nvme_qpair_manual_complete_request(qpair, req,
1163 NVME_SCT_GENERIC, NVME_SC_ABORTED_BY_REQUEST);
1164 } else {
1165 /*
1166 * Put the request on the qpair's request queue to be
1167 * processed when a tracker frees up via a command
1168 * completion or when the controller reset is
1169 * completed.
1170 */
1171 STAILQ_INSERT_TAIL(&qpair->queued_req, req, stailq);
1172 }
1173 return;
1174 }
1175
1176 TAILQ_REMOVE(&qpair->free_tr, tr, tailq);
1177 TAILQ_INSERT_TAIL(&qpair->outstanding_tr, tr, tailq);
1178 if (!qpair->timer_armed)
1179 tr->deadline = SBT_MAX;
1180 tr->req = req;
1181
1182 switch (req->type) {
1183 case NVME_REQUEST_VADDR:
1184 KASSERT(req->payload_size <= qpair->ctrlr->max_xfer_size,
1185 ("payload_size (%d) exceeds max_xfer_size (%d)\n",
1186 req->payload_size, qpair->ctrlr->max_xfer_size));
1187 err = bus_dmamap_load(tr->qpair->dma_tag_payload,
1188 tr->payload_dma_map, req->u.payload, req->payload_size,
1189 nvme_payload_map, tr, 0);
1190 if (err != 0)
1191 nvme_printf(qpair->ctrlr,
1192 "bus_dmamap_load returned 0x%x!\n", err);
1193 break;
1194 case NVME_REQUEST_NULL:
1195 nvme_qpair_submit_tracker(tr->qpair, tr);
1196 break;
1197 case NVME_REQUEST_BIO:
1198 KASSERT(req->u.bio->bio_bcount <= qpair->ctrlr->max_xfer_size,
1199 ("bio->bio_bcount (%jd) exceeds max_xfer_size (%d)\n",
1200 (intmax_t)req->u.bio->bio_bcount,
1201 qpair->ctrlr->max_xfer_size));
1202 err = bus_dmamap_load_bio(tr->qpair->dma_tag_payload,
1203 tr->payload_dma_map, req->u.bio, nvme_payload_map, tr, 0);
1204 if (err != 0)
1205 nvme_printf(qpair->ctrlr,
1206 "bus_dmamap_load_bio returned 0x%x!\n", err);
1207 break;
1208 case NVME_REQUEST_CCB:
1209 err = bus_dmamap_load_ccb(tr->qpair->dma_tag_payload,
1210 tr->payload_dma_map, req->u.payload,
1211 nvme_payload_map, tr, 0);
1212 if (err != 0)
1213 nvme_printf(qpair->ctrlr,
1214 "bus_dmamap_load_ccb returned 0x%x!\n", err);
1215 break;
1216 default:
1217 panic("unknown nvme request type 0x%x\n", req->type);
1218 break;
1219 }
1220
1221 if (err != 0) {
1222 /*
1223 * The dmamap operation failed, so we manually fail the
1224 * tracker here with DATA_TRANSFER_ERROR status.
1225 *
1226 * nvme_qpair_manual_complete_tracker must not be called
1227 * with the qpair lock held.
1228 */
1229 mtx_unlock(&qpair->lock);
1230 nvme_qpair_manual_complete_tracker(tr, NVME_SCT_GENERIC,
1231 NVME_SC_DATA_TRANSFER_ERROR, DO_NOT_RETRY, ERROR_PRINT_ALL);
1232 mtx_lock(&qpair->lock);
1233 }
1234 }
1235
1236 void
nvme_qpair_submit_request(struct nvme_qpair * qpair,struct nvme_request * req)1237 nvme_qpair_submit_request(struct nvme_qpair *qpair, struct nvme_request *req)
1238 {
1239
1240 mtx_lock(&qpair->lock);
1241 _nvme_qpair_submit_request(qpair, req);
1242 mtx_unlock(&qpair->lock);
1243 }
1244
1245 static void
nvme_qpair_enable(struct nvme_qpair * qpair)1246 nvme_qpair_enable(struct nvme_qpair *qpair)
1247 {
1248 mtx_assert(&qpair->lock, MA_OWNED);
1249
1250 qpair->recovery_state = RECOVERY_NONE;
1251 }
1252
1253 void
nvme_qpair_reset(struct nvme_qpair * qpair)1254 nvme_qpair_reset(struct nvme_qpair *qpair)
1255 {
1256
1257 qpair->sq_head = qpair->sq_tail = qpair->cq_head = 0;
1258
1259 /*
1260 * First time through the completion queue, HW will set phase
1261 * bit on completions to 1. So set this to 1 here, indicating
1262 * we're looking for a 1 to know which entries have completed.
1263 * we'll toggle the bit each time when the completion queue
1264 * rolls over.
1265 */
1266 qpair->phase = 1;
1267
1268 memset(qpair->cmd, 0,
1269 qpair->num_entries * sizeof(struct nvme_command));
1270 memset(qpair->cpl, 0,
1271 qpair->num_entries * sizeof(struct nvme_completion));
1272 }
1273
1274 void
nvme_admin_qpair_enable(struct nvme_qpair * qpair)1275 nvme_admin_qpair_enable(struct nvme_qpair *qpair)
1276 {
1277 struct nvme_tracker *tr;
1278 struct nvme_tracker *tr_temp;
1279
1280 /*
1281 * Manually abort each outstanding admin command. Do not retry
1282 * admin commands found here, since they will be left over from
1283 * a controller reset and its likely the context in which the
1284 * command was issued no longer applies.
1285 */
1286 TAILQ_FOREACH_SAFE(tr, &qpair->outstanding_tr, tailq, tr_temp) {
1287 nvme_printf(qpair->ctrlr,
1288 "aborting outstanding admin command\n");
1289 nvme_qpair_manual_complete_tracker(tr, NVME_SCT_GENERIC,
1290 NVME_SC_ABORTED_BY_REQUEST, DO_NOT_RETRY, ERROR_PRINT_ALL);
1291 }
1292
1293 mtx_lock(&qpair->lock);
1294 nvme_qpair_enable(qpair);
1295 mtx_unlock(&qpair->lock);
1296 }
1297
1298 void
nvme_io_qpair_enable(struct nvme_qpair * qpair)1299 nvme_io_qpair_enable(struct nvme_qpair *qpair)
1300 {
1301 STAILQ_HEAD(, nvme_request) temp;
1302 struct nvme_tracker *tr;
1303 struct nvme_tracker *tr_temp;
1304 struct nvme_request *req;
1305
1306 /*
1307 * Manually abort each outstanding I/O. This normally results in a
1308 * retry, unless the retry count on the associated request has
1309 * reached its limit.
1310 */
1311 TAILQ_FOREACH_SAFE(tr, &qpair->outstanding_tr, tailq, tr_temp) {
1312 nvme_printf(qpair->ctrlr, "aborting outstanding i/o\n");
1313 nvme_qpair_manual_complete_tracker(tr, NVME_SCT_GENERIC,
1314 NVME_SC_ABORTED_BY_REQUEST, 0, ERROR_PRINT_NO_RETRY);
1315 }
1316
1317 mtx_lock(&qpair->lock);
1318
1319 nvme_qpair_enable(qpair);
1320
1321 STAILQ_INIT(&temp);
1322 STAILQ_SWAP(&qpair->queued_req, &temp, nvme_request);
1323
1324 while (!STAILQ_EMPTY(&temp)) {
1325 req = STAILQ_FIRST(&temp);
1326 STAILQ_REMOVE_HEAD(&temp, stailq);
1327 nvme_printf(qpair->ctrlr, "resubmitting queued i/o\n");
1328 nvme_qpair_print_command(qpair, &req->cmd);
1329 _nvme_qpair_submit_request(qpair, req);
1330 }
1331
1332 mtx_unlock(&qpair->lock);
1333 }
1334
1335 static void
nvme_qpair_disable(struct nvme_qpair * qpair)1336 nvme_qpair_disable(struct nvme_qpair *qpair)
1337 {
1338 struct nvme_tracker *tr, *tr_temp;
1339
1340 mtx_lock(&qpair->lock);
1341 qpair->recovery_state = RECOVERY_WAITING;
1342 TAILQ_FOREACH_SAFE(tr, &qpair->outstanding_tr, tailq, tr_temp) {
1343 tr->deadline = SBT_MAX;
1344 }
1345 mtx_unlock(&qpair->lock);
1346 }
1347
1348 void
nvme_admin_qpair_disable(struct nvme_qpair * qpair)1349 nvme_admin_qpair_disable(struct nvme_qpair *qpair)
1350 {
1351
1352 nvme_qpair_disable(qpair);
1353 nvme_admin_qpair_abort_aers(qpair);
1354 }
1355
1356 void
nvme_io_qpair_disable(struct nvme_qpair * qpair)1357 nvme_io_qpair_disable(struct nvme_qpair *qpair)
1358 {
1359
1360 nvme_qpair_disable(qpair);
1361 }
1362
1363 void
nvme_qpair_fail(struct nvme_qpair * qpair)1364 nvme_qpair_fail(struct nvme_qpair *qpair)
1365 {
1366 struct nvme_tracker *tr;
1367 struct nvme_request *req;
1368
1369 if (!mtx_initialized(&qpair->lock))
1370 return;
1371
1372 mtx_lock(&qpair->lock);
1373
1374 while (!STAILQ_EMPTY(&qpair->queued_req)) {
1375 req = STAILQ_FIRST(&qpair->queued_req);
1376 STAILQ_REMOVE_HEAD(&qpair->queued_req, stailq);
1377 nvme_printf(qpair->ctrlr, "failing queued i/o\n");
1378 mtx_unlock(&qpair->lock);
1379 nvme_qpair_manual_complete_request(qpair, req, NVME_SCT_GENERIC,
1380 NVME_SC_ABORTED_BY_REQUEST);
1381 mtx_lock(&qpair->lock);
1382 }
1383
1384 /* Manually abort each outstanding I/O. */
1385 while (!TAILQ_EMPTY(&qpair->outstanding_tr)) {
1386 tr = TAILQ_FIRST(&qpair->outstanding_tr);
1387 /*
1388 * Do not remove the tracker. The abort_tracker path will
1389 * do that for us.
1390 */
1391 nvme_printf(qpair->ctrlr, "failing outstanding i/o\n");
1392 mtx_unlock(&qpair->lock);
1393 nvme_qpair_manual_complete_tracker(tr, NVME_SCT_GENERIC,
1394 NVME_SC_ABORTED_BY_REQUEST, DO_NOT_RETRY, ERROR_PRINT_ALL);
1395 mtx_lock(&qpair->lock);
1396 }
1397
1398 mtx_unlock(&qpair->lock);
1399 }
1400