1 /*-
2 * Copyright (c) 2016 Netflix, Inc.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer,
9 * without modification, immediately at the beginning of the file.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 */
25
26 #include <sys/cdefs.h>
27 #include <sys/param.h>
28 #include <sys/systm.h>
29 #include <sys/buf.h>
30 #include <sys/bus.h>
31 #include <sys/conf.h>
32 #include <sys/ioccom.h>
33 #include <sys/malloc.h>
34 #include <sys/proc.h>
35 #include <sys/smp.h>
36
37 #include <cam/cam.h>
38 #include <cam/cam_ccb.h>
39 #include <cam/cam_sim.h>
40 #include <cam/cam_xpt_sim.h>
41 #include <cam/cam_debug.h>
42
43 #include <dev/pci/pcivar.h>
44 #include <dev/pci/pcireg.h>
45
46 #include "nvme_private.h"
47
48 #define ccb_accb_ptr spriv_ptr0
49 #define ccb_ctrlr_ptr spriv_ptr1
50 static void nvme_sim_action(struct cam_sim *sim, union ccb *ccb);
51 static void nvme_sim_poll(struct cam_sim *sim);
52
53 #define sim2softc(sim) ((struct nvme_sim_softc *)cam_sim_softc(sim))
54 #define sim2ctrlr(sim) (sim2softc(sim)->s_ctrlr)
55
56 struct nvme_sim_softc
57 {
58 struct nvme_controller *s_ctrlr;
59 struct cam_sim *s_sim;
60 struct cam_path *s_path;
61 };
62
63 static void
nvme_sim_nvmeio_done(void * ccb_arg,const struct nvme_completion * cpl)64 nvme_sim_nvmeio_done(void *ccb_arg, const struct nvme_completion *cpl)
65 {
66 union ccb *ccb = (union ccb *)ccb_arg;
67
68 /*
69 * Let the periph know the completion, and let it sort out what
70 * it means. Make our best guess, though for the status code.
71 */
72 memcpy(&ccb->nvmeio.cpl, cpl, sizeof(*cpl));
73 ccb->ccb_h.status &= ~CAM_SIM_QUEUED;
74 if (nvme_completion_is_error(cpl)) {
75 ccb->ccb_h.status = CAM_REQ_CMP_ERR;
76 xpt_done(ccb);
77 } else {
78 ccb->ccb_h.status = CAM_REQ_CMP;
79 xpt_done_direct(ccb);
80 }
81 }
82
83 static void
nvme_sim_nvmeio(struct cam_sim * sim,union ccb * ccb)84 nvme_sim_nvmeio(struct cam_sim *sim, union ccb *ccb)
85 {
86 struct ccb_nvmeio *nvmeio = &ccb->nvmeio;
87 struct nvme_request *req;
88 void *payload;
89 uint32_t size;
90 struct nvme_controller *ctrlr;
91
92 ctrlr = sim2ctrlr(sim);
93 payload = nvmeio->data_ptr;
94 size = nvmeio->dxfer_len;
95 /* SG LIST ??? */
96 if ((nvmeio->ccb_h.flags & CAM_DATA_MASK) == CAM_DATA_BIO)
97 req = nvme_allocate_request_bio((struct bio *)payload,
98 nvme_sim_nvmeio_done, ccb);
99 else if ((nvmeio->ccb_h.flags & CAM_DATA_SG) == CAM_DATA_SG)
100 req = nvme_allocate_request_ccb(ccb, nvme_sim_nvmeio_done, ccb);
101 else if (payload == NULL)
102 req = nvme_allocate_request_null(nvme_sim_nvmeio_done, ccb);
103 else
104 req = nvme_allocate_request_vaddr(payload, size,
105 nvme_sim_nvmeio_done, ccb);
106
107 if (req == NULL) {
108 nvmeio->ccb_h.status = CAM_RESRC_UNAVAIL;
109 xpt_done(ccb);
110 return;
111 }
112 ccb->ccb_h.status |= CAM_SIM_QUEUED;
113
114 memcpy(&req->cmd, &ccb->nvmeio.cmd, sizeof(ccb->nvmeio.cmd));
115
116 if (ccb->ccb_h.func_code == XPT_NVME_IO)
117 nvme_ctrlr_submit_io_request(ctrlr, req);
118 else
119 nvme_ctrlr_submit_admin_request(ctrlr, req);
120 }
121
122 static uint32_t
nvme_link_kBps(struct nvme_controller * ctrlr)123 nvme_link_kBps(struct nvme_controller *ctrlr)
124 {
125 uint32_t speed, lanes, link[] = { 1, 250000, 500000, 985000, 1970000 };
126 uint32_t status;
127
128 status = pcie_read_config(ctrlr->dev, PCIER_LINK_STA, 2);
129 speed = status & PCIEM_LINK_STA_SPEED;
130 lanes = (status & PCIEM_LINK_STA_WIDTH) >> 4;
131 /*
132 * Failsafe on link speed indicator. If it is insane report the number of
133 * lanes as the speed. Not 100% accurate, but may be diagnostic.
134 */
135 if (speed >= nitems(link))
136 speed = 0;
137 return link[speed] * lanes;
138 }
139
140 static void
nvme_sim_action(struct cam_sim * sim,union ccb * ccb)141 nvme_sim_action(struct cam_sim *sim, union ccb *ccb)
142 {
143 struct nvme_controller *ctrlr;
144
145 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE,
146 ("nvme_sim_action: func= %#x\n",
147 ccb->ccb_h.func_code));
148
149 ctrlr = sim2ctrlr(sim);
150
151 switch (ccb->ccb_h.func_code) {
152 case XPT_CALC_GEOMETRY: /* Calculate Geometry Totally nuts ? XXX */
153 /*
154 * Only meaningful for old-school SCSI disks since only the SCSI
155 * da driver generates them. Reject all these that slip through.
156 */
157 /*FALLTHROUGH*/
158 case XPT_ABORT: /* Abort the specified CCB */
159 ccb->ccb_h.status = CAM_REQ_INVALID;
160 break;
161 case XPT_SET_TRAN_SETTINGS:
162 /*
163 * NVMe doesn't really have different transfer settings, but
164 * other parts of CAM think failure here is a big deal.
165 */
166 ccb->ccb_h.status = CAM_REQ_CMP;
167 break;
168 case XPT_PATH_INQ: /* Path routing inquiry */
169 {
170 struct ccb_pathinq *cpi = &ccb->cpi;
171 device_t dev = ctrlr->dev;
172
173 /*
174 * For devices that are reported as children of the AHCI
175 * controller, which has no access to the config space for this
176 * controller, report the AHCI controller's data.
177 */
178 if (ctrlr->quirks & QUIRK_AHCI)
179 dev = device_get_parent(dev);
180 cpi->version_num = 1;
181 cpi->hba_inquiry = 0;
182 cpi->target_sprt = 0;
183 cpi->hba_misc = PIM_UNMAPPED | PIM_NOSCAN;
184 cpi->hba_eng_cnt = 0;
185 cpi->max_target = 0;
186 cpi->max_lun = ctrlr->cdata.nn;
187 cpi->maxio = ctrlr->max_xfer_size;
188 cpi->initiator_id = 0;
189 cpi->bus_id = cam_sim_bus(sim);
190 cpi->base_transfer_speed = nvme_link_kBps(ctrlr);
191 strlcpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
192 strlcpy(cpi->hba_vid, "NVMe", HBA_IDLEN);
193 strlcpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
194 cpi->unit_number = cam_sim_unit(sim);
195 cpi->transport = XPORT_NVME; /* XXX XPORT_PCIE ? */
196 cpi->transport_version = nvme_mmio_read_4(ctrlr, vs);
197 cpi->protocol = PROTO_NVME;
198 cpi->protocol_version = nvme_mmio_read_4(ctrlr, vs);
199 cpi->xport_specific.nvme.nsid = xpt_path_lun_id(ccb->ccb_h.path);
200 cpi->xport_specific.nvme.domain = pci_get_domain(dev);
201 cpi->xport_specific.nvme.bus = pci_get_bus(dev);
202 cpi->xport_specific.nvme.slot = pci_get_slot(dev);
203 cpi->xport_specific.nvme.function = pci_get_function(dev);
204 cpi->xport_specific.nvme.extra = 0;
205 strncpy(cpi->xport_specific.nvme.dev_name, device_get_nameunit(dev),
206 sizeof(cpi->xport_specific.nvme.dev_name));
207 cpi->hba_vendor = pci_get_vendor(dev);
208 cpi->hba_device = pci_get_device(dev);
209 cpi->hba_subvendor = pci_get_subvendor(dev);
210 cpi->hba_subdevice = pci_get_subdevice(dev);
211 cpi->ccb_h.status = CAM_REQ_CMP;
212 break;
213 }
214 case XPT_GET_TRAN_SETTINGS: /* Get transport settings */
215 {
216 struct ccb_trans_settings *cts;
217 struct ccb_trans_settings_nvme *nvmep;
218 struct ccb_trans_settings_nvme *nvmex;
219 device_t dev;
220 uint32_t status, caps, flags;
221
222 dev = ctrlr->dev;
223 cts = &ccb->cts;
224 nvmex = &cts->xport_specific.nvme;
225 nvmep = &cts->proto_specific.nvme;
226
227 nvmex->spec = nvme_mmio_read_4(ctrlr, vs);
228 nvmex->valid = CTS_NVME_VALID_SPEC;
229 if ((ctrlr->quirks & QUIRK_AHCI) == 0) {
230 /* AHCI redirect makes it impossible to query */
231 status = pcie_read_config(dev, PCIER_LINK_STA, 2);
232 caps = pcie_read_config(dev, PCIER_LINK_CAP, 2);
233 flags = pcie_read_config(dev, PCIER_FLAGS, 2);
234 if ((flags & PCIEM_FLAGS_TYPE) == PCIEM_TYPE_ENDPOINT) {
235 nvmex->valid |= CTS_NVME_VALID_LINK;
236 nvmex->speed = status & PCIEM_LINK_STA_SPEED;
237 nvmex->lanes = (status & PCIEM_LINK_STA_WIDTH) >> 4;
238 nvmex->max_speed = caps & PCIEM_LINK_CAP_MAX_SPEED;
239 nvmex->max_lanes = (caps & PCIEM_LINK_CAP_MAX_WIDTH) >> 4;
240 }
241 }
242
243 /* XXX these should be something else maybe ? */
244 nvmep->valid = 1;
245 nvmep->spec = nvmex->spec;
246
247 cts->transport = XPORT_NVME;
248 cts->protocol = PROTO_NVME;
249 cts->ccb_h.status = CAM_REQ_CMP;
250 break;
251 }
252 case XPT_TERM_IO: /* Terminate the I/O process */
253 /*
254 * every driver handles this, but nothing generates it. Assume
255 * it's OK to just say 'that worked'.
256 */
257 /*FALLTHROUGH*/
258 case XPT_RESET_DEV: /* Bus Device Reset the specified device */
259 case XPT_RESET_BUS: /* Reset the specified bus */
260 /*
261 * NVMe doesn't really support physically resetting the bus. It's part
262 * of the bus scanning dance, so return sucess to tell the process to
263 * proceed.
264 */
265 ccb->ccb_h.status = CAM_REQ_CMP;
266 break;
267 case XPT_NVME_IO: /* Execute the requested I/O operation */
268 case XPT_NVME_ADMIN: /* or Admin operation */
269 if (ctrlr->is_failed) {
270 ccb->ccb_h.status = CAM_DEV_NOT_THERE;
271 break;
272 }
273 nvme_sim_nvmeio(sim, ccb);
274 return; /* no done */
275 default:
276 ccb->ccb_h.status = CAM_REQ_INVALID;
277 break;
278 }
279 xpt_done(ccb);
280 }
281
282 static void
nvme_sim_poll(struct cam_sim * sim)283 nvme_sim_poll(struct cam_sim *sim)
284 {
285
286 nvme_ctrlr_poll(sim2ctrlr(sim));
287 }
288
289 static void *
nvme_sim_new_controller(struct nvme_controller * ctrlr)290 nvme_sim_new_controller(struct nvme_controller *ctrlr)
291 {
292 struct nvme_sim_softc *sc;
293 struct cam_devq *devq;
294 int max_trans;
295
296 max_trans = ctrlr->max_hw_pend_io;
297 devq = cam_simq_alloc(max_trans);
298 if (devq == NULL)
299 return (NULL);
300
301 sc = malloc(sizeof(*sc), M_NVME, M_ZERO | M_WAITOK);
302 sc->s_ctrlr = ctrlr;
303
304 sc->s_sim = cam_sim_alloc(nvme_sim_action, nvme_sim_poll,
305 "nvme", sc, device_get_unit(ctrlr->dev),
306 NULL, max_trans, max_trans, devq);
307 if (sc->s_sim == NULL) {
308 printf("Failed to allocate a sim\n");
309 cam_simq_free(devq);
310 goto err1;
311 }
312 if (xpt_bus_register(sc->s_sim, ctrlr->dev, 0) != CAM_SUCCESS) {
313 printf("Failed to create a bus\n");
314 goto err2;
315 }
316 if (xpt_create_path(&sc->s_path, /*periph*/NULL, cam_sim_path(sc->s_sim),
317 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
318 printf("Failed to create a path\n");
319 goto err3;
320 }
321
322 return (sc);
323
324 err3:
325 xpt_bus_deregister(cam_sim_path(sc->s_sim));
326 err2:
327 cam_sim_free(sc->s_sim, /*free_devq*/TRUE);
328 err1:
329 free(sc, M_NVME);
330 return (NULL);
331 }
332
333 static void *
nvme_sim_ns_change(struct nvme_namespace * ns,void * sc_arg)334 nvme_sim_ns_change(struct nvme_namespace *ns, void *sc_arg)
335 {
336 struct nvme_sim_softc *sc = sc_arg;
337 union ccb *ccb;
338
339 ccb = xpt_alloc_ccb_nowait();
340 if (ccb == NULL) {
341 printf("unable to alloc CCB for rescan\n");
342 return (NULL);
343 }
344
345 /*
346 * We map the NVMe namespace idea onto the CAM unit LUN. For
347 * each new namespace, we create a new CAM path for it. We then
348 * rescan the path to get it to enumerate.
349 */
350 if (xpt_create_path(&ccb->ccb_h.path, /*periph*/NULL,
351 cam_sim_path(sc->s_sim), 0, ns->id) != CAM_REQ_CMP) {
352 printf("unable to create path for rescan\n");
353 xpt_free_ccb(ccb);
354 return (NULL);
355 }
356 xpt_rescan(ccb);
357
358 return (sc_arg);
359 }
360
361 static void
nvme_sim_controller_fail(void * ctrlr_arg)362 nvme_sim_controller_fail(void *ctrlr_arg)
363 {
364 struct nvme_sim_softc *sc = ctrlr_arg;
365
366 xpt_async(AC_LOST_DEVICE, sc->s_path, NULL);
367 xpt_free_path(sc->s_path);
368 xpt_bus_deregister(cam_sim_path(sc->s_sim));
369 cam_sim_free(sc->s_sim, /*free_devq*/TRUE);
370 free(sc, M_NVME);
371 }
372
373 struct nvme_consumer *consumer_cookie;
374
375 static void
nvme_sim_init(void)376 nvme_sim_init(void)
377 {
378 if (nvme_use_nvd)
379 return;
380
381 consumer_cookie = nvme_register_consumer(nvme_sim_ns_change,
382 nvme_sim_new_controller, NULL, nvme_sim_controller_fail);
383 }
384
385 SYSINIT(nvme_sim_register, SI_SUB_DRIVERS, SI_ORDER_ANY,
386 nvme_sim_init, NULL);
387
388 static void
nvme_sim_uninit(void)389 nvme_sim_uninit(void)
390 {
391 if (nvme_use_nvd)
392 return;
393 /* XXX Cleanup */
394
395 nvme_unregister_consumer(consumer_cookie);
396 }
397
398 SYSUNINIT(nvme_sim_unregister, SI_SUB_DRIVERS, SI_ORDER_ANY,
399 nvme_sim_uninit, NULL);
400