1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2013-2014 Qlogic Corporation
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
21 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27 * POSSIBILITY OF SUCH DAMAGE.
28 */
29
30 /*
31 * File: qls_dump.c
32 */
33 #include <sys/cdefs.h>
34 #include "qls_os.h"
35 #include "qls_hw.h"
36 #include "qls_def.h"
37 #include "qls_glbl.h"
38 #include "qls_dump.h"
39
40 qls_mpi_coredump_t ql_mpi_coredump;
41
42 #define Q81_CORE_SEG_NUM 1
43 #define Q81_TEST_LOGIC_SEG_NUM 2
44 #define Q81_RMII_SEG_NUM 3
45 #define Q81_FCMAC1_SEG_NUM 4
46 #define Q81_FCMAC2_SEG_NUM 5
47 #define Q81_FC1_MBOX_SEG_NUM 6
48 #define Q81_IDE_SEG_NUM 7
49 #define Q81_NIC1_MBOX_SEG_NUM 8
50 #define Q81_SMBUS_SEG_NUM 9
51 #define Q81_FC2_MBOX_SEG_NUM 10
52 #define Q81_NIC2_MBOX_SEG_NUM 11
53 #define Q81_I2C_SEG_NUM 12
54 #define Q81_MEMC_SEG_NUM 13
55 #define Q81_PBUS_SEG_NUM 14
56 #define Q81_MDE_SEG_NUM 15
57 #define Q81_NIC1_CONTROL_SEG_NUM 16
58 #define Q81_NIC2_CONTROL_SEG_NUM 17
59 #define Q81_NIC1_XGMAC_SEG_NUM 18
60 #define Q81_NIC2_XGMAC_SEG_NUM 19
61 #define Q81_WCS_RAM_SEG_NUM 20
62 #define Q81_MEMC_RAM_SEG_NUM 21
63 #define Q81_XAUI1_AN_SEG_NUM 22
64 #define Q81_XAUI1_HSS_PCS_SEG_NUM 23
65 #define Q81_XFI1_AN_SEG_NUM 24
66 #define Q81_XFI1_TRAIN_SEG_NUM 25
67 #define Q81_XFI1_HSS_PCS_SEG_NUM 26
68 #define Q81_XFI1_HSS_TX_SEG_NUM 27
69 #define Q81_XFI1_HSS_RX_SEG_NUM 28
70 #define Q81_XFI1_HSS_PLL_SEG_NUM 29
71 #define Q81_INTR_STATES_SEG_NUM 31
72 #define Q81_ETS_SEG_NUM 34
73 #define Q81_PROBE_DUMP_SEG_NUM 35
74 #define Q81_ROUTING_INDEX_SEG_NUM 36
75 #define Q81_MAC_PROTOCOL_SEG_NUM 37
76 #define Q81_XAUI2_AN_SEG_NUM 38
77 #define Q81_XAUI2_HSS_PCS_SEG_NUM 39
78 #define Q81_XFI2_AN_SEG_NUM 40
79 #define Q81_XFI2_TRAIN_SEG_NUM 41
80 #define Q81_XFI2_HSS_PCS_SEG_NUM 42
81 #define Q81_XFI2_HSS_TX_SEG_NUM 43
82 #define Q81_XFI2_HSS_RX_SEG_NUM 44
83 #define Q81_XFI2_HSS_PLL_SEG_NUM 45
84 #define Q81_WQC1_SEG_NUM 46
85 #define Q81_CQC1_SEG_NUM 47
86 #define Q81_WQC2_SEG_NUM 48
87 #define Q81_CQC2_SEG_NUM 49
88 #define Q81_SEM_REGS_SEG_NUM 50
89
90 enum
91 {
92 Q81_PAUSE_SRC_LO = 0x00000100,
93 Q81_PAUSE_SRC_HI = 0x00000104,
94 Q81_GLOBAL_CFG = 0x00000108,
95 Q81_GLOBAL_CFG_RESET = (1 << 0), /*Control*/
96 Q81_GLOBAL_CFG_JUMBO = (1 << 6), /*Control*/
97 Q81_GLOBAL_CFG_TX_STAT_EN = (1 << 10), /*Control*/
98 Q81_GLOBAL_CFG_RX_STAT_EN = (1 << 11), /*Control*/
99 Q81_TX_CFG = 0x0000010c,
100 Q81_TX_CFG_RESET = (1 << 0), /*Control*/
101 Q81_TX_CFG_EN = (1 << 1), /*Control*/
102 Q81_TX_CFG_PREAM = (1 << 2), /*Control*/
103 Q81_RX_CFG = 0x00000110,
104 Q81_RX_CFG_RESET = (1 << 0), /*Control*/
105 Q81_RX_CFG_EN = (1 << 1), /*Control*/
106 Q81_RX_CFG_PREAM = (1 << 2), /*Control*/
107 Q81_FLOW_CTL = 0x0000011c,
108 Q81_PAUSE_OPCODE = 0x00000120,
109 Q81_PAUSE_TIMER = 0x00000124,
110 Q81_PAUSE_FRM_DEST_LO = 0x00000128,
111 Q81_PAUSE_FRM_DEST_HI = 0x0000012c,
112 Q81_MAC_TX_PARAMS = 0x00000134,
113 Q81_MAC_TX_PARAMS_JUMBO = (1U << 31), /*Control*/
114 Q81_MAC_TX_PARAMS_SIZE_SHIFT = 16, /*Control*/
115 Q81_MAC_RX_PARAMS = 0x00000138,
116 Q81_MAC_SYS_INT = 0x00000144,
117 Q81_MAC_SYS_INT_MASK = 0x00000148,
118 Q81_MAC_MGMT_INT = 0x0000014c,
119 Q81_MAC_MGMT_IN_MASK = 0x00000150,
120 Q81_EXT_ARB_MODE = 0x000001fc,
121 Q81_TX_PKTS = 0x00000200,
122 Q81_TX_PKTS_LO = 0x00000204,
123 Q81_TX_BYTES = 0x00000208,
124 Q81_TX_BYTES_LO = 0x0000020C,
125 Q81_TX_MCAST_PKTS = 0x00000210,
126 Q81_TX_MCAST_PKTS_LO = 0x00000214,
127 Q81_TX_BCAST_PKTS = 0x00000218,
128 Q81_TX_BCAST_PKTS_LO = 0x0000021C,
129 Q81_TX_UCAST_PKTS = 0x00000220,
130 Q81_TX_UCAST_PKTS_LO = 0x00000224,
131 Q81_TX_CTL_PKTS = 0x00000228,
132 Q81_TX_CTL_PKTS_LO = 0x0000022c,
133 Q81_TX_PAUSE_PKTS = 0x00000230,
134 Q81_TX_PAUSE_PKTS_LO = 0x00000234,
135 Q81_TX_64_PKT = 0x00000238,
136 Q81_TX_64_PKT_LO = 0x0000023c,
137 Q81_TX_65_TO_127_PKT = 0x00000240,
138 Q81_TX_65_TO_127_PKT_LO = 0x00000244,
139 Q81_TX_128_TO_255_PKT = 0x00000248,
140 Q81_TX_128_TO_255_PKT_LO = 0x0000024c,
141 Q81_TX_256_511_PKT = 0x00000250,
142 Q81_TX_256_511_PKT_LO = 0x00000254,
143 Q81_TX_512_TO_1023_PKT = 0x00000258,
144 Q81_TX_512_TO_1023_PKT_LO = 0x0000025c,
145 Q81_TX_1024_TO_1518_PKT = 0x00000260,
146 Q81_TX_1024_TO_1518_PKT_LO = 0x00000264,
147 Q81_TX_1519_TO_MAX_PKT = 0x00000268,
148 Q81_TX_1519_TO_MAX_PKT_LO = 0x0000026c,
149 Q81_TX_UNDERSIZE_PKT = 0x00000270,
150 Q81_TX_UNDERSIZE_PKT_LO = 0x00000274,
151 Q81_TX_OVERSIZE_PKT = 0x00000278,
152 Q81_TX_OVERSIZE_PKT_LO = 0x0000027c,
153 Q81_RX_HALF_FULL_DET = 0x000002a0,
154 Q81_TX_HALF_FULL_DET_LO = 0x000002a4,
155 Q81_RX_OVERFLOW_DET = 0x000002a8,
156 Q81_TX_OVERFLOW_DET_LO = 0x000002ac,
157 Q81_RX_HALF_FULL_MASK = 0x000002b0,
158 Q81_TX_HALF_FULL_MASK_LO = 0x000002b4,
159 Q81_RX_OVERFLOW_MASK = 0x000002b8,
160 Q81_TX_OVERFLOW_MASK_LO = 0x000002bc,
161 Q81_STAT_CNT_CTL = 0x000002c0,
162 Q81_STAT_CNT_CTL_CLEAR_TX = (1 << 0), /*Control*/
163 Q81_STAT_CNT_CTL_CLEAR_RX = (1 << 1), /*Control*/
164 Q81_AUX_RX_HALF_FULL_DET = 0x000002d0,
165 Q81_AUX_TX_HALF_FULL_DET = 0x000002d4,
166 Q81_AUX_RX_OVERFLOW_DET = 0x000002d8,
167 Q81_AUX_TX_OVERFLOW_DET = 0x000002dc,
168 Q81_AUX_RX_HALF_FULL_MASK = 0x000002f0,
169 Q81_AUX_TX_HALF_FULL_MASK = 0x000002f4,
170 Q81_AUX_RX_OVERFLOW_MASK = 0x000002f8,
171 Q81_AUX_TX_OVERFLOW_MASK = 0x000002fc,
172 Q81_RX_BYTES = 0x00000300,
173 Q81_RX_BYTES_LO = 0x00000304,
174 Q81_RX_BYTES_OK = 0x00000308,
175 Q81_RX_BYTES_OK_LO = 0x0000030c,
176 Q81_RX_PKTS = 0x00000310,
177 Q81_RX_PKTS_LO = 0x00000314,
178 Q81_RX_PKTS_OK = 0x00000318,
179 Q81_RX_PKTS_OK_LO = 0x0000031c,
180 Q81_RX_BCAST_PKTS = 0x00000320,
181 Q81_RX_BCAST_PKTS_LO = 0x00000324,
182 Q81_RX_MCAST_PKTS = 0x00000328,
183 Q81_RX_MCAST_PKTS_LO = 0x0000032c,
184 Q81_RX_UCAST_PKTS = 0x00000330,
185 Q81_RX_UCAST_PKTS_LO = 0x00000334,
186 Q81_RX_UNDERSIZE_PKTS = 0x00000338,
187 Q81_RX_UNDERSIZE_PKTS_LO = 0x0000033c,
188 Q81_RX_OVERSIZE_PKTS = 0x00000340,
189 Q81_RX_OVERSIZE_PKTS_LO = 0x00000344,
190 Q81_RX_JABBER_PKTS = 0x00000348,
191 Q81_RX_JABBER_PKTS_LO = 0x0000034c,
192 Q81_RX_UNDERSIZE_FCERR_PKTS = 0x00000350,
193 Q81_RX_UNDERSIZE_FCERR_PKTS_LO = 0x00000354,
194 Q81_RX_DROP_EVENTS = 0x00000358,
195 Q81_RX_DROP_EVENTS_LO = 0x0000035c,
196 Q81_RX_FCERR_PKTS = 0x00000360,
197 Q81_RX_FCERR_PKTS_LO = 0x00000364,
198 Q81_RX_ALIGN_ERR = 0x00000368,
199 Q81_RX_ALIGN_ERR_LO = 0x0000036c,
200 Q81_RX_SYMBOL_ERR = 0x00000370,
201 Q81_RX_SYMBOL_ERR_LO = 0x00000374,
202 Q81_RX_MAC_ERR = 0x00000378,
203 Q81_RX_MAC_ERR_LO = 0x0000037c,
204 Q81_RX_CTL_PKTS = 0x00000380,
205 Q81_RX_CTL_PKTS_LO = 0x00000384,
206 Q81_RX_PAUSE_PKTS = 0x00000388,
207 Q81_RX_PAUSE_PKTS_LO = 0x0000038c,
208 Q81_RX_64_PKTS = 0x00000390,
209 Q81_RX_64_PKTS_LO = 0x00000394,
210 Q81_RX_65_TO_127_PKTS = 0x00000398,
211 Q81_RX_65_TO_127_PKTS_LO = 0x0000039c,
212 Q81_RX_128_255_PKTS = 0x000003a0,
213 Q81_RX_128_255_PKTS_LO = 0x000003a4,
214 Q81_RX_256_511_PKTS = 0x000003a8,
215 Q81_RX_256_511_PKTS_LO = 0x000003ac,
216 Q81_RX_512_TO_1023_PKTS = 0x000003b0,
217 Q81_RX_512_TO_1023_PKTS_LO = 0x000003b4,
218 Q81_RX_1024_TO_1518_PKTS = 0x000003b8,
219 Q81_RX_1024_TO_1518_PKTS_LO = 0x000003bc,
220 Q81_RX_1519_TO_MAX_PKTS = 0x000003c0,
221 Q81_RX_1519_TO_MAX_PKTS_LO = 0x000003c4,
222 Q81_RX_LEN_ERR_PKTS = 0x000003c8,
223 Q81_RX_LEN_ERR_PKTS_LO = 0x000003cc,
224 Q81_MDIO_TX_DATA = 0x00000400,
225 Q81_MDIO_RX_DATA = 0x00000410,
226 Q81_MDIO_CMD = 0x00000420,
227 Q81_MDIO_PHY_ADDR = 0x00000430,
228 Q81_MDIO_PORT = 0x00000440,
229 Q81_MDIO_STATUS = 0x00000450,
230 Q81_TX_CBFC_PAUSE_FRAMES0 = 0x00000500,
231 Q81_TX_CBFC_PAUSE_FRAMES0_LO = 0x00000504,
232 Q81_TX_CBFC_PAUSE_FRAMES1 = 0x00000508,
233 Q81_TX_CBFC_PAUSE_FRAMES1_LO = 0x0000050C,
234 Q81_TX_CBFC_PAUSE_FRAMES2 = 0x00000510,
235 Q81_TX_CBFC_PAUSE_FRAMES2_LO = 0x00000514,
236 Q81_TX_CBFC_PAUSE_FRAMES3 = 0x00000518,
237 Q81_TX_CBFC_PAUSE_FRAMES3_LO = 0x0000051C,
238 Q81_TX_CBFC_PAUSE_FRAMES4 = 0x00000520,
239 Q81_TX_CBFC_PAUSE_FRAMES4_LO = 0x00000524,
240 Q81_TX_CBFC_PAUSE_FRAMES5 = 0x00000528,
241 Q81_TX_CBFC_PAUSE_FRAMES5_LO = 0x0000052C,
242 Q81_TX_CBFC_PAUSE_FRAMES6 = 0x00000530,
243 Q81_TX_CBFC_PAUSE_FRAMES6_LO = 0x00000534,
244 Q81_TX_CBFC_PAUSE_FRAMES7 = 0x00000538,
245 Q81_TX_CBFC_PAUSE_FRAMES7_LO = 0x0000053C,
246 Q81_TX_FCOE_PKTS = 0x00000540,
247 Q81_TX_FCOE_PKTS_LO = 0x00000544,
248 Q81_TX_MGMT_PKTS = 0x00000548,
249 Q81_TX_MGMT_PKTS_LO = 0x0000054C,
250 Q81_RX_CBFC_PAUSE_FRAMES0 = 0x00000568,
251 Q81_RX_CBFC_PAUSE_FRAMES0_LO = 0x0000056C,
252 Q81_RX_CBFC_PAUSE_FRAMES1 = 0x00000570,
253 Q81_RX_CBFC_PAUSE_FRAMES1_LO = 0x00000574,
254 Q81_RX_CBFC_PAUSE_FRAMES2 = 0x00000578,
255 Q81_RX_CBFC_PAUSE_FRAMES2_LO = 0x0000057C,
256 Q81_RX_CBFC_PAUSE_FRAMES3 = 0x00000580,
257 Q81_RX_CBFC_PAUSE_FRAMES3_LO = 0x00000584,
258 Q81_RX_CBFC_PAUSE_FRAMES4 = 0x00000588,
259 Q81_RX_CBFC_PAUSE_FRAMES4_LO = 0x0000058C,
260 Q81_RX_CBFC_PAUSE_FRAMES5 = 0x00000590,
261 Q81_RX_CBFC_PAUSE_FRAMES5_LO = 0x00000594,
262 Q81_RX_CBFC_PAUSE_FRAMES6 = 0x00000598,
263 Q81_RX_CBFC_PAUSE_FRAMES6_LO = 0x0000059C,
264 Q81_RX_CBFC_PAUSE_FRAMES7 = 0x000005A0,
265 Q81_RX_CBFC_PAUSE_FRAMES7_LO = 0x000005A4,
266 Q81_RX_FCOE_PKTS = 0x000005A8,
267 Q81_RX_FCOE_PKTS_LO = 0x000005AC,
268 Q81_RX_MGMT_PKTS = 0x000005B0,
269 Q81_RX_MGMT_PKTS_LO = 0x000005B4,
270 Q81_RX_NIC_FIFO_DROP = 0x000005B8,
271 Q81_RX_NIC_FIFO_DROP_LO = 0x000005BC,
272 Q81_RX_FCOE_FIFO_DROP = 0x000005C0,
273 Q81_RX_FCOE_FIFO_DROP_LO = 0x000005C4,
274 Q81_RX_MGMT_FIFO_DROP = 0x000005C8,
275 Q81_RX_MGMT_FIFO_DROP_LO = 0x000005CC,
276 Q81_RX_PKTS_PRIORITY0 = 0x00000600,
277 Q81_RX_PKTS_PRIORITY0_LO = 0x00000604,
278 Q81_RX_PKTS_PRIORITY1 = 0x00000608,
279 Q81_RX_PKTS_PRIORITY1_LO = 0x0000060C,
280 Q81_RX_PKTS_PRIORITY2 = 0x00000610,
281 Q81_RX_PKTS_PRIORITY2_LO = 0x00000614,
282 Q81_RX_PKTS_PRIORITY3 = 0x00000618,
283 Q81_RX_PKTS_PRIORITY3_LO = 0x0000061C,
284 Q81_RX_PKTS_PRIORITY4 = 0x00000620,
285 Q81_RX_PKTS_PRIORITY4_LO = 0x00000624,
286 Q81_RX_PKTS_PRIORITY5 = 0x00000628,
287 Q81_RX_PKTS_PRIORITY5_LO = 0x0000062C,
288 Q81_RX_PKTS_PRIORITY6 = 0x00000630,
289 Q81_RX_PKTS_PRIORITY6_LO = 0x00000634,
290 Q81_RX_PKTS_PRIORITY7 = 0x00000638,
291 Q81_RX_PKTS_PRIORITY7_LO = 0x0000063C,
292 Q81_RX_OCTETS_PRIORITY0 = 0x00000640,
293 Q81_RX_OCTETS_PRIORITY0_LO = 0x00000644,
294 Q81_RX_OCTETS_PRIORITY1 = 0x00000648,
295 Q81_RX_OCTETS_PRIORITY1_LO = 0x0000064C,
296 Q81_RX_OCTETS_PRIORITY2 = 0x00000650,
297 Q81_RX_OCTETS_PRIORITY2_LO = 0x00000654,
298 Q81_RX_OCTETS_PRIORITY3 = 0x00000658,
299 Q81_RX_OCTETS_PRIORITY3_LO = 0x0000065C,
300 Q81_RX_OCTETS_PRIORITY4 = 0x00000660,
301 Q81_RX_OCTETS_PRIORITY4_LO = 0x00000664,
302 Q81_RX_OCTETS_PRIORITY5 = 0x00000668,
303 Q81_RX_OCTETS_PRIORITY5_LO = 0x0000066C,
304 Q81_RX_OCTETS_PRIORITY6 = 0x00000670,
305 Q81_RX_OCTETS_PRIORITY6_LO = 0x00000674,
306 Q81_RX_OCTETS_PRIORITY7 = 0x00000678,
307 Q81_RX_OCTETS_PRIORITY7_LO = 0x0000067C,
308 Q81_TX_PKTS_PRIORITY0 = 0x00000680,
309 Q81_TX_PKTS_PRIORITY0_LO = 0x00000684,
310 Q81_TX_PKTS_PRIORITY1 = 0x00000688,
311 Q81_TX_PKTS_PRIORITY1_LO = 0x0000068C,
312 Q81_TX_PKTS_PRIORITY2 = 0x00000690,
313 Q81_TX_PKTS_PRIORITY2_LO = 0x00000694,
314 Q81_TX_PKTS_PRIORITY3 = 0x00000698,
315 Q81_TX_PKTS_PRIORITY3_LO = 0x0000069C,
316 Q81_TX_PKTS_PRIORITY4 = 0x000006A0,
317 Q81_TX_PKTS_PRIORITY4_LO = 0x000006A4,
318 Q81_TX_PKTS_PRIORITY5 = 0x000006A8,
319 Q81_TX_PKTS_PRIORITY5_LO = 0x000006AC,
320 Q81_TX_PKTS_PRIORITY6 = 0x000006B0,
321 Q81_TX_PKTS_PRIORITY6_LO = 0x000006B4,
322 Q81_TX_PKTS_PRIORITY7 = 0x000006B8,
323 Q81_TX_PKTS_PRIORITY7_LO = 0x000006BC,
324 Q81_TX_OCTETS_PRIORITY0 = 0x000006C0,
325 Q81_TX_OCTETS_PRIORITY0_LO = 0x000006C4,
326 Q81_TX_OCTETS_PRIORITY1 = 0x000006C8,
327 Q81_TX_OCTETS_PRIORITY1_LO = 0x000006CC,
328 Q81_TX_OCTETS_PRIORITY2 = 0x000006D0,
329 Q81_TX_OCTETS_PRIORITY2_LO = 0x000006D4,
330 Q81_TX_OCTETS_PRIORITY3 = 0x000006D8,
331 Q81_TX_OCTETS_PRIORITY3_LO = 0x000006DC,
332 Q81_TX_OCTETS_PRIORITY4 = 0x000006E0,
333 Q81_TX_OCTETS_PRIORITY4_LO = 0x000006E4,
334 Q81_TX_OCTETS_PRIORITY5 = 0x000006E8,
335 Q81_TX_OCTETS_PRIORITY5_LO = 0x000006EC,
336 Q81_TX_OCTETS_PRIORITY6 = 0x000006F0,
337 Q81_TX_OCTETS_PRIORITY6_LO = 0x000006F4,
338 Q81_TX_OCTETS_PRIORITY7 = 0x000006F8,
339 Q81_TX_OCTETS_PRIORITY7_LO = 0x000006FC,
340 Q81_RX_DISCARD_PRIORITY0 = 0x00000700,
341 Q81_RX_DISCARD_PRIORITY0_LO = 0x00000704,
342 Q81_RX_DISCARD_PRIORITY1 = 0x00000708,
343 Q81_RX_DISCARD_PRIORITY1_LO = 0x0000070C,
344 Q81_RX_DISCARD_PRIORITY2 = 0x00000710,
345 Q81_RX_DISCARD_PRIORITY2_LO = 0x00000714,
346 Q81_RX_DISCARD_PRIORITY3 = 0x00000718,
347 Q81_RX_DISCARD_PRIORITY3_LO = 0x0000071C,
348 Q81_RX_DISCARD_PRIORITY4 = 0x00000720,
349 Q81_RX_DISCARD_PRIORITY4_LO = 0x00000724,
350 Q81_RX_DISCARD_PRIORITY5 = 0x00000728,
351 Q81_RX_DISCARD_PRIORITY5_LO = 0x0000072C,
352 Q81_RX_DISCARD_PRIORITY6 = 0x00000730,
353 Q81_RX_DISCARD_PRIORITY6_LO = 0x00000734,
354 Q81_RX_DISCARD_PRIORITY7 = 0x00000738,
355 Q81_RX_DISCARD_PRIORITY7_LO = 0x0000073C
356 };
357
358 static void
qls_mpid_seg_hdr(qls_mpid_seg_hdr_t * seg_hdr,uint32_t seg_num,uint32_t seg_size,unsigned char * desc)359 qls_mpid_seg_hdr(qls_mpid_seg_hdr_t *seg_hdr, uint32_t seg_num,
360 uint32_t seg_size, unsigned char *desc)
361 {
362 memset(seg_hdr, 0, sizeof(qls_mpid_seg_hdr_t));
363
364 seg_hdr->cookie = Q81_MPID_COOKIE;
365 seg_hdr->seg_num = seg_num;
366 seg_hdr->seg_size = seg_size;
367
368 memcpy(seg_hdr->desc, desc, (sizeof(seg_hdr->desc))-1);
369
370 return;
371 }
372
373 static int
qls_wait_reg_rdy(qla_host_t * ha,uint32_t reg,uint32_t bit,uint32_t err_bit)374 qls_wait_reg_rdy(qla_host_t *ha , uint32_t reg, uint32_t bit, uint32_t err_bit)
375 {
376 uint32_t data;
377 int count = 10;
378
379 while (count) {
380 data = READ_REG32(ha, reg);
381
382 if (data & err_bit)
383 return (-1);
384 else if (data & bit)
385 return (0);
386
387 qls_mdelay(__func__, 10);
388 count--;
389 }
390 return (-1);
391 }
392
393 static int
qls_rd_mpi_reg(qla_host_t * ha,uint32_t reg,uint32_t * data)394 qls_rd_mpi_reg(qla_host_t *ha, uint32_t reg, uint32_t *data)
395 {
396 int ret;
397
398 ret = qls_wait_reg_rdy(ha, Q81_CTL_PROC_ADDR, Q81_CTL_PROC_ADDR_RDY,
399 Q81_CTL_PROC_ADDR_ERR);
400
401 if (ret)
402 goto exit_qls_rd_mpi_reg;
403
404 WRITE_REG32(ha, Q81_CTL_PROC_ADDR, reg | Q81_CTL_PROC_ADDR_READ);
405
406 ret = qls_wait_reg_rdy(ha, Q81_CTL_PROC_ADDR, Q81_CTL_PROC_ADDR_RDY,
407 Q81_CTL_PROC_ADDR_ERR);
408
409 if (ret)
410 goto exit_qls_rd_mpi_reg;
411
412 *data = READ_REG32(ha, Q81_CTL_PROC_DATA);
413
414 exit_qls_rd_mpi_reg:
415 return (ret);
416 }
417
418 static int
qls_wr_mpi_reg(qla_host_t * ha,uint32_t reg,uint32_t data)419 qls_wr_mpi_reg(qla_host_t *ha, uint32_t reg, uint32_t data)
420 {
421 int ret = 0;
422
423 ret = qls_wait_reg_rdy(ha, Q81_CTL_PROC_ADDR, Q81_CTL_PROC_ADDR_RDY,
424 Q81_CTL_PROC_ADDR_ERR);
425 if (ret)
426 goto exit_qls_wr_mpi_reg;
427
428 WRITE_REG32(ha, Q81_CTL_PROC_DATA, data);
429
430 WRITE_REG32(ha, Q81_CTL_PROC_ADDR, reg);
431
432 ret = qls_wait_reg_rdy(ha, Q81_CTL_PROC_ADDR, Q81_CTL_PROC_ADDR_RDY,
433 Q81_CTL_PROC_ADDR_ERR);
434 exit_qls_wr_mpi_reg:
435 return (ret);
436 }
437
438 #define Q81_TEST_LOGIC_FUNC_PORT_CONFIG 0x1002
439 #define Q81_INVALID_NUM 0xFFFFFFFF
440
441 #define Q81_NIC1_FUNC_ENABLE 0x00000001
442 #define Q81_NIC1_FUNC_MASK 0x0000000e
443 #define Q81_NIC1_FUNC_SHIFT 1
444 #define Q81_NIC2_FUNC_ENABLE 0x00000010
445 #define Q81_NIC2_FUNC_MASK 0x000000e0
446 #define Q81_NIC2_FUNC_SHIFT 5
447 #define Q81_FUNCTION_SHIFT 6
448
449 static uint32_t
qls_get_other_fnum(qla_host_t * ha)450 qls_get_other_fnum(qla_host_t *ha)
451 {
452 int ret;
453 uint32_t o_func;
454 uint32_t test_logic;
455 uint32_t nic1_fnum = Q81_INVALID_NUM;
456 uint32_t nic2_fnum = Q81_INVALID_NUM;
457
458 ret = qls_rd_mpi_reg(ha, Q81_TEST_LOGIC_FUNC_PORT_CONFIG, &test_logic);
459 if (ret)
460 return(Q81_INVALID_NUM);
461
462 if (test_logic & Q81_NIC1_FUNC_ENABLE)
463 nic1_fnum = (test_logic & Q81_NIC1_FUNC_MASK) >>
464 Q81_NIC1_FUNC_SHIFT;
465
466 if (test_logic & Q81_NIC2_FUNC_ENABLE)
467 nic2_fnum = (test_logic & Q81_NIC2_FUNC_MASK) >>
468 Q81_NIC2_FUNC_SHIFT;
469
470 if (ha->pci_func == 0)
471 o_func = nic2_fnum;
472 else
473 o_func = nic1_fnum;
474
475 return(o_func);
476 }
477
478 static uint32_t
qls_rd_ofunc_reg(qla_host_t * ha,uint32_t reg)479 qls_rd_ofunc_reg(qla_host_t *ha, uint32_t reg)
480 {
481 uint32_t ofunc;
482 uint32_t data;
483 int ret = 0;
484
485 ofunc = qls_get_other_fnum(ha);
486
487 if (ofunc == Q81_INVALID_NUM)
488 return(Q81_INVALID_NUM);
489
490 reg = Q81_CTL_PROC_ADDR_REG_BLOCK | (ofunc << Q81_FUNCTION_SHIFT) | reg;
491
492 ret = qls_rd_mpi_reg(ha, reg, &data);
493
494 if (ret != 0)
495 return(Q81_INVALID_NUM);
496
497 return(data);
498 }
499
500 static void
qls_wr_ofunc_reg(qla_host_t * ha,uint32_t reg,uint32_t value)501 qls_wr_ofunc_reg(qla_host_t *ha, uint32_t reg, uint32_t value)
502 {
503 uint32_t ofunc;
504 int ret = 0;
505
506 ofunc = qls_get_other_fnum(ha);
507
508 if (ofunc == Q81_INVALID_NUM)
509 return;
510
511 reg = Q81_CTL_PROC_ADDR_REG_BLOCK | (ofunc << Q81_FUNCTION_SHIFT) | reg;
512
513 ret = qls_wr_mpi_reg(ha, reg, value);
514
515 return;
516 }
517
518 static int
qls_wait_ofunc_reg_rdy(qla_host_t * ha,uint32_t reg,uint32_t bit,uint32_t err_bit)519 qls_wait_ofunc_reg_rdy(qla_host_t *ha , uint32_t reg, uint32_t bit,
520 uint32_t err_bit)
521 {
522 uint32_t data;
523 int count = 10;
524
525 while (count) {
526 data = qls_rd_ofunc_reg(ha, reg);
527
528 if (data & err_bit)
529 return (-1);
530 else if (data & bit)
531 return (0);
532
533 qls_mdelay(__func__, 10);
534 count--;
535 }
536 return (-1);
537 }
538
539 #define Q81_XG_SERDES_ADDR_RDY BIT_31
540 #define Q81_XG_SERDES_ADDR_READ BIT_30
541
542 static int
qls_rd_ofunc_serdes_reg(qla_host_t * ha,uint32_t reg,uint32_t * data)543 qls_rd_ofunc_serdes_reg(qla_host_t *ha, uint32_t reg, uint32_t *data)
544 {
545 int ret;
546
547 /* wait for reg to come ready */
548 ret = qls_wait_ofunc_reg_rdy(ha, (Q81_CTL_XG_SERDES_ADDR >> 2),
549 Q81_XG_SERDES_ADDR_RDY, 0);
550 if (ret)
551 goto exit_qls_rd_ofunc_serdes_reg;
552
553 /* set up for reg read */
554 qls_wr_ofunc_reg(ha, (Q81_CTL_XG_SERDES_ADDR >> 2),
555 (reg | Q81_XG_SERDES_ADDR_READ));
556
557 /* wait for reg to come ready */
558 ret = qls_wait_ofunc_reg_rdy(ha, (Q81_CTL_XG_SERDES_ADDR >> 2),
559 Q81_XG_SERDES_ADDR_RDY, 0);
560 if (ret)
561 goto exit_qls_rd_ofunc_serdes_reg;
562
563 /* get the data */
564 *data = qls_rd_ofunc_reg(ha, (Q81_CTL_XG_SERDES_DATA >> 2));
565
566 exit_qls_rd_ofunc_serdes_reg:
567 return ret;
568 }
569
570 #define Q81_XGMAC_ADDR_RDY BIT_31
571 #define Q81_XGMAC_ADDR_R BIT_30
572 #define Q81_XGMAC_ADDR_XME BIT_29
573
574 static int
qls_rd_ofunc_xgmac_reg(qla_host_t * ha,uint32_t reg,uint32_t * data)575 qls_rd_ofunc_xgmac_reg(qla_host_t *ha, uint32_t reg, uint32_t *data)
576 {
577 int ret = 0;
578
579 ret = qls_wait_ofunc_reg_rdy(ha, (Q81_CTL_XGMAC_ADDR >> 2),
580 Q81_XGMAC_ADDR_RDY, Q81_XGMAC_ADDR_XME);
581
582 if (ret)
583 goto exit_qls_rd_ofunc_xgmac_reg;
584
585 qls_wr_ofunc_reg(ha, (Q81_XGMAC_ADDR_RDY >> 2),
586 (reg | Q81_XGMAC_ADDR_R));
587
588 ret = qls_wait_ofunc_reg_rdy(ha, (Q81_CTL_XGMAC_ADDR >> 2),
589 Q81_XGMAC_ADDR_RDY, Q81_XGMAC_ADDR_XME);
590 if (ret)
591 goto exit_qls_rd_ofunc_xgmac_reg;
592
593 *data = qls_rd_ofunc_reg(ha, Q81_CTL_XGMAC_DATA);
594
595 exit_qls_rd_ofunc_xgmac_reg:
596 return ret;
597 }
598
599 static int
qls_rd_serdes_reg(qla_host_t * ha,uint32_t reg,uint32_t * data)600 qls_rd_serdes_reg(qla_host_t *ha, uint32_t reg, uint32_t *data)
601 {
602 int ret;
603
604 ret = qls_wait_reg_rdy(ha, Q81_CTL_XG_SERDES_ADDR,
605 Q81_XG_SERDES_ADDR_RDY, 0);
606
607 if (ret)
608 goto exit_qls_rd_serdes_reg;
609
610 WRITE_REG32(ha, Q81_CTL_XG_SERDES_ADDR, \
611 (reg | Q81_XG_SERDES_ADDR_READ));
612
613 ret = qls_wait_reg_rdy(ha, Q81_CTL_XG_SERDES_ADDR,
614 Q81_XG_SERDES_ADDR_RDY, 0);
615
616 if (ret)
617 goto exit_qls_rd_serdes_reg;
618
619 *data = READ_REG32(ha, Q81_CTL_XG_SERDES_DATA);
620
621 exit_qls_rd_serdes_reg:
622
623 return ret;
624 }
625
626 static void
qls_get_both_serdes(qla_host_t * ha,uint32_t addr,uint32_t * dptr,uint32_t * ind_ptr,uint32_t dvalid,uint32_t ind_valid)627 qls_get_both_serdes(qla_host_t *ha, uint32_t addr, uint32_t *dptr,
628 uint32_t *ind_ptr, uint32_t dvalid, uint32_t ind_valid)
629 {
630 int ret = -1;
631
632 if (dvalid)
633 ret = qls_rd_serdes_reg(ha, addr, dptr);
634
635 if (ret)
636 *dptr = Q81_BAD_DATA;
637
638 ret = -1;
639
640 if(ind_valid)
641 ret = qls_rd_ofunc_serdes_reg(ha, addr, ind_ptr);
642
643 if (ret)
644 *ind_ptr = Q81_BAD_DATA;
645 }
646
647 #define Q81_XFI1_POWERED_UP 0x00000005
648 #define Q81_XFI2_POWERED_UP 0x0000000A
649 #define Q81_XAUI_POWERED_UP 0x00000001
650
651 static int
qls_rd_serdes_regs(qla_host_t * ha,qls_mpi_coredump_t * mpi_dump)652 qls_rd_serdes_regs(qla_host_t *ha, qls_mpi_coredump_t *mpi_dump)
653 {
654 int ret;
655 uint32_t xfi_d_valid, xfi_ind_valid, xaui_d_valid, xaui_ind_valid;
656 uint32_t temp, xaui_reg, i;
657 uint32_t *dptr, *indptr;
658
659 xfi_d_valid = xfi_ind_valid = xaui_d_valid = xaui_ind_valid = 0;
660
661 xaui_reg = 0x800;
662
663 ret = qls_rd_ofunc_serdes_reg(ha, xaui_reg, &temp);
664 if (ret)
665 temp = 0;
666
667 if ((temp & Q81_XAUI_POWERED_UP) == Q81_XAUI_POWERED_UP)
668 xaui_ind_valid = 1;
669
670 ret = qls_rd_serdes_reg(ha, xaui_reg, &temp);
671 if (ret)
672 temp = 0;
673
674 if ((temp & Q81_XAUI_POWERED_UP) == Q81_XAUI_POWERED_UP)
675 xaui_d_valid = 1;
676
677 ret = qls_rd_serdes_reg(ha, 0x1E06, &temp);
678 if (ret)
679 temp = 0;
680
681 if ((temp & Q81_XFI1_POWERED_UP) == Q81_XFI1_POWERED_UP) {
682 if (ha->pci_func & 1)
683 xfi_ind_valid = 1; /* NIC 2, so the indirect
684 (NIC1) xfi is up*/
685 else
686 xfi_d_valid = 1;
687 }
688
689 if((temp & Q81_XFI2_POWERED_UP) == Q81_XFI2_POWERED_UP) {
690 if(ha->pci_func & 1)
691 xfi_d_valid = 1; /* NIC 2, so the indirect (NIC1)
692 xfi is up */
693 else
694 xfi_ind_valid = 1;
695 }
696
697 if (ha->pci_func & 1) {
698 dptr = (uint32_t *)(&mpi_dump->serdes2_xaui_an);
699 indptr = (uint32_t *)(&mpi_dump->serdes1_xaui_an);
700 } else {
701 dptr = (uint32_t *)(&mpi_dump->serdes1_xaui_an);
702 indptr = (uint32_t *)(&mpi_dump->serdes2_xaui_an);
703 }
704
705 for (i = 0; i <= 0x000000034; i += 4, dptr ++, indptr ++) {
706 qls_get_both_serdes(ha, i, dptr, indptr,
707 xaui_d_valid, xaui_ind_valid);
708 }
709
710 if (ha->pci_func & 1) {
711 dptr = (uint32_t *)(&mpi_dump->serdes2_xaui_hss_pcs);
712 indptr = (uint32_t *)(&mpi_dump->serdes1_xaui_hss_pcs);
713 } else {
714 dptr = (uint32_t *)(&mpi_dump->serdes1_xaui_hss_pcs);
715 indptr = (uint32_t *)(&mpi_dump->serdes2_xaui_hss_pcs);
716 }
717
718 for (i = 0x800; i <= 0x880; i += 4, dptr ++, indptr ++) {
719 qls_get_both_serdes(ha, i, dptr, indptr,
720 xaui_d_valid, xaui_ind_valid);
721 }
722
723 if (ha->pci_func & 1) {
724 dptr = (uint32_t *)(&mpi_dump->serdes2_xfi_an);
725 indptr = (uint32_t *)(&mpi_dump->serdes1_xfi_an);
726 } else {
727 dptr = (uint32_t *)(&mpi_dump->serdes1_xfi_an);
728 indptr = (uint32_t *)(&mpi_dump->serdes2_xfi_an);
729 }
730
731 for (i = 0x1000; i <= 0x1034; i += 4, dptr ++, indptr ++) {
732 qls_get_both_serdes(ha, i, dptr, indptr,
733 xfi_d_valid, xfi_ind_valid);
734 }
735
736 if (ha->pci_func & 1) {
737 dptr = (uint32_t *)(&mpi_dump->serdes2_xfi_train);
738 indptr = (uint32_t *)(&mpi_dump->serdes1_xfi_train);
739 } else {
740 dptr = (uint32_t *)(&mpi_dump->serdes1_xfi_train);
741 indptr = (uint32_t *)(&mpi_dump->serdes2_xfi_train);
742 }
743
744 for (i = 0x1050; i <= 0x107c; i += 4, dptr ++, indptr ++) {
745 qls_get_both_serdes(ha, i, dptr, indptr,
746 xfi_d_valid, xfi_ind_valid);
747 }
748
749 if (ha->pci_func & 1) {
750 dptr = (uint32_t *)(&mpi_dump->serdes2_xfi_hss_pcs);
751 indptr = (uint32_t *)(&mpi_dump->serdes1_xfi_hss_pcs);
752 } else {
753 dptr = (uint32_t *)(&mpi_dump->serdes1_xfi_hss_pcs);
754 indptr = (uint32_t *)(&mpi_dump->serdes2_xfi_hss_pcs);
755 }
756
757 for (i = 0x1800; i <= 0x1838; i += 4, dptr++, indptr ++) {
758 qls_get_both_serdes(ha, i, dptr, indptr,
759 xfi_d_valid, xfi_ind_valid);
760 }
761
762 if (ha->pci_func & 1) {
763 dptr = (uint32_t *)(&mpi_dump->serdes2_xfi_hss_tx);
764 indptr = (uint32_t *)(&mpi_dump->serdes1_xfi_hss_tx);
765 } else {
766 dptr = (uint32_t *)(&mpi_dump->serdes1_xfi_hss_tx);
767 indptr = (uint32_t *)(&mpi_dump->serdes2_xfi_hss_tx);
768 }
769
770 for (i = 0x1c00; i <= 0x1c1f; i++, dptr ++, indptr ++) {
771 qls_get_both_serdes(ha, i, dptr, indptr,
772 xfi_d_valid, xfi_ind_valid);
773 }
774
775 if (ha->pci_func & 1) {
776 dptr = (uint32_t *)(&mpi_dump->serdes2_xfi_hss_rx);
777 indptr = (uint32_t *)(&mpi_dump->serdes1_xfi_hss_rx);
778 } else {
779 dptr = (uint32_t *)(&mpi_dump->serdes1_xfi_hss_rx);
780 indptr = (uint32_t *)(&mpi_dump->serdes2_xfi_hss_rx);
781 }
782
783 for (i = 0x1c40; i <= 0x1c5f; i++, dptr ++, indptr ++) {
784 qls_get_both_serdes(ha, i, dptr, indptr,
785 xfi_d_valid, xfi_ind_valid);
786 }
787
788 if (ha->pci_func & 1) {
789 dptr = (uint32_t *)(&mpi_dump->serdes2_xfi_hss_pll);
790 indptr = (uint32_t *)(&mpi_dump->serdes1_xfi_hss_pll);
791 } else {
792 dptr = (uint32_t *)(&mpi_dump->serdes1_xfi_hss_pll);
793 indptr = (uint32_t *)(&mpi_dump->serdes2_xfi_hss_pll);
794 }
795
796 for (i = 0x1e00; i <= 0x1e1f; i++, dptr ++, indptr ++) {
797 qls_get_both_serdes(ha, i, dptr, indptr,
798 xfi_d_valid, xfi_ind_valid);
799 }
800
801 return(0);
802 }
803
804 static int
qls_unpause_mpi_risc(qla_host_t * ha)805 qls_unpause_mpi_risc(qla_host_t *ha)
806 {
807 uint32_t data;
808
809 data = READ_REG32(ha, Q81_CTL_HOST_CMD_STATUS);
810
811 if (!(data & Q81_CTL_HCS_RISC_PAUSED))
812 return -1;
813
814 WRITE_REG32(ha, Q81_CTL_HOST_CMD_STATUS, \
815 Q81_CTL_HCS_CMD_CLR_RISC_PAUSE);
816
817 return 0;
818 }
819
820 static int
qls_pause_mpi_risc(qla_host_t * ha)821 qls_pause_mpi_risc(qla_host_t *ha)
822 {
823 uint32_t data;
824 int count = 10;
825
826 WRITE_REG32(ha, Q81_CTL_HOST_CMD_STATUS, \
827 Q81_CTL_HCS_CMD_SET_RISC_PAUSE);
828
829 do {
830 data = READ_REG32(ha, Q81_CTL_HOST_CMD_STATUS);
831
832 if (data & Q81_CTL_HCS_RISC_PAUSED)
833 break;
834
835 qls_mdelay(__func__, 10);
836
837 count--;
838
839 } while (count);
840
841 return ((count == 0) ? -1 : 0);
842 }
843
844 static void
qls_get_intr_states(qla_host_t * ha,uint32_t * buf)845 qls_get_intr_states(qla_host_t *ha, uint32_t *buf)
846 {
847 int i;
848
849 for (i = 0; i < MAX_RX_RINGS; i++, buf++) {
850 WRITE_REG32(ha, Q81_CTL_INTR_ENABLE, (0x037f0300 + i));
851
852 *buf = READ_REG32(ha, Q81_CTL_INTR_ENABLE);
853 }
854 }
855
856 static int
qls_rd_xgmac_reg(qla_host_t * ha,uint32_t reg,uint32_t * data)857 qls_rd_xgmac_reg(qla_host_t *ha, uint32_t reg, uint32_t*data)
858 {
859 int ret = 0;
860
861 ret = qls_wait_reg_rdy(ha, Q81_CTL_XGMAC_ADDR, Q81_XGMAC_ADDR_RDY,
862 Q81_XGMAC_ADDR_XME);
863 if (ret)
864 goto exit_qls_rd_xgmac_reg;
865
866 WRITE_REG32(ha, Q81_CTL_XGMAC_ADDR, (reg | Q81_XGMAC_ADDR_R));
867
868 ret = qls_wait_reg_rdy(ha, Q81_CTL_XGMAC_ADDR, Q81_XGMAC_ADDR_RDY,
869 Q81_XGMAC_ADDR_XME);
870 if (ret)
871 goto exit_qls_rd_xgmac_reg;
872
873 *data = READ_REG32(ha, Q81_CTL_XGMAC_DATA);
874
875 exit_qls_rd_xgmac_reg:
876 return ret;
877 }
878
879 static int
qls_rd_xgmac_regs(qla_host_t * ha,uint32_t * buf,uint32_t o_func)880 qls_rd_xgmac_regs(qla_host_t *ha, uint32_t *buf, uint32_t o_func)
881 {
882 int ret = 0;
883 int i;
884
885 for (i = 0; i < Q81_XGMAC_REGISTER_END; i += 4, buf ++) {
886 switch (i) {
887 case Q81_PAUSE_SRC_LO :
888 case Q81_PAUSE_SRC_HI :
889 case Q81_GLOBAL_CFG :
890 case Q81_TX_CFG :
891 case Q81_RX_CFG :
892 case Q81_FLOW_CTL :
893 case Q81_PAUSE_OPCODE :
894 case Q81_PAUSE_TIMER :
895 case Q81_PAUSE_FRM_DEST_LO :
896 case Q81_PAUSE_FRM_DEST_HI :
897 case Q81_MAC_TX_PARAMS :
898 case Q81_MAC_RX_PARAMS :
899 case Q81_MAC_SYS_INT :
900 case Q81_MAC_SYS_INT_MASK :
901 case Q81_MAC_MGMT_INT :
902 case Q81_MAC_MGMT_IN_MASK :
903 case Q81_EXT_ARB_MODE :
904 case Q81_TX_PKTS :
905 case Q81_TX_PKTS_LO :
906 case Q81_TX_BYTES :
907 case Q81_TX_BYTES_LO :
908 case Q81_TX_MCAST_PKTS :
909 case Q81_TX_MCAST_PKTS_LO :
910 case Q81_TX_BCAST_PKTS :
911 case Q81_TX_BCAST_PKTS_LO :
912 case Q81_TX_UCAST_PKTS :
913 case Q81_TX_UCAST_PKTS_LO :
914 case Q81_TX_CTL_PKTS :
915 case Q81_TX_CTL_PKTS_LO :
916 case Q81_TX_PAUSE_PKTS :
917 case Q81_TX_PAUSE_PKTS_LO :
918 case Q81_TX_64_PKT :
919 case Q81_TX_64_PKT_LO :
920 case Q81_TX_65_TO_127_PKT :
921 case Q81_TX_65_TO_127_PKT_LO :
922 case Q81_TX_128_TO_255_PKT :
923 case Q81_TX_128_TO_255_PKT_LO :
924 case Q81_TX_256_511_PKT :
925 case Q81_TX_256_511_PKT_LO :
926 case Q81_TX_512_TO_1023_PKT :
927 case Q81_TX_512_TO_1023_PKT_LO :
928 case Q81_TX_1024_TO_1518_PKT :
929 case Q81_TX_1024_TO_1518_PKT_LO :
930 case Q81_TX_1519_TO_MAX_PKT :
931 case Q81_TX_1519_TO_MAX_PKT_LO :
932 case Q81_TX_UNDERSIZE_PKT :
933 case Q81_TX_UNDERSIZE_PKT_LO :
934 case Q81_TX_OVERSIZE_PKT :
935 case Q81_TX_OVERSIZE_PKT_LO :
936 case Q81_RX_HALF_FULL_DET :
937 case Q81_TX_HALF_FULL_DET_LO :
938 case Q81_RX_OVERFLOW_DET :
939 case Q81_TX_OVERFLOW_DET_LO :
940 case Q81_RX_HALF_FULL_MASK :
941 case Q81_TX_HALF_FULL_MASK_LO :
942 case Q81_RX_OVERFLOW_MASK :
943 case Q81_TX_OVERFLOW_MASK_LO :
944 case Q81_STAT_CNT_CTL :
945 case Q81_AUX_RX_HALF_FULL_DET :
946 case Q81_AUX_TX_HALF_FULL_DET :
947 case Q81_AUX_RX_OVERFLOW_DET :
948 case Q81_AUX_TX_OVERFLOW_DET :
949 case Q81_AUX_RX_HALF_FULL_MASK :
950 case Q81_AUX_TX_HALF_FULL_MASK :
951 case Q81_AUX_RX_OVERFLOW_MASK :
952 case Q81_AUX_TX_OVERFLOW_MASK :
953 case Q81_RX_BYTES :
954 case Q81_RX_BYTES_LO :
955 case Q81_RX_BYTES_OK :
956 case Q81_RX_BYTES_OK_LO :
957 case Q81_RX_PKTS :
958 case Q81_RX_PKTS_LO :
959 case Q81_RX_PKTS_OK :
960 case Q81_RX_PKTS_OK_LO :
961 case Q81_RX_BCAST_PKTS :
962 case Q81_RX_BCAST_PKTS_LO :
963 case Q81_RX_MCAST_PKTS :
964 case Q81_RX_MCAST_PKTS_LO :
965 case Q81_RX_UCAST_PKTS :
966 case Q81_RX_UCAST_PKTS_LO :
967 case Q81_RX_UNDERSIZE_PKTS :
968 case Q81_RX_UNDERSIZE_PKTS_LO :
969 case Q81_RX_OVERSIZE_PKTS :
970 case Q81_RX_OVERSIZE_PKTS_LO :
971 case Q81_RX_JABBER_PKTS :
972 case Q81_RX_JABBER_PKTS_LO :
973 case Q81_RX_UNDERSIZE_FCERR_PKTS :
974 case Q81_RX_UNDERSIZE_FCERR_PKTS_LO :
975 case Q81_RX_DROP_EVENTS :
976 case Q81_RX_DROP_EVENTS_LO :
977 case Q81_RX_FCERR_PKTS :
978 case Q81_RX_FCERR_PKTS_LO :
979 case Q81_RX_ALIGN_ERR :
980 case Q81_RX_ALIGN_ERR_LO :
981 case Q81_RX_SYMBOL_ERR :
982 case Q81_RX_SYMBOL_ERR_LO :
983 case Q81_RX_MAC_ERR :
984 case Q81_RX_MAC_ERR_LO :
985 case Q81_RX_CTL_PKTS :
986 case Q81_RX_CTL_PKTS_LO :
987 case Q81_RX_PAUSE_PKTS :
988 case Q81_RX_PAUSE_PKTS_LO :
989 case Q81_RX_64_PKTS :
990 case Q81_RX_64_PKTS_LO :
991 case Q81_RX_65_TO_127_PKTS :
992 case Q81_RX_65_TO_127_PKTS_LO :
993 case Q81_RX_128_255_PKTS :
994 case Q81_RX_128_255_PKTS_LO :
995 case Q81_RX_256_511_PKTS :
996 case Q81_RX_256_511_PKTS_LO :
997 case Q81_RX_512_TO_1023_PKTS :
998 case Q81_RX_512_TO_1023_PKTS_LO :
999 case Q81_RX_1024_TO_1518_PKTS :
1000 case Q81_RX_1024_TO_1518_PKTS_LO :
1001 case Q81_RX_1519_TO_MAX_PKTS :
1002 case Q81_RX_1519_TO_MAX_PKTS_LO :
1003 case Q81_RX_LEN_ERR_PKTS :
1004 case Q81_RX_LEN_ERR_PKTS_LO :
1005 case Q81_MDIO_TX_DATA :
1006 case Q81_MDIO_RX_DATA :
1007 case Q81_MDIO_CMD :
1008 case Q81_MDIO_PHY_ADDR :
1009 case Q81_MDIO_PORT :
1010 case Q81_MDIO_STATUS :
1011 case Q81_TX_CBFC_PAUSE_FRAMES0 :
1012 case Q81_TX_CBFC_PAUSE_FRAMES0_LO :
1013 case Q81_TX_CBFC_PAUSE_FRAMES1 :
1014 case Q81_TX_CBFC_PAUSE_FRAMES1_LO :
1015 case Q81_TX_CBFC_PAUSE_FRAMES2 :
1016 case Q81_TX_CBFC_PAUSE_FRAMES2_LO :
1017 case Q81_TX_CBFC_PAUSE_FRAMES3 :
1018 case Q81_TX_CBFC_PAUSE_FRAMES3_LO :
1019 case Q81_TX_CBFC_PAUSE_FRAMES4 :
1020 case Q81_TX_CBFC_PAUSE_FRAMES4_LO :
1021 case Q81_TX_CBFC_PAUSE_FRAMES5 :
1022 case Q81_TX_CBFC_PAUSE_FRAMES5_LO :
1023 case Q81_TX_CBFC_PAUSE_FRAMES6 :
1024 case Q81_TX_CBFC_PAUSE_FRAMES6_LO :
1025 case Q81_TX_CBFC_PAUSE_FRAMES7 :
1026 case Q81_TX_CBFC_PAUSE_FRAMES7_LO :
1027 case Q81_TX_FCOE_PKTS :
1028 case Q81_TX_FCOE_PKTS_LO :
1029 case Q81_TX_MGMT_PKTS :
1030 case Q81_TX_MGMT_PKTS_LO :
1031 case Q81_RX_CBFC_PAUSE_FRAMES0 :
1032 case Q81_RX_CBFC_PAUSE_FRAMES0_LO :
1033 case Q81_RX_CBFC_PAUSE_FRAMES1 :
1034 case Q81_RX_CBFC_PAUSE_FRAMES1_LO :
1035 case Q81_RX_CBFC_PAUSE_FRAMES2 :
1036 case Q81_RX_CBFC_PAUSE_FRAMES2_LO :
1037 case Q81_RX_CBFC_PAUSE_FRAMES3 :
1038 case Q81_RX_CBFC_PAUSE_FRAMES3_LO :
1039 case Q81_RX_CBFC_PAUSE_FRAMES4 :
1040 case Q81_RX_CBFC_PAUSE_FRAMES4_LO :
1041 case Q81_RX_CBFC_PAUSE_FRAMES5 :
1042 case Q81_RX_CBFC_PAUSE_FRAMES5_LO :
1043 case Q81_RX_CBFC_PAUSE_FRAMES6 :
1044 case Q81_RX_CBFC_PAUSE_FRAMES6_LO :
1045 case Q81_RX_CBFC_PAUSE_FRAMES7 :
1046 case Q81_RX_CBFC_PAUSE_FRAMES7_LO :
1047 case Q81_RX_FCOE_PKTS :
1048 case Q81_RX_FCOE_PKTS_LO :
1049 case Q81_RX_MGMT_PKTS :
1050 case Q81_RX_MGMT_PKTS_LO :
1051 case Q81_RX_NIC_FIFO_DROP :
1052 case Q81_RX_NIC_FIFO_DROP_LO :
1053 case Q81_RX_FCOE_FIFO_DROP :
1054 case Q81_RX_FCOE_FIFO_DROP_LO :
1055 case Q81_RX_MGMT_FIFO_DROP :
1056 case Q81_RX_MGMT_FIFO_DROP_LO :
1057 case Q81_RX_PKTS_PRIORITY0 :
1058 case Q81_RX_PKTS_PRIORITY0_LO :
1059 case Q81_RX_PKTS_PRIORITY1 :
1060 case Q81_RX_PKTS_PRIORITY1_LO :
1061 case Q81_RX_PKTS_PRIORITY2 :
1062 case Q81_RX_PKTS_PRIORITY2_LO :
1063 case Q81_RX_PKTS_PRIORITY3 :
1064 case Q81_RX_PKTS_PRIORITY3_LO :
1065 case Q81_RX_PKTS_PRIORITY4 :
1066 case Q81_RX_PKTS_PRIORITY4_LO :
1067 case Q81_RX_PKTS_PRIORITY5 :
1068 case Q81_RX_PKTS_PRIORITY5_LO :
1069 case Q81_RX_PKTS_PRIORITY6 :
1070 case Q81_RX_PKTS_PRIORITY6_LO :
1071 case Q81_RX_PKTS_PRIORITY7 :
1072 case Q81_RX_PKTS_PRIORITY7_LO :
1073 case Q81_RX_OCTETS_PRIORITY0 :
1074 case Q81_RX_OCTETS_PRIORITY0_LO :
1075 case Q81_RX_OCTETS_PRIORITY1 :
1076 case Q81_RX_OCTETS_PRIORITY1_LO :
1077 case Q81_RX_OCTETS_PRIORITY2 :
1078 case Q81_RX_OCTETS_PRIORITY2_LO :
1079 case Q81_RX_OCTETS_PRIORITY3 :
1080 case Q81_RX_OCTETS_PRIORITY3_LO :
1081 case Q81_RX_OCTETS_PRIORITY4 :
1082 case Q81_RX_OCTETS_PRIORITY4_LO :
1083 case Q81_RX_OCTETS_PRIORITY5 :
1084 case Q81_RX_OCTETS_PRIORITY5_LO :
1085 case Q81_RX_OCTETS_PRIORITY6 :
1086 case Q81_RX_OCTETS_PRIORITY6_LO :
1087 case Q81_RX_OCTETS_PRIORITY7 :
1088 case Q81_RX_OCTETS_PRIORITY7_LO :
1089 case Q81_TX_PKTS_PRIORITY0 :
1090 case Q81_TX_PKTS_PRIORITY0_LO :
1091 case Q81_TX_PKTS_PRIORITY1 :
1092 case Q81_TX_PKTS_PRIORITY1_LO :
1093 case Q81_TX_PKTS_PRIORITY2 :
1094 case Q81_TX_PKTS_PRIORITY2_LO :
1095 case Q81_TX_PKTS_PRIORITY3 :
1096 case Q81_TX_PKTS_PRIORITY3_LO :
1097 case Q81_TX_PKTS_PRIORITY4 :
1098 case Q81_TX_PKTS_PRIORITY4_LO :
1099 case Q81_TX_PKTS_PRIORITY5 :
1100 case Q81_TX_PKTS_PRIORITY5_LO :
1101 case Q81_TX_PKTS_PRIORITY6 :
1102 case Q81_TX_PKTS_PRIORITY6_LO :
1103 case Q81_TX_PKTS_PRIORITY7 :
1104 case Q81_TX_PKTS_PRIORITY7_LO :
1105 case Q81_TX_OCTETS_PRIORITY0 :
1106 case Q81_TX_OCTETS_PRIORITY0_LO :
1107 case Q81_TX_OCTETS_PRIORITY1 :
1108 case Q81_TX_OCTETS_PRIORITY1_LO :
1109 case Q81_TX_OCTETS_PRIORITY2 :
1110 case Q81_TX_OCTETS_PRIORITY2_LO :
1111 case Q81_TX_OCTETS_PRIORITY3 :
1112 case Q81_TX_OCTETS_PRIORITY3_LO :
1113 case Q81_TX_OCTETS_PRIORITY4 :
1114 case Q81_TX_OCTETS_PRIORITY4_LO :
1115 case Q81_TX_OCTETS_PRIORITY5 :
1116 case Q81_TX_OCTETS_PRIORITY5_LO :
1117 case Q81_TX_OCTETS_PRIORITY6 :
1118 case Q81_TX_OCTETS_PRIORITY6_LO :
1119 case Q81_TX_OCTETS_PRIORITY7 :
1120 case Q81_TX_OCTETS_PRIORITY7_LO :
1121 case Q81_RX_DISCARD_PRIORITY0 :
1122 case Q81_RX_DISCARD_PRIORITY0_LO :
1123 case Q81_RX_DISCARD_PRIORITY1 :
1124 case Q81_RX_DISCARD_PRIORITY1_LO :
1125 case Q81_RX_DISCARD_PRIORITY2 :
1126 case Q81_RX_DISCARD_PRIORITY2_LO :
1127 case Q81_RX_DISCARD_PRIORITY3 :
1128 case Q81_RX_DISCARD_PRIORITY3_LO :
1129 case Q81_RX_DISCARD_PRIORITY4 :
1130 case Q81_RX_DISCARD_PRIORITY4_LO :
1131 case Q81_RX_DISCARD_PRIORITY5 :
1132 case Q81_RX_DISCARD_PRIORITY5_LO :
1133 case Q81_RX_DISCARD_PRIORITY6 :
1134 case Q81_RX_DISCARD_PRIORITY6_LO :
1135 case Q81_RX_DISCARD_PRIORITY7 :
1136 case Q81_RX_DISCARD_PRIORITY7_LO :
1137
1138 if (o_func)
1139 ret = qls_rd_ofunc_xgmac_reg(ha,
1140 i, buf);
1141 else
1142 ret = qls_rd_xgmac_reg(ha, i, buf);
1143
1144 if (ret)
1145 *buf = Q81_BAD_DATA;
1146
1147 break;
1148
1149 default:
1150 break;
1151 }
1152 }
1153 return 0;
1154 }
1155
1156 static int
qls_get_mpi_regs(qla_host_t * ha,uint32_t * buf,uint32_t offset,uint32_t count)1157 qls_get_mpi_regs(qla_host_t *ha, uint32_t *buf, uint32_t offset, uint32_t count)
1158 {
1159 int i, ret = 0;
1160
1161 for (i = 0; i < count; i++, buf++) {
1162 ret = qls_rd_mpi_reg(ha, (offset + i), buf);
1163
1164 if (ret)
1165 return ret;
1166 }
1167
1168 return (ret);
1169 }
1170
1171 static int
qls_get_mpi_shadow_regs(qla_host_t * ha,uint32_t * buf)1172 qls_get_mpi_shadow_regs(qla_host_t *ha, uint32_t *buf)
1173 {
1174 uint32_t i;
1175 int ret;
1176
1177 #define Q81_RISC_124 0x0000007c
1178 #define Q81_RISC_127 0x0000007f
1179 #define Q81_SHADOW_OFFSET 0xb0000000
1180
1181 for (i = 0; i < Q81_MPI_CORE_SH_REGS_CNT; i++, buf++) {
1182 ret = qls_wr_mpi_reg(ha,
1183 (Q81_CTL_PROC_ADDR_RISC_INT_REG | Q81_RISC_124),
1184 (Q81_SHADOW_OFFSET | i << 20));
1185 if (ret)
1186 goto exit_qls_get_mpi_shadow_regs;
1187
1188 ret = qls_mpi_risc_rd_reg(ha,
1189 (Q81_CTL_PROC_ADDR_RISC_INT_REG | Q81_RISC_127),
1190 buf);
1191 if (ret)
1192 goto exit_qls_get_mpi_shadow_regs;
1193 }
1194
1195 exit_qls_get_mpi_shadow_regs:
1196 return ret;
1197 }
1198
1199 #define SYS_CLOCK (0x00)
1200 #define PCI_CLOCK (0x80)
1201 #define FC_CLOCK (0x140)
1202 #define XGM_CLOCK (0x180)
1203
1204 #define Q81_ADDRESS_REGISTER_ENABLE 0x00010000
1205 #define Q81_UP 0x00008000
1206 #define Q81_MAX_MUX 0x40
1207 #define Q81_MAX_MODULES 0x1F
1208
1209 static uint32_t *
qls_get_probe(qla_host_t * ha,uint32_t clock,uint8_t * valid,uint32_t * buf)1210 qls_get_probe(qla_host_t *ha, uint32_t clock, uint8_t *valid, uint32_t *buf)
1211 {
1212 uint32_t module, mux_sel, probe, lo_val, hi_val;
1213
1214 for (module = 0; module < Q81_MAX_MODULES; module ++) {
1215 if (valid[module]) {
1216 for (mux_sel = 0; mux_sel < Q81_MAX_MUX; mux_sel++) {
1217 probe = clock | Q81_ADDRESS_REGISTER_ENABLE |
1218 mux_sel | (module << 9);
1219 WRITE_REG32(ha, Q81_CTL_XG_PROBE_MUX_ADDR,\
1220 probe);
1221
1222 lo_val = READ_REG32(ha,\
1223 Q81_CTL_XG_PROBE_MUX_DATA);
1224
1225 if (mux_sel == 0) {
1226 *buf = probe;
1227 buf ++;
1228 }
1229
1230 probe |= Q81_UP;
1231
1232 WRITE_REG32(ha, Q81_CTL_XG_PROBE_MUX_ADDR,\
1233 probe);
1234 hi_val = READ_REG32(ha,\
1235 Q81_CTL_XG_PROBE_MUX_DATA);
1236
1237 *buf = lo_val;
1238 buf++;
1239 *buf = hi_val;
1240 buf++;
1241 }
1242 }
1243 }
1244
1245 return(buf);
1246 }
1247
1248 static int
qls_get_probe_dump(qla_host_t * ha,uint32_t * buf)1249 qls_get_probe_dump(qla_host_t *ha, uint32_t *buf)
1250 {
1251
1252 uint8_t sys_clock_valid_modules[0x20] = {
1253 1, // 0x00
1254 1, // 0x01
1255 1, // 0x02
1256 0, // 0x03
1257 1, // 0x04
1258 1, // 0x05
1259 1, // 0x06
1260 1, // 0x07
1261 1, // 0x08
1262 1, // 0x09
1263 1, // 0x0A
1264 1, // 0x0B
1265 1, // 0x0C
1266 1, // 0x0D
1267 1, // 0x0E
1268 0, // 0x0F
1269 1, // 0x10
1270 1, // 0x11
1271 1, // 0x12
1272 1, // 0x13
1273 0, // 0x14
1274 0, // 0x15
1275 0, // 0x16
1276 0, // 0x17
1277 0, // 0x18
1278 0, // 0x19
1279 0, // 0x1A
1280 0, // 0x1B
1281 0, // 0x1C
1282 0, // 0x1D
1283 0, // 0x1E
1284 0 // 0x1F
1285 };
1286
1287 uint8_t pci_clock_valid_modules[0x20] = {
1288 1, // 0x00
1289 0, // 0x01
1290 0, // 0x02
1291 0, // 0x03
1292 0, // 0x04
1293 0, // 0x05
1294 1, // 0x06
1295 1, // 0x07
1296 0, // 0x08
1297 0, // 0x09
1298 0, // 0x0A
1299 0, // 0x0B
1300 0, // 0x0C
1301 0, // 0x0D
1302 1, // 0x0E
1303 0, // 0x0F
1304 0, // 0x10
1305 0, // 0x11
1306 0, // 0x12
1307 0, // 0x13
1308 0, // 0x14
1309 0, // 0x15
1310 0, // 0x16
1311 0, // 0x17
1312 0, // 0x18
1313 0, // 0x19
1314 0, // 0x1A
1315 0, // 0x1B
1316 0, // 0x1C
1317 0, // 0x1D
1318 0, // 0x1E
1319 0 // 0x1F
1320 };
1321
1322 uint8_t xgm_clock_valid_modules[0x20] = {
1323 1, // 0x00
1324 0, // 0x01
1325 0, // 0x02
1326 1, // 0x03
1327 0, // 0x04
1328 0, // 0x05
1329 0, // 0x06
1330 0, // 0x07
1331 1, // 0x08
1332 1, // 0x09
1333 0, // 0x0A
1334 0, // 0x0B
1335 1, // 0x0C
1336 1, // 0x0D
1337 1, // 0x0E
1338 0, // 0x0F
1339 1, // 0x10
1340 1, // 0x11
1341 0, // 0x12
1342 0, // 0x13
1343 0, // 0x14
1344 0, // 0x15
1345 0, // 0x16
1346 0, // 0x17
1347 0, // 0x18
1348 0, // 0x19
1349 0, // 0x1A
1350 0, // 0x1B
1351 0, // 0x1C
1352 0, // 0x1D
1353 0, // 0x1E
1354 0 // 0x1F
1355 };
1356
1357 uint8_t fc_clock_valid_modules[0x20] = {
1358 1, // 0x00
1359 0, // 0x01
1360 0, // 0x02
1361 0, // 0x03
1362 0, // 0x04
1363 0, // 0x05
1364 0, // 0x06
1365 0, // 0x07
1366 0, // 0x08
1367 0, // 0x09
1368 0, // 0x0A
1369 0, // 0x0B
1370 1, // 0x0C
1371 1, // 0x0D
1372 0, // 0x0E
1373 0, // 0x0F
1374 0, // 0x10
1375 0, // 0x11
1376 0, // 0x12
1377 0, // 0x13
1378 0, // 0x14
1379 0, // 0x15
1380 0, // 0x16
1381 0, // 0x17
1382 0, // 0x18
1383 0, // 0x19
1384 0, // 0x1A
1385 0, // 0x1B
1386 0, // 0x1C
1387 0, // 0x1D
1388 0, // 0x1E
1389 0 // 0x1F
1390 };
1391
1392 qls_wr_mpi_reg(ha, 0x100e, 0x18a20000);
1393
1394 buf = qls_get_probe(ha, SYS_CLOCK, sys_clock_valid_modules, buf);
1395
1396 buf = qls_get_probe(ha, PCI_CLOCK, pci_clock_valid_modules, buf);
1397
1398 buf = qls_get_probe(ha, XGM_CLOCK, xgm_clock_valid_modules, buf);
1399
1400 buf = qls_get_probe(ha, FC_CLOCK, fc_clock_valid_modules, buf);
1401
1402 return(0);
1403 }
1404
1405 static void
qls_get_ridx_registers(qla_host_t * ha,uint32_t * buf)1406 qls_get_ridx_registers(qla_host_t *ha, uint32_t *buf)
1407 {
1408 uint32_t type, idx, idx_max;
1409 uint32_t r_idx;
1410 uint32_t r_data;
1411 uint32_t val;
1412
1413 for (type = 0; type < 4; type ++) {
1414 if (type < 2)
1415 idx_max = 8;
1416 else
1417 idx_max = 16;
1418
1419 for (idx = 0; idx < idx_max; idx ++) {
1420 val = 0x04000000 | (type << 16) | (idx << 8);
1421 WRITE_REG32(ha, Q81_CTL_ROUTING_INDEX, val);
1422
1423 r_idx = 0;
1424 while ((r_idx & 0x40000000) == 0)
1425 r_idx = READ_REG32(ha, Q81_CTL_ROUTING_INDEX);
1426
1427 r_data = READ_REG32(ha, Q81_CTL_ROUTING_DATA);
1428
1429 *buf = type;
1430 buf ++;
1431 *buf = idx;
1432 buf ++;
1433 *buf = r_idx;
1434 buf ++;
1435 *buf = r_data;
1436 buf ++;
1437 }
1438 }
1439 }
1440
1441 static void
qls_get_mac_proto_regs(qla_host_t * ha,uint32_t * buf)1442 qls_get_mac_proto_regs(qla_host_t *ha, uint32_t* buf)
1443 {
1444
1445 #define Q81_RS_AND_ADR 0x06000000
1446 #define Q81_RS_ONLY 0x04000000
1447 #define Q81_NUM_TYPES 10
1448
1449 uint32_t result_index, result_data;
1450 uint32_t type;
1451 uint32_t index;
1452 uint32_t offset;
1453 uint32_t val;
1454 uint32_t initial_val;
1455 uint32_t max_index;
1456 uint32_t max_offset;
1457
1458 for (type = 0; type < Q81_NUM_TYPES; type ++) {
1459 switch (type) {
1460 case 0: // CAM
1461 initial_val = Q81_RS_AND_ADR;
1462 max_index = 512;
1463 max_offset = 3;
1464 break;
1465
1466 case 1: // Multicast MAC Address
1467 initial_val = Q81_RS_ONLY;
1468 max_index = 32;
1469 max_offset = 2;
1470 break;
1471
1472 case 2: // VLAN filter mask
1473 case 3: // MC filter mask
1474 initial_val = Q81_RS_ONLY;
1475 max_index = 4096;
1476 max_offset = 1;
1477 break;
1478
1479 case 4: // FC MAC addresses
1480 initial_val = Q81_RS_ONLY;
1481 max_index = 4;
1482 max_offset = 2;
1483 break;
1484
1485 case 5: // Mgmt MAC addresses
1486 initial_val = Q81_RS_ONLY;
1487 max_index = 8;
1488 max_offset = 2;
1489 break;
1490
1491 case 6: // Mgmt VLAN addresses
1492 initial_val = Q81_RS_ONLY;
1493 max_index = 16;
1494 max_offset = 1;
1495 break;
1496
1497 case 7: // Mgmt IPv4 address
1498 initial_val = Q81_RS_ONLY;
1499 max_index = 4;
1500 max_offset = 1;
1501 break;
1502
1503 case 8: // Mgmt IPv6 address
1504 initial_val = Q81_RS_ONLY;
1505 max_index = 4;
1506 max_offset = 4;
1507 break;
1508
1509 case 9: // Mgmt TCP/UDP Dest port
1510 initial_val = Q81_RS_ONLY;
1511 max_index = 4;
1512 max_offset = 1;
1513 break;
1514
1515 default:
1516 printf("Bad type!!! 0x%08x\n", type);
1517 max_index = 0;
1518 max_offset = 0;
1519 break;
1520 }
1521
1522 for (index = 0; index < max_index; index ++) {
1523 for (offset = 0; offset < max_offset; offset ++) {
1524 val = initial_val | (type << 16) |
1525 (index << 4) | (offset);
1526
1527 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_INDEX,\
1528 val);
1529
1530 result_index = 0;
1531
1532 while ((result_index & 0x40000000) == 0)
1533 result_index =
1534 READ_REG32(ha, \
1535 Q81_CTL_MAC_PROTO_ADDR_INDEX);
1536
1537 result_data = READ_REG32(ha,\
1538 Q81_CTL_MAC_PROTO_ADDR_DATA);
1539
1540 *buf = result_index;
1541 buf ++;
1542
1543 *buf = result_data;
1544 buf ++;
1545 }
1546 }
1547 }
1548 }
1549
1550 static int
qls_get_ets_regs(qla_host_t * ha,uint32_t * buf)1551 qls_get_ets_regs(qla_host_t *ha, uint32_t *buf)
1552 {
1553 int ret = 0;
1554 int i;
1555
1556 for(i = 0; i < 8; i ++, buf ++) {
1557 WRITE_REG32(ha, Q81_CTL_NIC_ENH_TX_SCHD, \
1558 ((i << 29) | 0x08000000));
1559 *buf = READ_REG32(ha, Q81_CTL_NIC_ENH_TX_SCHD);
1560 }
1561
1562 for(i = 0; i < 2; i ++, buf ++) {
1563 WRITE_REG32(ha, Q81_CTL_CNA_ENH_TX_SCHD, \
1564 ((i << 29) | 0x08000000));
1565 *buf = READ_REG32(ha, Q81_CTL_CNA_ENH_TX_SCHD);
1566 }
1567
1568 return ret;
1569 }
1570
1571 int
qls_mpi_core_dump(qla_host_t * ha)1572 qls_mpi_core_dump(qla_host_t *ha)
1573 {
1574 int ret;
1575 int i;
1576 uint32_t reg, reg_val;
1577
1578 qls_mpi_coredump_t *mpi_dump = &ql_mpi_coredump;
1579
1580 ret = qls_pause_mpi_risc(ha);
1581 if (ret) {
1582 printf("Failed RISC pause. Status = 0x%.08x\n",ret);
1583 return(-1);
1584 }
1585
1586 memset(&(mpi_dump->mpi_global_header), 0,
1587 sizeof(qls_mpid_glbl_hdr_t));
1588
1589 mpi_dump->mpi_global_header.cookie = Q81_MPID_COOKIE;
1590 mpi_dump->mpi_global_header.hdr_size =
1591 sizeof(qls_mpid_glbl_hdr_t);
1592 mpi_dump->mpi_global_header.img_size =
1593 sizeof(qls_mpi_coredump_t);
1594
1595 memcpy(mpi_dump->mpi_global_header.id, "MPI Coredump",
1596 sizeof(mpi_dump->mpi_global_header.id));
1597
1598 qls_mpid_seg_hdr(&mpi_dump->nic1_regs_seg_hdr,
1599 Q81_NIC1_CONTROL_SEG_NUM,
1600 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->nic1_regs)),
1601 "NIC1 Registers");
1602
1603 qls_mpid_seg_hdr(&mpi_dump->nic2_regs_seg_hdr,
1604 Q81_NIC2_CONTROL_SEG_NUM,
1605 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->nic2_regs)),
1606 "NIC2 Registers");
1607
1608 qls_mpid_seg_hdr(&mpi_dump->xgmac1_seg_hdr,
1609 Q81_NIC1_XGMAC_SEG_NUM,
1610 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->xgmac1)),
1611 "NIC1 XGMac Registers");
1612
1613 qls_mpid_seg_hdr(&mpi_dump->xgmac2_seg_hdr,
1614 Q81_NIC2_XGMAC_SEG_NUM,
1615 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->xgmac2)),
1616 "NIC2 XGMac Registers");
1617
1618 if (ha->pci_func & 1) {
1619 for (i = 0; i < 64; i++)
1620 mpi_dump->nic2_regs[i] =
1621 READ_REG32(ha, i * sizeof(uint32_t));
1622
1623 for (i = 0; i < 64; i++)
1624 mpi_dump->nic1_regs[i] =
1625 qls_rd_ofunc_reg(ha,
1626 (i * sizeof(uint32_t)) / 4);
1627
1628 qls_rd_xgmac_regs(ha, &mpi_dump->xgmac2[0], 0);
1629 qls_rd_xgmac_regs(ha, &mpi_dump->xgmac1[0], 1);
1630 } else {
1631 for (i = 0; i < 64; i++)
1632 mpi_dump->nic1_regs[i] =
1633 READ_REG32(ha, i * sizeof(uint32_t));
1634
1635 for (i = 0; i < 64; i++)
1636 mpi_dump->nic2_regs[i] =
1637 qls_rd_ofunc_reg(ha,
1638 (i * sizeof(uint32_t)) / 4);
1639
1640 qls_rd_xgmac_regs(ha, &mpi_dump->xgmac1[0], 0);
1641 qls_rd_xgmac_regs(ha, &mpi_dump->xgmac2[0], 1);
1642 }
1643
1644 qls_mpid_seg_hdr(&mpi_dump->xaui1_an_hdr,
1645 Q81_XAUI1_AN_SEG_NUM,
1646 (sizeof(qls_mpid_seg_hdr_t) +
1647 sizeof(mpi_dump->serdes1_xaui_an)),
1648 "XAUI1 AN Registers");
1649
1650 qls_mpid_seg_hdr(&mpi_dump->xaui1_hss_pcs_hdr,
1651 Q81_XAUI1_HSS_PCS_SEG_NUM,
1652 (sizeof(qls_mpid_seg_hdr_t) +
1653 sizeof(mpi_dump->serdes1_xaui_hss_pcs)),
1654 "XAUI1 HSS PCS Registers");
1655
1656 qls_mpid_seg_hdr(&mpi_dump->xfi1_an_hdr,
1657 Q81_XFI1_AN_SEG_NUM,
1658 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->serdes1_xfi_an)),
1659 "XFI1 AN Registers");
1660
1661 qls_mpid_seg_hdr(&mpi_dump->xfi1_train_hdr,
1662 Q81_XFI1_TRAIN_SEG_NUM,
1663 (sizeof(qls_mpid_seg_hdr_t) +
1664 sizeof(mpi_dump->serdes1_xfi_train)),
1665 "XFI1 TRAIN Registers");
1666
1667 qls_mpid_seg_hdr(&mpi_dump->xfi1_hss_pcs_hdr,
1668 Q81_XFI1_HSS_PCS_SEG_NUM,
1669 (sizeof(qls_mpid_seg_hdr_t) +
1670 sizeof(mpi_dump->serdes1_xfi_hss_pcs)),
1671 "XFI1 HSS PCS Registers");
1672
1673 qls_mpid_seg_hdr(&mpi_dump->xfi1_hss_tx_hdr,
1674 Q81_XFI1_HSS_TX_SEG_NUM,
1675 (sizeof(qls_mpid_seg_hdr_t) +
1676 sizeof(mpi_dump->serdes1_xfi_hss_tx)),
1677 "XFI1 HSS TX Registers");
1678
1679 qls_mpid_seg_hdr(&mpi_dump->xfi1_hss_rx_hdr,
1680 Q81_XFI1_HSS_RX_SEG_NUM,
1681 (sizeof(qls_mpid_seg_hdr_t) +
1682 sizeof(mpi_dump->serdes1_xfi_hss_rx)),
1683 "XFI1 HSS RX Registers");
1684
1685 qls_mpid_seg_hdr(&mpi_dump->xfi1_hss_pll_hdr,
1686 Q81_XFI1_HSS_PLL_SEG_NUM,
1687 (sizeof(qls_mpid_seg_hdr_t) +
1688 sizeof(mpi_dump->serdes1_xfi_hss_pll)),
1689 "XFI1 HSS PLL Registers");
1690
1691 qls_mpid_seg_hdr(&mpi_dump->xaui2_an_hdr,
1692 Q81_XAUI2_AN_SEG_NUM,
1693 (sizeof(qls_mpid_seg_hdr_t) +
1694 sizeof(mpi_dump->serdes2_xaui_an)),
1695 "XAUI2 AN Registers");
1696
1697 qls_mpid_seg_hdr(&mpi_dump->xaui2_hss_pcs_hdr,
1698 Q81_XAUI2_HSS_PCS_SEG_NUM,
1699 (sizeof(qls_mpid_seg_hdr_t) +
1700 sizeof(mpi_dump->serdes2_xaui_hss_pcs)),
1701 "XAUI2 HSS PCS Registers");
1702
1703 qls_mpid_seg_hdr(&mpi_dump->xfi2_an_hdr,
1704 Q81_XFI2_AN_SEG_NUM,
1705 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->serdes2_xfi_an)),
1706 "XFI2 AN Registers");
1707
1708 qls_mpid_seg_hdr(&mpi_dump->xfi2_train_hdr,
1709 Q81_XFI2_TRAIN_SEG_NUM,
1710 (sizeof(qls_mpid_seg_hdr_t) +
1711 sizeof(mpi_dump->serdes2_xfi_train)),
1712 "XFI2 TRAIN Registers");
1713
1714 qls_mpid_seg_hdr(&mpi_dump->xfi2_hss_pcs_hdr,
1715 Q81_XFI2_HSS_PCS_SEG_NUM,
1716 (sizeof(qls_mpid_seg_hdr_t) +
1717 sizeof(mpi_dump->serdes2_xfi_hss_pcs)),
1718 "XFI2 HSS PCS Registers");
1719
1720 qls_mpid_seg_hdr(&mpi_dump->xfi2_hss_tx_hdr,
1721 Q81_XFI2_HSS_TX_SEG_NUM,
1722 (sizeof(qls_mpid_seg_hdr_t) +
1723 sizeof(mpi_dump->serdes2_xfi_hss_tx)),
1724 "XFI2 HSS TX Registers");
1725
1726 qls_mpid_seg_hdr(&mpi_dump->xfi2_hss_rx_hdr,
1727 Q81_XFI2_HSS_RX_SEG_NUM,
1728 (sizeof(qls_mpid_seg_hdr_t) +
1729 sizeof(mpi_dump->serdes2_xfi_hss_rx)),
1730 "XFI2 HSS RX Registers");
1731
1732 qls_mpid_seg_hdr(&mpi_dump->xfi2_hss_pll_hdr,
1733 Q81_XFI2_HSS_PLL_SEG_NUM,
1734 (sizeof(qls_mpid_seg_hdr_t) +
1735 sizeof(mpi_dump->serdes2_xfi_hss_pll)),
1736 "XFI2 HSS PLL Registers");
1737
1738 qls_rd_serdes_regs(ha, mpi_dump);
1739
1740 qls_mpid_seg_hdr(&mpi_dump->core_regs_seg_hdr,
1741 Q81_CORE_SEG_NUM,
1742 (sizeof(mpi_dump->core_regs_seg_hdr) +
1743 sizeof(mpi_dump->mpi_core_regs) +
1744 sizeof(mpi_dump->mpi_core_sh_regs)),
1745 "Core Registers");
1746
1747 ret = qls_get_mpi_regs(ha, &mpi_dump->mpi_core_regs[0],
1748 Q81_MPI_CORE_REGS_ADDR, Q81_MPI_CORE_REGS_CNT);
1749
1750 ret = qls_get_mpi_shadow_regs(ha,
1751 &mpi_dump->mpi_core_sh_regs[0]);
1752
1753 qls_mpid_seg_hdr(&mpi_dump->test_logic_regs_seg_hdr,
1754 Q81_TEST_LOGIC_SEG_NUM,
1755 (sizeof(qls_mpid_seg_hdr_t) +
1756 sizeof(mpi_dump->test_logic_regs)),
1757 "Test Logic Regs");
1758
1759 ret = qls_get_mpi_regs(ha, &mpi_dump->test_logic_regs[0],
1760 Q81_TEST_REGS_ADDR, Q81_TEST_REGS_CNT);
1761
1762 qls_mpid_seg_hdr(&mpi_dump->rmii_regs_seg_hdr,
1763 Q81_RMII_SEG_NUM,
1764 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->rmii_regs)),
1765 "RMII Registers");
1766
1767 ret = qls_get_mpi_regs(ha, &mpi_dump->rmii_regs[0],
1768 Q81_RMII_REGS_ADDR, Q81_RMII_REGS_CNT);
1769
1770 qls_mpid_seg_hdr(&mpi_dump->fcmac1_regs_seg_hdr,
1771 Q81_FCMAC1_SEG_NUM,
1772 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->fcmac1_regs)),
1773 "FCMAC1 Registers");
1774
1775 ret = qls_get_mpi_regs(ha, &mpi_dump->fcmac1_regs[0],
1776 Q81_FCMAC1_REGS_ADDR, Q81_FCMAC_REGS_CNT);
1777
1778 qls_mpid_seg_hdr(&mpi_dump->fcmac2_regs_seg_hdr,
1779 Q81_FCMAC2_SEG_NUM,
1780 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->fcmac2_regs)),
1781 "FCMAC2 Registers");
1782
1783 ret = qls_get_mpi_regs(ha, &mpi_dump->fcmac2_regs[0],
1784 Q81_FCMAC2_REGS_ADDR, Q81_FCMAC_REGS_CNT);
1785
1786 qls_mpid_seg_hdr(&mpi_dump->fc1_mbx_regs_seg_hdr,
1787 Q81_FC1_MBOX_SEG_NUM,
1788 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->fc1_mbx_regs)),
1789 "FC1 MBox Regs");
1790
1791 ret = qls_get_mpi_regs(ha, &mpi_dump->fc1_mbx_regs[0],
1792 Q81_FC1_MBX_REGS_ADDR, Q81_FC_MBX_REGS_CNT);
1793
1794 qls_mpid_seg_hdr(&mpi_dump->ide_regs_seg_hdr,
1795 Q81_IDE_SEG_NUM,
1796 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->ide_regs)),
1797 "IDE Registers");
1798
1799 ret = qls_get_mpi_regs(ha, &mpi_dump->ide_regs[0],
1800 Q81_IDE_REGS_ADDR, Q81_IDE_REGS_CNT);
1801
1802 qls_mpid_seg_hdr(&mpi_dump->nic1_mbx_regs_seg_hdr,
1803 Q81_NIC1_MBOX_SEG_NUM,
1804 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->nic1_mbx_regs)),
1805 "NIC1 MBox Regs");
1806
1807 ret = qls_get_mpi_regs(ha, &mpi_dump->nic1_mbx_regs[0],
1808 Q81_NIC1_MBX_REGS_ADDR, Q81_NIC_MBX_REGS_CNT);
1809
1810 qls_mpid_seg_hdr(&mpi_dump->smbus_regs_seg_hdr,
1811 Q81_SMBUS_SEG_NUM,
1812 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->smbus_regs)),
1813 "SMBus Registers");
1814
1815 ret = qls_get_mpi_regs(ha, &mpi_dump->smbus_regs[0],
1816 Q81_SMBUS_REGS_ADDR, Q81_SMBUS_REGS_CNT);
1817
1818 qls_mpid_seg_hdr(&mpi_dump->fc2_mbx_regs_seg_hdr,
1819 Q81_FC2_MBOX_SEG_NUM,
1820 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->fc2_mbx_regs)),
1821 "FC2 MBox Regs");
1822
1823 ret = qls_get_mpi_regs(ha, &mpi_dump->fc2_mbx_regs[0],
1824 Q81_FC2_MBX_REGS_ADDR, Q81_FC_MBX_REGS_CNT);
1825
1826 qls_mpid_seg_hdr(&mpi_dump->nic2_mbx_regs_seg_hdr,
1827 Q81_NIC2_MBOX_SEG_NUM,
1828 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->nic2_mbx_regs)),
1829 "NIC2 MBox Regs");
1830
1831 ret = qls_get_mpi_regs(ha, &mpi_dump->nic2_mbx_regs[0],
1832 Q81_NIC2_MBX_REGS_ADDR, Q81_NIC_MBX_REGS_CNT);
1833
1834 qls_mpid_seg_hdr(&mpi_dump->i2c_regs_seg_hdr,
1835 Q81_I2C_SEG_NUM,
1836 (sizeof(qls_mpid_seg_hdr_t) +
1837 sizeof(mpi_dump->i2c_regs)),
1838 "I2C Registers");
1839
1840 ret = qls_get_mpi_regs(ha, &mpi_dump->i2c_regs[0],
1841 Q81_I2C_REGS_ADDR, Q81_I2C_REGS_CNT);
1842
1843 qls_mpid_seg_hdr(&mpi_dump->memc_regs_seg_hdr,
1844 Q81_MEMC_SEG_NUM,
1845 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->memc_regs)),
1846 "MEMC Registers");
1847
1848 ret = qls_get_mpi_regs(ha, &mpi_dump->memc_regs[0],
1849 Q81_MEMC_REGS_ADDR, Q81_MEMC_REGS_CNT);
1850
1851 qls_mpid_seg_hdr(&mpi_dump->pbus_regs_seg_hdr,
1852 Q81_PBUS_SEG_NUM,
1853 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->pbus_regs)),
1854 "PBUS Registers");
1855
1856 ret = qls_get_mpi_regs(ha, &mpi_dump->pbus_regs[0],
1857 Q81_PBUS_REGS_ADDR, Q81_PBUS_REGS_CNT);
1858
1859 qls_mpid_seg_hdr(&mpi_dump->mde_regs_seg_hdr,
1860 Q81_MDE_SEG_NUM,
1861 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->mde_regs)),
1862 "MDE Registers");
1863
1864 ret = qls_get_mpi_regs(ha, &mpi_dump->mde_regs[0],
1865 Q81_MDE_REGS_ADDR, Q81_MDE_REGS_CNT);
1866
1867 qls_mpid_seg_hdr(&mpi_dump->intr_states_seg_hdr,
1868 Q81_INTR_STATES_SEG_NUM,
1869 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->intr_states)),
1870 "INTR States");
1871
1872 qls_get_intr_states(ha, &mpi_dump->intr_states[0]);
1873
1874 qls_mpid_seg_hdr(&mpi_dump->probe_dump_seg_hdr,
1875 Q81_PROBE_DUMP_SEG_NUM,
1876 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->probe_dump)),
1877 "Probe Dump");
1878
1879 qls_get_probe_dump(ha, &mpi_dump->probe_dump[0]);
1880
1881 qls_mpid_seg_hdr(&mpi_dump->routing_reg_seg_hdr,
1882 Q81_ROUTING_INDEX_SEG_NUM,
1883 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->routing_regs)),
1884 "Routing Regs");
1885
1886 qls_get_ridx_registers(ha, &mpi_dump->routing_regs[0]);
1887
1888 qls_mpid_seg_hdr(&mpi_dump->mac_prot_reg_seg_hdr,
1889 Q81_MAC_PROTOCOL_SEG_NUM,
1890 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->mac_prot_regs)),
1891 "MAC Prot Regs");
1892
1893 qls_get_mac_proto_regs(ha, &mpi_dump->mac_prot_regs[0]);
1894
1895 qls_mpid_seg_hdr(&mpi_dump->ets_seg_hdr,
1896 Q81_ETS_SEG_NUM,
1897 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->ets)),
1898 "ETS Registers");
1899
1900 ret = qls_get_ets_regs(ha, &mpi_dump->ets[0]);
1901
1902 qls_mpid_seg_hdr(&mpi_dump->sem_regs_seg_hdr,
1903 Q81_SEM_REGS_SEG_NUM,
1904 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->sem_regs)),
1905 "Sem Registers");
1906
1907 for(i = 0; i < Q81_MAX_SEMAPHORE_FUNCTIONS ; i ++) {
1908 reg = Q81_CTL_PROC_ADDR_REG_BLOCK | (i << Q81_FUNCTION_SHIFT) |
1909 (Q81_CTL_SEMAPHORE >> 2);
1910
1911 ret = qls_mpi_risc_rd_reg(ha, reg, ®_val);
1912 mpi_dump->sem_regs[i] = reg_val;
1913
1914 if (ret != 0)
1915 mpi_dump->sem_regs[i] = Q81_BAD_DATA;
1916 }
1917
1918 ret = qls_unpause_mpi_risc(ha);
1919 if (ret)
1920 printf("Failed RISC unpause. Status = 0x%.08x\n",ret);
1921
1922 ret = qls_mpi_reset(ha);
1923 if (ret)
1924 printf("Failed RISC reset. Status = 0x%.08x\n",ret);
1925
1926 WRITE_REG32(ha, Q81_CTL_FUNC_SPECIFIC, 0x80008000);
1927
1928 qls_mpid_seg_hdr(&mpi_dump->memc_ram_seg_hdr,
1929 Q81_MEMC_RAM_SEG_NUM,
1930 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->memc_ram)),
1931 "MEMC RAM");
1932
1933 ret = qls_mbx_dump_risc_ram(ha, &mpi_dump->memc_ram[0],
1934 Q81_MEMC_RAM_ADDR, Q81_MEMC_RAM_CNT);
1935 if (ret)
1936 printf("Failed Dump of MEMC RAM. Status = 0x%.08x\n",ret);
1937
1938 qls_mpid_seg_hdr(&mpi_dump->code_ram_seg_hdr,
1939 Q81_WCS_RAM_SEG_NUM,
1940 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->code_ram)),
1941 "WCS RAM");
1942
1943 ret = qls_mbx_dump_risc_ram(ha, &mpi_dump->memc_ram[0],
1944 Q81_CODE_RAM_ADDR, Q81_CODE_RAM_CNT);
1945 if (ret)
1946 printf("Failed Dump of CODE RAM. Status = 0x%.08x\n",ret);
1947
1948 qls_mpid_seg_hdr(&mpi_dump->wqc1_seg_hdr,
1949 Q81_WQC1_SEG_NUM,
1950 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->wqc1)),
1951 "WQC 1");
1952
1953 qls_mpid_seg_hdr(&mpi_dump->wqc2_seg_hdr,
1954 Q81_WQC2_SEG_NUM,
1955 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->wqc2)),
1956 "WQC 2");
1957
1958 qls_mpid_seg_hdr(&mpi_dump->cqc1_seg_hdr,
1959 Q81_CQC1_SEG_NUM,
1960 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->cqc1)),
1961 "CQC 1");
1962
1963 qls_mpid_seg_hdr(&mpi_dump->cqc2_seg_hdr,
1964 Q81_CQC2_SEG_NUM,
1965 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->cqc2)),
1966 "CQC 2");
1967
1968 return 0;
1969 }
1970