1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 1999 Seigo Tanimura
5 * All rights reserved.
6 *
7 * Portions of this source are based on cwcealdr.cpp and dhwiface.cpp in
8 * cwcealdr1.zip, the sample sources by Crystal Semiconductor.
9 * Copyright (c) 1996-1998 Crystal Semiconductor Corp.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * SUCH DAMAGE.
31 */
32
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/kernel.h>
36 #include <sys/bus.h>
37 #include <sys/malloc.h>
38 #include <sys/module.h>
39 #include <machine/resource.h>
40 #include <machine/bus.h>
41 #include <sys/rman.h>
42
43 #ifdef HAVE_KERNEL_OPTION_HEADERS
44 #include "opt_snd.h"
45 #endif
46
47 #include <dev/sound/pcm/sound.h>
48 #include <dev/sound/chip.h>
49 #include <dev/sound/pci/csareg.h>
50 #include <dev/sound/pci/csavar.h>
51
52 #include <dev/pci/pcireg.h>
53 #include <dev/pci/pcivar.h>
54
55 #include <dev/sound/pci/cs461x_dsp.h>
56
57 SND_DECLARE_FILE("");
58
59 /* This is the pci device id. */
60 #define CS4610_PCI_ID 0x60011013
61 #define CS4614_PCI_ID 0x60031013
62 #define CS4615_PCI_ID 0x60041013
63
64 /* Here is the parameter structure per a device. */
65 struct csa_softc {
66 device_t dev; /* device */
67 csa_res res; /* resources */
68
69 device_t pcm; /* pcm device */
70 driver_intr_t* pcmintr; /* pcm intr */
71 void *pcmintr_arg; /* pcm intr arg */
72 device_t midi; /* midi device */
73 driver_intr_t* midiintr; /* midi intr */
74 void *midiintr_arg; /* midi intr arg */
75 void *ih; /* cookie */
76
77 struct csa_card *card;
78 struct csa_bridgeinfo binfo; /* The state of this bridge. */
79 };
80
81 typedef struct csa_softc *sc_p;
82
83 static int csa_probe(device_t dev);
84 static int csa_attach(device_t dev);
85 static struct resource *csa_alloc_resource(device_t bus, device_t child, int type, int *rid,
86 rman_res_t start, rman_res_t end,
87 rman_res_t count, u_int flags);
88 static int csa_release_resource(device_t bus, device_t child, int type, int rid,
89 struct resource *r);
90 static int csa_setup_intr(device_t bus, device_t child,
91 struct resource *irq, int flags,
92 driver_filter_t *filter,
93 driver_intr_t *intr, void *arg, void **cookiep);
94 static int csa_teardown_intr(device_t bus, device_t child,
95 struct resource *irq, void *cookie);
96 static driver_intr_t csa_intr;
97 static int csa_initialize(sc_p scp);
98 static int csa_downloadimage(csa_res *resp);
99 static int csa_transferimage(csa_res *resp, u_int32_t *src, u_long dest, u_long len);
100
101 static devclass_t csa_devclass;
102
103 static void
amp_none(void)104 amp_none(void)
105 {
106 }
107
108 static void
amp_voyetra(void)109 amp_voyetra(void)
110 {
111 }
112
113 static int
clkrun_hack(int run)114 clkrun_hack(int run)
115 {
116 #ifdef __i386__
117 device_t child;
118 int port;
119 u_int16_t control;
120 bus_space_tag_t btag;
121
122 child = pci_find_device(0x8086, 0x7113);
123 if (child == NULL)
124 return (ENXIO);
125
126 port = (pci_read_config(child, 0x41, 1) << 8) + 0x10;
127 /* XXX */
128 btag = X86_BUS_SPACE_IO;
129
130 control = bus_space_read_2(btag, 0x0, port);
131 control &= ~0x2000;
132 control |= run? 0 : 0x2000;
133 bus_space_write_2(btag, 0x0, port, control);
134 #endif
135 return (0);
136 }
137
138 static struct csa_card cards_4610[] = {
139 {0, 0, "Unknown/invalid SSID (CS4610)", NULL, NULL, NULL, 0},
140 };
141
142 static struct csa_card cards_4614[] = {
143 {0x1489, 0x7001, "Genius Soundmaker 128 value", amp_none, NULL, NULL, 0},
144 {0x5053, 0x3357, "Turtle Beach Santa Cruz", amp_voyetra, NULL, NULL, 1},
145 {0x1071, 0x6003, "Mitac MI6020/21", amp_voyetra, NULL, NULL, 0},
146 {0x14AF, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL, 0},
147 {0x1681, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL, 0},
148 {0x1014, 0x0132, "Thinkpad 570", amp_none, NULL, NULL, 0},
149 {0x1014, 0x0153, "Thinkpad 600X/A20/T20", amp_none, NULL, clkrun_hack, 0},
150 {0x1014, 0x1010, "Thinkpad 600E (unsupported)", NULL, NULL, NULL, 0},
151 {0x153b, 0x1136, "Terratec SiXPack 5.1+", NULL, NULL, NULL, 0},
152 {0, 0, "Unknown/invalid SSID (CS4614)", NULL, NULL, NULL, 0},
153 };
154
155 static struct csa_card cards_4615[] = {
156 {0, 0, "Unknown/invalid SSID (CS4615)", NULL, NULL, NULL, 0},
157 };
158
159 static struct csa_card nocard = {0, 0, "unknown", NULL, NULL, NULL, 0};
160
161 struct card_type {
162 u_int32_t devid;
163 char *name;
164 struct csa_card *cards;
165 };
166
167 static struct card_type cards[] = {
168 {CS4610_PCI_ID, "CS4610/CS4611", cards_4610},
169 {CS4614_PCI_ID, "CS4280/CS4614/CS4622/CS4624/CS4630", cards_4614},
170 {CS4615_PCI_ID, "CS4615", cards_4615},
171 {0, NULL, NULL},
172 };
173
174 static struct card_type *
csa_findcard(device_t dev)175 csa_findcard(device_t dev)
176 {
177 int i;
178
179 i = 0;
180 while (cards[i].devid != 0) {
181 if (pci_get_devid(dev) == cards[i].devid)
182 return &cards[i];
183 i++;
184 }
185 return NULL;
186 }
187
188 struct csa_card *
csa_findsubcard(device_t dev)189 csa_findsubcard(device_t dev)
190 {
191 int i;
192 struct card_type *card;
193 struct csa_card *subcard;
194
195 card = csa_findcard(dev);
196 if (card == NULL)
197 return &nocard;
198 subcard = card->cards;
199 i = 0;
200 while (subcard[i].subvendor != 0) {
201 if (pci_get_subvendor(dev) == subcard[i].subvendor
202 && pci_get_subdevice(dev) == subcard[i].subdevice) {
203 return &subcard[i];
204 }
205 i++;
206 }
207 return &subcard[i];
208 }
209
210 static int
csa_probe(device_t dev)211 csa_probe(device_t dev)
212 {
213 struct card_type *card;
214
215 card = csa_findcard(dev);
216 if (card) {
217 device_set_desc(dev, card->name);
218 return BUS_PROBE_DEFAULT;
219 }
220 return ENXIO;
221 }
222
223 static int
csa_attach(device_t dev)224 csa_attach(device_t dev)
225 {
226 sc_p scp;
227 csa_res *resp;
228 struct sndcard_func *func;
229 int error = ENXIO;
230
231 scp = device_get_softc(dev);
232
233 /* Fill in the softc. */
234 bzero(scp, sizeof(*scp));
235 scp->dev = dev;
236
237 pci_enable_busmaster(dev);
238
239 /* Allocate the resources. */
240 resp = &scp->res;
241 scp->card = csa_findsubcard(dev);
242 scp->binfo.card = scp->card;
243 printf("csa: card is %s\n", scp->card->name);
244 resp->io_rid = PCIR_BAR(0);
245 resp->io = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
246 &resp->io_rid, RF_ACTIVE);
247 if (resp->io == NULL)
248 return (ENXIO);
249 resp->mem_rid = PCIR_BAR(1);
250 resp->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
251 &resp->mem_rid, RF_ACTIVE);
252 if (resp->mem == NULL)
253 goto err_io;
254 resp->irq_rid = 0;
255 resp->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
256 &resp->irq_rid, RF_ACTIVE | RF_SHAREABLE);
257 if (resp->irq == NULL)
258 goto err_mem;
259
260 /* Enable interrupt. */
261 if (snd_setup_intr(dev, resp->irq, 0, csa_intr, scp, &scp->ih))
262 goto err_intr;
263 #if 0
264 if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0)
265 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
266 #endif
267
268 /* Initialize the chip. */
269 if (csa_initialize(scp))
270 goto err_teardown;
271
272 /* Reset the Processor. */
273 csa_resetdsp(resp);
274
275 /* Download the Processor Image to the processor. */
276 if (csa_downloadimage(resp))
277 goto err_teardown;
278
279 /* Attach the children. */
280
281 /* PCM Audio */
282 func = malloc(sizeof(struct sndcard_func), M_DEVBUF, M_NOWAIT | M_ZERO);
283 if (func == NULL) {
284 error = ENOMEM;
285 goto err_teardown;
286 }
287 func->varinfo = &scp->binfo;
288 func->func = SCF_PCM;
289 scp->pcm = device_add_child(dev, "pcm", -1);
290 device_set_ivars(scp->pcm, func);
291
292 /* Midi Interface */
293 func = malloc(sizeof(struct sndcard_func), M_DEVBUF, M_NOWAIT | M_ZERO);
294 if (func == NULL) {
295 error = ENOMEM;
296 goto err_teardown;
297 }
298 func->varinfo = &scp->binfo;
299 func->func = SCF_MIDI;
300 scp->midi = device_add_child(dev, "midi", -1);
301 device_set_ivars(scp->midi, func);
302
303 bus_generic_attach(dev);
304
305 return (0);
306
307 err_teardown:
308 bus_teardown_intr(dev, resp->irq, scp->ih);
309 err_intr:
310 bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq);
311 err_mem:
312 bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem);
313 err_io:
314 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io);
315 return (error);
316 }
317
318 static int
csa_detach(device_t dev)319 csa_detach(device_t dev)
320 {
321 csa_res *resp;
322 sc_p scp;
323 struct sndcard_func *func;
324 int err;
325
326 scp = device_get_softc(dev);
327 resp = &scp->res;
328
329 if (scp->midi != NULL) {
330 func = device_get_ivars(scp->midi);
331 err = device_delete_child(dev, scp->midi);
332 if (err != 0)
333 return err;
334 if (func != NULL)
335 free(func, M_DEVBUF);
336 scp->midi = NULL;
337 }
338
339 if (scp->pcm != NULL) {
340 func = device_get_ivars(scp->pcm);
341 err = device_delete_child(dev, scp->pcm);
342 if (err != 0)
343 return err;
344 if (func != NULL)
345 free(func, M_DEVBUF);
346 scp->pcm = NULL;
347 }
348
349 bus_teardown_intr(dev, resp->irq, scp->ih);
350 bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq);
351 bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem);
352 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io);
353
354 return bus_generic_detach(dev);
355 }
356
357 static int
csa_resume(device_t dev)358 csa_resume(device_t dev)
359 {
360 csa_res *resp;
361 sc_p scp;
362
363 scp = device_get_softc(dev);
364 resp = &scp->res;
365
366 /* Initialize the chip. */
367 if (csa_initialize(scp))
368 return (ENXIO);
369
370 /* Reset the Processor. */
371 csa_resetdsp(resp);
372
373 /* Download the Processor Image to the processor. */
374 if (csa_downloadimage(resp))
375 return (ENXIO);
376
377 return (bus_generic_resume(dev));
378 }
379
380 static struct resource *
csa_alloc_resource(device_t bus,device_t child,int type,int * rid,rman_res_t start,rman_res_t end,rman_res_t count,u_int flags)381 csa_alloc_resource(device_t bus, device_t child, int type, int *rid,
382 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
383 {
384 sc_p scp;
385 csa_res *resp;
386 struct resource *res;
387
388 scp = device_get_softc(bus);
389 resp = &scp->res;
390 switch (type) {
391 case SYS_RES_IRQ:
392 if (*rid != 0)
393 return (NULL);
394 res = resp->irq;
395 break;
396 case SYS_RES_MEMORY:
397 switch (*rid) {
398 case PCIR_BAR(0):
399 res = resp->io;
400 break;
401 case PCIR_BAR(1):
402 res = resp->mem;
403 break;
404 default:
405 return (NULL);
406 }
407 break;
408 default:
409 return (NULL);
410 }
411
412 return res;
413 }
414
415 static int
csa_release_resource(device_t bus,device_t child,int type,int rid,struct resource * r)416 csa_release_resource(device_t bus, device_t child, int type, int rid,
417 struct resource *r)
418 {
419 return (0);
420 }
421
422 /*
423 * The following three functions deal with interrupt handling.
424 * An interrupt is primarily handled by the bridge driver.
425 * The bridge driver then determines the child devices to pass
426 * the interrupt. Certain information of the device can be read
427 * only once(eg the value of HISR). The bridge driver is responsible
428 * to pass such the information to the children.
429 */
430
431 static int
csa_setup_intr(device_t bus,device_t child,struct resource * irq,int flags,driver_filter_t * filter,driver_intr_t * intr,void * arg,void ** cookiep)432 csa_setup_intr(device_t bus, device_t child,
433 struct resource *irq, int flags,
434 driver_filter_t *filter,
435 driver_intr_t *intr, void *arg, void **cookiep)
436 {
437 sc_p scp;
438 csa_res *resp;
439 struct sndcard_func *func;
440
441 if (filter != NULL) {
442 printf("ata-csa.c: we cannot use a filter here\n");
443 return (EINVAL);
444 }
445 scp = device_get_softc(bus);
446 resp = &scp->res;
447
448 /*
449 * Look at the function code of the child to determine
450 * the appropriate handler for it.
451 */
452 func = device_get_ivars(child);
453 if (func == NULL || irq != resp->irq)
454 return (EINVAL);
455
456 switch (func->func) {
457 case SCF_PCM:
458 scp->pcmintr = intr;
459 scp->pcmintr_arg = arg;
460 break;
461
462 case SCF_MIDI:
463 scp->midiintr = intr;
464 scp->midiintr_arg = arg;
465 break;
466
467 default:
468 return (EINVAL);
469 }
470 *cookiep = scp;
471 if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0)
472 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
473
474 return (0);
475 }
476
477 static int
csa_teardown_intr(device_t bus,device_t child,struct resource * irq,void * cookie)478 csa_teardown_intr(device_t bus, device_t child,
479 struct resource *irq, void *cookie)
480 {
481 sc_p scp;
482 csa_res *resp;
483 struct sndcard_func *func;
484
485 scp = device_get_softc(bus);
486 resp = &scp->res;
487
488 /*
489 * Look at the function code of the child to determine
490 * the appropriate handler for it.
491 */
492 func = device_get_ivars(child);
493 if (func == NULL || irq != resp->irq || cookie != scp)
494 return (EINVAL);
495
496 switch (func->func) {
497 case SCF_PCM:
498 scp->pcmintr = NULL;
499 scp->pcmintr_arg = NULL;
500 break;
501
502 case SCF_MIDI:
503 scp->midiintr = NULL;
504 scp->midiintr_arg = NULL;
505 break;
506
507 default:
508 return (EINVAL);
509 }
510
511 return (0);
512 }
513
514 /* The interrupt handler */
515 static void
csa_intr(void * arg)516 csa_intr(void *arg)
517 {
518 sc_p scp = arg;
519 csa_res *resp;
520 u_int32_t hisr;
521
522 resp = &scp->res;
523
524 /* Is this interrupt for us? */
525 hisr = csa_readio(resp, BA0_HISR);
526 if ((hisr & 0x7fffffff) == 0) {
527 /* Throw an eoi. */
528 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
529 return;
530 }
531
532 /*
533 * Pass the value of HISR via struct csa_bridgeinfo.
534 * The children get access through their ivars.
535 */
536 scp->binfo.hisr = hisr;
537
538 /* Invoke the handlers of the children. */
539 if ((hisr & (HISR_VC0 | HISR_VC1)) != 0 && scp->pcmintr != NULL) {
540 scp->pcmintr(scp->pcmintr_arg);
541 hisr &= ~(HISR_VC0 | HISR_VC1);
542 }
543 if ((hisr & HISR_MIDI) != 0 && scp->midiintr != NULL) {
544 scp->midiintr(scp->midiintr_arg);
545 hisr &= ~HISR_MIDI;
546 }
547
548 /* Throw an eoi. */
549 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
550 }
551
552 static int
csa_initialize(sc_p scp)553 csa_initialize(sc_p scp)
554 {
555 int i;
556 u_int32_t acsts, acisv;
557 csa_res *resp;
558
559 resp = &scp->res;
560
561 /*
562 * First, blast the clock control register to zero so that the PLL starts
563 * out in a known state, and blast the master serial port control register
564 * to zero so that the serial ports also start out in a known state.
565 */
566 csa_writeio(resp, BA0_CLKCR1, 0);
567 csa_writeio(resp, BA0_SERMC1, 0);
568
569 /*
570 * If we are in AC97 mode, then we must set the part to a host controlled
571 * AC-link. Otherwise, we won't be able to bring up the link.
572 */
573 #if 1
574 csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_1_03); /* 1.03 codec */
575 #else
576 csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_2_0); /* 2.0 codec */
577 #endif /* 1 */
578
579 /*
580 * Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
581 * spec) and then drive it high. This is done for non AC97 modes since
582 * there might be logic external to the CS461x that uses the ARST# line
583 * for a reset.
584 */
585 csa_writeio(resp, BA0_ACCTL, 1);
586 DELAY(50);
587 csa_writeio(resp, BA0_ACCTL, 0);
588 DELAY(50);
589 csa_writeio(resp, BA0_ACCTL, ACCTL_RSTN);
590
591 /*
592 * The first thing we do here is to enable sync generation. As soon
593 * as we start receiving bit clock, we'll start producing the SYNC
594 * signal.
595 */
596 csa_writeio(resp, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN);
597
598 /*
599 * Now wait for a short while to allow the AC97 part to start
600 * generating bit clock (so we don't try to start the PLL without an
601 * input clock).
602 */
603 DELAY(50000);
604
605 /*
606 * Set the serial port timing configuration, so that
607 * the clock control circuit gets its clock from the correct place.
608 */
609 csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97);
610 DELAY(700000);
611
612 /*
613 * Write the selected clock control setup to the hardware. Do not turn on
614 * SWCE yet (if requested), so that the devices clocked by the output of
615 * PLL are not clocked until the PLL is stable.
616 */
617 csa_writeio(resp, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ);
618 csa_writeio(resp, BA0_PLLM, 0x3a);
619 csa_writeio(resp, BA0_CLKCR2, CLKCR2_PDIVS_8);
620
621 /*
622 * Power up the PLL.
623 */
624 csa_writeio(resp, BA0_CLKCR1, CLKCR1_PLLP);
625
626 /*
627 * Wait until the PLL has stabilized.
628 */
629 DELAY(5000);
630
631 /*
632 * Turn on clocking of the core so that we can setup the serial ports.
633 */
634 csa_writeio(resp, BA0_CLKCR1, csa_readio(resp, BA0_CLKCR1) | CLKCR1_SWCE);
635
636 /*
637 * Fill the serial port FIFOs with silence.
638 */
639 csa_clearserialfifos(resp);
640
641 /*
642 * Set the serial port FIFO pointer to the first sample in the FIFO.
643 */
644 #ifdef notdef
645 csa_writeio(resp, BA0_SERBSP, 0);
646 #endif /* notdef */
647
648 /*
649 * Write the serial port configuration to the part. The master
650 * enable bit is not set until all other values have been written.
651 */
652 csa_writeio(resp, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN);
653 csa_writeio(resp, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN);
654 csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE);
655
656 /*
657 * Wait for the codec ready signal from the AC97 codec.
658 */
659 acsts = 0;
660 for (i = 0 ; i < 1000 ; i++) {
661 /*
662 * First, lets wait a short while to let things settle out a bit,
663 * and to prevent retrying the read too quickly.
664 */
665 DELAY(125);
666
667 /*
668 * Read the AC97 status register to see if we've seen a CODEC READY
669 * signal from the AC97 codec.
670 */
671 acsts = csa_readio(resp, BA0_ACSTS);
672 if ((acsts & ACSTS_CRDY) != 0)
673 break;
674 }
675
676 /*
677 * Make sure we sampled CODEC READY.
678 */
679 if ((acsts & ACSTS_CRDY) == 0)
680 return (ENXIO);
681
682 /*
683 * Assert the vaid frame signal so that we can start sending commands
684 * to the AC97 codec.
685 */
686 csa_writeio(resp, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
687
688 /*
689 * Wait until we've sampled input slots 3 and 4 as valid, meaning that
690 * the codec is pumping ADC data across the AC-link.
691 */
692 acisv = 0;
693 for (i = 0 ; i < 2000 ; i++) {
694 /*
695 * First, lets wait a short while to let things settle out a bit,
696 * and to prevent retrying the read too quickly.
697 */
698 #ifdef notdef
699 DELAY(10000000L); /* clw */
700 #else
701 DELAY(1000);
702 #endif /* notdef */
703 /*
704 * Read the input slot valid register and see if input slots 3 and
705 * 4 are valid yet.
706 */
707 acisv = csa_readio(resp, BA0_ACISV);
708 if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4))
709 break;
710 }
711 /*
712 * Make sure we sampled valid input slots 3 and 4. If not, then return
713 * an error.
714 */
715 if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) != (ACISV_ISV3 | ACISV_ISV4))
716 return (ENXIO);
717
718 /*
719 * Now, assert valid frame and the slot 3 and 4 valid bits. This will
720 * commense the transfer of digital audio data to the AC97 codec.
721 */
722 csa_writeio(resp, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4);
723
724 /*
725 * Power down the DAC and ADC. We will power them up (if) when we need
726 * them.
727 */
728 #ifdef notdef
729 csa_writeio(resp, BA0_AC97_POWERDOWN, 0x300);
730 #endif /* notdef */
731
732 /*
733 * Turn off the Processor by turning off the software clock enable flag in
734 * the clock control register.
735 */
736 #ifdef notdef
737 clkcr1 = csa_readio(resp, BA0_CLKCR1) & ~CLKCR1_SWCE;
738 csa_writeio(resp, BA0_CLKCR1, clkcr1);
739 #endif /* notdef */
740
741 /*
742 * Enable interrupts on the part.
743 */
744 #if 0
745 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
746 #endif /* notdef */
747
748 return (0);
749 }
750
751 void
csa_clearserialfifos(csa_res * resp)752 csa_clearserialfifos(csa_res *resp)
753 {
754 int i, j, pwr;
755 u_int8_t clkcr1, serbst;
756
757 /*
758 * See if the devices are powered down. If so, we must power them up first
759 * or they will not respond.
760 */
761 pwr = 1;
762 clkcr1 = csa_readio(resp, BA0_CLKCR1);
763 if ((clkcr1 & CLKCR1_SWCE) == 0) {
764 csa_writeio(resp, BA0_CLKCR1, clkcr1 | CLKCR1_SWCE);
765 pwr = 0;
766 }
767
768 /*
769 * We want to clear out the serial port FIFOs so we don't end up playing
770 * whatever random garbage happens to be in them. We fill the sample FIFOs
771 * with zero (silence).
772 */
773 csa_writeio(resp, BA0_SERBWP, 0);
774
775 /* Fill all 256 sample FIFO locations. */
776 serbst = 0;
777 for (i = 0 ; i < 256 ; i++) {
778 /* Make sure the previous FIFO write operation has completed. */
779 for (j = 0 ; j < 5 ; j++) {
780 DELAY(100);
781 serbst = csa_readio(resp, BA0_SERBST);
782 if ((serbst & SERBST_WBSY) == 0)
783 break;
784 }
785 if ((serbst & SERBST_WBSY) != 0) {
786 if (!pwr)
787 csa_writeio(resp, BA0_CLKCR1, clkcr1);
788 }
789 /* Write the serial port FIFO index. */
790 csa_writeio(resp, BA0_SERBAD, i);
791 /* Tell the serial port to load the new value into the FIFO location. */
792 csa_writeio(resp, BA0_SERBCM, SERBCM_WRC);
793 }
794 /*
795 * Now, if we powered up the devices, then power them back down again.
796 * This is kinda ugly, but should never happen.
797 */
798 if (!pwr)
799 csa_writeio(resp, BA0_CLKCR1, clkcr1);
800 }
801
802 void
csa_resetdsp(csa_res * resp)803 csa_resetdsp(csa_res *resp)
804 {
805 int i;
806
807 /*
808 * Write the reset bit of the SP control register.
809 */
810 csa_writemem(resp, BA1_SPCR, SPCR_RSTSP);
811
812 /*
813 * Write the control register.
814 */
815 csa_writemem(resp, BA1_SPCR, SPCR_DRQEN);
816
817 /*
818 * Clear the trap registers.
819 */
820 for (i = 0 ; i < 8 ; i++) {
821 csa_writemem(resp, BA1_DREG, DREG_REGID_TRAP_SELECT + i);
822 csa_writemem(resp, BA1_TWPR, 0xffff);
823 }
824 csa_writemem(resp, BA1_DREG, 0);
825
826 /*
827 * Set the frame timer to reflect the number of cycles per frame.
828 */
829 csa_writemem(resp, BA1_FRMT, 0xadf);
830 }
831
832 static int
csa_downloadimage(csa_res * resp)833 csa_downloadimage(csa_res *resp)
834 {
835 int ret;
836 u_long ul, offset;
837
838 for (ul = 0, offset = 0 ; ul < INKY_MEMORY_COUNT ; ul++) {
839 /*
840 * DMA this block from host memory to the appropriate
841 * memory on the CSDevice.
842 */
843 ret = csa_transferimage(resp,
844 cs461x_firmware.BA1Array + offset,
845 cs461x_firmware.MemoryStat[ul].ulDestAddr,
846 cs461x_firmware.MemoryStat[ul].ulSourceSize);
847 if (ret)
848 return (ret);
849 offset += cs461x_firmware.MemoryStat[ul].ulSourceSize >> 2;
850 }
851 return (0);
852 }
853
854 static int
csa_transferimage(csa_res * resp,u_int32_t * src,u_long dest,u_long len)855 csa_transferimage(csa_res *resp, u_int32_t *src, u_long dest, u_long len)
856 {
857 u_long ul;
858
859 /*
860 * We do not allow DMAs from host memory to host memory (although the DMA
861 * can do it) and we do not allow DMAs which are not a multiple of 4 bytes
862 * in size (because that DMA can not do that). Return an error if either
863 * of these conditions exist.
864 */
865 if ((len & 0x3) != 0)
866 return (EINVAL);
867
868 /* Check the destination address that it is a multiple of 4 */
869 if ((dest & 0x3) != 0)
870 return (EINVAL);
871
872 /* Write the buffer out. */
873 for (ul = 0 ; ul < len ; ul += 4)
874 csa_writemem(resp, dest + ul, src[ul >> 2]);
875 return (0);
876 }
877
878 int
csa_readcodec(csa_res * resp,u_long offset,u_int32_t * data)879 csa_readcodec(csa_res *resp, u_long offset, u_int32_t *data)
880 {
881 int i;
882 u_int32_t acctl, acsts;
883
884 /*
885 * Make sure that there is not data sitting around from a previous
886 * uncompleted access. ACSDA = Status Data Register = 47Ch
887 */
888 csa_readio(resp, BA0_ACSDA);
889
890 /*
891 * Setup the AC97 control registers on the CS461x to send the
892 * appropriate command to the AC97 to perform the read.
893 * ACCAD = Command Address Register = 46Ch
894 * ACCDA = Command Data Register = 470h
895 * ACCTL = Control Register = 460h
896 * set DCV - will clear when process completed
897 * set CRW - Read command
898 * set VFRM - valid frame enabled
899 * set ESYN - ASYNC generation enabled
900 * set RSTN - ARST# inactive, AC97 codec not reset
901 */
902
903 /*
904 * Get the actual AC97 register from the offset
905 */
906 csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET);
907 csa_writeio(resp, BA0_ACCDA, 0);
908 csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
909
910 /*
911 * Wait for the read to occur.
912 */
913 acctl = 0;
914 for (i = 0 ; i < 10 ; i++) {
915 /*
916 * First, we want to wait for a short time.
917 */
918 DELAY(25);
919
920 /*
921 * Now, check to see if the read has completed.
922 * ACCTL = 460h, DCV should be reset by now and 460h = 17h
923 */
924 acctl = csa_readio(resp, BA0_ACCTL);
925 if ((acctl & ACCTL_DCV) == 0)
926 break;
927 }
928
929 /*
930 * Make sure the read completed.
931 */
932 if ((acctl & ACCTL_DCV) != 0)
933 return (EAGAIN);
934
935 /*
936 * Wait for the valid status bit to go active.
937 */
938 acsts = 0;
939 for (i = 0 ; i < 10 ; i++) {
940 /*
941 * Read the AC97 status register.
942 * ACSTS = Status Register = 464h
943 */
944 acsts = csa_readio(resp, BA0_ACSTS);
945 /*
946 * See if we have valid status.
947 * VSTS - Valid Status
948 */
949 if ((acsts & ACSTS_VSTS) != 0)
950 break;
951 /*
952 * Wait for a short while.
953 */
954 DELAY(25);
955 }
956
957 /*
958 * Make sure we got valid status.
959 */
960 if ((acsts & ACSTS_VSTS) == 0)
961 return (EAGAIN);
962
963 /*
964 * Read the data returned from the AC97 register.
965 * ACSDA = Status Data Register = 474h
966 */
967 *data = csa_readio(resp, BA0_ACSDA);
968
969 return (0);
970 }
971
972 int
csa_writecodec(csa_res * resp,u_long offset,u_int32_t data)973 csa_writecodec(csa_res *resp, u_long offset, u_int32_t data)
974 {
975 int i;
976 u_int32_t acctl;
977
978 /*
979 * Setup the AC97 control registers on the CS461x to send the
980 * appropriate command to the AC97 to perform the write.
981 * ACCAD = Command Address Register = 46Ch
982 * ACCDA = Command Data Register = 470h
983 * ACCTL = Control Register = 460h
984 * set DCV - will clear when process completed
985 * set VFRM - valid frame enabled
986 * set ESYN - ASYNC generation enabled
987 * set RSTN - ARST# inactive, AC97 codec not reset
988 */
989
990 /*
991 * Get the actual AC97 register from the offset
992 */
993 csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET);
994 csa_writeio(resp, BA0_ACCDA, data);
995 csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
996
997 /*
998 * Wait for the write to occur.
999 */
1000 acctl = 0;
1001 for (i = 0 ; i < 10 ; i++) {
1002 /*
1003 * First, we want to wait for a short time.
1004 */
1005 DELAY(25);
1006
1007 /*
1008 * Now, check to see if the read has completed.
1009 * ACCTL = 460h, DCV should be reset by now and 460h = 17h
1010 */
1011 acctl = csa_readio(resp, BA0_ACCTL);
1012 if ((acctl & ACCTL_DCV) == 0)
1013 break;
1014 }
1015
1016 /*
1017 * Make sure the write completed.
1018 */
1019 if ((acctl & ACCTL_DCV) != 0)
1020 return (EAGAIN);
1021
1022 return (0);
1023 }
1024
1025 u_int32_t
csa_readio(csa_res * resp,u_long offset)1026 csa_readio(csa_res *resp, u_long offset)
1027 {
1028 u_int32_t ul;
1029
1030 if (offset < BA0_AC97_RESET)
1031 return bus_space_read_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset) & 0xffffffff;
1032 else {
1033 if (csa_readcodec(resp, offset, &ul))
1034 ul = 0;
1035 return (ul);
1036 }
1037 }
1038
1039 void
csa_writeio(csa_res * resp,u_long offset,u_int32_t data)1040 csa_writeio(csa_res *resp, u_long offset, u_int32_t data)
1041 {
1042 if (offset < BA0_AC97_RESET)
1043 bus_space_write_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset, data);
1044 else
1045 csa_writecodec(resp, offset, data);
1046 }
1047
1048 u_int32_t
csa_readmem(csa_res * resp,u_long offset)1049 csa_readmem(csa_res *resp, u_long offset)
1050 {
1051 return bus_space_read_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset);
1052 }
1053
1054 void
csa_writemem(csa_res * resp,u_long offset,u_int32_t data)1055 csa_writemem(csa_res *resp, u_long offset, u_int32_t data)
1056 {
1057 bus_space_write_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset, data);
1058 }
1059
1060 static device_method_t csa_methods[] = {
1061 /* Device interface */
1062 DEVMETHOD(device_probe, csa_probe),
1063 DEVMETHOD(device_attach, csa_attach),
1064 DEVMETHOD(device_detach, csa_detach),
1065 DEVMETHOD(device_shutdown, bus_generic_shutdown),
1066 DEVMETHOD(device_suspend, bus_generic_suspend),
1067 DEVMETHOD(device_resume, csa_resume),
1068
1069 /* Bus interface */
1070 DEVMETHOD(bus_alloc_resource, csa_alloc_resource),
1071 DEVMETHOD(bus_release_resource, csa_release_resource),
1072 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
1073 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
1074 DEVMETHOD(bus_setup_intr, csa_setup_intr),
1075 DEVMETHOD(bus_teardown_intr, csa_teardown_intr),
1076
1077 DEVMETHOD_END
1078 };
1079
1080 static driver_t csa_driver = {
1081 "csa",
1082 csa_methods,
1083 sizeof(struct csa_softc),
1084 };
1085
1086 /*
1087 * csa can be attached to a pci bus.
1088 */
1089 DRIVER_MODULE(snd_csa, pci, csa_driver, csa_devclass, 0, 0);
1090 MODULE_DEPEND(snd_csa, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
1091 MODULE_VERSION(snd_csa, 1);
1092