1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2009, Oleksandr Tymoshenko <gonzo@FreeBSD.org>
5 * Copyright (c) 2011, Luiz Otavio O Souza.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice unmodified, this list of conditions, and the following
13 * disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 */
30
31 #include <sys/cdefs.h>
32 #include "opt_ar71xx.h"
33
34 #include <sys/param.h>
35 #include <sys/systm.h>
36
37 #include <sys/bus.h>
38 #include <sys/interrupt.h>
39 #include <sys/malloc.h>
40 #include <sys/kernel.h>
41 #include <sys/module.h>
42 #include <sys/rman.h>
43
44 #include <vm/vm.h>
45 #include <vm/pmap.h>
46 #include <vm/vm_extern.h>
47
48 #include <machine/bus.h>
49 #include <machine/cpu.h>
50 #include <machine/intr_machdep.h>
51
52 #include <dev/pci/pcivar.h>
53 #include <dev/pci/pcireg.h>
54
55 #include <dev/pci/pcib_private.h>
56 #include "pcib_if.h"
57
58 #include <mips/atheros/ar71xxreg.h>
59 #include <mips/atheros/ar724xreg.h>
60 #include <mips/atheros/ar71xx_setup.h>
61 #include <mips/atheros/ar71xx_pci_bus_space.h>
62
63 #include <mips/atheros/ar71xx_cpudef.h>
64
65 #ifdef AR71XX_ATH_EEPROM
66 #include <mips/atheros/ar71xx_fixup.h>
67 #endif /* AR71XX_ATH_EEPROM */
68
69 #undef AR724X_PCI_DEBUG
70 #ifdef AR724X_PCI_DEBUG
71 #define dprintf printf
72 #else
73 #define dprintf(x, arg...)
74 #endif
75
76 struct ar71xx_pci_softc {
77 device_t sc_dev;
78
79 int sc_busno;
80 struct rman sc_mem_rman;
81 struct rman sc_irq_rman;
82
83 struct intr_event *sc_eventstab[AR71XX_PCI_NIRQS];
84 mips_intrcnt_t sc_intr_counter[AR71XX_PCI_NIRQS];
85 struct resource *sc_irq;
86 void *sc_ih;
87 };
88
89 static int ar724x_pci_setup_intr(device_t, device_t, struct resource *, int,
90 driver_filter_t *, driver_intr_t *, void *, void **);
91 static int ar724x_pci_teardown_intr(device_t, device_t, struct resource *,
92 void *);
93 static int ar724x_pci_intr(void *);
94
95 static void
ar724x_pci_write(uint32_t reg,uint32_t offset,uint32_t data,int bytes)96 ar724x_pci_write(uint32_t reg, uint32_t offset, uint32_t data, int bytes)
97 {
98 uint32_t val, mask, shift;
99
100 /* Register access is 32-bit aligned */
101 shift = (offset & 3) * 8;
102 if (bytes % 4)
103 mask = (1 << (bytes * 8)) - 1;
104 else
105 mask = 0xffffffff;
106
107 rmb();
108 val = ATH_READ_REG(reg + (offset & ~3));
109 val &= ~(mask << shift);
110 val |= ((data & mask) << shift);
111 ATH_WRITE_REG(reg + (offset & ~3), val);
112 wmb();
113
114 dprintf("%s: %#x/%#x addr=%#x, data=%#x(%#x), bytes=%d\n", __func__,
115 reg, reg + (offset & ~3), offset, data, val, bytes);
116 }
117
118 static uint32_t
ar724x_pci_read_config(device_t dev,u_int bus,u_int slot,u_int func,u_int reg,int bytes)119 ar724x_pci_read_config(device_t dev, u_int bus, u_int slot, u_int func,
120 u_int reg, int bytes)
121 {
122 uint32_t data, shift, mask;
123
124 /* Register access is 32-bit aligned */
125 shift = (reg & 3) * 8;
126
127 /* Create a mask based on the width, post-shift */
128 if (bytes == 2)
129 mask = 0xffff;
130 else if (bytes == 1)
131 mask = 0xff;
132 else
133 mask = 0xffffffff;
134
135 dprintf("%s: tag (%x, %x, %x) reg %d(%d)\n", __func__, bus, slot,
136 func, reg, bytes);
137
138 rmb();
139 if ((bus == 0) && (slot == 0) && (func == 0))
140 data = ATH_READ_REG(AR724X_PCI_CFG_BASE + (reg & ~3));
141 else
142 data = -1;
143
144 /* Get request bytes from 32-bit word */
145 data = (data >> shift) & mask;
146
147 dprintf("%s: read 0x%x\n", __func__, data);
148
149 return (data);
150 }
151
152 static void
ar724x_pci_write_config(device_t dev,u_int bus,u_int slot,u_int func,u_int reg,uint32_t data,int bytes)153 ar724x_pci_write_config(device_t dev, u_int bus, u_int slot, u_int func,
154 u_int reg, uint32_t data, int bytes)
155 {
156
157 dprintf("%s: tag (%x, %x, %x) reg %d(%d): %x\n", __func__, bus, slot,
158 func, reg, bytes, data);
159
160 if ((bus != 0) || (slot != 0) || (func != 0))
161 return;
162
163 /*
164 * WAR for BAR issue on AR7240 - We are unable to access the PCI
165 * device space if we set the BAR with proper base address.
166 *
167 * However, we _do_ want to allow programming in the probe value
168 * (0xffffffff) so the PCI code can find out how big the memory
169 * map is for this device. Without it, it'll think the memory
170 * map is 32 bits wide, the PCI code will then end up thinking
171 * the register window is '0' and fail to allocate resources.
172 *
173 * Note: Test on AR7241/AR7242/AR9344! Those use a WAR value of
174 * 0x1000ffff.
175 */
176 if (reg == PCIR_BAR(0) && bytes == 4
177 && ar71xx_soc == AR71XX_SOC_AR7240
178 && data != 0xffffffff)
179 ar724x_pci_write(AR724X_PCI_CFG_BASE, reg, 0xffff, bytes);
180 else
181 ar724x_pci_write(AR724X_PCI_CFG_BASE, reg, data, bytes);
182 }
183
184 static void
ar724x_pci_mask_irq(void * source)185 ar724x_pci_mask_irq(void *source)
186 {
187 uint32_t reg;
188 unsigned int irq = (unsigned int)source;
189
190 /* XXX - Only one interrupt ? Only one device ? */
191 if (irq != AR71XX_PCI_IRQ_START)
192 return;
193
194 /* Update the interrupt mask reg */
195 reg = ATH_READ_REG(AR724X_PCI_INTR_MASK);
196 ATH_WRITE_REG(AR724X_PCI_INTR_MASK,
197 reg & ~AR724X_PCI_INTR_DEV0);
198
199 /* Clear any pending interrupt */
200 reg = ATH_READ_REG(AR724X_PCI_INTR_STATUS);
201 ATH_WRITE_REG(AR724X_PCI_INTR_STATUS,
202 reg | AR724X_PCI_INTR_DEV0);
203 }
204
205 static void
ar724x_pci_unmask_irq(void * source)206 ar724x_pci_unmask_irq(void *source)
207 {
208 uint32_t reg;
209 unsigned int irq = (unsigned int)source;
210
211 /* XXX */
212 if (irq != AR71XX_PCI_IRQ_START)
213 return;
214
215 /* Update the interrupt mask reg */
216 reg = ATH_READ_REG(AR724X_PCI_INTR_MASK);
217 ATH_WRITE_REG(AR724X_PCI_INTR_MASK,
218 reg | AR724X_PCI_INTR_DEV0);
219 }
220
221 static int
ar724x_pci_setup(device_t dev)222 ar724x_pci_setup(device_t dev)
223 {
224 uint32_t reg;
225
226 /* setup COMMAND register */
227 reg = PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN | PCIM_CMD_SERRESPEN |
228 PCIM_CMD_BACKTOBACK | PCIM_CMD_PERRESPEN | PCIM_CMD_MWRICEN;
229
230 ar724x_pci_write(AR724X_PCI_CRP_BASE, PCIR_COMMAND, reg, 2);
231 ar724x_pci_write(AR724X_PCI_CRP_BASE, 0x20, 0x1ff01000, 4);
232 ar724x_pci_write(AR724X_PCI_CRP_BASE, 0x24, 0x1ff01000, 4);
233
234 reg = ATH_READ_REG(AR724X_PCI_RESET);
235 if (reg != 0x7) {
236 DELAY(100000);
237 ATH_WRITE_REG(AR724X_PCI_RESET, 0);
238 DELAY(100);
239 ATH_WRITE_REG(AR724X_PCI_RESET, 4);
240 DELAY(100000);
241 }
242
243 if (ar71xx_soc == AR71XX_SOC_AR7240)
244 reg = AR724X_PCI_APP_LTSSM_ENABLE;
245 else
246 reg = 0x1ffc1;
247 ATH_WRITE_REG(AR724X_PCI_APP, reg);
248 /* Flush write */
249 (void) ATH_READ_REG(AR724X_PCI_APP);
250
251 DELAY(1000);
252
253 reg = ATH_READ_REG(AR724X_PCI_RESET);
254 if ((reg & AR724X_PCI_RESET_LINK_UP) == 0) {
255 device_printf(dev, "no PCIe controller found\n");
256 return (ENXIO);
257 }
258
259 if (ar71xx_soc == AR71XX_SOC_AR7241 ||
260 ar71xx_soc == AR71XX_SOC_AR7242) {
261 reg = ATH_READ_REG(AR724X_PCI_APP);
262 reg |= (1 << 16);
263 ATH_WRITE_REG(AR724X_PCI_APP, reg);
264 }
265
266 return (0);
267 }
268
269 #ifdef AR71XX_ATH_EEPROM
270 #define AR5416_EEPROM_MAGIC 0xa55a
271
272 /*
273 * XXX - This should not be here ! And this looks like Atheros (if_ath) only.
274 */
275 static void
ar724x_pci_fixup(device_t dev,long flash_addr,int len)276 ar724x_pci_fixup(device_t dev, long flash_addr, int len)
277 {
278 uint32_t bar0, reg, val;
279 uint16_t *cal_data = (uint16_t *) MIPS_PHYS_TO_KSEG1(flash_addr);
280
281 #if 0
282 if (cal_data[0] != AR5416_EEPROM_MAGIC) {
283 device_printf(dev, "%s: Invalid calibration data from 0x%x\n",
284 __func__, (uintptr_t) flash_addr);
285 return;
286 }
287 #endif
288
289 /* Save bar(0) address - just to flush bar(0) (SoC WAR) ? */
290 bar0 = ar724x_pci_read_config(dev, 0, 0, 0, PCIR_BAR(0), 4);
291
292 /* Write temporary BAR0 to map the NIC into a fixed location */
293 /* XXX AR7240: 0xffff; 7241/7242/9344: 0x1000ffff */
294 ar724x_pci_write_config(dev, 0, 0, 0, PCIR_BAR(0),
295 AR71XX_PCI_MEM_BASE, 4);
296
297 val = ar724x_pci_read_config(dev, 0, 0, 0, PCIR_COMMAND, 2);
298 val |= (PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN);
299 ar724x_pci_write_config(dev, 0, 0, 0, PCIR_COMMAND, val, 2);
300
301 /* set pointer to first reg address */
302 cal_data += 3;
303 while (*cal_data != 0xffff) {
304 reg = *cal_data++;
305 val = *cal_data++;
306 val |= (*cal_data++) << 16;
307
308 if (bootverbose)
309 printf(" 0x%08x=0x%08x\n", reg, val);
310
311 /* Write eeprom fixup data to device memory */
312 ATH_WRITE_REG(AR71XX_PCI_MEM_BASE + reg, val);
313 DELAY(100);
314 }
315
316 val = ar724x_pci_read_config(dev, 0, 0, 0, PCIR_COMMAND, 2);
317 val &= ~(PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN);
318 ar724x_pci_write_config(dev, 0, 0, 0, PCIR_COMMAND, val, 2);
319
320 /* Write the saved bar(0) address */
321 ar724x_pci_write_config(dev, 0, 0, 0, PCIR_BAR(0), bar0, 4);
322 }
323 #undef AR5416_EEPROM_MAGIC
324
325 /*
326 * XXX This is (mostly) duplicated with ar71xx_pci.c.
327 * It should at some point be fixed.
328 */
329 static void
ar724x_pci_slot_fixup(device_t dev)330 ar724x_pci_slot_fixup(device_t dev)
331 {
332 long int flash_addr;
333 char buf[64];
334 int size;
335
336 /*
337 * Check whether the given slot has a hint to poke.
338 */
339 if (bootverbose)
340 device_printf(dev, "%s: checking dev %s, %d/%d/%d\n",
341 __func__, device_get_nameunit(dev), 0, 0, 0);
342
343 snprintf(buf, sizeof(buf), "bus.%d.%d.%d.ath_fixup_addr",
344 0, 0, 0);
345
346 if (resource_long_value(device_get_name(dev), device_get_unit(dev),
347 buf, &flash_addr) == 0) {
348 snprintf(buf, sizeof(buf), "bus.%d.%d.%d.ath_fixup_size",
349 0, 0, 0);
350 if (resource_int_value(device_get_name(dev),
351 device_get_unit(dev), buf, &size) != 0) {
352 device_printf(dev,
353 "%s: missing hint '%s', aborting EEPROM\n",
354 __func__, buf);
355 return;
356 }
357
358 device_printf(dev, "found EEPROM at 0x%lx on %d.%d.%d\n",
359 flash_addr, 0, 0, 0);
360 ar724x_pci_fixup(dev, flash_addr, size);
361 ar71xx_pci_slot_create_eeprom_firmware(dev, 0, 0, 0,
362 flash_addr, size);
363 }
364 }
365 #endif /* AR71XX_ATH_EEPROM */
366
367 static int
ar724x_pci_probe(device_t dev)368 ar724x_pci_probe(device_t dev)
369 {
370
371 return (BUS_PROBE_NOWILDCARD);
372 }
373
374 static int
ar724x_pci_attach(device_t dev)375 ar724x_pci_attach(device_t dev)
376 {
377 struct ar71xx_pci_softc *sc = device_get_softc(dev);
378 int rid = 0;
379
380 sc->sc_mem_rman.rm_type = RMAN_ARRAY;
381 sc->sc_mem_rman.rm_descr = "ar724x PCI memory window";
382 if (rman_init(&sc->sc_mem_rman) != 0 ||
383 rman_manage_region(&sc->sc_mem_rman, AR71XX_PCI_MEM_BASE,
384 AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1) != 0) {
385 panic("ar724x_pci_attach: failed to set up I/O rman");
386 }
387
388 sc->sc_irq_rman.rm_type = RMAN_ARRAY;
389 sc->sc_irq_rman.rm_descr = "ar724x PCI IRQs";
390 if (rman_init(&sc->sc_irq_rman) != 0 ||
391 rman_manage_region(&sc->sc_irq_rman, AR71XX_PCI_IRQ_START,
392 AR71XX_PCI_IRQ_END) != 0)
393 panic("ar724x_pci_attach: failed to set up IRQ rman");
394
395 /* Disable interrupts */
396 ATH_WRITE_REG(AR724X_PCI_INTR_STATUS, 0);
397 ATH_WRITE_REG(AR724X_PCI_INTR_MASK, 0);
398
399 /* Hook up our interrupt handler. */
400 if ((sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
401 RF_SHAREABLE | RF_ACTIVE)) == NULL) {
402 device_printf(dev, "unable to allocate IRQ resource\n");
403 return (ENXIO);
404 }
405
406 if ((bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_MISC,
407 ar724x_pci_intr, NULL, sc, &sc->sc_ih))) {
408 device_printf(dev,
409 "WARNING: unable to register interrupt handler\n");
410 return (ENXIO);
411 }
412
413 /* Reset PCIe core and PCIe PHY */
414 ar71xx_device_stop(AR724X_RESET_PCIE);
415 ar71xx_device_stop(AR724X_RESET_PCIE_PHY);
416 ar71xx_device_stop(AR724X_RESET_PCIE_PHY_SERIAL);
417 DELAY(100);
418
419 ar71xx_device_start(AR724X_RESET_PCIE_PHY_SERIAL);
420 DELAY(100);
421 ar71xx_device_start(AR724X_RESET_PCIE_PHY);
422 ar71xx_device_start(AR724X_RESET_PCIE);
423
424 if (ar724x_pci_setup(dev))
425 return (ENXIO);
426
427 #ifdef AR71XX_ATH_EEPROM
428 ar724x_pci_slot_fixup(dev);
429 #endif /* AR71XX_ATH_EEPROM */
430
431 /* Fixup internal PCI bridge */
432 ar724x_pci_write_config(dev, 0, 0, 0, PCIR_COMMAND,
433 PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN
434 | PCIM_CMD_SERRESPEN | PCIM_CMD_BACKTOBACK
435 | PCIM_CMD_PERRESPEN | PCIM_CMD_MWRICEN, 2);
436
437 device_add_child(dev, "pci", -1);
438 return (bus_generic_attach(dev));
439 }
440
441 static int
ar724x_pci_read_ivar(device_t dev,device_t child,int which,uintptr_t * result)442 ar724x_pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
443 {
444 struct ar71xx_pci_softc *sc = device_get_softc(dev);
445
446 switch (which) {
447 case PCIB_IVAR_DOMAIN:
448 *result = 0;
449 return (0);
450 case PCIB_IVAR_BUS:
451 *result = sc->sc_busno;
452 return (0);
453 }
454
455 return (ENOENT);
456 }
457
458 static int
ar724x_pci_write_ivar(device_t dev,device_t child,int which,uintptr_t result)459 ar724x_pci_write_ivar(device_t dev, device_t child, int which, uintptr_t result)
460 {
461 struct ar71xx_pci_softc * sc = device_get_softc(dev);
462
463 switch (which) {
464 case PCIB_IVAR_BUS:
465 sc->sc_busno = result;
466 return (0);
467 }
468
469 return (ENOENT);
470 }
471
472 static struct resource *
ar724x_pci_alloc_resource(device_t bus,device_t child,int type,int * rid,rman_res_t start,rman_res_t end,rman_res_t count,u_int flags)473 ar724x_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
474 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
475 {
476 struct ar71xx_pci_softc *sc = device_get_softc(bus);
477 struct resource *rv;
478 struct rman *rm;
479
480 switch (type) {
481 case SYS_RES_IRQ:
482 rm = &sc->sc_irq_rman;
483 break;
484 case SYS_RES_MEMORY:
485 rm = &sc->sc_mem_rman;
486 break;
487 default:
488 return (NULL);
489 }
490
491 rv = rman_reserve_resource(rm, start, end, count, flags, child);
492
493 if (rv == NULL)
494 return (NULL);
495
496 rman_set_rid(rv, *rid);
497
498 if (flags & RF_ACTIVE) {
499 if (bus_activate_resource(child, type, *rid, rv)) {
500 rman_release_resource(rv);
501 return (NULL);
502 }
503 }
504
505 return (rv);
506 }
507
508 static int
ar724x_pci_activate_resource(device_t bus,device_t child,int type,int rid,struct resource * r)509 ar724x_pci_activate_resource(device_t bus, device_t child, int type, int rid,
510 struct resource *r)
511 {
512 int res = (BUS_ACTIVATE_RESOURCE(device_get_parent(bus),
513 child, type, rid, r));
514
515 if (!res) {
516 switch(type) {
517 case SYS_RES_MEMORY:
518 case SYS_RES_IOPORT:
519
520 rman_set_bustag(r, ar71xx_bus_space_pcimem);
521 break;
522 }
523 }
524
525 return (res);
526 }
527
528 static int
ar724x_pci_setup_intr(device_t bus,device_t child,struct resource * ires,int flags,driver_filter_t * filt,driver_intr_t * handler,void * arg,void ** cookiep)529 ar724x_pci_setup_intr(device_t bus, device_t child, struct resource *ires,
530 int flags, driver_filter_t *filt, driver_intr_t *handler,
531 void *arg, void **cookiep)
532 {
533 struct ar71xx_pci_softc *sc = device_get_softc(bus);
534 struct intr_event *event;
535 int irq, error;
536
537 irq = rman_get_start(ires);
538 if (irq > AR71XX_PCI_IRQ_END)
539 panic("%s: bad irq %d", __func__, irq);
540
541 event = sc->sc_eventstab[irq];
542 if (event == NULL) {
543 error = intr_event_create(&event, (void *)irq, 0, irq,
544 ar724x_pci_mask_irq, ar724x_pci_unmask_irq, NULL, NULL,
545 "pci intr%d:", irq);
546
547 if (error == 0) {
548 sc->sc_eventstab[irq] = event;
549 sc->sc_intr_counter[irq] =
550 mips_intrcnt_create(event->ie_name);
551 }
552 else
553 return error;
554 }
555
556 intr_event_add_handler(event, device_get_nameunit(child), filt,
557 handler, arg, intr_priority(flags), flags, cookiep);
558 mips_intrcnt_setname(sc->sc_intr_counter[irq], event->ie_fullname);
559
560 ar724x_pci_unmask_irq((void*)irq);
561
562 return (0);
563 }
564
565 static int
ar724x_pci_teardown_intr(device_t dev,device_t child,struct resource * ires,void * cookie)566 ar724x_pci_teardown_intr(device_t dev, device_t child, struct resource *ires,
567 void *cookie)
568 {
569 struct ar71xx_pci_softc *sc = device_get_softc(dev);
570 int irq, result;
571
572 irq = rman_get_start(ires);
573 if (irq > AR71XX_PCI_IRQ_END)
574 panic("%s: bad irq %d", __func__, irq);
575
576 if (sc->sc_eventstab[irq] == NULL)
577 panic("Trying to teardown unoccupied IRQ");
578
579 ar724x_pci_mask_irq((void*)irq);
580
581 result = intr_event_remove_handler(cookie);
582 if (!result)
583 sc->sc_eventstab[irq] = NULL;
584
585 return (result);
586 }
587
588 static int
ar724x_pci_intr(void * arg)589 ar724x_pci_intr(void *arg)
590 {
591 struct ar71xx_pci_softc *sc = arg;
592 struct intr_event *event;
593 uint32_t reg, irq, mask;
594
595 reg = ATH_READ_REG(AR724X_PCI_INTR_STATUS);
596 mask = ATH_READ_REG(AR724X_PCI_INTR_MASK);
597 /*
598 * Handle only unmasked interrupts
599 */
600 reg &= mask;
601 if (reg & AR724X_PCI_INTR_DEV0) {
602 irq = AR71XX_PCI_IRQ_START;
603 event = sc->sc_eventstab[irq];
604 if (!event || CK_SLIST_EMPTY(&event->ie_handlers)) {
605 printf("Stray IRQ %d\n", irq);
606 return (FILTER_STRAY);
607 }
608
609 /* Flush pending memory transactions */
610 ar71xx_device_flush_ddr(AR71XX_CPU_DDR_FLUSH_PCIE);
611
612 /* TODO: frame instead of NULL? */
613 intr_event_handle(event, NULL);
614 mips_intrcnt_inc(sc->sc_intr_counter[irq]);
615 }
616
617 return (FILTER_HANDLED);
618 }
619
620 static int
ar724x_pci_maxslots(device_t dev)621 ar724x_pci_maxslots(device_t dev)
622 {
623
624 return (PCI_SLOTMAX);
625 }
626
627 static int
ar724x_pci_route_interrupt(device_t pcib,device_t device,int pin)628 ar724x_pci_route_interrupt(device_t pcib, device_t device, int pin)
629 {
630
631 return (pci_get_slot(device));
632 }
633
634 static device_method_t ar724x_pci_methods[] = {
635 /* Device interface */
636 DEVMETHOD(device_probe, ar724x_pci_probe),
637 DEVMETHOD(device_attach, ar724x_pci_attach),
638 DEVMETHOD(device_shutdown, bus_generic_shutdown),
639 DEVMETHOD(device_suspend, bus_generic_suspend),
640 DEVMETHOD(device_resume, bus_generic_resume),
641
642 /* Bus interface */
643 DEVMETHOD(bus_read_ivar, ar724x_pci_read_ivar),
644 DEVMETHOD(bus_write_ivar, ar724x_pci_write_ivar),
645 DEVMETHOD(bus_alloc_resource, ar724x_pci_alloc_resource),
646 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
647 DEVMETHOD(bus_activate_resource, ar724x_pci_activate_resource),
648 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
649 DEVMETHOD(bus_setup_intr, ar724x_pci_setup_intr),
650 DEVMETHOD(bus_teardown_intr, ar724x_pci_teardown_intr),
651
652 /* pcib interface */
653 DEVMETHOD(pcib_maxslots, ar724x_pci_maxslots),
654 DEVMETHOD(pcib_read_config, ar724x_pci_read_config),
655 DEVMETHOD(pcib_write_config, ar724x_pci_write_config),
656 DEVMETHOD(pcib_route_interrupt, ar724x_pci_route_interrupt),
657 DEVMETHOD(pcib_request_feature, pcib_request_feature_allow),
658
659 DEVMETHOD_END
660 };
661
662 static driver_t ar724x_pci_driver = {
663 "pcib",
664 ar724x_pci_methods,
665 sizeof(struct ar71xx_pci_softc),
666 };
667
668 static devclass_t ar724x_pci_devclass;
669
670 DRIVER_MODULE(ar724x_pci, nexus, ar724x_pci_driver, ar724x_pci_devclass, 0, 0);
671