1 /*-
2 * Copyright (c) 2015 Adrian Chadd <adrian@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 #include "opt_ddb.h"
29
30 #include <sys/param.h>
31 #include <sys/conf.h>
32 #include <sys/kernel.h>
33 #include <sys/systm.h>
34 #include <sys/bus.h>
35 #include <sys/cons.h>
36 #include <sys/kdb.h>
37 #include <sys/reboot.h>
38
39 #include <vm/vm.h>
40 #include <vm/vm_page.h>
41
42 #include <net/ethernet.h>
43
44 #include <machine/clock.h>
45 #include <machine/cpu.h>
46 #include <machine/cpuregs.h>
47 #include <machine/hwfunc.h>
48 #include <machine/md_var.h>
49 #include <machine/trap.h>
50 #include <machine/vmparam.h>
51
52 #include <mips/atheros/ar71xxreg.h>
53 //#include <mips/atheros/ar934xreg.h>
54 #include <mips/atheros/qca955xreg.h>
55
56 #include <mips/atheros/ar71xx_cpudef.h>
57 #include <mips/atheros/ar71xx_setup.h>
58
59 #include <mips/atheros/ar71xx_chip.h>
60
61 #include <mips/atheros/qca955x_chip.h>
62
63 static void
qca955x_chip_detect_mem_size(void)64 qca955x_chip_detect_mem_size(void)
65 {
66 }
67
68 static void
qca955x_chip_detect_sys_frequency(void)69 qca955x_chip_detect_sys_frequency(void)
70 {
71 unsigned long ref_rate;
72 unsigned long cpu_rate;
73 unsigned long ddr_rate;
74 unsigned long ahb_rate;
75 uint32_t pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
76 uint32_t cpu_pll, ddr_pll;
77 uint32_t bootstrap;
78
79 bootstrap = ATH_READ_REG(QCA955X_RESET_REG_BOOTSTRAP);
80 if (bootstrap & QCA955X_BOOTSTRAP_REF_CLK_40)
81 ref_rate = 40 * 1000 * 1000;
82 else
83 ref_rate = 25 * 1000 * 1000;
84
85 pll = ATH_READ_REG(QCA955X_PLL_CPU_CONFIG_REG);
86 out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
87 QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK;
88 ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
89 QCA955X_PLL_CPU_CONFIG_REFDIV_MASK;
90 nint = (pll >> QCA955X_PLL_CPU_CONFIG_NINT_SHIFT) &
91 QCA955X_PLL_CPU_CONFIG_NINT_MASK;
92 frac = (pll >> QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
93 QCA955X_PLL_CPU_CONFIG_NFRAC_MASK;
94
95 cpu_pll = nint * ref_rate / ref_div;
96 cpu_pll += frac * ref_rate / (ref_div * (1 << 6));
97 cpu_pll /= (1 << out_div);
98
99 pll = ATH_READ_REG(QCA955X_PLL_DDR_CONFIG_REG);
100 out_div = (pll >> QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
101 QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK;
102 ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
103 QCA955X_PLL_DDR_CONFIG_REFDIV_MASK;
104 nint = (pll >> QCA955X_PLL_DDR_CONFIG_NINT_SHIFT) &
105 QCA955X_PLL_DDR_CONFIG_NINT_MASK;
106 frac = (pll >> QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
107 QCA955X_PLL_DDR_CONFIG_NFRAC_MASK;
108
109 ddr_pll = nint * ref_rate / ref_div;
110 ddr_pll += frac * ref_rate / (ref_div * (1 << 10));
111 ddr_pll /= (1 << out_div);
112
113 clk_ctrl = ATH_READ_REG(QCA955X_PLL_CLK_CTRL_REG);
114
115 postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
116 QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
117
118 if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
119 cpu_rate = ref_rate;
120 else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
121 cpu_rate = ddr_pll / (postdiv + 1);
122 else
123 cpu_rate = cpu_pll / (postdiv + 1);
124
125 postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
126 QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
127
128 if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
129 ddr_rate = ref_rate;
130 else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
131 ddr_rate = cpu_pll / (postdiv + 1);
132 else
133 ddr_rate = ddr_pll / (postdiv + 1);
134
135 postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
136 QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
137
138 if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
139 ahb_rate = ref_rate;
140 else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
141 ahb_rate = ddr_pll / (postdiv + 1);
142 else
143 ahb_rate = cpu_pll / (postdiv + 1);
144
145 u_ar71xx_ddr_freq = ddr_rate;
146 u_ar71xx_cpu_freq = cpu_rate;
147 u_ar71xx_ahb_freq = ahb_rate;
148
149 u_ar71xx_wdt_freq = ref_rate;
150 u_ar71xx_uart_freq = ref_rate;
151 u_ar71xx_mdio_freq = ref_rate;
152 u_ar71xx_refclk = ref_rate;
153 }
154
155 static void
qca955x_chip_device_stop(uint32_t mask)156 qca955x_chip_device_stop(uint32_t mask)
157 {
158 uint32_t reg;
159
160 reg = ATH_READ_REG(QCA955X_RESET_REG_RESET_MODULE);
161 ATH_WRITE_REG(QCA955X_RESET_REG_RESET_MODULE, reg | mask);
162 }
163
164 static void
qca955x_chip_device_start(uint32_t mask)165 qca955x_chip_device_start(uint32_t mask)
166 {
167 uint32_t reg;
168
169 reg = ATH_READ_REG(QCA955X_RESET_REG_RESET_MODULE);
170 ATH_WRITE_REG(QCA955X_RESET_REG_RESET_MODULE, reg & ~mask);
171 }
172
173 static int
qca955x_chip_device_stopped(uint32_t mask)174 qca955x_chip_device_stopped(uint32_t mask)
175 {
176 uint32_t reg;
177
178 reg = ATH_READ_REG(QCA955X_RESET_REG_RESET_MODULE);
179 return ((reg & mask) == mask);
180 }
181
182 static void
qca955x_chip_set_mii_speed(uint32_t unit,uint32_t speed)183 qca955x_chip_set_mii_speed(uint32_t unit, uint32_t speed)
184 {
185
186 /* XXX TODO */
187 return;
188 }
189
190 static void
qca955x_chip_set_pll_ge(int unit,int speed,uint32_t pll)191 qca955x_chip_set_pll_ge(int unit, int speed, uint32_t pll)
192 {
193 switch (unit) {
194 case 0:
195 ATH_WRITE_REG(QCA955X_PLL_ETH_XMII_CONTROL_REG, pll);
196 break;
197 case 1:
198 ATH_WRITE_REG(QCA955X_PLL_ETH_SGMII_CONTROL_REG, pll);
199 break;
200 default:
201 printf("%s: invalid PLL set for arge unit: %d\n",
202 __func__, unit);
203 return;
204 }
205 }
206
207 static void
qca955x_chip_ddr_flush(ar71xx_flush_ddr_id_t id)208 qca955x_chip_ddr_flush(ar71xx_flush_ddr_id_t id)
209 {
210
211 switch (id) {
212 case AR71XX_CPU_DDR_FLUSH_GE0:
213 ar71xx_ddr_flush(QCA955X_DDR_REG_FLUSH_GE0);
214 break;
215 case AR71XX_CPU_DDR_FLUSH_GE1:
216 ar71xx_ddr_flush(QCA955X_DDR_REG_FLUSH_GE1);
217 break;
218 case AR71XX_CPU_DDR_FLUSH_USB:
219 ar71xx_ddr_flush(QCA955X_DDR_REG_FLUSH_USB);
220 break;
221 case AR71XX_CPU_DDR_FLUSH_PCIE:
222 ar71xx_ddr_flush(QCA955X_DDR_REG_FLUSH_PCIE);
223 break;
224 case AR71XX_CPU_DDR_FLUSH_WMAC:
225 ar71xx_ddr_flush(QCA955X_DDR_REG_FLUSH_WMAC);
226 break;
227 case AR71XX_CPU_DDR_FLUSH_PCIE_EP:
228 ar71xx_ddr_flush(QCA955X_DDR_REG_FLUSH_SRC1);
229 break;
230 case AR71XX_CPU_DDR_FLUSH_CHECKSUM:
231 ar71xx_ddr_flush(QCA955X_DDR_REG_FLUSH_SRC2);
232 break;
233 default:
234 printf("%s: invalid flush (%d)\n", __func__, id);
235 }
236 }
237
238 static uint32_t
qca955x_chip_get_eth_pll(unsigned int mac,int speed)239 qca955x_chip_get_eth_pll(unsigned int mac, int speed)
240 {
241 uint32_t pll;
242
243 switch (speed) {
244 case 10:
245 pll = QCA955X_PLL_VAL_10;
246 break;
247 case 100:
248 pll = QCA955X_PLL_VAL_100;
249 break;
250 case 1000:
251 pll = QCA955X_PLL_VAL_1000;
252 break;
253 default:
254 printf("%s%d: invalid speed %d\n", __func__, mac, speed);
255 pll = 0;
256 }
257 return (pll);
258 }
259
260 static void
qca955x_chip_reset_ethernet_switch(void)261 qca955x_chip_reset_ethernet_switch(void)
262 {
263 #if 0
264 ar71xx_device_stop(AR934X_RESET_ETH_SWITCH);
265 DELAY(100);
266 ar71xx_device_start(AR934X_RESET_ETH_SWITCH);
267 DELAY(100);
268 #endif
269 }
270
271 static void
qca955x_configure_gmac(uint32_t gmac_cfg)272 qca955x_configure_gmac(uint32_t gmac_cfg)
273 {
274 uint32_t reg;
275
276 reg = ATH_READ_REG(QCA955X_GMAC_REG_ETH_CFG);
277 printf("%s: ETH_CFG=0x%08x\n", __func__, reg);
278 reg &= ~(QCA955X_ETH_CFG_RGMII_EN | QCA955X_ETH_CFG_GE0_SGMII);
279 reg |= gmac_cfg;
280 ATH_WRITE_REG(QCA955X_GMAC_REG_ETH_CFG, reg);
281 }
282
283 static void
qca955x_chip_init_usb_peripheral(void)284 qca955x_chip_init_usb_peripheral(void)
285 {
286 }
287
288 static void
qca955x_chip_set_mii_if(uint32_t unit,uint32_t mii_mode)289 qca955x_chip_set_mii_if(uint32_t unit, uint32_t mii_mode)
290 {
291
292 /*
293 * XXX !
294 *
295 * Nothing to see here; although gmac0 can have its
296 * MII configuration changed, the register values
297 * are slightly different.
298 */
299 }
300
301 /*
302 * XXX TODO: fetch default MII divider configuration
303 */
304
305 static void
qca955x_chip_reset_wmac(void)306 qca955x_chip_reset_wmac(void)
307 {
308
309 /* XXX TODO */
310 }
311
312 static void
qca955x_chip_init_gmac(void)313 qca955x_chip_init_gmac(void)
314 {
315 long gmac_cfg;
316
317 if (resource_long_value("qca955x_gmac", 0, "gmac_cfg",
318 &gmac_cfg) == 0) {
319 printf("%s: gmac_cfg=0x%08lx\n",
320 __func__,
321 (long) gmac_cfg);
322 qca955x_configure_gmac((uint32_t) gmac_cfg);
323 }
324 }
325
326 /*
327 * Reset the NAND Flash Controller.
328 *
329 * + active=1 means "make it active".
330 * + active=0 means "make it inactive".
331 */
332 static void
qca955x_chip_reset_nfc(int active)333 qca955x_chip_reset_nfc(int active)
334 {
335 #if 0
336 if (active) {
337 ar71xx_device_start(AR934X_RESET_NANDF);
338 DELAY(100);
339
340 ar71xx_device_start(AR934X_RESET_ETH_SWITCH_ANALOG);
341 DELAY(250);
342 } else {
343 ar71xx_device_stop(AR934X_RESET_ETH_SWITCH_ANALOG);
344 DELAY(250);
345
346 ar71xx_device_stop(AR934X_RESET_NANDF);
347 DELAY(100);
348 }
349 #endif
350 }
351
352 /*
353 * Configure the GPIO output mux setup.
354 *
355 * The QCA955x has an output mux which allowed
356 * certain functions to be configured on any pin.
357 * Specifically, the switch PHY link LEDs and
358 * WMAC external RX LNA switches are not limited to
359 * a specific GPIO pin.
360 */
361 static void
qca955x_chip_gpio_output_configure(int gpio,uint8_t func)362 qca955x_chip_gpio_output_configure(int gpio, uint8_t func)
363 {
364 uint32_t reg, s;
365 uint32_t t;
366
367 if (gpio > QCA955X_GPIO_COUNT)
368 return;
369
370 reg = QCA955X_GPIO_REG_OUT_FUNC0 + rounddown(gpio, 4);
371 s = 8 * (gpio % 4);
372
373 /* read-modify-write */
374 t = ATH_READ_REG(AR71XX_GPIO_BASE + reg);
375 t &= ~(0xff << s);
376 t |= func << s;
377 ATH_WRITE_REG(AR71XX_GPIO_BASE + reg, t);
378
379 /* flush write */
380 ATH_READ_REG(AR71XX_GPIO_BASE + reg);
381 }
382
383 struct ar71xx_cpu_def qca955x_chip_def = {
384 &qca955x_chip_detect_mem_size,
385 &qca955x_chip_detect_sys_frequency,
386 &qca955x_chip_device_stop,
387 &qca955x_chip_device_start,
388 &qca955x_chip_device_stopped,
389 &qca955x_chip_set_pll_ge,
390 &qca955x_chip_set_mii_speed,
391 &qca955x_chip_set_mii_if,
392 &qca955x_chip_get_eth_pll,
393 &qca955x_chip_ddr_flush,
394 &qca955x_chip_init_usb_peripheral,
395 &qca955x_chip_reset_ethernet_switch,
396 &qca955x_chip_reset_wmac,
397 &qca955x_chip_init_gmac,
398 &qca955x_chip_reset_nfc,
399 &qca955x_chip_gpio_output_configure,
400 };
401