1 /*- 2 * Copyright 2015 Alexander Kabaev <kan@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #ifndef _MIPS_INGENIC_JZ4780_CLK_H 28 #define _MIPS_INGENIC_JZ4780_CLK_H 29 30 #include <dev/extres/clk/clk.h> 31 #include <dev/extres/clk/clk_gate.h> 32 33 /* Convenience bitfiled manipulation macros */ 34 #define REG_MSK(field) (((1u << field ## _WIDTH) - 1) << field ##_SHIFT) 35 #define REG_VAL(field, val) ((val) << field ##_SHIFT) 36 #define REG_CLR(reg, field) ((reg) & ~REG_MSK(field)) 37 #define REG_GET(reg, field) (((reg) & REG_MSK(field)) >> field ##_SHIFT) 38 #define REG_SET(reg, field, val) (REG_CLR(reg, field) | REG_VAL(field, val)) 39 40 /* Common clock macros */ 41 #define CLK_LOCK(_sc) mtx_lock((_sc)->clk_mtx) 42 #define CLK_UNLOCK(_sc) mtx_unlock((_sc)->clk_mtx) 43 44 #define CLK_WR_4(_sc, off, val) bus_write_4((_sc)->clk_res, (off), (val)) 45 #define CLK_RD_4(_sc, off) bus_read_4((_sc)->clk_res, (off)) 46 47 struct jz4780_clk_mux_descr { 48 uint16_t mux_reg; 49 uint16_t mux_shift: 5; 50 uint16_t mux_bits: 5; 51 uint16_t mux_map: 4; /* Map into mux space */ 52 }; 53 54 struct jz4780_clk_div_descr { 55 uint16_t div_reg; 56 uint16_t div_shift: 5; 57 uint16_t div_bits: 5; 58 uint16_t div_lg: 5; 59 int div_ce_bit: 6; /* -1, if CE bit is not present */ 60 int div_st_bit: 6; /* Can be negative */ 61 int div_busy_bit: 6; /* Can be negative */ 62 }; 63 64 struct jz4780_clk_descr { 65 uint16_t clk_id: 6; 66 uint16_t clk_type: 3; 67 int clk_gate_bit: 7; /* Can be negative */ 68 struct jz4780_clk_mux_descr clk_mux; 69 struct jz4780_clk_div_descr clk_div; 70 const char *clk_name; 71 const char *clk_pnames[4]; 72 }; 73 74 /* clk_type bits */ 75 #define CLK_MASK_GATE 0x01 76 #define CLK_MASK_DIV 0x02 77 #define CLK_MASK_MUX 0x04 78 79 extern int jz4780_clk_gen_register(struct clkdom *clkdom, 80 const struct jz4780_clk_descr *descr, struct mtx *dev_mtx, 81 struct resource *mem_res); 82 83 extern int jz4780_clk_pll_register(struct clkdom *clkdom, 84 struct clknode_init_def *clkdef, struct mtx *dev_mtx, 85 struct resource *mem_res, uint32_t mem_reg); 86 87 extern int jz4780_clk_otg_register(struct clkdom *clkdom, 88 struct clknode_init_def *clkdef, struct mtx *dev_mtx, 89 struct resource *mem_res); 90 91 #endif /* _MIPS_INGENIC_JZ4780_CLK_PLL_H */ 92