1 /*-
2 * Copyright 2015 Alexander Kabaev <kan@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 /*
28 * Ingenic JZ4780 OTG PHY clock driver.
29 *
30 */
31
32 #include <sys/cdefs.h>
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/conf.h>
36 #include <sys/bus.h>
37 #include <sys/lock.h>
38 #include <sys/mutex.h>
39 #include <sys/resource.h>
40
41 #include <machine/bus.h>
42
43 #include <mips/ingenic/jz4780_clk.h>
44 #include <mips/ingenic/jz4780_regs.h>
45
46 /* JZ4780 OTG PHY clock */
47 static int jz4780_clk_otg_init(struct clknode *clk, device_t dev);
48 static int jz4780_clk_otg_recalc_freq(struct clknode *clk, uint64_t *freq);
49 static int jz4780_clk_otg_set_freq(struct clknode *clk, uint64_t fin,
50 uint64_t *fout, int flags, int *stop);
51
52 struct jz4780_clk_otg_sc {
53 struct mtx *clk_mtx;
54 struct resource *clk_res;
55 };
56
57 /*
58 * JZ4780 OTG PHY clock methods
59 */
60 static clknode_method_t jz4780_clk_otg_methods[] = {
61 CLKNODEMETHOD(clknode_init, jz4780_clk_otg_init),
62 CLKNODEMETHOD(clknode_recalc_freq, jz4780_clk_otg_recalc_freq),
63 CLKNODEMETHOD(clknode_set_freq, jz4780_clk_otg_set_freq),
64
65 CLKNODEMETHOD_END
66 };
67 DEFINE_CLASS_1(jz4780_clk_pll, jz4780_clk_otg_class, jz4780_clk_otg_methods,
68 sizeof(struct jz4780_clk_otg_sc), clknode_class);
69
70 static int
jz4780_clk_otg_init(struct clknode * clk,device_t dev)71 jz4780_clk_otg_init(struct clknode *clk, device_t dev)
72 {
73 struct jz4780_clk_otg_sc *sc;
74 uint32_t reg;
75
76 sc = clknode_get_softc(clk);
77 CLK_LOCK(sc);
78 /* Force the use fo the core clock */
79 reg = CLK_RD_4(sc, JZ_USBPCR1);
80 reg &= ~PCR_REFCLK_M;
81 reg |= PCR_REFCLK_CORE;
82 CLK_WR_4(sc, JZ_USBPCR1, reg);
83 CLK_UNLOCK(sc);
84
85 clknode_init_parent_idx(clk, 0);
86 return (0);
87 }
88
89 static const struct {
90 uint32_t div_val;
91 uint32_t freq;
92 } otg_div_table[] = {
93 { PCR_CLK_12, 12000000 },
94 { PCR_CLK_192, 19200000 },
95 { PCR_CLK_24, 24000000 },
96 { PCR_CLK_48, 48000000 }
97 };
98
99 static int
jz4780_clk_otg_recalc_freq(struct clknode * clk,uint64_t * freq)100 jz4780_clk_otg_recalc_freq(struct clknode *clk, uint64_t *freq)
101 {
102 struct jz4780_clk_otg_sc *sc;
103 uint32_t reg;
104 int i;
105
106 sc = clknode_get_softc(clk);
107 reg = CLK_RD_4(sc, JZ_USBPCR1);
108 reg &= PCR_CLK_M;
109
110 for (i = 0; i < nitems(otg_div_table); i++)
111 if (otg_div_table[i].div_val == reg)
112 *freq = otg_div_table[i].freq;
113 return (0);
114 }
115
116 static int
jz4780_clk_otg_set_freq(struct clknode * clk,uint64_t fin,uint64_t * fout,int flags,int * stop)117 jz4780_clk_otg_set_freq(struct clknode *clk, uint64_t fin,
118 uint64_t *fout, int flags, int *stop)
119 {
120 struct jz4780_clk_otg_sc *sc;
121 uint32_t reg;
122 int i;
123
124 sc = clknode_get_softc(clk);
125
126 for (i = 0; i < nitems(otg_div_table) - 1; i++) {
127 if (*fout < (otg_div_table[i].freq + otg_div_table[i + 1].freq) / 2)
128 break;
129 }
130
131 *fout = otg_div_table[i].freq;
132
133 *stop = 1;
134 if (flags & CLK_SET_DRYRUN)
135 return (0);
136
137 CLK_LOCK(sc);
138 reg = CLK_RD_4(sc, JZ_USBPCR1);
139 /* Set the calculated values */
140 reg &= ~PCR_CLK_M;
141 reg |= otg_div_table[i].div_val;
142 /* Initiate the change */
143 CLK_WR_4(sc, JZ_USBPCR1, reg);
144 CLK_UNLOCK(sc);
145
146 return (0);
147 }
148
jz4780_clk_otg_register(struct clkdom * clkdom,struct clknode_init_def * clkdef,struct mtx * dev_mtx,struct resource * mem_res)149 int jz4780_clk_otg_register(struct clkdom *clkdom,
150 struct clknode_init_def *clkdef, struct mtx *dev_mtx,
151 struct resource *mem_res)
152 {
153 struct clknode *clk;
154 struct jz4780_clk_otg_sc *sc;
155
156 clk = clknode_create(clkdom, &jz4780_clk_otg_class, clkdef);
157 if (clk == NULL)
158 return (1);
159
160 sc = clknode_get_softc(clk);
161 sc->clk_mtx = dev_mtx;
162 sc->clk_res = mem_res;
163 clknode_register(clkdom, clk);
164 return (0);
165 }
166