1 /*- 2 * Copyright (c) 2015 Alexander Kabaev <kan@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 15 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 16 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 18 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 19 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 20 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 21 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 22 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 23 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 24 * POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #ifndef JZ4780_CPUREGS_H 28 #define JZ4780_CPUREGS_H 29 30 /* Core control register */ 31 #define JZ_CORECTL_SLP1M_SHIFT 17 32 #define JZ_CORECTL_SLP1M (1u << JZ_CORECTL_SLP1M_SHIFT) 33 #define JZ_CORECTL_SLP0M_SHIFT 16 34 #define JZ_CORECTL_SLP0M (1u << JZ_CORECTL_SLP0M_SHIFT) 35 #define JZ_CORECTL_RPC1_SHIFT 9 36 #define JZ_CORECTL_RPC1 (1u << JZ_CORECTL_RPC1_SHIFT) 37 #define JZ_CORECTL_RPC0_SHIFT 8 38 #define JZ_CORECTL_RPC0 (1u << JZ_CORECTL_RPC0_SHIFT) 39 #define JZ_CORECTL_SWRST1_SHIFT 1 40 #define JZ_CORECTL_SWRST1 (1u << JZ_CORECTL_SWRST1_SHIFT) 41 #define JZ_CORECTL_SWRST0_SHIFT 0 42 #define JZ_CORECTL_SWRST0 (1u << JZ_CORECTL_SWRST0_SHIFT) 43 44 /* Core status register */ 45 #define JZ_CORESTS_SLP1_SHIFT 17 46 #define JZ_CORESTS_SLP1 (1u << JZ_CORESTS_SLP1_SHIFT) 47 #define JZ_CORESTS_SLP0_SHIFT 16 48 #define JZ_CORESTS_SLP0 (1u << JZ_CORESTS_SLP0_SHIFT) 49 #define JZ_CORESTS_IRQ1P_SHIFT 9 50 #define JZ_CORESTS_IRQ1P (1u << JZ_CORESTS_IRQ1P_SHIFT) 51 #define JZ_CORESTS_IRQ0P_SHIFT 8 52 #define JZ_CORESTS_IRQ0P (1u << JZ_CORESTS_IRQ0P_SHIFT) 53 #define JZ_CORESTS_MIRQ1P_SHIFT 1 54 #define JZ_CORESTS_MIRQ1P (1u << JZ_CORESTS_MIRQ1P_SHIFT) 55 #define JZ_CORESTS_MIRQ0P_SHIFT 0 56 #define JZ_CORESTS_MIRQ0P (1u << JZ_CORESTS_MIRQ0P_SHIFT) 57 58 /* Reset entry and IRQ mask */ 59 #define JZ_REIM_ENTRY_SHIFT 16 60 #define JZ_REIM_ENTRY_WIDTH 16 61 #define JZ_REIM_ENTRY_MASK (0xFFFFu << JZ_REIM_ENTRY_SHIFT) 62 #define JZ_REIM_IRQ1M_SHIFT 9 63 #define JZ_REIM_IRQ1M (1u << JZ_REIM_IRQ1M_SHIFT) 64 #define JZ_REIM_IRQ0M_SHIFT 8 65 #define JZ_REIM_IRQ0M (1u << JZ_REIM_IRQ0M_SHIFT) 66 #define JZ_REIM_MIRQ1M_SHIFT 1 67 #define JZ_REIM_MIRQ1M (1u << JZ_REIM_MIRQ1M_SHIFT) 68 #define JZ_REIM_MIRQ0M_SHIFT 0 69 #define JZ_REIM_MIRQ0M (1u << JZ_REIM_MIRQ0M_SHIFT) 70 71 #endif /* JZ4780_CPUREGS_H */ 72