1 /*-
2 * Copyright 2013-2015 Alexander Kabaev <kan@FreeBSD.org>
3 * Copyright 2013-2015 John Wehle <john@feith.com>
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 */
28
29 #include <sys/cdefs.h>
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <sys/bus.h>
33 #include <sys/kernel.h>
34 #include <sys/module.h>
35 #include <sys/malloc.h>
36 #include <sys/rman.h>
37 #include <sys/timetc.h>
38 #include <sys/timeet.h>
39
40 #include <machine/bus.h>
41 #include <machine/cpu.h>
42 #include <machine/hwfunc.h>
43
44 #include <dev/extres/clk/clk.h>
45
46 #include <dev/fdt/fdt_common.h>
47 #include <dev/ofw/ofw_bus.h>
48 #include <dev/ofw/ofw_bus_subr.h>
49
50 #include <mips/ingenic/jz4780_regs.h>
51
52 struct jz4780_timer_softc {
53 device_t dev;
54 struct resource * res[4];
55 void * ih_cookie;
56 struct eventtimer et;
57 struct timecounter tc;
58 };
59
60 static struct resource_spec jz4780_timer_spec[] = {
61 { SYS_RES_MEMORY, 0, RF_ACTIVE },
62 { SYS_RES_IRQ, 0, RF_ACTIVE }, /* OST */
63 { SYS_RES_IRQ, 1, RF_ACTIVE }, /* TC5 */
64 { SYS_RES_IRQ, 2, RF_ACTIVE }, /* TC0-4,6 */
65 { -1, 0 }
66 };
67
68 /*
69 * devclass_get_device / device_get_softc could be used
70 * to dynamically locate this, however the timers are a
71 * required device which can't be unloaded so there's
72 * no need for the overhead.
73 */
74 static struct jz4780_timer_softc *jz4780_timer_sc = NULL;
75
76 #define CSR_WRITE_4(sc, reg, val) bus_write_4((sc)->res[0], reg, (val))
77 #define CSR_READ_4(sc, reg) bus_read_4((sc)->res[0], reg)
78
79 static unsigned
jz4780_get_timecount(struct timecounter * tc)80 jz4780_get_timecount(struct timecounter *tc)
81 {
82 struct jz4780_timer_softc *sc =
83 (struct jz4780_timer_softc *)tc->tc_priv;
84
85 return CSR_READ_4(sc, JZ_OST_CNT_LO);
86 }
87
88 static int
jz4780_hardclock(void * arg)89 jz4780_hardclock(void *arg)
90 {
91 struct jz4780_timer_softc *sc = (struct jz4780_timer_softc *)arg;
92
93 CSR_WRITE_4(sc, JZ_TC_TFCR, TFR_FFLAG5);
94 CSR_WRITE_4(sc, JZ_TC_TECR, TESR_TCST5);
95
96 if (sc->et.et_active)
97 sc->et.et_event_cb(&sc->et, sc->et.et_arg);
98
99 return (FILTER_HANDLED);
100 }
101
102 static int
jz4780_timer_start(struct eventtimer * et,sbintime_t first,sbintime_t period)103 jz4780_timer_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
104 {
105 struct jz4780_timer_softc *sc =
106 (struct jz4780_timer_softc *)et->et_priv;
107 uint32_t ticks;
108
109 ticks = (first * et->et_frequency) / SBT_1S;
110 if (ticks == 0)
111 return (EINVAL);
112
113 CSR_WRITE_4(sc, JZ_TC_TDFR(5), ticks);
114 CSR_WRITE_4(sc, JZ_TC_TCNT(5), 0);
115 CSR_WRITE_4(sc, JZ_TC_TESR, TESR_TCST5);
116
117 return (0);
118 }
119
120 static int
jz4780_timer_stop(struct eventtimer * et)121 jz4780_timer_stop(struct eventtimer *et)
122 {
123 struct jz4780_timer_softc *sc =
124 (struct jz4780_timer_softc *)et->et_priv;
125
126 CSR_WRITE_4(sc, JZ_TC_TECR, TESR_TCST5);
127 return (0);
128 }
129
130 static int
jz4780_timer_probe(device_t dev)131 jz4780_timer_probe(device_t dev)
132 {
133
134 if (!ofw_bus_status_okay(dev))
135 return (ENXIO);
136
137 if (!ofw_bus_is_compatible(dev, "ingenic,jz4780-tcu"))
138 return (ENXIO);
139
140 device_set_desc(dev, "Ingenic JZ4780 timer");
141
142 return (BUS_PROBE_DEFAULT);
143 }
144
145 static int
jz4780_timer_attach(device_t dev)146 jz4780_timer_attach(device_t dev)
147 {
148 struct jz4780_timer_softc *sc = device_get_softc(dev);
149 pcell_t counter_freq;
150 clk_t clk;
151
152 /* There should be exactly one instance. */
153 if (jz4780_timer_sc != NULL)
154 return (ENXIO);
155
156 sc->dev = dev;
157
158 if (bus_alloc_resources(dev, jz4780_timer_spec, sc->res)) {
159 device_printf(dev, "can not allocate resources for device\n");
160 return (ENXIO);
161 }
162
163 counter_freq = 0;
164 if (clk_get_by_name(dev, "ext", &clk) == 0) {
165 uint64_t clk_freq;
166
167 if (clk_get_freq(clk, &clk_freq) == 0)
168 counter_freq = (uint32_t)clk_freq / 16;
169 clk_release(clk);
170 }
171 if (counter_freq == 0) {
172 device_printf(dev, "unable to determine ext clock frequency\n");
173 /* Hardcode value we 'know' is correct */
174 counter_freq = 48000000 / 16;
175 }
176
177 /*
178 * Disable the timers, select the input for each timer,
179 * clear and then start OST.
180 */
181
182 /* Stop OST, if it happens to be running */
183 CSR_WRITE_4(sc, JZ_TC_TECR, TESR_OST);
184 /* Stop all other channels as well */
185 CSR_WRITE_4(sc, JZ_TC_TECR, TESR_TCST0 | TESR_TCST1 | TESR_TCST2 |
186 TESR_TCST3 | TESR_TCST4 | TESR_TCST5 | TESR_TCST6 | TESR_TCST7);
187 /* Clear detect mask flags */
188 CSR_WRITE_4(sc, JZ_TC_TFCR, 0xFFFFFFFF);
189 /* Mask all interrupts */
190 CSR_WRITE_4(sc, JZ_TC_TMSR, 0xFFFFFFFF);
191
192 /* Init counter with known data */
193 CSR_WRITE_4(sc, JZ_OST_CTRL, 0);
194 CSR_WRITE_4(sc, JZ_OST_CNT_LO, 0);
195 CSR_WRITE_4(sc, JZ_OST_CNT_HI, 0);
196 CSR_WRITE_4(sc, JZ_OST_DATA, 0xffffffff);
197
198 /* Configure counter for external clock */
199 CSR_WRITE_4(sc, JZ_OST_CTRL, OSTC_EXT_EN | OSTC_MODE | OSTC_DIV_16);
200
201 /* Start the counter again */
202 CSR_WRITE_4(sc, JZ_TC_TESR, TESR_OST);
203
204 /* Configure TCU channel 5 similarly to OST and leave it disabled */
205 CSR_WRITE_4(sc, JZ_TC_TCSR(5), TCSR_EXT_EN | TCSR_DIV_16);
206 CSR_WRITE_4(sc, JZ_TC_TMCR, TMR_FMASK(5));
207
208 if (bus_setup_intr(dev, sc->res[2], INTR_TYPE_CLK,
209 jz4780_hardclock, NULL, sc, &sc->ih_cookie)) {
210 device_printf(dev, "could not setup interrupt handler\n");
211 bus_release_resources(dev, jz4780_timer_spec, sc->res);
212 return (ENXIO);
213 }
214
215 sc->et.et_name = "JZ4780 TCU5";
216 sc->et.et_flags = ET_FLAGS_ONESHOT;
217 sc->et.et_frequency = counter_freq;
218 sc->et.et_quality = 1000;
219 sc->et.et_min_period = (0x00000002LLU * SBT_1S) / sc->et.et_frequency;
220 sc->et.et_max_period = (0x0000fffeLLU * SBT_1S) / sc->et.et_frequency;
221 sc->et.et_start = jz4780_timer_start;
222 sc->et.et_stop = jz4780_timer_stop;
223 sc->et.et_priv = sc;
224
225 et_register(&sc->et);
226
227 sc->tc.tc_get_timecount = jz4780_get_timecount;
228 sc->tc.tc_name = "JZ4780 OST";
229 sc->tc.tc_frequency = counter_freq;
230 sc->tc.tc_counter_mask = ~0u;
231 sc->tc.tc_quality = 1000;
232 sc->tc.tc_priv = sc;
233
234 tc_init(&sc->tc);
235
236 /* Now when tc is initialized, allow DELAY to find it */
237 jz4780_timer_sc = sc;
238
239 return (0);
240 }
241
242 static int
jz4780_timer_detach(device_t dev)243 jz4780_timer_detach(device_t dev)
244 {
245
246 return (EBUSY);
247 }
248
249 static device_method_t jz4780_timer_methods[] = {
250 /* Device interface */
251 DEVMETHOD(device_probe, jz4780_timer_probe),
252 DEVMETHOD(device_attach, jz4780_timer_attach),
253 DEVMETHOD(device_detach, jz4780_timer_detach),
254
255 DEVMETHOD_END
256 };
257
258 static driver_t jz4780_timer_driver = {
259 "timer",
260 jz4780_timer_methods,
261 sizeof(struct jz4780_timer_softc),
262 };
263
264 static devclass_t jz4780_timer_devclass;
265
266 EARLY_DRIVER_MODULE(timer, simplebus, jz4780_timer_driver,
267 jz4780_timer_devclass, 0, 0, BUS_PASS_TIMER);
268
269 void
DELAY(int usec)270 DELAY(int usec)
271 {
272 uint32_t counter;
273 uint32_t delta, now, previous, remaining;
274
275 /* Timer has not yet been initialized */
276 if (jz4780_timer_sc == NULL) {
277 for (; usec > 0; usec--)
278 for (counter = 200; counter > 0; counter--) {
279 /* Prevent gcc from optimizing out the loop */
280 mips_rd_cause();
281 }
282 return;
283 }
284 TSENTER();
285
286 /*
287 * Some of the other timers in the source tree do this calculation as:
288 *
289 * usec * ((sc->tc.tc_frequency / 1000000) + 1)
290 *
291 * which gives a fairly pessimistic result when tc_frequency is an exact
292 * multiple of 1000000. Given the data type and typical values for
293 * tc_frequency adding 999999 shouldn't overflow.
294 */
295 remaining = usec * ((jz4780_timer_sc->tc.tc_frequency + 999999) /
296 1000000);
297
298 /*
299 * We add one since the first iteration may catch the counter just
300 * as it is changing.
301 */
302 remaining += 1;
303
304 previous = jz4780_get_timecount(&jz4780_timer_sc->tc);
305
306 for ( ; ; ) {
307 now = jz4780_get_timecount(&jz4780_timer_sc->tc);
308
309 /*
310 * If the timer has rolled over, then we have the case:
311 *
312 * if (previous > now) {
313 * delta = (0 - previous) + now
314 * }
315 *
316 * which is really no different then the normal case.
317 * Both cases are simply:
318 *
319 * delta = now - previous.
320 */
321 delta = now - previous;
322
323 if (delta >= remaining)
324 break;
325
326 previous = now;
327 remaining -= delta;
328 }
329 TSEXIT();
330 }
331
332 void
platform_initclocks(void)333 platform_initclocks(void)
334 {
335
336 }
337